| ... | ... | @@ -230,6 +230,29 @@ fn _start() callconv(.naked) noreturn { |
| 230 | 230 | ); |
| 231 | 231 | } |
| 232 | 232 | |
| 233 | // This is the first userspace frame. Prevent DWARF-based unwinders from unwinding further. We |
| 234 | // prevent FP-based unwinders from unwinding further by zeroing the register further below. |
| 235 | asm volatile (switch (native_arch) { |
| 236 | .arc => ".cfi_undefined blink", |
| 237 | .arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891 |
| 238 | .aarch64, .aarch64_be => ".cfi_undefined lr", |
| 239 | .csky => ".cfi_undefined lr", |
| 240 | .hexagon => ".cfi_undefined r31", |
| 241 | .loongarch32, .loongarch64 => ".cfi_undefined 1", |
| 242 | .m68k => ".cfi_undefined pc", |
| 243 | .mips, .mipsel, .mips64, .mips64el => ".cfi_undefined $ra", |
| 244 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => ".cfi_undefined lr", |
| 245 | .riscv32, .riscv64 => if (builtin.zig_backend == .stage2_riscv64) |
| 246 | "" |
| 247 | else |
| 248 | ".cfi_undefined ra", |
| 249 | .s390x => ".cfi_undefined %%r14", |
| 250 | .sparc, .sparc64 => ".cfi_undefined %%i7", |
| 251 | .x86 => ".cfi_undefined %%eip", |
| 252 | .x86_64 => ".cfi_undefined %%rip", |
| 253 | else => @compileError("unsupported arch"), |
| 254 | }); |
| 255 | |
| 233 | 256 | // Move this to the riscv prong below when this is resolved: https://github.com/ziglang/zig/issues/20918 |
| 234 | 257 | if (builtin.cpu.arch.isRISCV() and builtin.zig_backend != .stage2_riscv64) asm volatile ( |
| 235 | 258 | \\ .weak __global_pointer$ |
| ... | ... | @@ -247,7 +270,6 @@ fn _start() callconv(.naked) noreturn { |
| 247 | 270 | // linker explicitly. |
| 248 | 271 | asm volatile (switch (native_arch) { |
| 249 | 272 | .x86_64 => |
| 250 | | \\ .cfi_undefined %%rip |
| 251 | 273 | \\ xorl %%ebp, %%ebp |
| 252 | 274 | \\ movq %%rsp, %%rdi |
| 253 | 275 | \\ andq $-16, %%rsp |