authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-05-10 23:21:53-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-06-13 02:21:38-07:00
log7ed2f2156f4e93fa6463fb81f134c0d5e7e7cc89
treef4e137d7fe20f4799467a9eaa661a56e81bdfbc8
parent381a1043eb53971b9fe5bde088211d04e63dfd58
signaturelock-open Commit is signed but in an unrecognized format.

riscv: fix register clobber in certain edge cases

4 files changed, 12 insertions(+), 16 deletions(-)

src/arch/riscv64/CodeGen.zig+12-12
......@@ -1841,7 +1841,7 @@ fn airMinMax(
18411841 if (int_info.bits > 64) return self.fail("TODO: > 64 bit @min", .{});
18421842
18431843 const lhs_reg, const lhs_lock = blk: {
1844 if (lhs == .register) break :blk .{ lhs.register, null };
1844 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
18451845
18461846 const lhs_reg, const lhs_lock = try self.allocReg();
18471847 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -1850,7 +1850,7 @@ fn airMinMax(
18501850 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
18511851
18521852 const rhs_reg, const rhs_lock = blk: {
1853 if (rhs == .register) break :blk .{ rhs.register, null };
1853 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
18541854
18551855 const rhs_reg, const rhs_lock = try self.allocReg();
18561856 try self.genSetReg(rhs_ty, rhs_reg, rhs);
......@@ -2088,7 +2088,7 @@ fn binOpRegister(
20882088 rhs_ty: Type,
20892089) !MCValue {
20902090 const lhs_reg, const lhs_lock = blk: {
2091 if (lhs == .register) break :blk .{ lhs.register, null };
2091 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
20922092
20932093 const lhs_reg, const lhs_lock = try self.allocReg();
20942094 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -2097,7 +2097,7 @@ fn binOpRegister(
20972097 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
20982098
20992099 const rhs_reg, const rhs_lock = blk: {
2100 if (rhs == .register) break :blk .{ rhs.register, null };
2100 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
21012101
21022102 const rhs_reg, const rhs_lock = try self.allocReg();
21032103 try self.genSetReg(rhs_ty, rhs_reg, rhs);
......@@ -2358,7 +2358,7 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
23582358 const offset = result_mcv.load_frame;
23592359
23602360 const lhs_reg, const lhs_lock = blk: {
2361 if (lhs == .register) break :blk .{ lhs.register, null };
2361 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
23622362
23632363 const lhs_reg, const lhs_lock = try self.allocReg();
23642364 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -2367,7 +2367,7 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
23672367 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
23682368
23692369 const rhs_reg, const rhs_lock = blk: {
2370 if (rhs == .register) break :blk .{ rhs.register, null };
2370 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
23712371
23722372 const rhs_reg, const rhs_lock = try self.allocReg();
23732373 try self.genSetReg(rhs_ty, rhs_reg, rhs);
......@@ -2596,7 +2596,7 @@ fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void {
25962596 const rhs_ty = self.typeOf(bin_op.rhs);
25972597
25982598 const lhs_reg, const lhs_lock = blk: {
2599 if (lhs == .register) break :blk .{ lhs.register, null };
2599 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
26002600
26012601 const lhs_reg, const lhs_lock = try self.allocReg();
26022602 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -2605,7 +2605,7 @@ fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void {
26052605 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
26062606
26072607 const rhs_reg, const rhs_lock = blk: {
2608 if (rhs == .register) break :blk .{ rhs.register, null };
2608 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
26092609
26102610 const rhs_reg, const rhs_lock = try self.allocReg();
26112611 try self.genSetReg(rhs_ty, rhs_reg, rhs);
......@@ -2641,7 +2641,7 @@ fn airBitOr(self: *Self, inst: Air.Inst.Index) !void {
26412641 const rhs_ty = self.typeOf(bin_op.rhs);
26422642
26432643 const lhs_reg, const lhs_lock = blk: {
2644 if (lhs == .register) break :blk .{ lhs.register, null };
2644 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
26452645
26462646 const lhs_reg, const lhs_lock = try self.allocReg();
26472647 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -2650,7 +2650,7 @@ fn airBitOr(self: *Self, inst: Air.Inst.Index) !void {
26502650 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
26512651
26522652 const rhs_reg, const rhs_lock = blk: {
2653 if (rhs == .register) break :blk .{ rhs.register, null };
2653 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
26542654
26552655 const rhs_reg, const rhs_lock = try self.allocReg();
26562656 try self.genSetReg(rhs_ty, rhs_reg, rhs);
......@@ -4717,7 +4717,7 @@ fn airBoolOp(self: *Self, inst: Air.Inst.Index) !void {
47174717 const rhs_ty = Type.bool;
47184718
47194719 const lhs_reg, const lhs_lock = blk: {
4720 if (lhs == .register) break :blk .{ lhs.register, null };
4720 if (lhs == .register) break :blk .{ lhs.register, self.register_manager.lockReg(lhs.register) };
47214721
47224722 const lhs_reg, const lhs_lock = try self.allocReg();
47234723 try self.genSetReg(lhs_ty, lhs_reg, lhs);
......@@ -4726,7 +4726,7 @@ fn airBoolOp(self: *Self, inst: Air.Inst.Index) !void {
47264726 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
47274727
47284728 const rhs_reg, const rhs_lock = blk: {
4729 if (rhs == .register) break :blk .{ rhs.register, null };
4729 if (rhs == .register) break :blk .{ rhs.register, self.register_manager.lockReg(rhs.register) };
47304730
47314731 const rhs_reg, const rhs_lock = try self.allocReg();
47324732 try self.genSetReg(rhs_ty, rhs_reg, rhs);
test/behavior/cast.zig-1
......@@ -677,7 +677,6 @@ test "@floatCast cast down" {
677677test "peer type resolution: unreachable, error set, unreachable" {
678678 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
679679 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
680 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
681680
682681 const Error = error{
683682 FileDescriptorAlreadyPresentInSet,
test/behavior/enum.zig-2
......@@ -618,7 +618,6 @@ test "enum with specified tag values" {
618618test "non-exhaustive enum" {
619619 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
620620 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
621 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
622621
623622 const S = struct {
624623 const E = enum(u8) { a, b, _ };
......@@ -683,7 +682,6 @@ test "empty non-exhaustive enum" {
683682test "single field non-exhaustive enum" {
684683 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
685684 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
686 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
687685
688686 const S = struct {
689687 const E = enum(u8) { a, _ };
test/behavior/switch.zig-1
......@@ -216,7 +216,6 @@ fn poll() void {
216216
217217test "switch on global mutable var isn't constant-folded" {
218218 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
219 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
220219
221220 while (state < 2) {
222221 poll();