| ... | ... | @@ -34,7 +34,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature { |
| 34 | 34 | .stage2_arm => .arm_backend, |
| 35 | 35 | .stage2_c => .c_backend, |
| 36 | 36 | .stage2_llvm => .llvm_backend, |
| 37 | | .stage2_powerpc => .powerpc_backend, |
| 37 | .stage2_powerpc => unreachable, |
| 38 | 38 | .stage2_riscv64 => .riscv64_backend, |
| 39 | 39 | .stage2_sparc64 => .sparc64_backend, |
| 40 | 40 | .stage2_spirv => .spirv_backend, |
| ... | ... | @@ -52,7 +52,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type { |
| 52 | 52 | .stage2_arm => @import("arch/arm/CodeGen.zig"), |
| 53 | 53 | .stage2_c => @import("codegen/c.zig"), |
| 54 | 54 | .stage2_llvm => @import("codegen/llvm.zig"), |
| 55 | | .stage2_powerpc => @import("arch/powerpc/CodeGen.zig"), |
| 55 | .stage2_powerpc => unreachable, |
| 56 | 56 | .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"), |
| 57 | 57 | .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"), |
| 58 | 58 | .stage2_spirv => @import("codegen/spirv.zig"), |
| ... | ... | @@ -77,7 +77,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co |
| 77 | 77 | .stage2_riscv64, |
| 78 | 78 | .stage2_sparc64, |
| 79 | 79 | .stage2_spirv, |
| 80 | | .stage2_powerpc, |
| 81 | 80 | => |backend| { |
| 82 | 81 | dev.check(devFeatureForBackend(backend)); |
| 83 | 82 | return importBackend(backend).legalizeFeatures(target); |
| ... | ... | @@ -91,7 +90,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co |
| 91 | 90 | pub const AnyMir = union { |
| 92 | 91 | aarch64: @import("arch/aarch64/Mir.zig"), |
| 93 | 92 | arm: @import("arch/arm/Mir.zig"), |
| 94 | | powerpc: noreturn, //@import("arch/powerpc/Mir.zig"), |
| 95 | 93 | riscv64: @import("arch/riscv64/Mir.zig"), |
| 96 | 94 | sparc64: @import("arch/sparc64/Mir.zig"), |
| 97 | 95 | x86_64: @import("arch/x86_64/Mir.zig"), |
| ... | ... | @@ -102,7 +100,6 @@ pub const AnyMir = union { |
| 102 | 100 | return switch (backend) { |
| 103 | 101 | .stage2_aarch64 => "aarch64", |
| 104 | 102 | .stage2_arm => "arm", |
| 105 | | .stage2_powerpc => "powerpc", |
| 106 | 103 | .stage2_riscv64 => "riscv64", |
| 107 | 104 | .stage2_sparc64 => "sparc64", |
| 108 | 105 | .stage2_x86_64 => "x86_64", |
| ... | ... | @@ -119,7 +116,6 @@ pub const AnyMir = union { |
| 119 | 116 | else => unreachable, |
| 120 | 117 | inline .stage2_aarch64, |
| 121 | 118 | .stage2_arm, |
| 122 | | .stage2_powerpc, |
| 123 | 119 | .stage2_riscv64, |
| 124 | 120 | .stage2_sparc64, |
| 125 | 121 | .stage2_x86_64, |
| ... | ... | @@ -150,7 +146,6 @@ pub fn generateFunction( |
| 150 | 146 | else => unreachable, |
| 151 | 147 | inline .stage2_aarch64, |
| 152 | 148 | .stage2_arm, |
| 153 | | .stage2_powerpc, |
| 154 | 149 | .stage2_riscv64, |
| 155 | 150 | .stage2_sparc64, |
| 156 | 151 | .stage2_x86_64, |
| ... | ... | @@ -188,7 +183,6 @@ pub fn emitFunction( |
| 188 | 183 | else => unreachable, |
| 189 | 184 | inline .stage2_aarch64, |
| 190 | 185 | .stage2_arm, |
| 191 | | .stage2_powerpc, |
| 192 | 186 | .stage2_riscv64, |
| 193 | 187 | .stage2_sparc64, |
| 194 | 188 | .stage2_x86_64, |
| ... | ... | @@ -215,10 +209,7 @@ pub fn generateLazyFunction( |
| 215 | 209 | zcu.getTarget(); |
| 216 | 210 | switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) { |
| 217 | 211 | else => unreachable, |
| 218 | | inline .stage2_powerpc, |
| 219 | | .stage2_riscv64, |
| 220 | | .stage2_x86_64, |
| 221 | | => |backend| { |
| 212 | inline .stage2_riscv64, .stage2_x86_64 => |backend| { |
| 222 | 213 | dev.check(devFeatureForBackend(backend)); |
| 223 | 214 | return importBackend(backend).generateLazy(lf, pt, src_loc, lazy_sym, code, debug_output); |
| 224 | 215 | }, |