| author |  Alex Rønne Petersen <alex@alexrp.com> 2025-10-16 12:57:05+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2025-10-18 00:36:52+02:00 |
| log | 81fe640dd21c1ba2d8406f4e9bb996d32f30df80 |
| tree | 054a7c53fa6f41f0103f5516f942867a60f86826 |
| parent | 0b55393a2f7d6c3ea233eee53067c535f857a62f |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.debug: add CPU context and DWARF mappings for lanai
2 files changed, 58 insertions(+), 0 deletions(-)
lib- std
lib/std/debug/Dwarf.zig+3
| ... | @@ -1432,6 +1432,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 { | ... | @@ -1432,6 +1432,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 { |
| 1432 | .aarch64, .aarch64_be => 32, | 1432 | .aarch64, .aarch64_be => 32, |
| 1433 | .arm, .armeb, .thumb, .thumbeb => 15, | 1433 | .arm, .armeb, .thumb, .thumbeb => 15, |
| 1434 | .hexagon => 76, | 1434 | .hexagon => 76, |
| 1435 | .lanai => 2, | ||
| 1435 | .loongarch32, .loongarch64 => 64, | 1436 | .loongarch32, .loongarch64 => 64, |
| 1436 | .mips, .mipsel, .mips64, .mips64el => 66, | 1437 | .mips, .mipsel, .mips64, .mips64el => 66, |
| 1437 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67, | 1438 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67, |
| ... | @@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 { | ... | @@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 { |
| 1450 | .aarch64, .aarch64_be => 29, | 1451 | .aarch64, .aarch64_be => 29, |
| 1451 | .arm, .armeb, .thumb, .thumbeb => 11, | 1452 | .arm, .armeb, .thumb, .thumbeb => 11, |
| 1452 | .hexagon => 30, | 1453 | .hexagon => 30, |
| 1454 | .lanai => 5, | ||
| 1453 | .loongarch32, .loongarch64 => 22, | 1455 | .loongarch32, .loongarch64 => 22, |
| 1454 | .mips, .mipsel, .mips64, .mips64el => 30, | 1456 | .mips, .mipsel, .mips64, .mips64el => 30, |
| 1455 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, | 1457 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, |
| ... | @@ -1468,6 +1470,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 { | ... | @@ -1468,6 +1470,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 { |
| 1468 | .aarch64, .aarch64_be => 31, | 1470 | .aarch64, .aarch64_be => 31, |
| 1469 | .arm, .armeb, .thumb, .thumbeb => 13, | 1471 | .arm, .armeb, .thumb, .thumbeb => 13, |
| 1470 | .hexagon => 29, | 1472 | .hexagon => 29, |
| 1473 | .lanai => 4, | ||
| 1471 | .loongarch32, .loongarch64 => 3, | 1474 | .loongarch32, .loongarch64 => 3, |
| 1472 | .mips, .mipsel, .mips64, .mips64el => 29, | 1475 | .mips, .mipsel, .mips64, .mips64el => 29, |
| 1473 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, | 1476 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, |
lib/std/debug/cpu_context.zig+55
| ... | @@ -7,6 +7,7 @@ else switch (native_arch) { | ... | @@ -7,6 +7,7 @@ else switch (native_arch) { |
| 7 | .aarch64, .aarch64_be => Aarch64, | 7 | .aarch64, .aarch64_be => Aarch64, |
| 8 | .arm, .armeb, .thumb, .thumbeb => Arm, | 8 | .arm, .armeb, .thumb, .thumbeb => Arm, |
| 9 | .hexagon => Hexagon, | 9 | .hexagon => Hexagon, |
| 10 | .lanai => Lanai, | ||
| 10 | .loongarch32, .loongarch64 => LoongArch, | 11 | .loongarch32, .loongarch64 => LoongArch, |
| 11 | .mips, .mipsel, .mips64, .mips64el => Mips, | 12 | .mips, .mipsel, .mips64, .mips64el => Mips, |
| 12 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc, | 13 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc, |
| ... | @@ -500,6 +501,60 @@ const Hexagon = extern struct { | ... | @@ -500,6 +501,60 @@ const Hexagon = extern struct { |
| 500 | } | 501 | } |
| 501 | }; | 502 | }; |
| 502 | 503 | ||
| 504 | /// This is an `extern struct` so that inline assembly in `current` can use field offsets. | ||
| 505 | const Lanai = extern struct { | ||
| 506 | r: [32]u32, | ||
| 507 | |||
| 508 | pub inline fn current() Lanai { | ||
| 509 | var ctx: Lanai = undefined; | ||
| 510 | asm volatile ( | ||
| 511 | \\ st %%r0, 0[r9] | ||
| 512 | \\ st %%r1, 4[r9] | ||
| 513 | \\ st %%r2, 8[r9] | ||
| 514 | \\ st %%r3, 12[r9] | ||
| 515 | \\ st %%r4, 16[r9] | ||
| 516 | \\ st %%r5, 20[r9] | ||
| 517 | \\ st %%r6, 24[r9] | ||
| 518 | \\ st %%r7, 28[r9] | ||
| 519 | \\ st %%r8, 32[r9] | ||
| 520 | \\ st %%r9, 36[r9] | ||
| 521 | \\ st %%r10, 40[r9] | ||
| 522 | \\ st %%r11, 44[r9] | ||
| 523 | \\ st %%r12, 48[r9] | ||
| 524 | \\ st %%r13, 52[r9] | ||
| 525 | \\ st %%r14, 56[r9] | ||
| 526 | \\ st %%r15, 60[r9] | ||
| 527 | \\ st %%r16, 64[r9] | ||
| 528 | \\ st %%r17, 68[r9] | ||
| 529 | \\ st %%r18, 72[r9] | ||
| 530 | \\ st %%r19, 76[r9] | ||
| 531 | \\ st %%r20, 80[r9] | ||
| 532 | \\ st %%r21, 84[r9] | ||
| 533 | \\ st %%r22, 88[r9] | ||
| 534 | \\ st %%r23, 92[r9] | ||
| 535 | \\ st %%r24, 96[r9] | ||
| 536 | \\ st %%r25, 100[r9] | ||
| 537 | \\ st %%r26, 104[r9] | ||
| 538 | \\ st %%r27, 108[r9] | ||
| 539 | \\ st %%r28, 112[r9] | ||
| 540 | \\ st %%r29, 116[r9] | ||
| 541 | \\ st %%r30, 120[r9] | ||
| 542 | \\ st %%r31, 124[r9] | ||
| 543 | : | ||
| 544 | : [ctx] "{r9}" (&ctx), | ||
| 545 | : .{ .memory = true }); | ||
| 546 | return ctx; | ||
| 547 | } | ||
| 548 | |||
| 549 | pub fn dwarfRegisterBytes(ctx: *Lanai, register_num: u16) DwarfRegisterError![]u8 { | ||
| 550 | switch (register_num) { | ||
| 551 | 0...31 => return @ptrCast(&ctx.s[register_num]), | ||
| 552 | |||
| 553 | else => return error.InvalidRegister, | ||
| 554 | } | ||
| 555 | } | ||
| 556 | }; | ||
| 557 | |||
| 503 | /// This is an `extern struct` so that inline assembly in `current` can use field offsets. | 558 | /// This is an `extern struct` so that inline assembly in `current` can use field offsets. |
| 504 | const LoongArch = extern struct { | 559 | const LoongArch = extern struct { |
| 505 | /// The numbered general-purpose registers r0 - r31. r0 must be zero. | 560 | /// The numbered general-purpose registers r0 - r31. r0 must be zero. |