authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-10-17 12:54:44-07:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-10-17 12:54:44-07:00
log8504e1f550ba697f29fd72f181d9009ebad09501
tree1a90c3da1ff4afdb23dc5415370874efe5778f23
parent816dfca0b579440604eb871c6a76a3edd250240f
parent6302a90cbf9978766757e11808e7764d5c4611b1
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #21610 from alexrp/riscv-abis

Fix some RISC-V ABI issues and add ILP32/LP64 (soft float) to module tests

4 files changed, 44 insertions(+), 39 deletions(-)

lib/compiler_rt/common.zig+1-1
......@@ -103,7 +103,7 @@ pub fn F16T(comptime OtherType: type) type {
103103 else
104104 u16,
105105 .aarch64, .aarch64_be => f16,
106 .riscv64 => if (builtin.zig_backend == .stage1) u16 else f16,
106 .riscv32, .riscv64 => f16,
107107 .x86, .x86_64 => if (builtin.target.isDarwin()) switch (OtherType) {
108108 // Starting with LLVM 16, Darwin uses different abi for f16
109109 // depending on the type of the other return/argument..???
src/codegen/llvm.zig+6-26
......@@ -1688,12 +1688,6 @@ pub const Object = struct {
16881688 else
16891689 try wip.load(.normal, param_llvm_ty, arg_ptr, param_alignment, ""));
16901690 },
1691 .as_u16 => {
1692 assert(!it.byval_attr);
1693 const param = wip.arg(llvm_arg_i);
1694 llvm_arg_i += 1;
1695 args.appendAssumeCapacity(try wip.cast(.bitcast, param, .half, ""));
1696 },
16971691 .float_array => {
16981692 const param_ty = Type.fromInterned(fn_info.param_types.get(ip)[it.zig_index - 1]);
16991693 const param_llvm_ty = try o.lowerType(param_ty);
......@@ -3096,7 +3090,6 @@ pub const Object = struct {
30963090 .no_bits,
30973091 .abi_sized_int,
30983092 .multiple_llvm_types,
3099 .as_u16,
31003093 .float_array,
31013094 .i32_array,
31023095 .i64_array,
......@@ -3771,9 +3764,6 @@ pub const Object = struct {
37713764 .multiple_llvm_types => {
37723765 try llvm_params.appendSlice(o.gpa, it.types_buffer[0..it.types_len]);
37733766 },
3774 .as_u16 => {
3775 try llvm_params.append(o.gpa, .i16);
3776 },
37773767 .float_array => |count| {
37783768 const param_ty = Type.fromInterned(fn_info.param_types.get(ip)[it.zig_index - 1]);
37793769 const float_ty = try o.lowerType(aarch64_c_abi.getFloatArrayType(param_ty, zcu).?);
......@@ -5588,12 +5578,6 @@ pub const FuncGen = struct {
55885578 llvm_args.appendAssumeCapacity(loaded);
55895579 }
55905580 },
5591 .as_u16 => {
5592 const arg = args[it.zig_index - 1];
5593 const llvm_arg = try self.resolveInst(arg);
5594 const casted = try self.wip.cast(.bitcast, llvm_arg, .i16, "");
5595 try llvm_args.append(casted);
5596 },
55975581 .float_array => |count| {
55985582 const arg = args[it.zig_index - 1];
55995583 const arg_ty = self.typeOf(arg);
......@@ -5655,7 +5639,6 @@ pub const FuncGen = struct {
56555639 .no_bits,
56565640 .abi_sized_int,
56575641 .multiple_llvm_types,
5658 .as_u16,
56595642 .float_array,
56605643 .i32_array,
56615644 .i64_array,
......@@ -11969,7 +11952,6 @@ const ParamTypeIterator = struct {
1196911952 abi_sized_int,
1197011953 multiple_llvm_types,
1197111954 slice,
11972 as_u16,
1197311955 float_array: u8,
1197411956 i32_array: u8,
1197511957 i64_array: u8,
......@@ -12091,8 +12073,6 @@ const ParamTypeIterator = struct {
1209112073 .riscv32, .riscv64 => {
1209212074 it.zig_index += 1;
1209312075 it.llvm_index += 1;
12094 if (ty.toIntern() == .f16_type and
12095 !std.Target.riscv.featureSetHas(target.cpu.features, .d)) return .as_u16;
1209612076 switch (riscv_c_abi.classifyType(ty, zcu)) {
1209712077 .memory => return .byref_mut,
1209812078 .byval => return .byval,
......@@ -12440,7 +12420,8 @@ fn isScalar(zcu: *Zcu, ty: Type) bool {
1244012420}
1244112421
1244212422/// This function returns true if we expect LLVM to lower x86_fp80 correctly
12443/// and false if we expect LLVM to crash if it counters an x86_fp80 type.
12423/// and false if we expect LLVM to crash if it encounters an x86_fp80 type,
12424/// or if it produces miscompilations.
1244412425fn backendSupportsF80(target: std.Target) bool {
1244512426 return switch (target.cpu.arch) {
1244612427 .x86_64, .x86 => !std.Target.x86.featureSetHas(target.cpu.features, .soft_float),
......@@ -12449,8 +12430,8 @@ fn backendSupportsF80(target: std.Target) bool {
1244912430}
1245012431
1245112432/// This function returns true if we expect LLVM to lower f16 correctly
12452/// and false if we expect LLVM to crash if it counters an f16 type or
12453/// if it produces miscompilations.
12433/// and false if we expect LLVM to crash if it encounters an f16 type,
12434/// or if it produces miscompilations.
1245412435fn backendSupportsF16(target: std.Target) bool {
1245512436 return switch (target.cpu.arch) {
1245612437 // LoongArch can be removed from this list with LLVM 20.
......@@ -12467,7 +12448,6 @@ fn backendSupportsF16(target: std.Target) bool {
1246712448 .mipsel,
1246812449 .mips64,
1246912450 .mips64el,
12470 .riscv32,
1247112451 .s390x,
1247212452 => false,
1247312453 .arm,
......@@ -12483,7 +12463,7 @@ fn backendSupportsF16(target: std.Target) bool {
1248312463}
1248412464
1248512465/// This function returns true if we expect LLVM to lower f128 correctly,
12486/// and false if we expect LLVm to crash if it encounters and f128 type
12466/// and false if we expect LLVM to crash if it encounters an f128 type,
1248712467/// or if it produces miscompilations.
1248812468fn backendSupportsF128(target: std.Target) bool {
1248912469 return switch (target.cpu.arch) {
......@@ -12510,7 +12490,7 @@ fn backendSupportsF128(target: std.Target) bool {
1251012490}
1251112491
1251212492/// LLVM does not support all relevant intrinsics for all targets, so we
12513/// may need to manually generate a libc call
12493/// may need to manually generate a compiler-rt call.
1251412494fn intrinsicsAllowed(scalar_ty: Type, target: std.Target) bool {
1251512495 return switch (scalar_ty.toIntern()) {
1251612496 .f16_type => backendSupportsF16(target),
src/target.zig+8-11
......@@ -427,17 +427,14 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 {
427427 // Once our self-hosted linker can handle both ABIs, this hack should go away.
428428 if (target.cpu.arch == .powerpc64) return "elfv2";
429429
430 const have_float = switch (target.abi) {
431 .gnueabihf, .musleabihf, .eabihf => true,
432 else => false,
433 };
434
435430 switch (target.cpu.arch) {
436431 .riscv64 => {
437432 const featureSetHas = std.Target.riscv.featureSetHas;
438 if (featureSetHas(target.cpu.features, .d)) {
433 if (featureSetHas(target.cpu.features, .e)) {
434 return "lp64e";
435 } else if (featureSetHas(target.cpu.features, .d)) {
439436 return "lp64d";
440 } else if (have_float) {
437 } else if (featureSetHas(target.cpu.features, .f)) {
441438 return "lp64f";
442439 } else {
443440 return "lp64";
......@@ -445,12 +442,12 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 {
445442 },
446443 .riscv32 => {
447444 const featureSetHas = std.Target.riscv.featureSetHas;
448 if (featureSetHas(target.cpu.features, .d)) {
445 if (featureSetHas(target.cpu.features, .e)) {
446 return "ilp32e";
447 } else if (featureSetHas(target.cpu.features, .d)) {
449448 return "ilp32d";
450 } else if (have_float) {
449 } else if (featureSetHas(target.cpu.features, .f)) {
451450 return "ilp32f";
452 } else if (featureSetHas(target.cpu.features, .e)) {
453 return "ilp32e";
454451 } else {
455452 return "ilp32";
456453 }
test/tests.zig+29-1
......@@ -579,6 +579,20 @@ const test_targets = blk: {
579579 .link_libc = true,
580580 },
581581
582 .{
583 .target = std.Target.Query.parse(.{
584 .arch_os_abi = "riscv32-linux-none",
585 .cpu_features = "baseline-d-f",
586 }) catch unreachable,
587 },
588 .{
589 .target = std.Target.Query.parse(.{
590 .arch_os_abi = "riscv32-linux-musl",
591 .cpu_features = "baseline-d-f",
592 }) catch unreachable,
593 .link_libc = true,
594 },
595
582596 .{
583597 .target = .{
584598 .cpu_arch = .riscv32,
......@@ -603,6 +617,20 @@ const test_targets = blk: {
603617 .link_libc = true,
604618 },
605619
620 .{
621 .target = std.Target.Query.parse(.{
622 .arch_os_abi = "riscv64-linux-none",
623 .cpu_features = "baseline-d-f",
624 }) catch unreachable,
625 },
626 .{
627 .target = std.Target.Query.parse(.{
628 .arch_os_abi = "riscv64-linux-musl",
629 .cpu_features = "baseline-d-f",
630 }) catch unreachable,
631 .link_libc = true,
632 },
633
606634 .{
607635 .target = .{
608636 .cpu_arch = .riscv64,
......@@ -631,7 +659,7 @@ const test_targets = blk: {
631659 .target = std.Target.Query.parse(.{
632660 .arch_os_abi = "riscv64-linux-musl",
633661 .cpu_features = "baseline+v+zbb",
634 }) catch @panic("OOM"),
662 }) catch unreachable,
635663 .use_llvm = false,
636664 .use_lld = false,
637665 },