authorgravatar for shawn@anastas.ioShawn Anastasio <shawn@anastas.io> 2020-07-01 16:12:27-05:00
committergravatar for shawn@anastas.ioShawn Anastasio <shawn@anastas.io> 2020-07-01 16:12:27-05:00
log8574861ca0bc5e8103c27e3c78866e3a4eb56f98
treeec6ef9861dacd915c0896692261a8602b014ce6c
parent15371775d18e6425d1528643cedb70d6f0b7e6ea

Implement required ABI bits for powerpc{,64,64le}

3 files changed, 11 insertions(+), 4 deletions(-)

src/analyze.cpp+2-1
...@@ -1003,7 +1003,8 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) {...@@ -1003,7 +1003,8 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) {
1003 g->zig_target->arch == ZigLLVM_x86_64 ||1003 g->zig_target->arch == ZigLLVM_x86_64 ||
1004 target_is_arm(g->zig_target) ||1004 target_is_arm(g->zig_target) ||
1005 target_is_riscv(g->zig_target) ||1005 target_is_riscv(g->zig_target) ||
1006 target_is_wasm(g->zig_target))1006 target_is_wasm(g->zig_target) ||
1007 target_is_ppc(g->zig_target))
1007 {1008 {
1008 X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type);1009 X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type);
1009 return abi_class == X64CABIClass_MEMORY || abi_class == X64CABIClass_MEMORY_nobyval;1010 return abi_class == X64CABIClass_MEMORY || abi_class == X64CABIClass_MEMORY_nobyval;
src/target.cpp+8-3
...@@ -853,6 +853,9 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {...@@ -853,6 +853,9 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
853 case ZigLLVM_riscv32:853 case ZigLLVM_riscv32:
854 case ZigLLVM_riscv64:854 case ZigLLVM_riscv64:
855 case ZigLLVM_mipsel:855 case ZigLLVM_mipsel:
856 case ZigLLVM_ppc:
857 case ZigLLVM_ppc64:
858 case ZigLLVM_ppc64le:
856 return "sp";859 return "sp";
857860
858 case ZigLLVM_wasm32:861 case ZigLLVM_wasm32:
...@@ -879,7 +882,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {...@@ -879,7 +882,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
879 case ZigLLVM_msp430:882 case ZigLLVM_msp430:
880 case ZigLLVM_nvptx:883 case ZigLLVM_nvptx:
881 case ZigLLVM_nvptx64:884 case ZigLLVM_nvptx64:
882 case ZigLLVM_ppc64le:
883 case ZigLLVM_r600:885 case ZigLLVM_r600:
884 case ZigLLVM_renderscript32:886 case ZigLLVM_renderscript32:
885 case ZigLLVM_renderscript64:887 case ZigLLVM_renderscript64:
...@@ -893,8 +895,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {...@@ -893,8 +895,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
893 case ZigLLVM_tce:895 case ZigLLVM_tce:
894 case ZigLLVM_tcele:896 case ZigLLVM_tcele:
895 case ZigLLVM_xcore:897 case ZigLLVM_xcore:
896 case ZigLLVM_ppc:
897 case ZigLLVM_ppc64:
898 case ZigLLVM_ve:898 case ZigLLVM_ve:
899 zig_panic("TODO populate this table with stack pointer register name for this CPU architecture");899 zig_panic("TODO populate this table with stack pointer register name for this CPU architecture");
900 }900 }
...@@ -1318,6 +1318,11 @@ bool target_is_mips(const ZigTarget *target) {...@@ -1318,6 +1318,11 @@ bool target_is_mips(const ZigTarget *target) {
1318 target->arch == ZigLLVM_mips64 || target->arch == ZigLLVM_mips64el;1318 target->arch == ZigLLVM_mips64 || target->arch == ZigLLVM_mips64el;
1319}1319}
13201320
1321bool target_is_ppc(const ZigTarget *target) {
1322 return target->arch == ZigLLVM_ppc || target->arch == ZigLLVM_ppc64 ||
1323 target->arch == ZigLLVM_ppc64le;
1324}
1325
1321unsigned target_fn_align(const ZigTarget *target) {1326unsigned target_fn_align(const ZigTarget *target) {
1322 return 16;1327 return 16;
1323}1328}
src/target.hpp+1
...@@ -95,6 +95,7 @@ ZigLLVM_OSType get_llvm_os_type(Os os_type);...@@ -95,6 +95,7 @@ ZigLLVM_OSType get_llvm_os_type(Os os_type);
9595
96bool target_is_arm(const ZigTarget *target);96bool target_is_arm(const ZigTarget *target);
97bool target_is_mips(const ZigTarget *target);97bool target_is_mips(const ZigTarget *target);
98bool target_is_ppc(const ZigTarget *target);
98bool target_allows_addr_zero(const ZigTarget *target);99bool target_allows_addr_zero(const ZigTarget *target);
99bool target_has_valgrind_support(const ZigTarget *target);100bool target_has_valgrind_support(const ZigTarget *target);
100bool target_os_is_darwin(Os os);101bool target_os_is_darwin(Os os);