authorgravatar for ntamtam614@gmail.comNeel <ntamtam614@gmail.com> 2026-04-07 12:24:13-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2026-04-08 14:37:48+02:00
log86853ba0a49579fdd8a41ac2c243075d8e51d83c
tree4b753c435ee11e70c83fa0ef750a47681fd715b3
parentcf0f6dd17fc9c534b11c6a3f3f6e448702a9a93a

Add RISC-V ABI register alias names for inline asm clobbers

2 files changed, 83 insertions(+), 0 deletions(-)

lib/std/builtin/assembly.zig+68
...@@ -682,6 +682,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {...@@ -682,6 +682,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
682 x30: bool = false,682 x30: bool = false,
683 x31: bool = false,683 x31: bool = false,
684684
685 // ABI aliases for integer registers
686 ra: bool = false,
687 sp: bool = false,
688 gp: bool = false,
689 tp: bool = false,
690 t0: bool = false,
691 t1: bool = false,
692 t2: bool = false,
693 s0: bool = false,
694 fp: bool = false,
695 s1: bool = false,
696 a0: bool = false,
697 a1: bool = false,
698 a2: bool = false,
699 a3: bool = false,
700 a4: bool = false,
701 a5: bool = false,
702 a6: bool = false,
703 a7: bool = false,
704 s2: bool = false,
705 s3: bool = false,
706 s4: bool = false,
707 s5: bool = false,
708 s6: bool = false,
709 s7: bool = false,
710 s8: bool = false,
711 s9: bool = false,
712 s10: bool = false,
713 s11: bool = false,
714 t3: bool = false,
715 t4: bool = false,
716 t5: bool = false,
717 t6: bool = false,
718
685 fflags: bool = false,719 fflags: bool = false,
686 frm: bool = false,720 frm: bool = false,
687721
...@@ -718,6 +752,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {...@@ -718,6 +752,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
718 f30: bool = false,752 f30: bool = false,
719 f31: bool = false,753 f31: bool = false,
720754
755 // ABI aliases for float registers
756 ft0: bool = false,
757 ft1: bool = false,
758 ft2: bool = false,
759 ft3: bool = false,
760 ft4: bool = false,
761 ft5: bool = false,
762 ft6: bool = false,
763 ft7: bool = false,
764 fs0: bool = false,
765 fs1: bool = false,
766 fa0: bool = false,
767 fa1: bool = false,
768 fa2: bool = false,
769 fa3: bool = false,
770 fa4: bool = false,
771 fa5: bool = false,
772 fa6: bool = false,
773 fa7: bool = false,
774 fs2: bool = false,
775 fs3: bool = false,
776 fs4: bool = false,
777 fs5: bool = false,
778 fs6: bool = false,
779 fs7: bool = false,
780 fs8: bool = false,
781 fs9: bool = false,
782 fs10: bool = false,
783 fs11: bool = false,
784 ft8: bool = false,
785 ft9: bool = false,
786 ft10: bool = false,
787 ft11: bool = false,
788
721 vtype: bool = false,789 vtype: bool = false,
722 vl: bool = false,790 vl: bool = false,
723 vxsat: bool = false,791 vxsat: bool = false,
test/behavior/asm.zig+15
...@@ -246,3 +246,18 @@ test "extern output types (x86_64)" {...@@ -246,3 +246,18 @@ test "extern output types (x86_64)" {
246 try expect(u.x == 123);246 try expect(u.x == 123);
247 }247 }
248}248}
249
250test "riscv abi register aliases as clobbers" {
251 if (!builtin.target.cpu.arch.isRISCV()) return error.SkipZigTest;
252 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
253 if (builtin.zig_backend == .stage2_c and builtin.os.tag == .windows) return error.SkipZigTest;
254
255 if (!comptime builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
256
257 // Verify that ABI alias names are accepted as clobbers for RISC-V.
258 asm volatile ("" ::: .{ .ra = true, .sp = true, .gp = true, .tp = true });
259 asm volatile ("" ::: .{ .a0 = true, .a1 = true, .a2 = true, .a3 = true, .a4 = true, .a5 = true, .a6 = true, .a7 = true });
260 asm volatile ("" ::: .{ .t0 = true, .t1 = true, .t2 = true, .t3 = true, .t4 = true, .t5 = true, .t6 = true });
261 asm volatile ("" ::: .{ .s0 = true, .fp = true, .s1 = true, .s2 = true, .s3 = true, .s4 = true, .s5 = true, .s6 = true, .s7 = true, .s8 = true, .s9 = true, .s10 = true, .s11 = true });
262 asm volatile ("" ::: .{ .fa0 = true, .fa1 = true, .ft0 = true, .fs0 = true });
263}