authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-26 06:14:04+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-30 01:32:48+02:00
log876383cb2a003484a81c47e60b5034b342fa9b14
tree21139f32162a54fde708252b728fd637433315cf
parent7e0f9c45f2ee6980cf6582c8f7ef09f3e10f200e
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.os.linux: Hook up newly added syscall enums.

1 files changed, 11 insertions(+), 1 deletions(-)

lib/std/os/linux.zig+11-1
...@@ -104,14 +104,24 @@ pub const SYS = switch (@import("builtin").cpu.arch) {...@@ -104,14 +104,24 @@ pub const SYS = switch (@import("builtin").cpu.arch) {
104 .x86 => syscalls.X86,104 .x86 => syscalls.X86,
105 .x86_64 => syscalls.X64,105 .x86_64 => syscalls.X64,
106 .aarch64, .aarch64_be => syscalls.Arm64,106 .aarch64, .aarch64_be => syscalls.Arm64,
107 .arc => syscalls.Arc,
107 .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,108 .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
109 .csky => syscalls.CSky,
110 .hexagon => syscalls.Hexagon,
108 .riscv32 => syscalls.RiscV32,111 .riscv32 => syscalls.RiscV32,
109 .riscv64 => syscalls.RiscV64,112 .riscv64 => syscalls.RiscV64,
113 .sparc, .sparcel => syscalls.Sparc,
110 .sparc64 => syscalls.Sparc64,114 .sparc64 => syscalls.Sparc64,
115 .m68k => syscalls.M68k,
111 .mips, .mipsel => syscalls.MipsO32,116 .mips, .mipsel => syscalls.MipsO32,
112 .mips64, .mips64el => syscalls.MipsN64,117 .mips64, .mips64el => if (builtin.abi == .gnuabin32)
118 syscalls.MipsN32
119 else
120 syscalls.MipsN64,
113 .powerpc, .powerpcle => syscalls.PowerPC,121 .powerpc, .powerpcle => syscalls.PowerPC,
114 .powerpc64, .powerpc64le => syscalls.PowerPC64,122 .powerpc64, .powerpc64le => syscalls.PowerPC64,
123 .s390x => syscalls.S390x,
124 .xtensa => syscalls.Xtensa,
115 else => @compileError("The Zig Standard Library is missing syscall definitions for the target CPU architecture"),125 else => @compileError("The Zig Standard Library is missing syscall definitions for the target CPU architecture"),
116};126};
117127