| author |  Koakuma <koachan@protonmail.com> 2022-06-01 19:32:14+07:00 |
| committer | Koakuma <koachan@protonmail.com> 2022-06-06 20:34:53+07:00 |
| log | 8b70abfcc66e375d71acf1e753d3589e38ba1a3d |
| tree | a6ec1c4af6162c92853d61dfcf79fbd15a49e6e8 |
| parent | 4d50e52c37cad45bd3d8fd520359cdaee70aaf1f |
stage2: sparc64: Fix & optimize 64-bit truncRegister
1 files changed, 3 insertions(+), 1 deletions(-)
src- arch
- sparc64
src/arch/sparc64/CodeGen.zig+3-1
| ... | ... | @@ -3569,11 +3569,13 @@ fn truncRegister( |
| 3569 | 3569 | }); |
| 3570 | 3570 | }, |
| 3571 | 3571 | 64 => { |
| 3572 | if (dest_reg == operand_reg) | |
| 3573 | return; // Copy register to itself; nothing to do. | |
| 3572 | 3574 | _ = try self.addInst(.{ |
| 3573 | 3575 | .tag = .mov, |
| 3574 | 3576 | .data = .{ |
| 3575 | 3577 | .arithmetic_2op = .{ |
| 3576 | .is_imm = true, | |
| 3578 | .is_imm = false, | |
| 3577 | 3579 | .rs1 = dest_reg, |
| 3578 | 3580 | .rs2_or_imm = .{ .rs2 = operand_reg }, |
| 3579 | 3581 | }, |