authorgravatar for 19855629+SuperAuguste@users.noreply.github.comAuguste Rame <19855629+SuperAuguste@users.noreply.github.com> 2023-04-07 20:52:04-04:00
committergravatar for 19855629+SuperAuguste@users.noreply.github.comAuguste Rame <19855629+SuperAuguste@users.noreply.github.com> 2023-04-07 20:52:04-04:00
log8ba3ab948a2675fb1be88a2654555eb3dbc3df09
tree697809ec42443fbfd53a38fd36070a8fb153242c
parent1e310d335078c441c8b37bc220715aab938538e0
signaturelock-open Commit is signed but in an unrecognized format.

Handle compile time case for vector element access using lane access


2 files changed, 47 insertions(+), 9 deletions(-)

src/arch/wasm/CodeGen.zig+30-9
......@@ -4527,17 +4527,38 @@ fn airArrayElemVal(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
45274527 } else {
45284528 std.debug.assert(array_ty.zigTypeTag() == .Vector);
45294529
4530 // TODO: Check if index is constant; if so, use a lane extract
4530 switch (index) {
4531 inline .imm32, .imm64 => |lane| {
4532 const opcode: wasm.SimdOpcode = switch (elem_ty.bitSize(func.target)) {
4533 8 => if (elem_ty.isSignedInt()) .i8x16_extract_lane_s else .i8x16_extract_lane_u,
4534 16 => if (elem_ty.isSignedInt()) .i16x8_extract_lane_s else .i16x8_extract_lane_u,
4535 32 => if (elem_ty.isInt()) .i32x4_extract_lane else .f32x4_extract_lane,
4536 64 => if (elem_ty.isInt()) .i64x2_extract_lane else .f64x2_extract_lane,
4537 else => unreachable,
4538 };
45314539
4532 var stack_vec = try func.allocStack(array_ty);
4533 try func.store(stack_vec, array, array_ty, 0);
4540 var operands = [_]u32{ std.wasm.simdOpcode(opcode), @intCast(u8, lane) };
45344541
4535 // Is a non-unrolled vector (v128)
4536 try func.lowerToStack(stack_vec);
4537 try func.emitWValue(index);
4538 try func.addImm32(@bitCast(i32, @intCast(u32, elem_size)));
4539 try func.addTag(.i32_mul);
4540 try func.addTag(.i32_add);
4542 try func.emitWValue(array);
4543
4544 const extra_index = @intCast(u32, func.mir_extra.items.len);
4545 try func.mir_extra.appendSlice(func.gpa, &operands);
4546 try func.addInst(.{ .tag = .simd_prefix, .data = .{ .payload = extra_index } });
4547
4548 return func.finishAir(inst, try WValue.toLocal(.stack, func, elem_ty), &.{ bin_op.lhs, bin_op.rhs });
4549 },
4550 else => {
4551 var stack_vec = try func.allocStack(array_ty);
4552 try func.store(stack_vec, array, array_ty, 0);
4553
4554 // Is a non-unrolled vector (v128)
4555 try func.lowerToStack(stack_vec);
4556 try func.emitWValue(index);
4557 try func.addImm32(@bitCast(i32, @intCast(u32, elem_size)));
4558 try func.addTag(.i32_mul);
4559 try func.addTag(.i32_add);
4560 },
4561 }
45414562 }
45424563
45434564 const elem_result = val: {
src/arch/wasm/Emit.zig+17
......@@ -492,6 +492,23 @@ fn emitSimd(emit: *Emit, inst: Mir.Inst.Index) !void {
492492 const simd_value = emit.mir.extra[extra_index + 1 ..][0..4];
493493 try writer.writeAll(std.mem.asBytes(simd_value));
494494 },
495 .i8x16_extract_lane_s,
496 .i8x16_extract_lane_u,
497 .i8x16_replace_lane,
498 .i16x8_extract_lane_s,
499 .i16x8_extract_lane_u,
500 .i16x8_replace_lane,
501 .i32x4_extract_lane,
502 .i32x4_replace_lane,
503 .i64x2_extract_lane,
504 .i64x2_replace_lane,
505 .f32x4_extract_lane,
506 .f32x4_replace_lane,
507 .f64x2_extract_lane,
508 .f64x2_replace_lane,
509 => {
510 try writer.writeByte(@intCast(u8, emit.mir.extra[extra_index + 1]));
511 },
495512 .i8x16_splat,
496513 .i16x8_splat,
497514 .i32x4_splat,