authorgravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2019-12-17 00:28:17+02:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2019-12-23 11:54:47+02:00
log8bb1e0444951b7b83254277c52534c7ab58fd135
treec334c30c388ba0920b92c06e1ca939582a9cd1d7
parent25e71216c4640a3d88c8f63912ea574ad6fa004c
signature Commit is signed but in an unrecognized format.

support some atomic operations with floats

5 files changed, 64 insertions(+), 9 deletions(-)

doc/langref.html.in+3-3
......@@ -6695,7 +6695,7 @@ async fn func(y: *i32) void {
66956695 This builtin function atomically dereferences a pointer and returns the value.
66966696 </p>
66976697 <p>
6698 {#syntax#}T{#endsyntax#} must be a pointer type, a {#syntax#}bool{#endsyntax#}
6698 {#syntax#}T{#endsyntax#} must be a pointer type, a {#syntax#}bool{#endsyntax#}, a float,
66996699 an integer whose bit count meets these requirements:
67006700 </p>
67016701 <ul>
......@@ -6730,7 +6730,7 @@ async fn func(y: *i32) void {
67306730 Supported operations:
67316731 </p>
67326732 <ul>
6733 <li>{#syntax#}.Xchg{#endsyntax#} - stores the operand unmodified.</li>
6733 <li>{#syntax#}.Xchg{#endsyntax#} - stores the operand unmodified. Supports enums, integers and floats.</li>
67346734 <li>{#syntax#}.Add{#endsyntax#} - for integers, twos complement wraparound addition.
67356735 Also supports {#link|Floats#}.</li>
67366736 <li>{#syntax#}.Sub{#endsyntax#} - for integers, twos complement wraparound subtraction.
......@@ -6749,7 +6749,7 @@ async fn func(y: *i32) void {
67496749 This builtin function atomically stores a value.
67506750 </p>
67516751 <p>
6752 {#syntax#}T{#endsyntax#} must be a pointer type, a {#syntax#}bool{#endsyntax#}
6752 {#syntax#}T{#endsyntax#} must be a pointer type, a {#syntax#}bool{#endsyntax#}, a float,
67536753 an integer whose bit count meets these requirements:
67546754 </p>
67556755 <ul>
src/codegen.cpp+7-5
......@@ -5129,11 +5129,13 @@ static LLVMAtomicOrdering to_LLVMAtomicOrdering(AtomicOrder atomic_order) {
51295129 zig_unreachable();
51305130}
51315131
5132static LLVMAtomicRMWBinOp to_LLVMAtomicRMWBinOp(AtomicRmwOp op, bool is_signed) {
5132static LLVMAtomicRMWBinOp to_LLVMAtomicRMWBinOp(AtomicRmwOp op, bool is_signed, bool is_float) {
51335133 switch (op) {
51345134 case AtomicRmwOp_xchg: return LLVMAtomicRMWBinOpXchg;
5135 case AtomicRmwOp_add: return LLVMAtomicRMWBinOpAdd;
5136 case AtomicRmwOp_sub: return LLVMAtomicRMWBinOpSub;
5135 case AtomicRmwOp_add:
5136 return is_float ? LLVMAtomicRMWBinOpFAdd: LLVMAtomicRMWBinOpAdd;
5137 case AtomicRmwOp_sub:
5138 return is_float ? LLVMAtomicRMWBinOpFSub: LLVMAtomicRMWBinOpSub;
51375139 case AtomicRmwOp_and: return LLVMAtomicRMWBinOpAnd;
51385140 case AtomicRmwOp_nand: return LLVMAtomicRMWBinOpNand;
51395141 case AtomicRmwOp_or: return LLVMAtomicRMWBinOpOr;
......@@ -5725,14 +5727,14 @@ static LLVMValueRef ir_render_panic(CodeGen *g, IrExecutable *executable, IrInst
57255727static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, IrExecutable *executable,
57265728 IrInstructionAtomicRmw *instruction)
57275729{
5728 bool is_signed;
57295730 ZigType *operand_type = instruction->operand->value->type;
5731 bool is_float = operand_type->id == ZigTypeIdFloat;
57305732 if (operand_type->id == ZigTypeIdInt) {
57315733 is_signed = operand_type->data.integral.is_signed;
57325734 } else {
57335735 is_signed = false;
57345736 }
5735 LLVMAtomicRMWBinOp op = to_LLVMAtomicRMWBinOp(instruction->resolved_op, is_signed);
5737 LLVMAtomicRMWBinOp op = to_LLVMAtomicRMWBinOp(instruction->resolved_op, is_signed, is_float);
57365738 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->resolved_ordering);
57375739 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
57385740 LLVMValueRef operand = ir_llvm_value(g, instruction->operand);
src/ir.cpp+19-1
......@@ -23956,6 +23956,12 @@ static IrInstruction *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstructi
2395623956 if (type_is_invalid(operand_type))
2395723957 return ira->codegen->invalid_instruction;
2395823958
23959 if (operand_type->id == ZigTypeIdFloat) {
23960 ir_add_error(ira, instruction->type_value->child,
23961 buf_sprintf("expected integer, enum or pointer type, found '%s'", buf_ptr(&operand_type->name)));
23962 return ira->codegen->invalid_instruction;
23963 }
23964
2395923965 IrInstruction *ptr = instruction->ptr->child;
2396023966 if (type_is_invalid(ptr->value->type))
2396123967 return ira->codegen->invalid_instruction;
......@@ -27433,9 +27439,17 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstruction *op
2743327439 buf_sprintf("%" PRIu32 "-bit enum tag type is not a power of 2", int_type->data.integral.bit_count));
2743427440 return ira->codegen->builtin_types.entry_invalid;
2743527441 }
27442 } else if (operand_type->id == ZigTypeIdFloat) {
27443 uint32_t max_atomic_bits = target_arch_largest_atomic_bits(ira->codegen->zig_target->arch);
27444 if (operand_type->data.floating.bit_count > max_atomic_bits) {
27445 ir_add_error(ira, op,
27446 buf_sprintf("expected %" PRIu32 "-bit float or smaller, found %" PRIu32 "-bit float",
27447 max_atomic_bits, (uint32_t) operand_type->data.floating.bit_count));
27448 return ira->codegen->builtin_types.entry_invalid;
27449 }
2743627450 } else if (get_codegen_ptr_type(operand_type) == nullptr) {
2743727451 ir_add_error(ira, op,
27438 buf_sprintf("expected integer, enum or pointer type, found '%s'", buf_ptr(&operand_type->name)));
27452 buf_sprintf("expected integer, float, enum or pointer type, found '%s'", buf_ptr(&operand_type->name)));
2743927453 return ira->codegen->builtin_types.entry_invalid;
2744027454 }
2744127455
......@@ -27470,6 +27484,10 @@ static IrInstruction *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstru
2747027484 ir_add_error(ira, instruction->op,
2747127485 buf_sprintf("@atomicRmw on enum only works with .Xchg"));
2747227486 return ira->codegen->invalid_instruction;
27487 } else if (operand_type->id == ZigTypeIdFloat && op > AtomicRmwOp_sub) {
27488 ir_add_error(ira, instruction->op,
27489 buf_sprintf("@atomicRmw with float only works with .Xchg, .Add and .Sub"));
27490 return ira->codegen->invalid_instruction;
2747327491 }
2747427492
2747527493 IrInstruction *operand = instruction->operand->child;
test/compile_errors.zig+20
......@@ -13,6 +13,26 @@ pub fn addCases(cases: *tests.CompileErrorContext) void {
1313 "tmp.zig:3:12: note: destination pointer requires a terminating '0' sentinel",
1414 });
1515
16 cases.add(
17 "cmpxchg with float",
18 \\export fn entry() void {
19 \\ var x: f32 = 0;
20 \\ _ = @cmpxchgWeak(f32, &x, 1, 2, .SeqCst, .SeqCst);
21 \\}
22 ,
23 "tmp.zig:3:22: error: expected integer, enum or pointer type, found 'f32'",
24 );
25
26 cases.add(
27 "atomicrmw with float op not .Xchg, .Add or .Sub",
28 \\export fn entry() void {
29 \\ var x: f32 = 0;
30 \\ _ = @atomicRmw(f32, &x, .And, 2, .SeqCst);
31 \\}
32 ,
33 "tmp.zig:3:29: error: @atomicRmw with float only works with .Xchg, .Add and .Sub",
34 );
35
1636 cases.add("intToPtr with misaligned address",
1737 \\pub fn main() void {
1838 \\ var y = @intToPtr([*]align(4) u8, 5);
test/stage1/behavior/atomics.zig+15
......@@ -144,3 +144,18 @@ fn testAtomicStore() void {
144144 @atomicStore(u32, &x, 12345678, .SeqCst);
145145 expect(@atomicLoad(u32, &x, .SeqCst) == 12345678);
146146}
147
148test "atomicrmw with floats" {
149 testAtomicRmwFloat();
150}
151
152fn testAtomicRmwFloat() void {
153 var x: f32 = 0;
154 expect(x == 0);
155 _ = @atomicRmw(f32, &x, .Xchg, 1, .SeqCst);
156 expect(x == 1);
157 _ = @atomicRmw(f32, &x, .Add, 5, .SeqCst);
158 expect(x == 6);
159 _ = @atomicRmw(f32, &x, .Sub, 2, .SeqCst);
160 expect(x == 4);
161}