authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-23 05:38:11-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-23 22:42:18-04:00
log8f69e977f16d55539d55e8c84852a7c1c6a8cdf3
tree05ea1ff0469413016fa03d9776b72e786dcc82cc
parentfbe8c8938b4efef12a2aa992eec3c947e5f65e70

x86_64: implement 128-bit builtins

* `@clz` * `@ctz` * `@popCount` * `@byteSwap` * `@bitReverse` * various encodings used by std

48 files changed, 545 insertions(+), 541 deletions(-)

lib/compiler_rt/addf3_test.zig-3
......@@ -76,9 +76,6 @@ fn test__subtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) !void {
7676}
7777
7878test "subtf3" {
79 if (builtin.zig_backend == .stage2_x86_64 and
80 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
81
8279 // qNaN - any = qNaN
8380 try test__subtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0);
8481
lib/compiler_rt/divtf3_test.zig-4
......@@ -1,5 +1,4 @@
11const std = @import("std");
2const builtin = @import("builtin");
32const math = std.math;
43const testing = std.testing;
54
......@@ -31,9 +30,6 @@ fn test__divtf3(a: f128, b: f128, expectedHi: u64, expectedLo: u64) !void {
3130}
3231
3332test "divtf3" {
34 if (builtin.zig_backend == .stage2_x86_64 and
35 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
36
3733 // NaN / any = NaN
3834 try test__divtf3(math.nan(f128), 0x1.23456789abcdefp+5, 0x7fff800000000000, 0);
3935 // inf / any(except inf and nan) = inf
lib/compiler_rt/float_from_int_test.zig-22
......@@ -1,5 +1,4 @@
11const std = @import("std");
2const builtin = @import("builtin");
32const testing = std.testing;
43const math = std.math;
54
......@@ -126,9 +125,6 @@ fn test__floatuntisf(a: u128, expected: f32) !void {
126125}
127126
128127test "floattisf" {
129 if (builtin.zig_backend == .stage2_x86_64 and
130 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
131
132128 try test__floattisf(0, 0.0);
133129
134130 try test__floattisf(1, 1.0);
......@@ -175,9 +171,6 @@ test "floattisf" {
175171}
176172
177173test "floatuntisf" {
178 if (builtin.zig_backend == .stage2_x86_64 and
179 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
180
181174 try test__floatuntisf(0, 0.0);
182175
183176 try test__floatuntisf(1, 1.0);
......@@ -374,9 +367,6 @@ fn test__floatuntidf(a: u128, expected: f64) !void {
374367}
375368
376369test "floattidf" {
377 if (builtin.zig_backend == .stage2_x86_64 and
378 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
379
380370 try test__floattidf(0, 0.0);
381371
382372 try test__floattidf(1, 1.0);
......@@ -447,9 +437,6 @@ test "floattidf" {
447437}
448438
449439test "floatuntidf" {
450 if (builtin.zig_backend == .stage2_x86_64 and
451 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
452
453440 try test__floatuntidf(0, 0.0);
454441
455442 try test__floatuntidf(1, 1.0);
......@@ -595,9 +582,6 @@ test "floatditf" {
595582}
596583
597584test "floatunditf" {
598 if (builtin.zig_backend == .stage2_x86_64 and
599 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
600
601585 try test__floatunditf(0xffffffffffffffff, 0x403effffffffffff, 0xfffe000000000000);
602586 try test__floatunditf(0xfffffffffffffffe, 0x403effffffffffff, 0xfffc000000000000);
603587 try test__floatunditf(0x8000000000000000, 0x403e000000000000, 0x0);
......@@ -619,9 +603,6 @@ fn test__floatuntitf(a: u128, expected: f128) !void {
619603}
620604
621605test "floattitf" {
622 if (builtin.zig_backend == .stage2_x86_64 and
623 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
624
625606 try test__floattitf(0, 0.0);
626607
627608 try test__floattitf(1, 1.0);
......@@ -704,9 +685,6 @@ test "floattitf" {
704685}
705686
706687test "floatuntitf" {
707 if (builtin.zig_backend == .stage2_x86_64 and
708 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
709
710688 try test__floatuntitf(0, 0.0);
711689
712690 try test__floatuntitf(1, 1.0);
lib/compiler_rt/fma.zig-5
......@@ -6,10 +6,8 @@
66//! https://git.musl-libc.org/cgit/musl/tree/src/math/fma.c
77
88const std = @import("std");
9const builtin = @import("builtin");
109const math = std.math;
1110const expect = std.testing.expect;
12const arch = builtin.cpu.arch;
1311const common = @import("common.zig");
1412
1513pub const panic = common.panic;
......@@ -343,9 +341,6 @@ test "64" {
343341}
344342
345343test "128" {
346 if (builtin.zig_backend == .stage2_x86_64 and
347 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
348
349344 const epsilon = 0.000001;
350345
351346 try expect(math.approxEqAbs(f128, fmaq(0.0, 5.0, 9.124), 9.124, epsilon));
lib/compiler_rt/fmodx_test.zig+1-1
......@@ -24,7 +24,7 @@ fn test_fmodx_infs() !void {
2424
2525test "fmodx" {
2626 if (builtin.zig_backend == .stage2_x86_64 and
27 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
27 !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .lzcnt)) return error.SkipZigTest;
2828
2929 try test_fmodx(6.4, 4.0, 2.4);
3030 try test_fmodx(6.4, -4.0, 2.4);
lib/compiler_rt/mulf3_test.zig-4
......@@ -3,7 +3,6 @@
33// https://github.com/llvm/llvm-project/blob/2ffb1b0413efa9a24eb3c49e710e36f92e2cb50b/compiler-rt/test/builtins/Unit/multf3_test.c
44
55const std = @import("std");
6const builtin = @import("builtin");
76const math = std.math;
87const qnan128: f128 = @bitCast(@as(u128, 0x7fff800000000000) << 64);
98const inf128: f128 = @bitCast(@as(u128, 0x7fff000000000000) << 64);
......@@ -49,9 +48,6 @@ fn makeNaN128(rand: u64) f128 {
4948 return @bitCast(int_result);
5049}
5150test "multf3" {
52 if (builtin.zig_backend == .stage2_x86_64 and
53 !comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .bmi, .lzcnt })) return error.SkipZigTest;
54
5551 // qNaN * any = qNaN
5652 try test__multf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0);
5753
lib/compiler_rt/udivmodei4.zig+2-4
......@@ -129,10 +129,8 @@ pub fn __umodei4(r_p: [*]u32, u_p: [*]const u32, v_p: [*]const u32, bits: usize)
129129}
130130
131131test "__udivei4/__umodei4" {
132 switch (builtin.zig_backend) {
133 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
134 else => {},
135 }
132 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
133 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
136134
137135 const RndGen = std.rand.DefaultPrng;
138136 var rnd = RndGen.init(42);
lib/std/Build/Cache.zig-8
......@@ -1007,8 +1007,6 @@ test "cache file and then recall it" {
10071007 return error.SkipZigTest;
10081008 }
10091009
1010 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1011
10121010 var tmp = testing.tmpDir(.{});
10131011 defer tmp.cleanup();
10141012
......@@ -1075,8 +1073,6 @@ test "check that changing a file makes cache fail" {
10751073 return error.SkipZigTest;
10761074 }
10771075
1078 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1079
10801076 var tmp = testing.tmpDir(.{});
10811077 defer tmp.cleanup();
10821078
......@@ -1151,8 +1147,6 @@ test "no file inputs" {
11511147 return error.SkipZigTest;
11521148 }
11531149
1154 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1155
11561150 var tmp = testing.tmpDir(.{});
11571151 defer tmp.cleanup();
11581152
......@@ -1201,8 +1195,6 @@ test "Manifest with files added after initial hash work" {
12011195 return error.SkipZigTest;
12021196 }
12031197
1204 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1205
12061198 var tmp = testing.tmpDir(.{});
12071199 defer tmp.cleanup();
12081200
lib/std/Thread/Condition.zig+2-2
......@@ -324,6 +324,8 @@ test "Condition - wait and signal" {
324324 return error.SkipZigTest;
325325 }
326326
327 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
328
327329 const num_threads = 4;
328330
329331 const MultiWait = struct {
......@@ -369,8 +371,6 @@ test "Condition - signal" {
369371 return error.SkipZigTest;
370372 }
371373
372 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
373
374374 const num_threads = 4;
375375
376376 const SignalTest = struct {
lib/std/Thread/Semaphore.zig+2
......@@ -39,6 +39,8 @@ test "Thread.Semaphore" {
3939 return error.SkipZigTest;
4040 }
4141
42 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
43
4244 const TestContext = struct {
4345 sem: *Semaphore,
4446 n: *i32,
lib/std/base64.zig-2
......@@ -363,8 +363,6 @@ test "base64" {
363363}
364364
365365test "base64 padding dest overflow" {
366 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
367
368366 const input = "foo";
369367
370368 var expect: [128]u8 = undefined;
lib/std/compress/deflate/huffman_code.zig-2
......@@ -360,8 +360,6 @@ fn byFreq(context: void, a: LiteralNode, b: LiteralNode) bool {
360360}
361361
362362test "generate a Huffman code from an array of frequencies" {
363 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
364
365363 var freqs: [19]u16 = [_]u16{
366364 8, // 0
367365 1, // 1
lib/std/compress/gzip.zig-2
......@@ -174,8 +174,6 @@ fn testReader(data: []const u8, comptime expected: []const u8) !void {
174174// https://tools.ietf.org/rfc/rfc1952.txt length=25037 bytes
175175// SHA256=164ef0897b4cbec63abf1b57f069f3599bd0fb7c72c2a4dee21bd7e03ec9af67
176176test "compressed data" {
177 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
178
179177 try testReader(
180178 @embedFile("testdata/rfc1952.txt.gz"),
181179 @embedFile("testdata/rfc1952.txt"),
lib/std/compress/zlib.zig-2
......@@ -199,8 +199,6 @@ fn testDecompress(data: []const u8, expected: []const u8) !void {
199199// https://tools.ietf.org/rfc/rfc1951.txt length=36944 bytes
200200// SHA256=5ebf4b5b7fe1c3a0c0ab9aa3ac8c0f3853a7dc484905e76e03b0b0f301350009
201201test "compressed data" {
202 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
203
204202 const rfc1951_txt = @embedFile("testdata/rfc1951.txt");
205203
206204 // Compressed with compression level = 0
lib/std/crypto.zig-2
......@@ -314,8 +314,6 @@ test "CSPRNG" {
314314}
315315
316316test "issue #4532: no index out of bounds" {
317 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
318
319317 const types = [_]type{
320318 hash.Md5,
321319 hash.Sha1,
lib/std/crypto/25519/x25519.zig-4
......@@ -137,8 +137,6 @@ test "x25519 rfc7748 one iteration" {
137137}
138138
139139test "x25519 rfc7748 1,000 iterations" {
140 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
141
142140 // These iteration tests are slow so we always skip them. Results have been verified.
143141 if (true) {
144142 return error.SkipZigTest;
......@@ -161,8 +159,6 @@ test "x25519 rfc7748 1,000 iterations" {
161159}
162160
163161test "x25519 rfc7748 1,000,000 iterations" {
164 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
165
166162 if (true) {
167163 return error.SkipZigTest;
168164 }
lib/std/crypto/aegis.zig-15
......@@ -17,7 +17,6 @@
1717//! https://datatracker.ietf.org/doc/draft-irtf-cfrg-aegis-aead/
1818
1919const std = @import("std");
20const builtin = @import("builtin");
2120const crypto = std.crypto;
2221const mem = std.mem;
2322const assert = std.debug.assert;
......@@ -514,8 +513,6 @@ const htest = @import("test.zig");
514513const testing = std.testing;
515514
516515test "Aegis128L test vector 1" {
517 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
518
519516 const key: [Aegis128L.key_length]u8 = [_]u8{ 0x10, 0x01 } ++ [_]u8{0x00} ** 14;
520517 const nonce: [Aegis128L.nonce_length]u8 = [_]u8{ 0x10, 0x00, 0x02 } ++ [_]u8{0x00} ** 13;
521518 const ad = [8]u8{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 };
......@@ -539,8 +536,6 @@ test "Aegis128L test vector 1" {
539536}
540537
541538test "Aegis128L test vector 2" {
542 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
543
544539 const key: [Aegis128L.key_length]u8 = [_]u8{0x00} ** 16;
545540 const nonce: [Aegis128L.nonce_length]u8 = [_]u8{0x00} ** 16;
546541 const ad = [_]u8{};
......@@ -558,8 +553,6 @@ test "Aegis128L test vector 2" {
558553}
559554
560555test "Aegis128L test vector 3" {
561 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
562
563556 const key: [Aegis128L.key_length]u8 = [_]u8{0x00} ** 16;
564557 const nonce: [Aegis128L.nonce_length]u8 = [_]u8{0x00} ** 16;
565558 const ad = [_]u8{};
......@@ -576,8 +569,6 @@ test "Aegis128L test vector 3" {
576569}
577570
578571test "Aegis256 test vector 1" {
579 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
580
581572 const key: [Aegis256.key_length]u8 = [_]u8{ 0x10, 0x01 } ++ [_]u8{0x00} ** 30;
582573 const nonce: [Aegis256.nonce_length]u8 = [_]u8{ 0x10, 0x00, 0x02 } ++ [_]u8{0x00} ** 29;
583574 const ad = [8]u8{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 };
......@@ -601,8 +592,6 @@ test "Aegis256 test vector 1" {
601592}
602593
603594test "Aegis256 test vector 2" {
604 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
605
606595 const key: [Aegis256.key_length]u8 = [_]u8{0x00} ** 32;
607596 const nonce: [Aegis256.nonce_length]u8 = [_]u8{0x00} ** 32;
608597 const ad = [_]u8{};
......@@ -620,8 +609,6 @@ test "Aegis256 test vector 2" {
620609}
621610
622611test "Aegis256 test vector 3" {
623 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
624
625612 const key: [Aegis256.key_length]u8 = [_]u8{0x00} ** 32;
626613 const nonce: [Aegis256.nonce_length]u8 = [_]u8{0x00} ** 32;
627614 const ad = [_]u8{};
......@@ -638,8 +625,6 @@ test "Aegis256 test vector 3" {
638625}
639626
640627test "Aegis MAC" {
641 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
642
643628 const key = [_]u8{0x00} ** Aegis128LMac.key_length;
644629 var msg: [64]u8 = undefined;
645630 for (&msg, 0..) |*m, i| {
lib/std/crypto/aes.zig+1-9
......@@ -6,7 +6,7 @@ const has_aesni = std.Target.x86.featureSetHas(builtin.cpu.features, .aes);
66const has_avx = std.Target.x86.featureSetHas(builtin.cpu.features, .avx);
77const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes);
88// C backend doesn't currently support passing vectors to inline asm.
9const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_aesni and has_avx) impl: {
9const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and builtin.zig_backend != .stage2_x86_64 and has_aesni and has_avx) impl: {
1010 break :impl @import("aes/aesni.zig");
1111} else if (builtin.cpu.arch == .aarch64 and builtin.zig_backend != .stage2_c and has_armaes)
1212impl: {
......@@ -55,8 +55,6 @@ test "ctr" {
5555}
5656
5757test "encrypt" {
58 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
59
6058 // Appendix B
6159 {
6260 const key = [_]u8{ 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
......@@ -86,8 +84,6 @@ test "encrypt" {
8684}
8785
8886test "decrypt" {
89 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
90
9187 // Appendix B
9288 {
9389 const key = [_]u8{ 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
......@@ -117,8 +113,6 @@ test "decrypt" {
117113}
118114
119115test "expand 128-bit key" {
120 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
121
122116 const key = [_]u8{ 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
123117 const exp_enc = [_]*const [32:0]u8{
124118 "2b7e151628aed2a6abf7158809cf4f3c", "a0fafe1788542cb123a339392a6c7605", "f2c295f27a96b9435935807a7359f67f", "3d80477d4716fe3e1e237e446d7a883b", "ef44a541a8525b7fb671253bdb0bad00", "d4d1c6f87c839d87caf2b8bc11f915bc", "6d88a37a110b3efddbf98641ca0093fd", "4e54f70e5f5fc9f384a64fb24ea6dc4f", "ead27321b58dbad2312bf5607f8d292f", "ac7766f319fadc2128d12941575c006e", "d014f9a8c9ee2589e13f0cc8b6630ca6",
......@@ -141,8 +135,6 @@ test "expand 128-bit key" {
141135}
142136
143137test "expand 256-bit key" {
144 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
145
146138 const key = [_]u8{
147139 0x60, 0x3d, 0xeb, 0x10,
148140 0x15, 0xca, 0x71, 0xbe,
lib/std/crypto/aes_ocb.zig+8-16
......@@ -261,10 +261,8 @@ inline fn xorWith(x: *Block, y: Block) void {
261261const hexToBytes = std.fmt.hexToBytes;
262262
263263test "AesOcb test vector 1" {
264 switch (builtin.zig_backend) {
265 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
266 else => {},
267 }
264 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
265 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
268266
269267 var k: [Aes128Ocb.key_length]u8 = undefined;
270268 var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
......@@ -283,10 +281,8 @@ test "AesOcb test vector 1" {
283281}
284282
285283test "AesOcb test vector 2" {
286 switch (builtin.zig_backend) {
287 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
288 else => {},
289 }
284 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
285 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
290286
291287 var k: [Aes128Ocb.key_length]u8 = undefined;
292288 var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
......@@ -307,10 +303,8 @@ test "AesOcb test vector 2" {
307303}
308304
309305test "AesOcb test vector 3" {
310 switch (builtin.zig_backend) {
311 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
312 else => {},
313 }
306 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
307 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
314308
315309 var k: [Aes128Ocb.key_length]u8 = undefined;
316310 var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
......@@ -334,10 +328,8 @@ test "AesOcb test vector 3" {
334328}
335329
336330test "AesOcb test vector 4" {
337 switch (builtin.zig_backend) {
338 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
339 else => {},
340 }
331 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
332 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
341333
342334 var k: [Aes128Ocb.key_length]u8 = undefined;
343335 var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
lib/std/crypto/ghash_polyval.zig-2
......@@ -476,8 +476,6 @@ test "ghash2" {
476476}
477477
478478test "polyval" {
479 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
480
481479 const key = [_]u8{0x42} ** 16;
482480 const m = [_]u8{0x69} ** 256;
483481
lib/std/crypto/kyber_d00.zig-2
......@@ -1667,8 +1667,6 @@ test "Test happy flow" {
16671667const sha2 = crypto.hash.sha2;
16681668
16691669test "NIST KAT test" {
1670 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1671
16721670 inline for (.{
16731671 .{ Kyber512, "e9c2bd37133fcb40772f81559f14b1f58dccd1c816701be9ba6214d43baf4547" },
16741672 .{ Kyber1024, "89248f2f33f7f4f7051729111f3049c409a933ec904aedadf035f30fa5646cd5" },
lib/std/fs.zig+6-6
......@@ -3244,15 +3244,15 @@ fn copy_file(fd_in: os.fd_t, fd_out: os.fd_t, maybe_size: ?u64) CopyFileRawError
32443244}
32453245
32463246test {
3247 if (builtin.zig_backend != .stage2_x86_64) {
3248 if (builtin.os.tag != .wasi) {
3249 _ = &makeDirAbsolute;
3250 _ = &makeDirAbsoluteZ;
3251 _ = &copyFileAbsolute;
3247 if (builtin.os.tag != .wasi) {
3248 _ = &makeDirAbsolute;
3249 _ = &makeDirAbsoluteZ;
3250 _ = &copyFileAbsolute;
3251 if (builtin.zig_backend != .stage2_x86_64) {
32523252 _ = &updateFileAbsolute;
32533253 }
3254 _ = &Dir.copyFile;
32553254 }
3255 _ = &Dir.copyFile;
32563256 _ = @import("fs/test.zig");
32573257 _ = @import("fs/path.zig");
32583258 _ = @import("fs/file.zig");
lib/std/fs/test.zig-98
......@@ -124,8 +124,6 @@ fn testWithAllSupportedPathTypes(test_func: anytype) !void {
124124}
125125
126126test "Dir.readLink" {
127 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
128
129127 try testWithAllSupportedPathTypes(struct {
130128 fn impl(ctx: *TestContext) !void {
131129 // Create some targets
......@@ -163,8 +161,6 @@ fn testReadLink(dir: Dir, target_path: []const u8, symlink_path: []const u8) !vo
163161}
164162
165163test "relative symlink to parent directory" {
166 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
167
168164 var tmp = tmpDir(.{});
169165 defer tmp.cleanup();
170166
......@@ -182,8 +178,6 @@ test "relative symlink to parent directory" {
182178}
183179
184180test "openDir" {
185 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
186
187181 try testWithAllSupportedPathTypes(struct {
188182 fn impl(ctx: *TestContext) !void {
189183 const allocator = ctx.arena.allocator();
......@@ -202,8 +196,6 @@ test "openDir" {
202196test "accessAbsolute" {
203197 if (builtin.os.tag == .wasi) return error.SkipZigTest;
204198
205 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
206
207199 var tmp = tmpDir(.{});
208200 defer tmp.cleanup();
209201
......@@ -222,8 +214,6 @@ test "accessAbsolute" {
222214test "openDirAbsolute" {
223215 if (builtin.os.tag == .wasi) return error.SkipZigTest;
224216
225 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
226
227217 var tmp = tmpDir(.{});
228218 defer tmp.cleanup();
229219
......@@ -262,8 +252,6 @@ test "openDir non-cwd parent .." {
262252 else => {},
263253 }
264254
265 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
266
267255 var tmp = tmpDir(.{});
268256 defer tmp.cleanup();
269257
......@@ -285,8 +273,6 @@ test "openDir non-cwd parent .." {
285273test "readLinkAbsolute" {
286274 if (builtin.os.tag == .wasi) return error.SkipZigTest;
287275
288 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
289
290276 var tmp = tmpDir(.{});
291277 defer tmp.cleanup();
292278
......@@ -337,8 +323,6 @@ fn testReadLinkAbsolute(target_path: []const u8, symlink_path: []const u8) !void
337323}
338324
339325test "Dir.Iterator" {
340 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
341
342326 var tmp_dir = tmpIterableDir(.{});
343327 defer tmp_dir.cleanup();
344328
......@@ -369,8 +353,6 @@ test "Dir.Iterator" {
369353}
370354
371355test "Dir.Iterator many entries" {
372 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
373
374356 var tmp_dir = tmpIterableDir(.{});
375357 defer tmp_dir.cleanup();
376358
......@@ -406,8 +388,6 @@ test "Dir.Iterator many entries" {
406388}
407389
408390test "Dir.Iterator twice" {
409 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
410
411391 var tmp_dir = tmpIterableDir(.{});
412392 defer tmp_dir.cleanup();
413393
......@@ -441,8 +421,6 @@ test "Dir.Iterator twice" {
441421}
442422
443423test "Dir.Iterator reset" {
444 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
445
446424 var tmp_dir = tmpIterableDir(.{});
447425 defer tmp_dir.cleanup();
448426
......@@ -479,8 +457,6 @@ test "Dir.Iterator reset" {
479457}
480458
481459test "Dir.Iterator but dir is deleted during iteration" {
482 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
483
484460 var tmp = std.testing.tmpDir(.{});
485461 defer tmp.cleanup();
486462
......@@ -523,8 +499,6 @@ fn contains(entries: *const std.ArrayList(IterableDir.Entry), el: IterableDir.En
523499test "Dir.realpath smoke test" {
524500 if (!comptime std.os.isGetFdPathSupportedOnTarget(builtin.os)) return error.SkipZigTest;
525501
526 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
527
528502 try testWithAllSupportedPathTypes(struct {
529503 fn impl(ctx: *TestContext) !void {
530504 const allocator = ctx.arena.allocator();
......@@ -575,8 +549,6 @@ test "Dir.realpath smoke test" {
575549}
576550
577551test "readAllAlloc" {
578 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
579
580552 var tmp_dir = tmpDir(.{});
581553 defer tmp_dir.cleanup();
582554
......@@ -613,8 +585,6 @@ test "Dir.statFile" {
613585 // TODO: Re-enable once https://github.com/ziglang/zig/issues/17034 is solved
614586 if (builtin.os.tag == .linux and builtin.link_libc and builtin.abi == .gnu) return error.SkipZigTest;
615587
616 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
617
618588 try testWithAllSupportedPathTypes(struct {
619589 fn impl(ctx: *TestContext) !void {
620590 const test_file_name = try ctx.transformPath("test_file");
......@@ -630,8 +600,6 @@ test "Dir.statFile" {
630600}
631601
632602test "directory operations on files" {
633 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
634
635603 try testWithAllSupportedPathTypes(struct {
636604 fn impl(ctx: *TestContext) !void {
637605 const test_file_name = try ctx.transformPath("test_file");
......@@ -661,8 +629,6 @@ test "file operations on directories" {
661629 // TODO: fix this test on FreeBSD. https://github.com/ziglang/zig/issues/1759
662630 if (builtin.os.tag == .freebsd) return error.SkipZigTest;
663631
664 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
665
666632 try testWithAllSupportedPathTypes(struct {
667633 fn impl(ctx: *TestContext) !void {
668634 const test_dir_name = try ctx.transformPath("test_dir");
......@@ -698,8 +664,6 @@ test "file operations on directories" {
698664}
699665
700666test "makeOpenPath parent dirs do not exist" {
701 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
702
703667 var tmp_dir = tmpDir(.{});
704668 defer tmp_dir.cleanup();
705669
......@@ -712,8 +676,6 @@ test "makeOpenPath parent dirs do not exist" {
712676}
713677
714678test "deleteDir" {
715 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
716
717679 try testWithAllSupportedPathTypes(struct {
718680 fn impl(ctx: *TestContext) !void {
719681 const test_dir_path = try ctx.transformPath("test_dir");
......@@ -735,8 +697,6 @@ test "deleteDir" {
735697}
736698
737699test "Dir.rename files" {
738 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
739
740700 try testWithAllSupportedPathTypes(struct {
741701 fn impl(ctx: *TestContext) !void {
742702 // Rename on Windows can hit intermittent AccessDenied errors
......@@ -779,8 +739,6 @@ test "Dir.rename files" {
779739}
780740
781741test "Dir.rename directories" {
782 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
783
784742 try testWithAllSupportedPathTypes(struct {
785743 fn impl(ctx: *TestContext) !void {
786744 // Rename on Windows can hit intermittent AccessDenied errors
......@@ -822,8 +780,6 @@ test "Dir.rename directory onto empty dir" {
822780 // TODO: Fix on Windows, see https://github.com/ziglang/zig/issues/6364
823781 if (builtin.os.tag == .windows) return error.SkipZigTest;
824782
825 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
826
827783 try testWithAllSupportedPathTypes(struct {
828784 fn impl(ctx: *TestContext) !void {
829785 const test_dir_path = try ctx.transformPath("test_dir");
......@@ -845,8 +801,6 @@ test "Dir.rename directory onto non-empty dir" {
845801 // TODO: Fix on Windows, see https://github.com/ziglang/zig/issues/6364
846802 if (builtin.os.tag == .windows) return error.SkipZigTest;
847803
848 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
849
850804 try testWithAllSupportedPathTypes(struct {
851805 fn impl(ctx: *TestContext) !void {
852806 const test_dir_path = try ctx.transformPath("test_dir");
......@@ -873,8 +827,6 @@ test "Dir.rename file <-> dir" {
873827 // TODO: Fix on Windows, see https://github.com/ziglang/zig/issues/6364
874828 if (builtin.os.tag == .windows) return error.SkipZigTest;
875829
876 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
877
878830 try testWithAllSupportedPathTypes(struct {
879831 fn impl(ctx: *TestContext) !void {
880832 const test_file_path = try ctx.transformPath("test_file");
......@@ -890,8 +842,6 @@ test "Dir.rename file <-> dir" {
890842}
891843
892844test "rename" {
893 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
894
895845 var tmp_dir1 = tmpDir(.{});
896846 defer tmp_dir1.cleanup();
897847
......@@ -914,8 +864,6 @@ test "rename" {
914864test "renameAbsolute" {
915865 if (builtin.os.tag == .wasi) return error.SkipZigTest;
916866
917 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
918
919867 var tmp_dir = tmpDir(.{});
920868 defer tmp_dir.cleanup();
921869
......@@ -974,8 +922,6 @@ test "openSelfExe" {
974922}
975923
976924test "makePath, put some files in it, deleteTree" {
977 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
978
979925 try testWithAllSupportedPathTypes(struct {
980926 fn impl(ctx: *TestContext) !void {
981927 const allocator = ctx.arena.allocator();
......@@ -992,8 +938,6 @@ test "makePath, put some files in it, deleteTree" {
992938}
993939
994940test "makePath, put some files in it, deleteTreeMinStackSize" {
995 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
996
997941 try testWithAllSupportedPathTypes(struct {
998942 fn impl(ctx: *TestContext) !void {
999943 const allocator = ctx.arena.allocator();
......@@ -1012,8 +956,6 @@ test "makePath, put some files in it, deleteTreeMinStackSize" {
1012956test "makePath in a directory that no longer exists" {
1013957 if (builtin.os.tag == .windows) return error.SkipZigTest; // Windows returns FileBusy if attempting to remove an open dir
1014958
1015 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1016
1017959 var tmp = tmpDir(.{});
1018960 defer tmp.cleanup();
1019961 try tmp.parent_dir.deleteTree(&tmp.sub_path);
......@@ -1045,8 +987,6 @@ fn testFilenameLimits(iterable_dir: IterableDir, maxed_filename: []const u8) !vo
1045987}
1046988
1047989test "max file name component lengths" {
1048 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1049
1050990 var tmp = tmpIterableDir(.{});
1051991 defer tmp.cleanup();
1052992
......@@ -1068,8 +1008,6 @@ test "max file name component lengths" {
10681008}
10691009
10701010test "writev, readv" {
1071 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1072
10731011 var tmp = tmpDir(.{});
10741012 defer tmp.cleanup();
10751013
......@@ -1112,8 +1050,6 @@ test "writev, readv" {
11121050}
11131051
11141052test "pwritev, preadv" {
1115 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1116
11171053 var tmp = tmpDir(.{});
11181054 defer tmp.cleanup();
11191055
......@@ -1155,8 +1091,6 @@ test "pwritev, preadv" {
11551091}
11561092
11571093test "access file" {
1158 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1159
11601094 try testWithAllSupportedPathTypes(struct {
11611095 fn impl(ctx: *TestContext) !void {
11621096 const dir_path = try ctx.transformPath("os_test_tmp");
......@@ -1173,8 +1107,6 @@ test "access file" {
11731107}
11741108
11751109test "sendfile" {
1176 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1177
11781110 var tmp = tmpDir(.{});
11791111 defer tmp.cleanup();
11801112
......@@ -1240,8 +1172,6 @@ test "sendfile" {
12401172}
12411173
12421174test "copyRangeAll" {
1243 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1244
12451175 var tmp = tmpDir(.{});
12461176 defer tmp.cleanup();
12471177
......@@ -1268,8 +1198,6 @@ test "copyRangeAll" {
12681198}
12691199
12701200test "copyFile" {
1271 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1272
12731201 try testWithAllSupportedPathTypes(struct {
12741202 fn impl(ctx: *TestContext) !void {
12751203 const data = "u6wj+JmdF3qHsFPE BUlH2g4gJCmEz0PP";
......@@ -1300,8 +1228,6 @@ fn expectFileContents(dir: Dir, file_path: []const u8, data: []const u8) !void {
13001228}
13011229
13021230test "AtomicFile" {
1303 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1304
13051231 try testWithAllSupportedPathTypes(struct {
13061232 fn impl(ctx: *TestContext) !void {
13071233 const allocator = ctx.arena.allocator();
......@@ -1328,8 +1254,6 @@ test "AtomicFile" {
13281254test "open file with exclusive nonblocking lock twice" {
13291255 if (builtin.os.tag == .wasi) return error.SkipZigTest;
13301256
1331 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1332
13331257 try testWithAllSupportedPathTypes(struct {
13341258 fn impl(ctx: *TestContext) !void {
13351259 const filename = try ctx.transformPath("file_nonblocking_lock_test.txt");
......@@ -1346,8 +1270,6 @@ test "open file with exclusive nonblocking lock twice" {
13461270test "open file with shared and exclusive nonblocking lock" {
13471271 if (builtin.os.tag == .wasi) return error.SkipZigTest;
13481272
1349 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1350
13511273 try testWithAllSupportedPathTypes(struct {
13521274 fn impl(ctx: *TestContext) !void {
13531275 const filename = try ctx.transformPath("file_nonblocking_lock_test.txt");
......@@ -1364,8 +1286,6 @@ test "open file with shared and exclusive nonblocking lock" {
13641286test "open file with exclusive and shared nonblocking lock" {
13651287 if (builtin.os.tag == .wasi) return error.SkipZigTest;
13661288
1367 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1368
13691289 try testWithAllSupportedPathTypes(struct {
13701290 fn impl(ctx: *TestContext) !void {
13711291 const filename = try ctx.transformPath("file_nonblocking_lock_test.txt");
......@@ -1380,8 +1300,6 @@ test "open file with exclusive and shared nonblocking lock" {
13801300}
13811301
13821302test "open file with exclusive lock twice, make sure second lock waits" {
1383 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1384
13851303 if (builtin.single_threaded) return error.SkipZigTest;
13861304
13871305 if (std.io.is_async) {
......@@ -1432,8 +1350,6 @@ test "open file with exclusive lock twice, make sure second lock waits" {
14321350test "open file with exclusive nonblocking lock twice (absolute paths)" {
14331351 if (builtin.os.tag == .wasi) return error.SkipZigTest;
14341352
1435 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1436
14371353 var random_bytes: [12]u8 = undefined;
14381354 std.crypto.random.bytes(&random_bytes);
14391355
......@@ -1468,8 +1384,6 @@ test "open file with exclusive nonblocking lock twice (absolute paths)" {
14681384test "walker" {
14691385 if (builtin.os.tag == .wasi and builtin.link_libc) return error.SkipZigTest;
14701386
1471 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1472
14731387 var tmp = tmpIterableDir(.{});
14741388 defer tmp.cleanup();
14751389
......@@ -1523,8 +1437,6 @@ test "walker" {
15231437test "walker without fully iterating" {
15241438 if (builtin.os.tag == .wasi and builtin.link_libc) return error.SkipZigTest;
15251439
1526 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1527
15281440 var tmp = tmpIterableDir(.{});
15291441 defer tmp.cleanup();
15301442
......@@ -1637,8 +1549,6 @@ test "chmod" {
16371549 if (builtin.os.tag == .windows or builtin.os.tag == .wasi)
16381550 return error.SkipZigTest;
16391551
1640 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1641
16421552 var tmp = tmpDir(.{});
16431553 defer tmp.cleanup();
16441554
......@@ -1661,8 +1571,6 @@ test "chown" {
16611571 if (builtin.os.tag == .windows or builtin.os.tag == .wasi)
16621572 return error.SkipZigTest;
16631573
1664 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1665
16661574 var tmp = tmpDir(.{});
16671575 defer tmp.cleanup();
16681576
......@@ -1678,8 +1586,6 @@ test "chown" {
16781586}
16791587
16801588test "File.Metadata" {
1681 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1682
16831589 var tmp = tmpDir(.{});
16841590 defer tmp.cleanup();
16851591
......@@ -1763,8 +1669,6 @@ test "delete a read-only file on windows" {
17631669 if (builtin.os.tag != .windows)
17641670 return error.SkipZigTest;
17651671
1766 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1767
17681672 var tmp = testing.tmpDir(.{});
17691673 defer tmp.cleanup();
17701674
......@@ -1795,8 +1699,6 @@ test "delete a read-only file on windows" {
17951699test "delete a setAsCwd directory on Windows" {
17961700 if (builtin.os.tag != .windows) return error.SkipZigTest;
17971701
1798 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1799
18001702 var tmp = tmpDir(.{});
18011703 // Set tmp dir as current working directory.
18021704 try tmp.dir.setAsCwd();
lib/std/hash/xxhash.zig-12
......@@ -862,8 +862,6 @@ test "xxhash3 iterative api" {
862862}
863863
864864test "xxhash64" {
865 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
866
867865 const H = XxHash64;
868866 try testExpect(H, 0, "", 0xef46db3751d8e999);
869867 try testExpect(H, 0, "a", 0xd24ec4f1a98c6e5b);
......@@ -875,8 +873,6 @@ test "xxhash64" {
875873}
876874
877875test "xxhash64 smhasher" {
878 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
879
880876 const Test = struct {
881877 fn do() !void {
882878 try expectEqual(verify.smhasher(XxHash64.hash), 0x024B7CF4);
......@@ -888,8 +884,6 @@ test "xxhash64 smhasher" {
888884}
889885
890886test "xxhash64 iterative api" {
891 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
892
893887 const Test = struct {
894888 fn do() !void {
895889 try verify.iterativeApi(XxHash64);
......@@ -901,8 +895,6 @@ test "xxhash64 iterative api" {
901895}
902896
903897test "xxhash32" {
904 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
905
906898 const H = XxHash32;
907899
908900 try testExpect(H, 0, "", 0x02cc5d05);
......@@ -915,8 +907,6 @@ test "xxhash32" {
915907}
916908
917909test "xxhash32 smhasher" {
918 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
919
920910 const Test = struct {
921911 fn do() !void {
922912 try expectEqual(verify.smhasher(XxHash32.hash), 0xBA88B743);
......@@ -928,8 +918,6 @@ test "xxhash32 smhasher" {
928918}
929919
930920test "xxhash32 iterative api" {
931 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
932
933921 const Test = struct {
934922 fn do() !void {
935923 try verify.iterativeApi(XxHash32);
lib/std/hash_map.zig-2
......@@ -1873,8 +1873,6 @@ test "std.hash_map multiple removes on same metadata" {
18731873}
18741874
18751875test "std.hash_map put and remove loop in random order" {
1876 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1877
18781876 var map = AutoHashMap(u32, u32).init(std.testing.allocator);
18791877 defer map.deinit();
18801878
lib/std/heap/general_purpose_allocator.zig-4
......@@ -1042,8 +1042,6 @@ const TraceKind = enum {
10421042const test_config = Config{};
10431043
10441044test "small allocations - free in same order" {
1045 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1046
10471045 var gpa = GeneralPurposeAllocator(test_config){};
10481046 defer std.testing.expect(gpa.deinit() == .ok) catch @panic("leak");
10491047 const allocator = gpa.allocator();
......@@ -1063,8 +1061,6 @@ test "small allocations - free in same order" {
10631061}
10641062
10651063test "small allocations - free in reverse order" {
1066 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
1067
10681064 var gpa = GeneralPurposeAllocator(test_config){};
10691065 defer std.testing.expect(gpa.deinit() == .ok) catch @panic("leak");
10701066 const allocator = gpa.allocator();
lib/std/http/Client.zig-2
......@@ -491,8 +491,6 @@ pub const Response = struct {
491491 }
492492
493493 test parseInt3 {
494 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
495
496494 const expectEqual = testing.expectEqual;
497495 try expectEqual(@as(u10, 0), parseInt3("000".*));
498496 try expectEqual(@as(u10, 418), parseInt3("418".*));
lib/std/io/multi_writer.zig-1
......@@ -36,7 +36,6 @@ pub fn multiWriter(streams: anytype) MultiWriter(@TypeOf(streams)) {
3636const testing = std.testing;
3737
3838test "MultiWriter" {
39 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
4039 var tmp = testing.tmpDir(.{});
4140 defer tmp.cleanup();
4241 var f = try tmp.dir.createFile("t.txt", .{});
lib/std/io/test.zig-6
......@@ -15,8 +15,6 @@ const native_endian = builtin.target.cpu.arch.endian();
1515const tmpDir = std.testing.tmpDir;
1616
1717test "write a file, read it, then delete it" {
18 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
19
2018 var tmp = tmpDir(.{});
2119 defer tmp.cleanup();
2220
......@@ -110,8 +108,6 @@ test "BitStreams with File Stream" {
110108}
111109
112110test "File seek ops" {
113 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
114
115111 var tmp = tmpDir(.{});
116112 defer tmp.cleanup();
117113
......@@ -139,8 +135,6 @@ test "File seek ops" {
139135}
140136
141137test "setEndPos" {
142 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
143
144138 var tmp = tmpDir(.{});
145139 defer tmp.cleanup();
146140
lib/std/math/big/int_test.zig-2
......@@ -71,8 +71,6 @@ test "big.int set negative minimum" {
7171}
7272
7373test "big.int set double-width maximum then zero" {
74 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
75
7674 var a = try Managed.initSet(testing.allocator, maxInt(DoubleLimb));
7775 defer a.deinit();
7876 try a.set(@as(DoubleLimb, 0));
lib/std/math/ilogb.zig-6
......@@ -125,8 +125,6 @@ test "80" {
125125}
126126
127127test "128" {
128 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
129
130128 try expect(ilogbX(f128, 0.0) == fp_ilogb0);
131129 try expect(ilogbX(f128, 0.5) == -1);
132130 try expect(ilogbX(f128, 0.8923) == -1);
......@@ -162,8 +160,6 @@ test "64 special" {
162160}
163161
164162test "80 special" {
165 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
166
167163 try expect(ilogbX(f80, math.inf(f80)) == maxInt(i32));
168164 try expect(ilogbX(f80, -math.inf(f80)) == maxInt(i32));
169165 try expect(ilogbX(f80, 0.0) == minInt(i32));
......@@ -171,8 +167,6 @@ test "80 special" {
171167}
172168
173169test "128 special" {
174 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
175
176170 try expect(ilogbX(f128, math.inf(f128)) == maxInt(i32));
177171 try expect(ilogbX(f128, -math.inf(f128)) == maxInt(i32));
178172 try expect(ilogbX(f128, 0.0) == minInt(i32));
lib/std/math/scalbn.zig-2
......@@ -7,8 +7,6 @@ const expect = std.testing.expect;
77pub const scalbn = @import("ldexp.zig").ldexp;
88
99test "math.scalbn" {
10 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
11
1210 // Verify we are using base 2.
1311 try expect(scalbn(@as(f16, 1.5), 4) == 24.0);
1412 try expect(scalbn(@as(f32, 1.5), 4) == 24.0);
lib/std/mem.zig+2-4
......@@ -2060,10 +2060,7 @@ pub fn writeVarPackedInt(bytes: []u8, bit_offset: usize, bit_count: usize, value
20602060}
20612061
20622062test "writeIntBig and writeIntLittle" {
2063 switch (builtin.zig_backend) {
2064 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
2065 else => {},
2066 }
2063 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
20672064
20682065 var buf0: [0]u8 = undefined;
20692066 var buf1: [1]u8 = undefined;
......@@ -4664,6 +4661,7 @@ test "read/write(Var)PackedInt" {
46644661 .stage2_c, .stage2_x86_64 => return error.SkipZigTest,
46654662 else => {},
46664663 }
4664
46674665 switch (builtin.cpu.arch) {
46684666 // This test generates too much code to execute on WASI.
46694667 // LLVM backend fails with "too many locals: locals exceed maximum"
lib/std/net/test.zig-2
......@@ -294,8 +294,6 @@ test "listen on a unix socket, send bytes, receive bytes" {
294294 if (builtin.single_threaded) return error.SkipZigTest;
295295 if (!net.has_unix_sockets) return error.SkipZigTest;
296296
297 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
298
299297 if (builtin.os.tag == .windows) {
300298 _ = try std.os.windows.WSAStartup(2, 2);
301299 }
lib/std/os/linux/io_uring.zig-26
......@@ -1741,8 +1741,6 @@ test "readv" {
17411741test "writev/fsync/readv" {
17421742 if (builtin.os.tag != .linux) return error.SkipZigTest;
17431743
1744 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1745
17461744 var ring = IO_Uring.init(4, 0) catch |err| switch (err) {
17471745 error.SystemOutdated => return error.SkipZigTest,
17481746 error.PermissionDenied => return error.SkipZigTest,
......@@ -1813,8 +1811,6 @@ test "writev/fsync/readv" {
18131811test "write/read" {
18141812 if (builtin.os.tag != .linux) return error.SkipZigTest;
18151813
1816 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1817
18181814 var ring = IO_Uring.init(2, 0) catch |err| switch (err) {
18191815 error.SystemOutdated => return error.SkipZigTest,
18201816 error.PermissionDenied => return error.SkipZigTest,
......@@ -1862,8 +1858,6 @@ test "write/read" {
18621858test "splice/read" {
18631859 if (builtin.os.tag != .linux) return error.SkipZigTest;
18641860
1865 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1866
18671861 var ring = IO_Uring.init(4, 0) catch |err| switch (err) {
18681862 error.SystemOutdated => return error.SkipZigTest,
18691863 error.PermissionDenied => return error.SkipZigTest,
......@@ -1935,8 +1929,6 @@ test "splice/read" {
19351929test "write_fixed/read_fixed" {
19361930 if (builtin.os.tag != .linux) return error.SkipZigTest;
19371931
1938 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1939
19401932 var ring = IO_Uring.init(2, 0) catch |err| switch (err) {
19411933 error.SystemOutdated => return error.SkipZigTest,
19421934 error.PermissionDenied => return error.SkipZigTest,
......@@ -2002,8 +1994,6 @@ test "write_fixed/read_fixed" {
20021994test "openat" {
20031995 if (builtin.os.tag != .linux) return error.SkipZigTest;
20041996
2005 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2006
20071997 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
20081998 error.SystemOutdated => return error.SkipZigTest,
20091999 error.PermissionDenied => return error.SkipZigTest,
......@@ -2055,8 +2045,6 @@ test "openat" {
20552045test "close" {
20562046 if (builtin.os.tag != .linux) return error.SkipZigTest;
20572047
2058 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2059
20602048 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
20612049 error.SystemOutdated => return error.SkipZigTest,
20622050 error.PermissionDenied => return error.SkipZigTest,
......@@ -2392,8 +2380,6 @@ test "accept/connect/recv/link_timeout" {
23922380test "fallocate" {
23932381 if (builtin.os.tag != .linux) return error.SkipZigTest;
23942382
2395 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2396
23972383 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
23982384 error.SystemOutdated => return error.SkipZigTest,
23992385 error.PermissionDenied => return error.SkipZigTest,
......@@ -2440,8 +2426,6 @@ test "fallocate" {
24402426test "statx" {
24412427 if (builtin.os.tag != .linux) return error.SkipZigTest;
24422428
2443 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2444
24452429 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
24462430 error.SystemOutdated => return error.SkipZigTest,
24472431 error.PermissionDenied => return error.SkipZigTest,
......@@ -2698,8 +2682,6 @@ test "shutdown" {
26982682test "renameat" {
26992683 if (builtin.os.tag != .linux) return error.SkipZigTest;
27002684
2701 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2702
27032685 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
27042686 error.SystemOutdated => return error.SkipZigTest,
27052687 error.PermissionDenied => return error.SkipZigTest,
......@@ -2769,8 +2751,6 @@ test "renameat" {
27692751test "unlinkat" {
27702752 if (builtin.os.tag != .linux) return error.SkipZigTest;
27712753
2772 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2773
27742754 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
27752755 error.SystemOutdated => return error.SkipZigTest,
27762756 error.PermissionDenied => return error.SkipZigTest,
......@@ -2823,8 +2803,6 @@ test "unlinkat" {
28232803test "mkdirat" {
28242804 if (builtin.os.tag != .linux) return error.SkipZigTest;
28252805
2826 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2827
28282806 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
28292807 error.SystemOutdated => return error.SkipZigTest,
28302808 error.PermissionDenied => return error.SkipZigTest,
......@@ -2869,8 +2847,6 @@ test "mkdirat" {
28692847test "symlinkat" {
28702848 if (builtin.os.tag != .linux) return error.SkipZigTest;
28712849
2872 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2873
28742850 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
28752851 error.SystemOutdated => return error.SkipZigTest,
28762852 error.PermissionDenied => return error.SkipZigTest,
......@@ -2919,8 +2895,6 @@ test "symlinkat" {
29192895test "linkat" {
29202896 if (builtin.os.tag != .linux) return error.SkipZigTest;
29212897
2922 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2923
29242898 var ring = IO_Uring.init(1, 0) catch |err| switch (err) {
29252899 error.SystemOutdated => return error.SkipZigTest,
29262900 error.PermissionDenied => return error.SkipZigTest,
lib/std/os/linux/test.zig-6
......@@ -8,8 +8,6 @@ const expectEqual = std.testing.expectEqual;
88const fs = std.fs;
99
1010test "fallocate" {
11 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
12
1311 var tmp = std.testing.tmpDir(.{});
1412 defer tmp.cleanup();
1513
......@@ -71,8 +69,6 @@ test "timer" {
7169}
7270
7371test "statx" {
74 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
75
7672 var tmp = std.testing.tmpDir(.{});
7773 defer tmp.cleanup();
7874
......@@ -111,8 +107,6 @@ test "user and group ids" {
111107}
112108
113109test "fadvise" {
114 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
115
116110 var tmp = std.testing.tmpDir(.{});
117111 defer tmp.cleanup();
118112
lib/std/os/test.zig-42
......@@ -88,8 +88,6 @@ test "chdir smoke test" {
8888test "open smoke test" {
8989 if (native_os == .wasi) return error.SkipZigTest;
9090
91 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
92
9391 // TODO verify file attributes using `fstat`
9492
9593 var tmp = tmpDir(.{});
......@@ -144,8 +142,6 @@ test "open smoke test" {
144142test "openat smoke test" {
145143 if (native_os == .wasi and builtin.link_libc) return error.SkipZigTest;
146144
147 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
148
149145 // TODO verify file attributes using `fstatat`
150146
151147 var tmp = tmpDir(.{});
......@@ -280,8 +276,6 @@ test "link with relative paths" {
280276test "linkat with different directories" {
281277 if (native_os == .wasi and builtin.link_libc) return error.SkipZigTest;
282278
283 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
284
285279 switch (native_os) {
286280 .wasi, .linux, .solaris, .illumos => {},
287281 else => return error.SkipZigTest,
......@@ -327,8 +321,6 @@ test "fstatat" {
327321 // enable when `fstat` and `fstatat` are implemented on Windows
328322 if (native_os == .windows) return error.SkipZigTest;
329323
330 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
331
332324 var tmp = tmpDir(.{});
333325 defer tmp.cleanup();
334326
......@@ -348,8 +340,6 @@ test "fstatat" {
348340}
349341
350342test "readlinkat" {
351 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
352
353343 var tmp = tmpDir(.{});
354344 defer tmp.cleanup();
355345
......@@ -583,8 +573,6 @@ test "mmap" {
583573 if (native_os == .windows or native_os == .wasi)
584574 return error.SkipZigTest;
585575
586 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
587
588576 var tmp = tmpDir(.{});
589577 defer tmp.cleanup();
590578
......@@ -695,8 +683,6 @@ test "fcntl" {
695683 if (native_os == .windows or native_os == .wasi)
696684 return error.SkipZigTest;
697685
698 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
699
700686 var tmp = tmpDir(.{});
701687 defer tmp.cleanup();
702688
......@@ -737,8 +723,6 @@ test "sync" {
737723 if (native_os != .linux)
738724 return error.SkipZigTest;
739725
740 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
741
742726 var tmp = tmpDir(.{});
743727 defer tmp.cleanup();
744728
......@@ -759,8 +743,6 @@ test "fsync" {
759743 else => return error.SkipZigTest,
760744 }
761745
762 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
763
764746 var tmp = tmpDir(.{});
765747 defer tmp.cleanup();
766748
......@@ -780,8 +762,6 @@ test "getrlimit and setrlimit" {
780762 return error.SkipZigTest;
781763 }
782764
783 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
784
785765 inline for (std.meta.fields(os.rlimit_resource)) |field| {
786766 const resource = @as(os.rlimit_resource, @enumFromInt(field.value));
787767 const limit = try os.getrlimit(resource);
......@@ -903,8 +883,6 @@ test "dup & dup2" {
903883 else => return error.SkipZigTest,
904884 }
905885
906 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
907
908886 var tmp = tmpDir(.{});
909887 defer tmp.cleanup();
910888
......@@ -934,8 +912,6 @@ test "dup & dup2" {
934912test "writev longer than IOV_MAX" {
935913 if (native_os == .windows or native_os == .wasi) return error.SkipZigTest;
936914
937 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
938
939915 var tmp = tmpDir(.{});
940916 defer tmp.cleanup();
941917
......@@ -953,8 +929,6 @@ test "POSIX file locking with fcntl" {
953929 return error.SkipZigTest;
954930 }
955931
956 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
957
958932 if (true) {
959933 // https://github.com/ziglang/zig/issues/11074
960934 return error.SkipZigTest;
......@@ -1017,8 +991,6 @@ test "POSIX file locking with fcntl" {
1017991test "rename smoke test" {
1018992 if (native_os == .wasi) return error.SkipZigTest;
1019993
1020 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1021
1022994 var tmp = tmpDir(.{});
1023995 defer tmp.cleanup();
1024996
......@@ -1075,8 +1047,6 @@ test "rename smoke test" {
10751047test "access smoke test" {
10761048 if (native_os == .wasi) return error.SkipZigTest;
10771049
1078 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1079
10801050 var tmp = tmpDir(.{});
10811051 defer tmp.cleanup();
10821052
......@@ -1141,8 +1111,6 @@ test "timerfd" {
11411111}
11421112
11431113test "isatty" {
1144 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1145
11461114 var tmp = tmpDir(.{});
11471115 defer tmp.cleanup();
11481116
......@@ -1155,8 +1123,6 @@ test "isatty" {
11551123test "read with empty buffer" {
11561124 if (native_os == .wasi) return error.SkipZigTest;
11571125
1158 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1159
11601126 var tmp = tmpDir(.{});
11611127 defer tmp.cleanup();
11621128
......@@ -1182,8 +1148,6 @@ test "read with empty buffer" {
11821148test "pread with empty buffer" {
11831149 if (native_os == .wasi) return error.SkipZigTest;
11841150
1185 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1186
11871151 var tmp = tmpDir(.{});
11881152 defer tmp.cleanup();
11891153
......@@ -1209,8 +1173,6 @@ test "pread with empty buffer" {
12091173test "write with empty buffer" {
12101174 if (native_os == .wasi) return error.SkipZigTest;
12111175
1212 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1213
12141176 var tmp = tmpDir(.{});
12151177 defer tmp.cleanup();
12161178
......@@ -1236,8 +1198,6 @@ test "write with empty buffer" {
12361198test "pwrite with empty buffer" {
12371199 if (native_os == .wasi) return error.SkipZigTest;
12381200
1239 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1240
12411201 var tmp = tmpDir(.{});
12421202 defer tmp.cleanup();
12431203
......@@ -1263,8 +1223,6 @@ test "pwrite with empty buffer" {
12631223test "fchmodat smoke test" {
12641224 if (!std.fs.has_executable_bit) return error.SkipZigTest;
12651225
1266 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1267
12681226 var tmp = tmpDir(.{});
12691227 defer tmp.cleanup();
12701228
lib/std/os/windows.zig-2
......@@ -2491,8 +2491,6 @@ pub fn ntToWin32Namespace(path: []const u16) !PathSpace {
24912491}
24922492
24932493test "ntToWin32Namespace" {
2494 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2495
24962494 const L = std.unicode.utf8ToUtf16LeStringLiteral;
24972495
24982496 try testNtToWin32Namespace(L("UNC"), L("\\??\\UNC"));
lib/std/priority_dequeue.zig-2
......@@ -705,8 +705,6 @@ test "std.PriorityDequeue: fromOwnedSlice trivial case 1" {
705705}
706706
707707test "std.PriorityDequeue: fromOwnedSlice" {
708 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
709
710708 const items = [_]u32{ 15, 7, 21, 14, 13, 22, 12, 6, 7, 25, 5, 24, 11, 16, 15, 24, 2, 1 };
711709 const queue_items = try testing.allocator.dupe(u32, items[0..]);
712710 var queue = PDQ.fromOwnedSlice(testing.allocator, queue_items[0..], {});
lib/std/priority_queue.zig-2
......@@ -385,8 +385,6 @@ test "std.PriorityQueue: fromOwnedSlice trivial case 1" {
385385}
386386
387387test "std.PriorityQueue: fromOwnedSlice" {
388 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
389
390388 const items = [_]u32{ 15, 7, 21, 14, 13, 22, 12, 6, 7, 25, 5, 24, 11, 16, 15, 24, 2, 1 };
391389 const heap_items = try testing.allocator.dupe(u32, items[0..]);
392390 var queue = PQlt.fromOwnedSlice(testing.allocator, heap_items[0..], {});
lib/std/time.zig-2
......@@ -321,8 +321,6 @@ pub const Timer = struct {
321321};
322322
323323test "Timer + Instant" {
324 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
325
326324 const margin = ns_per_ms * 150;
327325
328326 var timer = try Timer.start();
src/arch/x86_64/CodeGen.zig+339-187
......@@ -1460,7 +1460,10 @@ fn asmRegisterRegisterRegisterImmediate(
14601460 .r1 = reg1,
14611461 .r2 = reg2,
14621462 .r3 = reg3,
1463 .i = @as(u8, @intCast(imm.unsigned)),
1463 .i = switch (imm) {
1464 .signed => |s| @bitCast(@as(i8, @intCast(s))),
1465 .unsigned => |u| @intCast(u),
1466 },
14641467 } },
14651468 });
14661469}
......@@ -2084,7 +2087,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
20842087 .get_union_tag => try self.airGetUnionTag(inst),
20852088 .clz => try self.airClz(inst),
20862089 .ctz => try self.airCtz(inst),
2087 .popcount => try self.airPopcount(inst),
2090 .popcount => try self.airPopCount(inst),
20882091 .byte_swap => try self.airByteSwap(inst),
20892092 .bit_reverse => try self.airBitReverse(inst),
20902093 .tag_name => try self.airTagName(inst),
......@@ -3019,11 +3022,8 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
30193022 else if (dst_abi_size <= 8)
30203023 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv)
30213024 else if (dst_abi_size <= 16) dst: {
3022 const dst_regs = try self.register_manager.allocRegs(
3023 2,
3024 .{ inst, inst },
3025 abi.RegisterClass.gp,
3026 );
3025 const dst_regs =
3026 try self.register_manager.allocRegs(2, .{ inst, inst }, abi.RegisterClass.gp);
30273027 const dst_mcv: MCValue = .{ .register_pair = dst_regs };
30283028 const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
30293029 defer for (dst_locks) |lock| self.register_manager.unlockReg(lock);
......@@ -4671,6 +4671,19 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
46714671 if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{
46724672 src_ty.fmt(mod),
46734673 });
4674 const src_bits: u32 = @intCast(src_ty.bitSize(mod));
4675
4676 const has_lzcnt = self.hasFeature(.lzcnt);
4677 if (src_bits > 64 and !has_lzcnt) {
4678 var callee_buf: ["__clz?i2".len]u8 = undefined;
4679 break :result try self.genCall(.{ .lib = .{
4680 .return_type = .i32_type,
4681 .param_types = &.{src_ty.toIntern()},
4682 .callee = std.fmt.bufPrint(&callee_buf, "__clz{c}i2", .{
4683 intCompilerRtAbiName(src_bits),
4684 }) catch unreachable,
4685 } }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});
4686 }
46744687
46754688 const src_mcv = try self.resolveInst(ty_op.operand);
46764689 const mat_src_mcv = switch (src_mcv) {
......@@ -4688,8 +4701,7 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
46884701 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
46894702 defer self.register_manager.unlockReg(dst_lock);
46904703
4691 const src_bits = src_ty.bitSize(mod);
4692 if (self.hasFeature(.lzcnt)) {
4704 if (has_lzcnt) {
46934705 if (src_bits <= 8) {
46944706 const wide_reg = try self.copyToTmpRegister(src_ty, mat_src_mcv);
46954707 try self.truncateRegister(src_ty, wide_reg);
......@@ -4712,24 +4724,33 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
47124724 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
47134725 defer self.register_manager.unlockReg(tmp_lock);
47144726
4715 try self.genBinOpMir(.{ ._, .lzcnt }, Type.u64, dst_mcv, mat_src_mcv);
4727 try self.genBinOpMir(
4728 .{ ._, .lzcnt },
4729 Type.u64,
4730 dst_mcv,
4731 if (mat_src_mcv.isMemory())
4732 mat_src_mcv
4733 else
4734 .{ .register = mat_src_mcv.register_pair[0] },
4735 );
47164736 try self.genBinOpMir(.{ ._, .add }, dst_ty, dst_mcv, .{ .immediate = 64 });
47174737 try self.genBinOpMir(
47184738 .{ ._, .lzcnt },
47194739 Type.u64,
47204740 tmp_mcv,
4721 mat_src_mcv.address().offset(8).deref(),
4741 if (mat_src_mcv.isMemory())
4742 mat_src_mcv.address().offset(8).deref()
4743 else
4744 .{ .register = mat_src_mcv.register_pair[1] },
47224745 );
47234746 try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());
47244747
4725 if (src_bits < 128) {
4726 try self.genBinOpMir(
4727 .{ ._, .sub },
4728 dst_ty,
4729 dst_mcv,
4730 .{ .immediate = 128 - src_bits },
4731 );
4732 }
4748 if (src_bits < 128) try self.genBinOpMir(
4749 .{ ._, .sub },
4750 dst_ty,
4751 dst_mcv,
4752 .{ .immediate = 128 - src_bits },
4753 );
47334754 } else return self.fail("TODO airClz of {}", .{src_ty.fmt(mod)});
47344755 break :result dst_mcv;
47354756 }
......@@ -4800,7 +4821,22 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
48004821 const result = result: {
48014822 const dst_ty = self.typeOfIndex(inst);
48024823 const src_ty = self.typeOf(ty_op.operand);
4803 const src_bits = src_ty.bitSize(mod);
4824 if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{
4825 src_ty.fmt(mod),
4826 });
4827 const src_bits: u32 = @intCast(src_ty.bitSize(mod));
4828
4829 const has_bmi = self.hasFeature(.bmi);
4830 if (src_bits > 64 and !has_bmi) {
4831 var callee_buf: ["__ctz?i2".len]u8 = undefined;
4832 break :result try self.genCall(.{ .lib = .{
4833 .return_type = .i32_type,
4834 .param_types = &.{src_ty.toIntern()},
4835 .callee = std.fmt.bufPrint(&callee_buf, "__ctz{c}i2", .{
4836 intCompilerRtAbiName(src_bits),
4837 }) catch unreachable,
4838 } }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});
4839 }
48044840
48054841 const src_mcv = try self.resolveInst(ty_op.operand);
48064842 const mat_src_mcv = switch (src_mcv) {
......@@ -4845,8 +4881,16 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
48454881 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
48464882 defer self.register_manager.unlockReg(tmp_lock);
48474883
4884 const lo_mat_src_mcv: MCValue = if (mat_src_mcv.isMemory())
4885 mat_src_mcv
4886 else
4887 .{ .register = mat_src_mcv.register_pair[0] };
4888 const hi_mat_src_mcv: MCValue = if (mat_src_mcv.isMemory())
4889 mat_src_mcv.address().offset(8).deref()
4890 else
4891 .{ .register = mat_src_mcv.register_pair[1] };
48484892 const masked_mcv = if (src_bits < 128) masked: {
4849 try self.genCopy(Type.u64, dst_mcv, mat_src_mcv.address().offset(8).deref());
4893 try self.genCopy(Type.u64, dst_mcv, hi_mat_src_mcv);
48504894 try self.genBinOpMir(
48514895 .{ ._, .@"or" },
48524896 Type.u64,
......@@ -4854,10 +4898,10 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
48544898 .{ .immediate = @as(u64, math.maxInt(u64)) << @intCast(src_bits - 64) },
48554899 );
48564900 break :masked dst_mcv;
4857 } else mat_src_mcv.address().offset(8).deref();
4901 } else hi_mat_src_mcv;
48584902 try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, dst_mcv, masked_mcv);
48594903 try self.genBinOpMir(.{ ._, .add }, dst_ty, dst_mcv, .{ .immediate = 64 });
4860 try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, tmp_mcv, mat_src_mcv);
4904 try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, tmp_mcv, lo_mat_src_mcv);
48614905 try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());
48624906 } else return self.fail("TODO airCtz of {}", .{src_ty.fmt(mod)});
48634907 break :result dst_mcv;
......@@ -4889,155 +4933,216 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
48894933 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
48904934}
48914935
4892fn airPopcount(self: *Self, inst: Air.Inst.Index) !void {
4936fn airPopCount(self: *Self, inst: Air.Inst.Index) !void {
48934937 const mod = self.bin_file.options.module.?;
48944938 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
48954939 const result: MCValue = result: {
4940 try self.spillEflagsIfOccupied();
4941
48964942 const src_ty = self.typeOf(ty_op.operand);
48974943 const src_abi_size: u32 = @intCast(src_ty.abiSize(mod));
4898 if (src_ty.zigTypeTag(mod) == .Vector or src_abi_size > 8)
4899 return self.fail("TODO implement airPopcount for {}", .{src_ty.fmt(mod)});
4944 if (src_ty.zigTypeTag(mod) == .Vector or src_abi_size > 16)
4945 return self.fail("TODO implement airPopCount for {}", .{src_ty.fmt(mod)});
49004946 const src_mcv = try self.resolveInst(ty_op.operand);
49014947
4902 if (self.hasFeature(.popcnt)) {
4903 const mat_src_mcv = switch (src_mcv) {
4904 .immediate => MCValue{ .register = try self.copyToTmpRegister(src_ty, src_mcv) },
4905 else => src_mcv,
4906 };
4907 const mat_src_lock = switch (mat_src_mcv) {
4908 .register => |reg| self.register_manager.lockReg(reg),
4909 else => null,
4910 };
4911 defer if (mat_src_lock) |lock| self.register_manager.unlockReg(lock);
4948 const mat_src_mcv = switch (src_mcv) {
4949 .immediate => MCValue{ .register = try self.copyToTmpRegister(src_ty, src_mcv) },
4950 else => src_mcv,
4951 };
4952 const mat_src_lock = switch (mat_src_mcv) {
4953 .register => |reg| self.register_manager.lockReg(reg),
4954 else => null,
4955 };
4956 defer if (mat_src_lock) |lock| self.register_manager.unlockReg(lock);
49124957
4913 const dst_mcv: MCValue =
4914 if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
4915 src_mcv
4958 if (src_abi_size <= 8) {
4959 const dst_contains_src =
4960 src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv);
4961 const dst_reg = if (dst_contains_src)
4962 src_mcv.getReg().?
49164963 else
4917 .{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.gp) };
4964 try self.register_manager.allocReg(inst, abi.RegisterClass.gp);
4965 const dst_lock = self.register_manager.lockReg(dst_reg);
4966 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
49184967
4919 const popcnt_ty = if (src_abi_size > 1) src_ty else Type.u16;
4920 try self.genBinOpMir(.{ ._, .popcnt }, popcnt_ty, dst_mcv, mat_src_mcv);
4921 break :result dst_mcv;
4968 try self.genPopCount(dst_reg, src_ty, mat_src_mcv, dst_contains_src);
4969 break :result .{ .register = dst_reg };
49224970 }
49234971
4924 const mask = @as(u64, math.maxInt(u64)) >> @intCast(64 - src_abi_size * 8);
4925 const imm_0_1 = Immediate.u(mask / 0b1_1);
4926 const imm_00_11 = Immediate.u(mask / 0b01_01);
4927 const imm_0000_1111 = Immediate.u(mask / 0b0001_0001);
4928 const imm_0000_0001 = Immediate.u(mask / 0b1111_1111);
4972 assert(src_abi_size > 8 and src_abi_size <= 16);
4973 const tmp_regs = try self.register_manager.allocRegs(2, .{ inst, null }, abi.RegisterClass.gp);
4974 const tmp_locks = self.register_manager.lockRegsAssumeUnused(2, tmp_regs);
4975 defer for (tmp_locks) |lock| self.register_manager.unlockReg(lock);
49294976
4930 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
4931 src_mcv
4977 try self.genPopCount(tmp_regs[0], Type.usize, if (mat_src_mcv.isMemory())
4978 mat_src_mcv
49324979 else
4933 try self.copyToRegisterWithInstTracking(inst, src_ty, src_mcv);
4934 const dst_reg = dst_mcv.register;
4935 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
4936 defer self.register_manager.unlockReg(dst_lock);
4980 .{ .register = mat_src_mcv.register_pair[0] }, false);
4981 try self.genPopCount(tmp_regs[1], Type.usize, if (mat_src_mcv.isMemory())
4982 mat_src_mcv.address().offset(8).deref()
4983 else
4984 .{ .register = mat_src_mcv.register_pair[1] }, false);
4985 try self.asmRegisterRegister(.{ ._, .add }, tmp_regs[0].to8(), tmp_regs[1].to8());
4986 break :result .{ .register = tmp_regs[0] };
4987 };
4988 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
4989}
49374990
4938 const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
4939 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
4940 defer self.register_manager.unlockReg(tmp_lock);
4991fn genPopCount(
4992 self: *Self,
4993 dst_reg: Register,
4994 src_ty: Type,
4995 src_mcv: MCValue,
4996 dst_contains_src: bool,
4997) !void {
4998 const mod = self.bin_file.options.module.?;
49414999
4942 {
4943 const dst = registerAlias(dst_reg, src_abi_size);
4944 const tmp = registerAlias(tmp_reg, src_abi_size);
4945 const imm = if (src_abi_size > 4)
4946 try self.register_manager.allocReg(null, abi.RegisterClass.gp)
4947 else
4948 undefined;
4949
4950 // dst = operand
4951 try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
4952 // tmp = operand
4953 try self.asmRegisterImmediate(.{ ._r, .sh }, tmp, Immediate.u(1));
4954 // tmp = operand >> 1
4955 if (src_abi_size > 4) {
4956 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0_1);
4957 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
4958 } else try self.asmRegisterImmediate(.{ ._, .@"and" }, tmp, imm_0_1);
4959 // tmp = (operand >> 1) & 0x55...55
4960 try self.asmRegisterRegister(.{ ._, .sub }, dst, tmp);
4961 // dst = temp1 = operand - ((operand >> 1) & 0x55...55)
4962 try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
4963 // tmp = temp1
4964 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u(2));
4965 // dst = temp1 >> 2
4966 if (src_abi_size > 4) {
4967 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_00_11);
4968 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
4969 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
4970 } else {
4971 try self.asmRegisterImmediate(.{ ._, .@"and" }, tmp, imm_00_11);
4972 try self.asmRegisterImmediate(.{ ._, .@"and" }, dst, imm_00_11);
4973 }
4974 // tmp = temp1 & 0x33...33
4975 // dst = (temp1 >> 2) & 0x33...33
4976 try self.asmRegisterRegister(.{ ._, .add }, tmp, dst);
4977 // tmp = temp2 = (temp1 & 0x33...33) + ((temp1 >> 2) & 0x33...33)
4978 try self.asmRegisterRegister(.{ ._, .mov }, dst, tmp);
4979 // dst = temp2
4980 try self.asmRegisterImmediate(.{ ._r, .sh }, tmp, Immediate.u(4));
4981 // tmp = temp2 >> 4
4982 try self.asmRegisterRegister(.{ ._, .add }, dst, tmp);
4983 // dst = temp2 + (temp2 >> 4)
4984 if (src_abi_size > 4) {
4985 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0000_1111);
4986 try self.asmRegisterImmediate(.{ ._, .mov }, tmp, imm_0000_0001);
4987 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
4988 try self.asmRegisterRegister(.{ .i_, .mul }, dst, tmp);
4989 } else {
4990 try self.asmRegisterImmediate(.{ ._, .@"and" }, dst, imm_0000_1111);
4991 if (src_abi_size > 1) {
4992 try self.asmRegisterRegisterImmediate(.{ .i_, .mul }, dst, dst, imm_0000_0001);
4993 }
4994 }
4995 // dst = temp3 = (temp2 + (temp2 >> 4)) & 0x0f...0f
4996 // dst = temp3 * 0x01...01
4997 if (src_abi_size > 1) {
4998 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u((src_abi_size - 1) * 8));
4999 }
5000 // dst = (temp3 * 0x01...01) >> (bits - 8)
5000 const src_abi_size: u32 = @intCast(src_ty.abiSize(mod));
5001 if (self.hasFeature(.popcnt)) return self.genBinOpMir(
5002 .{ ._, .popcnt },
5003 if (src_abi_size > 1) src_ty else Type.u16,
5004 .{ .register = dst_reg },
5005 src_mcv,
5006 );
5007
5008 const mask = @as(u64, math.maxInt(u64)) >> @intCast(64 - src_abi_size * 8);
5009 const imm_0_1 = Immediate.u(mask / 0b1_1);
5010 const imm_00_11 = Immediate.u(mask / 0b01_01);
5011 const imm_0000_1111 = Immediate.u(mask / 0b0001_0001);
5012 const imm_0000_0001 = Immediate.u(mask / 0b1111_1111);
5013
5014 const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
5015 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
5016 defer self.register_manager.unlockReg(tmp_lock);
5017
5018 const dst = registerAlias(dst_reg, src_abi_size);
5019 const tmp = registerAlias(tmp_reg, src_abi_size);
5020 const imm = if (src_abi_size > 4)
5021 try self.register_manager.allocReg(null, abi.RegisterClass.gp)
5022 else
5023 undefined;
5024
5025 if (!dst_contains_src) try self.genSetReg(dst, src_ty, src_mcv);
5026 // dst = operand
5027 try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
5028 // tmp = operand
5029 try self.asmRegisterImmediate(.{ ._r, .sh }, tmp, Immediate.u(1));
5030 // tmp = operand >> 1
5031 if (src_abi_size > 4) {
5032 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0_1);
5033 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
5034 } else try self.asmRegisterImmediate(.{ ._, .@"and" }, tmp, imm_0_1);
5035 // tmp = (operand >> 1) & 0x55...55
5036 try self.asmRegisterRegister(.{ ._, .sub }, dst, tmp);
5037 // dst = temp1 = operand - ((operand >> 1) & 0x55...55)
5038 try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
5039 // tmp = temp1
5040 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u(2));
5041 // dst = temp1 >> 2
5042 if (src_abi_size > 4) {
5043 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_00_11);
5044 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
5045 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
5046 } else {
5047 try self.asmRegisterImmediate(.{ ._, .@"and" }, tmp, imm_00_11);
5048 try self.asmRegisterImmediate(.{ ._, .@"and" }, dst, imm_00_11);
5049 }
5050 // tmp = temp1 & 0x33...33
5051 // dst = (temp1 >> 2) & 0x33...33
5052 try self.asmRegisterRegister(.{ ._, .add }, tmp, dst);
5053 // tmp = temp2 = (temp1 & 0x33...33) + ((temp1 >> 2) & 0x33...33)
5054 try self.asmRegisterRegister(.{ ._, .mov }, dst, tmp);
5055 // dst = temp2
5056 try self.asmRegisterImmediate(.{ ._r, .sh }, tmp, Immediate.u(4));
5057 // tmp = temp2 >> 4
5058 try self.asmRegisterRegister(.{ ._, .add }, dst, tmp);
5059 // dst = temp2 + (temp2 >> 4)
5060 if (src_abi_size > 4) {
5061 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0000_1111);
5062 try self.asmRegisterImmediate(.{ ._, .mov }, tmp, imm_0000_0001);
5063 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
5064 try self.asmRegisterRegister(.{ .i_, .mul }, dst, tmp);
5065 } else {
5066 try self.asmRegisterImmediate(.{ ._, .@"and" }, dst, imm_0000_1111);
5067 if (src_abi_size > 1) {
5068 try self.asmRegisterRegisterImmediate(.{ .i_, .mul }, dst, dst, imm_0000_0001);
50015069 }
5002 break :result dst_mcv;
5003 };
5004 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
5070 }
5071 // dst = temp3 = (temp2 + (temp2 >> 4)) & 0x0f...0f
5072 // dst = temp3 * 0x01...01
5073 if (src_abi_size > 1) {
5074 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u((src_abi_size - 1) * 8));
5075 }
5076 // dst = (temp3 * 0x01...01) >> (bits - 8)
50055077}
50065078
5007fn byteSwap(self: *Self, inst: Air.Inst.Index, src_ty: Type, src_mcv: MCValue, mem_ok: bool) !MCValue {
5079fn genByteSwap(
5080 self: *Self,
5081 inst: Air.Inst.Index,
5082 src_ty: Type,
5083 src_mcv: MCValue,
5084 mem_ok: bool,
5085) !MCValue {
50085086 const mod = self.bin_file.options.module.?;
50095087 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
50105088
50115089 if (src_ty.zigTypeTag(mod) == .Vector) return self.fail(
5012 "TODO implement byteSwap for {}",
5090 "TODO implement genByteSwap for {}",
50135091 .{src_ty.fmt(mod)},
50145092 );
5015 const src_bits = self.regBitSize(src_ty);
5093 const abi_size: u32 = @intCast(src_ty.abiSize(mod));
50165094 const src_lock = switch (src_mcv) {
50175095 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
50185096 else => null,
50195097 };
50205098 defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
50215099
5022 switch (src_bits) {
5023 else => return self.fail("TODO implement byteSwap for {}", .{
5100 switch (abi_size) {
5101 else => return self.fail("TODO implement genByteSwap for {}", .{
50245102 src_ty.fmt(mod),
50255103 }),
5026 8 => return if ((mem_ok or src_mcv.isRegister()) and
5104 1 => return if ((mem_ok or src_mcv.isRegister()) and
50275105 self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
50285106 src_mcv
50295107 else
50305108 try self.copyToRegisterWithInstTracking(inst, src_ty, src_mcv),
5031 16 => if ((mem_ok or src_mcv.isRegister()) and
5109 2 => if ((mem_ok or src_mcv.isRegister()) and
50325110 self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
50335111 {
50345112 try self.genBinOpMir(.{ ._l, .ro }, src_ty, src_mcv, .{ .immediate = 8 });
50355113 return src_mcv;
50365114 },
5037 32, 64 => if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) {
5115 3...8 => if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) {
50385116 try self.genUnOpMir(.{ ._, .bswap }, src_ty, src_mcv);
50395117 return src_mcv;
50405118 },
5119 9...16 => {
5120 switch (src_mcv) {
5121 .register_pair => |src_regs| if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) {
5122 for (src_regs) |src_reg| try self.asmRegister(.{ ._, .bswap }, src_reg.to64());
5123 return .{ .register_pair = .{ src_regs[1], src_regs[0] } };
5124 },
5125 else => {},
5126 }
5127
5128 const dst_regs =
5129 try self.register_manager.allocRegs(2, .{ inst, inst }, abi.RegisterClass.gp);
5130 const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
5131 defer for (dst_locks) |lock| self.register_manager.unlockReg(lock);
5132
5133 if (src_mcv.isMemory()) {
5134 try self.asmRegisterMemory(
5135 .{ ._, .movbe },
5136 dst_regs[0],
5137 src_mcv.address().offset(8).deref().mem(.qword),
5138 );
5139 try self.asmRegisterMemory(.{ ._, .movbe }, dst_regs[1], src_mcv.mem(.qword));
5140 } else for (dst_regs, src_mcv.register_pair) |dst_reg, src_reg| {
5141 try self.asmRegisterRegister(.{ ._, .mov }, dst_reg.to64(), src_reg.to64());
5142 try self.asmRegister(.{ ._, .bswap }, dst_reg.to64());
5143 }
5144 return .{ .register_pair = dst_regs };
5145 },
50415146 }
50425147
50435148 if (src_mcv.isRegister()) {
......@@ -5050,10 +5155,10 @@ fn byteSwap(self: *Self, inst: Air.Inst.Index, src_ty: Type, src_mcv: MCValue, m
50505155 defer self.register_manager.unlockReg(dst_lock);
50515156
50525157 try self.genSetReg(dst_mcv.register, src_ty, src_mcv);
5053 switch (src_bits) {
5158 switch (abi_size) {
50545159 else => unreachable,
5055 16 => try self.genBinOpMir(.{ ._l, .ro }, src_ty, dst_mcv, .{ .immediate = 8 }),
5056 32, 64 => try self.genUnOpMir(.{ ._, .bswap }, src_ty, dst_mcv),
5160 2 => try self.genBinOpMir(.{ ._l, .ro }, src_ty, dst_mcv, .{ .immediate = 8 }),
5161 3...8 => try self.genUnOpMir(.{ ._, .bswap }, src_ty, dst_mcv),
50575162 }
50585163 } else try self.genBinOpMir(.{ ._, .movbe }, src_ty, dst_mcv, src_mcv);
50595164 return dst_mcv;
......@@ -5073,18 +5178,19 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {
50735178 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
50745179
50755180 const src_ty = self.typeOf(ty_op.operand);
5181 const abi_size: u32 = @intCast(src_ty.abiSize(mod));
5182 const bit_size: u32 = @intCast(src_ty.bitSize(mod));
50765183 const src_mcv = try self.resolveInst(ty_op.operand);
50775184
5078 const dst_mcv = try self.byteSwap(inst, src_ty, src_mcv, true);
5079 switch (self.regExtraBits(src_ty)) {
5080 0 => {},
5081 else => |extra| try self.genBinOpMir(
5082 if (src_ty.isSignedInt(mod)) .{ ._r, .sa } else .{ ._r, .sh },
5083 src_ty,
5084 dst_mcv,
5085 .{ .immediate = extra },
5086 ),
5087 }
5185 const dst_mcv = try self.genByteSwap(inst, src_ty, src_mcv, true);
5186
5187 const extra_bits = abi_size * 8 - bit_size;
5188 const signedness: std.builtin.Signedness =
5189 if (src_ty.isAbiInt(mod)) src_ty.intInfo(mod).signedness else .unsigned;
5190 if (extra_bits > 0) try self.genShiftBinOpMir(switch (signedness) {
5191 .signed => .{ ._r, .sa },
5192 .unsigned => .{ ._r, .sh },
5193 }, src_ty, dst_mcv, .{ .immediate = extra_bits });
50885194
50895195 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
50905196}
......@@ -5094,37 +5200,43 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
50945200 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
50955201
50965202 const src_ty = self.typeOf(ty_op.operand);
5097 const src_abi_size: u32 = @intCast(src_ty.abiSize(mod));
5203 const abi_size: u32 = @intCast(src_ty.abiSize(mod));
5204 const bit_size: u32 = @intCast(src_ty.bitSize(mod));
50985205 const src_mcv = try self.resolveInst(ty_op.operand);
50995206
5100 const dst_mcv = try self.byteSwap(inst, src_ty, src_mcv, false);
5101 const dst_reg = dst_mcv.register;
5102 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
5103 defer self.register_manager.unlockReg(dst_lock);
5207 const dst_mcv = try self.genByteSwap(inst, src_ty, src_mcv, false);
5208 const dst_locks: [2]?RegisterLock = switch (dst_mcv) {
5209 .register => |dst_reg| .{ self.register_manager.lockReg(dst_reg), null },
5210 .register_pair => |dst_regs| self.register_manager.lockRegs(2, dst_regs),
5211 else => unreachable,
5212 };
5213 defer for (dst_locks) |dst_lock| if (dst_lock) |lock| self.register_manager.unlockReg(lock);
51045214
51055215 const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
51065216 const tmp_lock = self.register_manager.lockReg(tmp_reg);
51075217 defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
51085218
5109 {
5110 const dst = registerAlias(dst_reg, src_abi_size);
5111 const tmp = registerAlias(tmp_reg, src_abi_size);
5112 const imm = if (src_abi_size > 4)
5113 try self.register_manager.allocReg(null, abi.RegisterClass.gp)
5114 else
5115 undefined;
5219 const limb_abi_size: u32 = @min(abi_size, 8);
5220 const tmp = registerAlias(tmp_reg, limb_abi_size);
5221 const imm = if (limb_abi_size > 4)
5222 try self.register_manager.allocReg(null, abi.RegisterClass.gp)
5223 else
5224 undefined;
51165225
5117 const mask = @as(u64, math.maxInt(u64)) >> @intCast(64 - src_abi_size * 8);
5118 const imm_0000_1111 = Immediate.u(mask / 0b0001_0001);
5119 const imm_00_11 = Immediate.u(mask / 0b01_01);
5120 const imm_0_1 = Immediate.u(mask / 0b1_1);
5226 const mask = @as(u64, math.maxInt(u64)) >> @intCast(64 - limb_abi_size * 8);
5227 const imm_0000_1111 = Immediate.u(mask / 0b0001_0001);
5228 const imm_00_11 = Immediate.u(mask / 0b01_01);
5229 const imm_0_1 = Immediate.u(mask / 0b1_1);
5230
5231 for (dst_mcv.getRegs()) |dst_reg| {
5232 const dst = registerAlias(dst_reg, limb_abi_size);
51215233
51225234 // dst = temp1 = bswap(operand)
51235235 try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
51245236 // tmp = temp1
51255237 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u(4));
51265238 // dst = temp1 >> 4
5127 if (src_abi_size > 4) {
5239 if (limb_abi_size > 4) {
51285240 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0000_1111);
51295241 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
51305242 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
......@@ -5142,7 +5254,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
51425254 // tmp = temp2
51435255 try self.asmRegisterImmediate(.{ ._r, .sh }, dst, Immediate.u(2));
51445256 // dst = temp2 >> 2
5145 if (src_abi_size > 4) {
5257 if (limb_abi_size > 4) {
51465258 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_00_11);
51475259 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
51485260 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
......@@ -5154,7 +5266,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
51545266 // dst = (temp2 >> 2) & 0x33...33
51555267 try self.asmRegisterMemory(
51565268 .{ ._, .lea },
5157 if (src_abi_size > 4) tmp.to64() else tmp.to32(),
5269 if (limb_abi_size > 4) tmp.to64() else tmp.to32(),
51585270 Memory.sib(.qword, .{
51595271 .base = .{ .reg = dst.to64() },
51605272 .scale_index = .{ .index = tmp.to64(), .scale = 1 << 2 },
......@@ -5165,7 +5277,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
51655277 // dst = temp3
51665278 try self.asmRegisterImmediate(.{ ._r, .sh }, tmp, Immediate.u(1));
51675279 // tmp = temp3 >> 1
5168 if (src_abi_size > 4) {
5280 if (limb_abi_size > 4) {
51695281 try self.asmRegisterImmediate(.{ ._, .mov }, imm, imm_0_1);
51705282 try self.asmRegisterRegister(.{ ._, .@"and" }, dst, imm);
51715283 try self.asmRegisterRegister(.{ ._, .@"and" }, tmp, imm);
......@@ -5177,7 +5289,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
51775289 // tmp = (temp3 >> 1) & 0x55...55
51785290 try self.asmRegisterMemory(
51795291 .{ ._, .lea },
5180 if (src_abi_size > 4) dst.to64() else dst.to32(),
5292 if (limb_abi_size > 4) dst.to64() else dst.to32(),
51815293 Memory.sib(.qword, .{
51825294 .base = .{ .reg = tmp.to64() },
51835295 .scale_index = .{ .index = dst.to64(), .scale = 1 << 1 },
......@@ -5186,15 +5298,13 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
51865298 // dst = ((temp3 >> 1) & 0x55...55) + ((temp3 & 0x55...55) << 1)
51875299 }
51885300
5189 switch (self.regExtraBits(src_ty)) {
5190 0 => {},
5191 else => |extra| try self.genBinOpMir(
5192 if (src_ty.isSignedInt(mod)) .{ ._r, .sa } else .{ ._r, .sh },
5193 src_ty,
5194 dst_mcv,
5195 .{ .immediate = extra },
5196 ),
5197 }
5301 const extra_bits = abi_size * 8 - bit_size;
5302 const signedness: std.builtin.Signedness =
5303 if (src_ty.isAbiInt(mod)) src_ty.intInfo(mod).signedness else .unsigned;
5304 if (extra_bits > 0) try self.genShiftBinOpMir(switch (signedness) {
5305 .signed => .{ ._r, .sa },
5306 .unsigned => .{ ._r, .sh },
5307 }, src_ty, dst_mcv, .{ .immediate = extra_bits });
51985308
51995309 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
52005310}
......@@ -10861,29 +10971,41 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
1086110971 },
1086210972 else => return self.fail("invalid constraint: '{s}'", .{constraint}),
1086310973 };
10974 const is_early_clobber = constraint[1] == '&';
10975 const rest = constraint[@as(usize, 1) + @intFromBool(is_early_clobber) ..];
1086410976 const arg_mcv: MCValue = arg_mcv: {
10865 const arg_maybe_reg: ?Register = if (mem.eql(u8, constraint[1..], "r"))
10866 self.register_manager.tryAllocReg(maybe_inst, self.regClassForType(ty)) orelse
10867 return self.fail("ran out of registers lowering inline asm", .{})
10868 else if (mem.eql(u8, constraint[1..], "m"))
10977 const arg_maybe_reg: ?Register = if (mem.eql(u8, rest, "r") or
10978 mem.eql(u8, rest, "f") or mem.eql(u8, rest, "x"))
10979 registerAlias(
10980 self.register_manager.tryAllocReg(maybe_inst, switch (rest[0]) {
10981 'r' => abi.RegisterClass.gp,
10982 'f' => abi.RegisterClass.x87,
10983 'x' => abi.RegisterClass.sse,
10984 else => unreachable,
10985 }) orelse return self.fail("ran out of registers lowering inline asm", .{}),
10986 @intCast(ty.abiSize(mod)),
10987 )
10988 else if (mem.eql(u8, rest, "m"))
1086910989 if (output != .none) null else return self.fail(
1087010990 "memory constraint unsupported for asm result: '{s}'",
1087110991 .{constraint},
1087210992 )
10873 else if (mem.eql(u8, constraint[1..], "g") or
10874 mem.eql(u8, constraint[1..], "rm") or mem.eql(u8, constraint[1..], "mr") or
10875 mem.eql(u8, constraint[1..], "r,m") or mem.eql(u8, constraint[1..], "m,r"))
10876 self.register_manager.tryAllocReg(maybe_inst, self.regClassForType(ty)) orelse
10993 else if (mem.eql(u8, rest, "g") or
10994 mem.eql(u8, rest, "rm") or mem.eql(u8, rest, "mr") or
10995 mem.eql(u8, rest, "r,m") or mem.eql(u8, rest, "m,r"))
10996 self.register_manager.tryAllocReg(maybe_inst, abi.RegisterClass.gp) orelse
1087710997 if (output != .none)
1087810998 null
1087910999 else
1088011000 return self.fail("ran out of registers lowering inline asm", .{})
10881 else if (mem.startsWith(u8, constraint[1..], "{") and mem.endsWith(u8, constraint[1..], "}"))
10882 parseRegName(constraint[1 + "{".len .. constraint.len - "}".len]) orelse
11001 else if (mem.startsWith(u8, rest, "{") and mem.endsWith(u8, rest, "}"))
11002 parseRegName(rest["{".len .. rest.len - "}".len]) orelse
1088311003 return self.fail("invalid register constraint: '{s}'", .{constraint})
10884 else if (constraint.len == 2 and std.ascii.isDigit(constraint[1])) {
10885 const index = std.fmt.charToDigit(constraint[0], 10) catch unreachable;
10886 if (index >= args.items.len) return self.fail("constraint out of bounds: '{s}'", .{constraint});
11004 else if (rest.len == 1 and std.ascii.isDigit(rest[0])) {
11005 const index = std.fmt.charToDigit(rest[0], 10) catch unreachable;
11006 if (index >= args.items.len) return self.fail("constraint out of bounds: '{s}'", .{
11007 constraint,
11008 });
1088711009 break :arg_mcv args.items[index];
1088811010 } else return self.fail("invalid constraint: '{s}'", .{constraint});
1088911011 break :arg_mcv if (arg_maybe_reg) |reg| .{ .register = reg } else arg: {
......@@ -10917,10 +11039,29 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
1091711039
1091811040 const ty = self.typeOf(input);
1091911041 const input_mcv = try self.resolveInst(input);
10920 const arg_mcv: MCValue = if (mem.eql(u8, constraint, "r")) switch (input_mcv) {
10921 .register => input_mcv,
10922 else => .{ .register = try self.copyToTmpRegister(ty, input_mcv) },
10923 } else if (mem.eql(u8, constraint, "m")) arg: {
11042 const arg_mcv: MCValue = if (mem.eql(u8, constraint, "r") or
11043 mem.eql(u8, constraint, "f") or mem.eql(u8, constraint, "x"))
11044 arg: {
11045 const rc = switch (constraint[0]) {
11046 'r' => abi.RegisterClass.gp,
11047 'f' => abi.RegisterClass.x87,
11048 'x' => abi.RegisterClass.sse,
11049 else => unreachable,
11050 };
11051 if (input_mcv.isRegister() and
11052 rc.isSet(RegisterManager.indexOfRegIntoTracked(input_mcv.getReg().?).?))
11053 break :arg input_mcv;
11054 const reg = try self.register_manager.allocReg(null, rc);
11055 try self.genSetReg(reg, ty, input_mcv);
11056 break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(mod))) };
11057 } else if (mem.eql(u8, constraint, "i") or mem.eql(u8, constraint, "n"))
11058 switch (input_mcv) {
11059 .immediate => |imm| .{ .immediate = imm },
11060 else => return self.fail("immediate operand requires comptime value: '{s}'", .{
11061 constraint,
11062 }),
11063 }
11064 else if (mem.eql(u8, constraint, "m")) arg: {
1092411065 switch (input_mcv) {
1092511066 .memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |_|
1092611067 break :arg input_mcv,
......@@ -11144,6 +11285,10 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
1114411285 arg_map.get(op_str["%[".len .. colon orelse op_str.len - "]".len]) orelse
1114511286 return self.fail("no matching constraint: '{s}'", .{op_str})
1114611287 ]) {
11288 .immediate => |imm| if (mem.eql(u8, modifier, "") or mem.eql(u8, modifier, "c"))
11289 .{ .imm = Immediate.u(imm) }
11290 else
11291 return self.fail("invalid modifier: '{s}'", .{modifier}),
1114711292 .register => |reg| if (mem.eql(u8, modifier, ""))
1114811293 .{ .reg = reg }
1114911294 else
......@@ -11272,6 +11417,13 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
1127211417 .none => self.asmRegisterImmediate(mnem_fixed_tag, reg1, imm0),
1127311418 .reg => |reg2| switch (ops[3]) {
1127411419 .none => self.asmRegisterRegisterImmediate(mnem_fixed_tag, reg2, reg1, imm0),
11420 .reg => |reg3| self.asmRegisterRegisterRegisterImmediate(
11421 mnem_fixed_tag,
11422 reg3,
11423 reg2,
11424 reg1,
11425 imm0,
11426 ),
1127511427 else => error.InvalidInstruction,
1127611428 },
1127711429 .mem => |mem2| switch (ops[3]) {
src/arch/x86_64/Encoding.zig+26-7
......@@ -269,6 +269,9 @@ pub const Mnemonic = enum {
269269 pcmpeqb, pcmpeqd, pcmpeqw,
270270 pcmpgtb, pcmpgtd, pcmpgtw,
271271 pmulhw, pmullw,
272 pslld, psllq, psllw,
273 psrad, psraw,
274 psrld, psrlq, psrlw,
272275 psubb, psubd, psubq, psubsb, psubsw, psubusb, psubusw, psubw,
273276 // SSE
274277 addps, addss,
......@@ -309,8 +312,8 @@ pub const Mnemonic = enum {
309312 movupd,
310313 mulpd, mulsd,
311314 orpd,
312 pshufhw, pshuflw,
313 psrld, psrlq, psrlw,
315 pshufd, pshufhw, pshuflw,
316 pslldq, psrldq,
314317 punpckhbw, punpckhdq, punpckhqdq, punpckhwd,
315318 punpcklbw, punpckldq, punpcklqdq, punpcklwd,
316319 shufpd,
......@@ -321,7 +324,7 @@ pub const Mnemonic = enum {
321324 // SSE3
322325 movddup, movshdup, movsldup,
323326 // SSSE3
324 pabsb, pabsd, pabsw,
327 pabsb, pabsd, pabsw, palignr,
325328 // SSE4.1
326329 blendpd, blendps, blendvpd, blendvps,
327330 extractps,
......@@ -335,8 +338,15 @@ pub const Mnemonic = enum {
335338 roundpd, roundps, roundsd, roundss,
336339 // SSE4.2
337340 pcmpgtq,
341 // PCLMUL
342 pclmulqdq,
343 // AES
344 aesdec, aesdeclast, aesenc, aesenclast, aesimc, aeskeygenassist,
345 // SHA
346 sha256msg1, sha256msg2, sha256rnds2,
338347 // AVX
339348 vaddpd, vaddps, vaddsd, vaddss,
349 vaesdec, vaesdeclast, vaesenc, vaesenclast, vaesimc, vaeskeygenassist,
340350 vandnpd, vandnps, vandpd, vandps,
341351 vblendpd, vblendps, vblendvpd, vblendvps,
342352 vbroadcastf128, vbroadcastsd, vbroadcastss,
......@@ -366,7 +376,7 @@ pub const Mnemonic = enum {
366376 vpabsb, vpabsd, vpabsw,
367377 vpackssdw, vpacksswb, vpackusdw, vpackuswb,
368378 vpaddb, vpaddd, vpaddq, vpaddsb, vpaddsw, vpaddusb, vpaddusw, vpaddw,
369 vpand, vpandn,
379 vpalignr, vpand, vpandn, vpclmulqdq,
370380 vpcmpeqb, vpcmpeqd, vpcmpeqq, vpcmpeqw,
371381 vpcmpgtb, vpcmpgtd, vpcmpgtq, vpcmpgtw,
372382 vpextrb, vpextrd, vpextrq, vpextrw,
......@@ -376,8 +386,10 @@ pub const Mnemonic = enum {
376386 vpmovmskb,
377387 vpmulhw, vpmulld, vpmullw,
378388 vpor,
379 vpshufhw, vpshuflw,
380 vpsrld, vpsrlq, vpsrlw,
389 vpshufd, vpshufhw, vpshuflw,
390 vpslld, vpslldq, vpsllq, vpsllw,
391 vpsrad, vpsraq, vpsraw,
392 vpsrld, vpsrldq, vpsrlq, vpsrlw,
381393 vpsubb, vpsubd, vpsubq, vpsubsb, vpsubsw, vpsubusb, vpsubusw, vpsubw,
382394 vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
383395 vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
......@@ -753,6 +765,8 @@ pub const Mode = enum {
753765
754766pub const Feature = enum {
755767 none,
768 aes,
769 @"aes avx",
756770 avx,
757771 avx2,
758772 bmi,
......@@ -760,6 +774,8 @@ pub const Feature = enum {
760774 fma,
761775 lzcnt,
762776 movbe,
777 pclmul,
778 @"pclmul avx",
763779 popcnt,
764780 sse,
765781 sse2,
......@@ -767,6 +783,9 @@ pub const Feature = enum {
767783 sse4_1,
768784 sse4_2,
769785 ssse3,
786 sha,
787 vaes,
788 vpclmulqdq,
770789 x87,
771790};
772791
......@@ -784,7 +803,7 @@ fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Op
784803}
785804
786805const mnemonic_to_encodings_map = init: {
787 @setEvalBranchQuota(50_000);
806 @setEvalBranchQuota(60_000);
788807 const encodings = @import("encodings.zig");
789808 var entries = encodings.table;
790809 std.mem.sort(encodings.Entry, &entries, {}, struct {
src/arch/x86_64/Mir.zig+34-4
......@@ -494,6 +494,12 @@ pub const Inst = struct {
494494 mull,
495495 /// Multiply packed signed integers and store high result
496496 mulh,
497 /// Shift packed data left logical
498 sll,
499 /// Shift packed data right arithmetic
500 sra,
501 /// Shift packed data right logical
502 srl,
497503 /// Subtract packed signed integers with signed saturation
498504 subs,
499505 /// Subtract packed unsigned integers with unsigned saturation
......@@ -592,15 +598,13 @@ pub const Inst = struct {
592598 movdqu,
593599 /// Packed interleave shuffle of quadruplets of single-precision floating-point values
594600 /// Packed interleave shuffle of pairs of double-precision floating-point values
601 /// Shuffle packed doublewords
602 /// Shuffle packed words
595603 shuf,
596604 /// Shuffle packed high words
597605 shufh,
598606 /// Shuffle packed low words
599607 shufl,
600 /// Shift packed data right logical
601 /// Shift packed data right logical
602 /// Shift packed data right logical
603 srl,
604608 /// Unpack high data
605609 unpckhbw,
606610 /// Unpack high data
......@@ -625,6 +629,9 @@ pub const Inst = struct {
625629 /// Replicate single floating-point values
626630 movsldup,
627631
632 /// Packed align right
633 alignr,
634
628635 /// Pack with unsigned saturation
629636 ackusd,
630637 /// Blend packed single-precision floating-point values
......@@ -648,6 +655,29 @@ pub const Inst = struct {
648655 /// Round scalar double-precision floating-point value
649656 round,
650657
658 /// Carry-less multiplication quadword
659 clmulq,
660
661 /// Perform one round of an AES decryption flow
662 aesdec,
663 /// Perform last round of an AES decryption flow
664 aesdeclast,
665 /// Perform one round of an AES encryption flow
666 aesenc,
667 /// Perform last round of an AES encryption flow
668 aesenclast,
669 /// Perform the AES InvMixColumn transformation
670 aesimc,
671 /// AES round key generation assist
672 aeskeygenassist,
673
674 /// Perform an intermediate calculation for the next four SHA256 message dwords
675 sha256msg1,
676 /// Perform a final calculation for the next four SHA256 message dwords
677 sha256msg2,
678 /// Perform two rounds of SHA256 operation
679 sha256rnds2,
680
651681 /// Load with broadcast floating-point data
652682 broadcast,
653683
src/arch/x86_64/encodings.zig+120
......@@ -1075,10 +1075,26 @@ pub const table = [_]Entry{
10751075
10761076 .{ .por, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .none, .sse2 },
10771077
1078 .{ .pshufd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x70 }, 0, .none, .sse2 },
1079
10781080 .{ .pshufhw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .none, .sse2 },
10791081
10801082 .{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },
10811083
1084 .{ .psllw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf1 }, 0, .none, .sse2 },
1085 .{ .psllw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 6, .none, .sse2 },
1086 .{ .pslld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf2 }, 0, .none, .sse2 },
1087 .{ .pslld, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 6, .none, .sse2 },
1088 .{ .psllq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf3 }, 0, .none, .sse2 },
1089 .{ .psllq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 6, .none, .sse2 },
1090
1091 .{ .pslldq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 7, .none, .sse2 },
1092
1093 .{ .psraw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe1 }, 0, .none, .sse2 },
1094 .{ .psraw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 4, .none, .sse2 },
1095 .{ .psrad, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe2 }, 0, .none, .sse2 },
1096 .{ .psrad, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 4, .none, .sse2 },
1097
10821098 .{ .psrlw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .none, .sse2 },
10831099 .{ .psrlw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .none, .sse2 },
10841100 .{ .psrld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .none, .sse2 },
......@@ -1086,6 +1102,8 @@ pub const table = [_]Entry{
10861102 .{ .psrlq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .none, .sse2 },
10871103 .{ .psrlq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .none, .sse2 },
10881104
1105 .{ .psrldq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 3, .none, .sse2 },
1106
10891107 .{ .psubb, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf8 }, 0, .none, .sse2 },
10901108 .{ .psubw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf9 }, 0, .none, .sse2 },
10911109 .{ .psubd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfa }, 0, .none, .sse2 },
......@@ -1139,13 +1157,17 @@ pub const table = [_]Entry{
11391157 .{ .pabsw, .rm, &.{ .mm, .mm_m64 }, &.{ 0x0f, 0x38, 0x1d }, 0, .none, .ssse3 },
11401158 .{ .pabsw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x1d }, 0, .none, .ssse3 },
11411159
1160 .{ .palignr, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0f }, 0, .none, .ssse3 },
1161
11421162 // SSE4.1
11431163 .{ .blendpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0d }, 0, .none, .sse4_1 },
11441164
11451165 .{ .blendps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0c }, 0, .none, .sse4_1 },
11461166
1167 .{ .blendvpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x15 }, 0, .none, .sse4_1 },
11471168 .{ .blendvpd, .rm0, &.{ .xmm, .xmm_m128, .xmm0 }, &.{ 0x66, 0x0f, 0x38, 0x15 }, 0, .none, .sse4_1 },
11481169
1170 .{ .blendvps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x14 }, 0, .none, .sse4_1 },
11491171 .{ .blendvps, .rm0, &.{ .xmm, .xmm_m128, .xmm0 }, &.{ 0x66, 0x0f, 0x38, 0x14 }, 0, .none, .sse4_1 },
11501172
11511173 .{ .extractps, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x17 }, 0, .none, .sse4_1 },
......@@ -1193,6 +1215,30 @@ pub const table = [_]Entry{
11931215 // SSE4.2
11941216 .{ .pcmpgtq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x37 }, 0, .none, .sse4_2 },
11951217
1218 // PCLMUL
1219 .{ .pclmulqdq, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x44 }, 0, .none, .pclmul },
1220
1221 // AES
1222 .{ .aesdec, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xde }, 0, .none, .aes },
1223
1224 .{ .aesdeclast, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdf }, 0, .none, .aes },
1225
1226 .{ .aesenc, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdc }, 0, .none, .aes },
1227
1228 .{ .aesenclast, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdd }, 0, .none, .aes },
1229
1230 .{ .aesimc, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdb }, 0, .none, .aes },
1231
1232 .{ .aeskeygenassist, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0xdf }, 0, .none, .aes },
1233
1234 // SHA
1235 .{ .sha256msg1, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x38, 0xcc }, 0, .none, .sha },
1236
1237 .{ .sha256msg2, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x38, 0xcd }, 0, .none, .sha },
1238
1239 .{ .sha256rnds2, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x38, 0xcb }, 0, .none, .sha },
1240 .{ .sha256rnds2, .rm0, &.{ .xmm, .xmm_m128, .xmm0 }, &.{ 0x0f, 0x38, 0xcb }, 0, .none, .sha },
1241
11961242 // AVX
11971243 .{ .vaddpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x58 }, 0, .vex_128_wig, .avx },
11981244 .{ .vaddpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x58 }, 0, .vex_256_wig, .avx },
......@@ -1204,6 +1250,18 @@ pub const table = [_]Entry{
12041250
12051251 .{ .vaddss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .vex_lig_wig, .avx },
12061252
1253 .{ .vaesdec, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xde }, 0, .vex_128_wig, .@"aes avx" },
1254
1255 .{ .vaesdeclast, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdf }, 0, .vex_128_wig, .@"aes avx" },
1256
1257 .{ .vaesenc, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdc }, 0, .vex_128_wig, .@"aes avx" },
1258
1259 .{ .vaesenclast, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdd }, 0, .vex_128_wig, .@"aes avx" },
1260
1261 .{ .vaesimc, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xdb }, 0, .vex_128_wig, .@"aes avx" },
1262
1263 .{ .vaeskeygenassist, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0xdf }, 0, .vex_128_wig, .@"aes avx" },
1264
12071265 .{ .vandnpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_128_wig, .avx },
12081266 .{ .vandnpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_256_wig, .avx },
12091267
......@@ -1436,10 +1494,14 @@ pub const table = [_]Entry{
14361494 .{ .vpaddusb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdc }, 0, .vex_128_wig, .avx },
14371495 .{ .vpaddusw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdd }, 0, .vex_128_wig, .avx },
14381496
1497 .{ .vpalignr, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0f }, 0, .vex_128_wig, .avx },
1498
14391499 .{ .vpand, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_128_wig, .avx },
14401500
14411501 .{ .vpandn, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_128_wig, .avx },
14421502
1503 .{ .vpclmulqdq, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x44 }, 0, .vex_128_wig, .@"pclmul avx" },
1504
14431505 .{ .vpcmpeqb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x74 }, 0, .vex_128_wig, .avx },
14441506 .{ .vpcmpeqw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x75 }, 0, .vex_128_wig, .avx },
14451507 .{ .vpcmpeqd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x76 }, 0, .vex_128_wig, .avx },
......@@ -1494,6 +1556,26 @@ pub const table = [_]Entry{
14941556
14951557 .{ .vpor, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_128_wig, .avx },
14961558
1559 .{ .vpshufd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x70 }, 0, .vex_128_wig, .avx },
1560
1561 .{ .vpshufhw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .vex_128_wig, .avx },
1562
1563 .{ .vpshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .vex_128_wig, .avx },
1564
1565 .{ .vpsllw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf1 }, 0, .vex_128_wig, .avx },
1566 .{ .vpsllw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 6, .vex_128_wig, .avx },
1567 .{ .vpslld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf2 }, 0, .vex_128_wig, .avx },
1568 .{ .vpslld, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 6, .vex_128_wig, .avx },
1569 .{ .vpsllq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf3 }, 0, .vex_128_wig, .avx },
1570 .{ .vpsllq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 6, .vex_128_wig, .avx },
1571
1572 .{ .vpslldq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 7, .vex_128_wig, .avx },
1573
1574 .{ .vpsraw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe1 }, 0, .vex_128_wig, .avx },
1575 .{ .vpsraw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 4, .vex_128_wig, .avx },
1576 .{ .vpsrad, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe2 }, 0, .vex_128_wig, .avx },
1577 .{ .vpsrad, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 4, .vex_128_wig, .avx },
1578
14971579 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },
14981580 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },
14991581 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },
......@@ -1501,6 +1583,8 @@ pub const table = [_]Entry{
15011583 .{ .vpsrlq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_128_wig, .avx },
15021584 .{ .vpsrlq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_128_wig, .avx },
15031585
1586 .{ .vpsrldq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 3, .vex_128_wig, .avx },
1587
15041588 .{ .vpsubb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf8 }, 0, .vex_128_wig, .avx },
15051589 .{ .vpsubw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf9 }, 0, .vex_128_wig, .avx },
15061590 .{ .vpsubd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfa }, 0, .vex_128_wig, .avx },
......@@ -1597,6 +1681,18 @@ pub const table = [_]Entry{
15971681 .{ .vfmadd213ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_lig_w0, .fma },
15981682 .{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w0, .fma },
15991683
1684 // VPCLMULQDQ
1685 .{ .vpclmulqdq, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x44 }, 0, .vex_256_wig, .vpclmulqdq },
1686
1687 // VAES
1688 .{ .vaesdec, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xde }, 0, .vex_256_wig, .vaes },
1689
1690 .{ .vaesdeclast, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xdf }, 0, .vex_256_wig, .vaes },
1691
1692 .{ .vaesenc, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xdc }, 0, .vex_256_wig, .vaes },
1693
1694 .{ .vaesenclast, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xdd }, 0, .vex_256_wig, .vaes },
1695
16001696 // AVX2
16011697 .{ .vbroadcastss, .rm, &.{ .xmm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx2 },
16021698 .{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },
......@@ -1624,6 +1720,8 @@ pub const table = [_]Entry{
16241720 .{ .vpaddusb, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdc }, 0, .vex_256_wig, .avx2 },
16251721 .{ .vpaddusw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdd }, 0, .vex_256_wig, .avx2 },
16261722
1723 .{ .vpalignr, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0f }, 0, .vex_256_wig, .avx2 },
1724
16271725 .{ .vpand, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_256_wig, .avx2 },
16281726
16291727 .{ .vpandn, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_256_wig, .avx2 },
......@@ -1669,6 +1767,26 @@ pub const table = [_]Entry{
16691767
16701768 .{ .vpor, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_256_wig, .avx2 },
16711769
1770 .{ .vpshufd, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x70 }, 0, .vex_256_wig, .avx2 },
1771
1772 .{ .vpshufhw, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .vex_256_wig, .avx2 },
1773
1774 .{ .vpshuflw, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .vex_256_wig, .avx2 },
1775
1776 .{ .vpsllw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf1 }, 0, .vex_256_wig, .avx2 },
1777 .{ .vpsllw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 6, .vex_256_wig, .avx2 },
1778 .{ .vpslld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf2 }, 0, .vex_256_wig, .avx2 },
1779 .{ .vpslld, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 6, .vex_256_wig, .avx2 },
1780 .{ .vpsllq, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xf3 }, 0, .vex_256_wig, .avx2 },
1781 .{ .vpsllq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 6, .vex_256_wig, .avx2 },
1782
1783 .{ .vpslldq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 7, .vex_256_wig, .avx2 },
1784
1785 .{ .vpsraw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe1 }, 0, .vex_256_wig, .avx2 },
1786 .{ .vpsraw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 4, .vex_256_wig, .avx2 },
1787 .{ .vpsrad, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xe2 }, 0, .vex_256_wig, .avx2 },
1788 .{ .vpsrad, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 4, .vex_256_wig, .avx2 },
1789
16721790 .{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
16731791 .{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
16741792 .{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
......@@ -1676,6 +1794,8 @@ pub const table = [_]Entry{
16761794 .{ .vpsrlq, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_256_wig, .avx2 },
16771795 .{ .vpsrlq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_256_wig, .avx2 },
16781796
1797 .{ .vpsrldq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 3, .vex_128_wig, .avx2 },
1798
16791799 .{ .vpsubb, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xf8 }, 0, .vex_256_wig, .avx2 },
16801800 .{ .vpsubw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xf9 }, 0, .vex_256_wig, .avx2 },
16811801 .{ .vpsubd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xfa }, 0, .vex_256_wig, .avx2 },
test/behavior/bitreverse.zig+1-1
......@@ -11,11 +11,11 @@ test "@bitReverse large exotic integer" {
1111
1212test "@bitReverse" {
1313 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
14 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1514 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
1615 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
1716 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1817 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
18 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
1919
2020 try comptime testBitReverse();
2121 try testBitReverse();
test/behavior/byteswap.zig+1-1
......@@ -4,11 +4,11 @@ const expect = std.testing.expect;
44
55test "@byteSwap integers" {
66 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
7 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
87 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
98 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
109 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
1110 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
11 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
1212
1313 const ByteSwapIntTest = struct {
1414 fn run() !void {
test/behavior/popcount.zig-1
......@@ -14,7 +14,6 @@ test "@popCount integers" {
1414}
1515
1616test "@popCount 128bit integer" {
17 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1817 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1918 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2019 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO