| ... | ... | @@ -4985,35 +4985,45 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, IrInst *source_in |
| 4985 | 4985 | return &instruction->base; |
| 4986 | 4986 | } |
| 4987 | 4987 | |
| 4988 | | static IrInstSrc *ir_build_wasm_memory_size_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node) { |
| 4988 | static IrInstSrc *ir_build_wasm_memory_size_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *index) { |
| 4989 | 4989 | IrInstSrcWasmMemorySize *instruction = ir_build_instruction<IrInstSrcWasmMemorySize>(irb, scope, source_node); |
| 4990 | instruction->index = index; |
| 4991 | |
| 4992 | ir_ref_instruction(index, irb->current_basic_block); |
| 4990 | 4993 | |
| 4991 | 4994 | return &instruction->base; |
| 4992 | 4995 | } |
| 4993 | 4996 | |
| 4994 | | static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, IrInst *source_instr) { |
| 4997 | static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, IrInst *source_instr, IrInstGen *index) { |
| 4995 | 4998 | IrInstGenWasmMemorySize *instruction = ir_build_inst_gen<IrInstGenWasmMemorySize>(&ira->new_irb, |
| 4996 | 4999 | source_instr->scope, source_instr->source_node); |
| 4997 | 5000 | instruction->base.value->type = ira->codegen->builtin_types.entry_i32; |
| 5001 | instruction->index = index; |
| 5002 | |
| 5003 | ir_ref_inst_gen(index); |
| 4998 | 5004 | |
| 4999 | 5005 | return &instruction->base; |
| 5000 | 5006 | } |
| 5001 | 5007 | |
| 5002 | | static IrInstSrc *ir_build_wasm_memory_grow_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *delta) { |
| 5008 | static IrInstSrc *ir_build_wasm_memory_grow_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *index, IrInstSrc *delta) { |
| 5003 | 5009 | IrInstSrcWasmMemoryGrow *instruction = ir_build_instruction<IrInstSrcWasmMemoryGrow>(irb, scope, source_node); |
| 5010 | instruction->index = index; |
| 5004 | 5011 | instruction->delta = delta; |
| 5005 | 5012 | |
| 5013 | ir_ref_instruction(index, irb->current_basic_block); |
| 5006 | 5014 | ir_ref_instruction(delta, irb->current_basic_block); |
| 5007 | 5015 | |
| 5008 | 5016 | return &instruction->base; |
| 5009 | 5017 | } |
| 5010 | 5018 | |
| 5011 | | static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, IrInst *source_instr, IrInstGen *delta) { |
| 5019 | static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, IrInst *source_instr, IrInstGen *index, IrInstGen *delta) { |
| 5012 | 5020 | IrInstGenWasmMemoryGrow *instruction = ir_build_inst_gen<IrInstGenWasmMemoryGrow>(&ira->new_irb, |
| 5013 | 5021 | source_instr->scope, source_instr->source_node); |
| 5014 | 5022 | instruction->base.value->type = ira->codegen->builtin_types.entry_i32; |
| 5023 | instruction->index = index; |
| 5015 | 5024 | instruction->delta = delta; |
| 5016 | 5025 | |
| 5026 | ir_ref_inst_gen(index); |
| 5017 | 5027 | ir_ref_inst_gen(delta); |
| 5018 | 5028 | |
| 5019 | 5029 | return &instruction->base; |
| ... | ... | @@ -6815,7 +6825,12 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod |
| 6815 | 6825 | } |
| 6816 | 6826 | case BuiltinFnIdWasmMemorySize: |
| 6817 | 6827 | { |
| 6818 | | IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(irb, scope, node); |
| 6828 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); |
| 6829 | IrInstSrc *arg0_value = ir_gen_node(irb, arg0_node, scope); |
| 6830 | if (arg0_value == irb->codegen->invalid_inst_src) |
| 6831 | return arg0_value; |
| 6832 | |
| 6833 | IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(irb, scope, node, arg0_value); |
| 6819 | 6834 | return ir_lval_wrap(irb, scope, ir_wasm_memory_size, lval, result_loc); |
| 6820 | 6835 | } |
| 6821 | 6836 | case BuiltinFnIdWasmMemoryGrow: |
| ... | ... | @@ -6825,7 +6840,12 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod |
| 6825 | 6840 | if (arg0_value == irb->codegen->invalid_inst_src) |
| 6826 | 6841 | return arg0_value; |
| 6827 | 6842 | |
| 6828 | | IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(irb, scope, node, arg0_value); |
| 6843 | AstNode *arg1_node = node->data.fn_call_expr.params.at(1); |
| 6844 | IrInstSrc *arg1_value = ir_gen_node(irb, arg1_node, scope); |
| 6845 | if (arg1_value == irb->codegen->invalid_inst_src) |
| 6846 | return arg1_value; |
| 6847 | |
| 6848 | IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(irb, scope, node, arg0_value, arg1_value); |
| 6829 | 6849 | return ir_lval_wrap(irb, scope, ir_wasm_memory_grow, lval, result_loc); |
| 6830 | 6850 | } |
| 6831 | 6851 | case BuiltinFnIdField: |
| ... | ... | @@ -27733,7 +27753,17 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInst |
| 27733 | 27753 | return ira->codegen->invalid_inst_gen; |
| 27734 | 27754 | } |
| 27735 | 27755 | |
| 27736 | | return ir_build_wasm_memory_size_gen(ira, &instruction->base.base); |
| 27756 | IrInstGen *index = instruction->index->child; |
| 27757 | if (type_is_invalid(index->value->type)) |
| 27758 | return ira->codegen->invalid_inst_gen; |
| 27759 | |
| 27760 | ZigType *i32_type = ira->codegen->builtin_types.entry_i32; |
| 27761 | |
| 27762 | IrInstGen *casted_index = ir_implicit_cast(ira, index, i32_type); |
| 27763 | if (type_is_invalid(casted_index->value->type)) |
| 27764 | return ira->codegen->invalid_inst_gen; |
| 27765 | |
| 27766 | return ir_build_wasm_memory_size_gen(ira, &instruction->base.base, casted_index); |
| 27737 | 27767 | } |
| 27738 | 27768 | |
| 27739 | 27769 | static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInstSrcWasmMemoryGrow *instruction) { |
| ... | ... | @@ -27744,17 +27774,25 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInst |
| 27744 | 27774 | return ira->codegen->invalid_inst_gen; |
| 27745 | 27775 | } |
| 27746 | 27776 | |
| 27747 | | IrInstGen *delta = instruction->delta->child; |
| 27748 | | if (type_is_invalid(delta->value->type)) |
| 27777 | IrInstGen *index = instruction->index->child; |
| 27778 | if (type_is_invalid(index->value->type)) |
| 27749 | 27779 | return ira->codegen->invalid_inst_gen; |
| 27750 | 27780 | |
| 27751 | 27781 | ZigType *i32_type = ira->codegen->builtin_types.entry_i32; |
| 27752 | 27782 | |
| 27783 | IrInstGen *casted_index = ir_implicit_cast(ira, index, i32_type); |
| 27784 | if (type_is_invalid(casted_index->value->type)) |
| 27785 | return ira->codegen->invalid_inst_gen; |
| 27786 | |
| 27787 | IrInstGen *delta = instruction->delta->child; |
| 27788 | if (type_is_invalid(delta->value->type)) |
| 27789 | return ira->codegen->invalid_inst_gen; |
| 27790 | |
| 27753 | 27791 | IrInstGen *casted_delta = ir_implicit_cast(ira, delta, i32_type); |
| 27754 | 27792 | if (type_is_invalid(casted_delta->value->type)) |
| 27755 | 27793 | return ira->codegen->invalid_inst_gen; |
| 27756 | 27794 | |
| 27757 | | return ir_build_wasm_memory_grow_gen(ira, &instruction->base.base, casted_delta); |
| 27795 | return ir_build_wasm_memory_grow_gen(ira, &instruction->base.base, casted_index, casted_delta); |
| 27758 | 27796 | } |
| 27759 | 27797 | |
| 27760 | 27798 | static IrInstGen *ir_analyze_instruction_breakpoint(IrAnalyze *ira, IrInstSrcBreakpoint *instruction) { |