authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-09-18 06:36:47+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-09-19 18:20:22-07:00
log916eaad1efe9256943fcab66d52b782b484aa98c
tree65bd1a25870a199fb760d759c3d319aa41121a3b
parenta463c369cd9d0fe10dae4af41bbf6f47c32ee085

std.Target: Update CPU models/features for LLVM 19.1.0.

3 files changed, 90 insertions(+), 1 deletions(-)

lib/std/Target/aarch64.zig+1-1
...@@ -2045,7 +2045,7 @@ pub const cpu = struct {...@@ -2045,7 +2045,7 @@ pub const cpu = struct {
2045 .sme2,2045 .sme2,
2046 .sme_f64f64,2046 .sme_f64f64,
2047 .sme_i16i64,2047 .sme_i16i64,
2048 .v9_2a,2048 .v8_7a,
2049 .zcm,2049 .zcm,
2050 .zcz,2050 .zcz,
2051 }),2051 }),
lib/std/Target/amdgpu.zig+12
...@@ -180,6 +180,7 @@ pub const Feature = enum {...@@ -180,6 +180,7 @@ pub const Feature = enum {
180 vgpr_index_mode,180 vgpr_index_mode,
181 vgpr_singleuse_hint,181 vgpr_singleuse_hint,
182 vmem_to_scalar_write_hazard,182 vmem_to_scalar_write_hazard,
183 vmem_write_vgpr_in_order,
183 volcanic_islands,184 volcanic_islands,
184 vop3_literal,185 vop3_literal,
185 vop3p,186 vop3p,
...@@ -605,6 +606,7 @@ pub const all_features = blk: {...@@ -605,6 +606,7 @@ pub const all_features = blk: {
605 .sdwa_sdst,606 .sdwa_sdst,
606 .unaligned_buffer_access,607 .unaligned_buffer_access,
607 .unaligned_ds_access,608 .unaligned_ds_access,
609 .vmem_write_vgpr_in_order,
608 .vop3_literal,610 .vop3_literal,
609 .vop3p,611 .vop3p,
610 .vscnt,612 .vscnt,
...@@ -675,6 +677,7 @@ pub const all_features = blk: {...@@ -675,6 +677,7 @@ pub const all_features = blk: {
675 .true16,677 .true16,
676 .unaligned_buffer_access,678 .unaligned_buffer_access,
677 .unaligned_ds_access,679 .unaligned_ds_access,
680 .vmem_write_vgpr_in_order,
678 .vop3_literal,681 .vop3_literal,
679 .vop3p,682 .vop3p,
680 .vopd,683 .vopd,
...@@ -791,6 +794,7 @@ pub const all_features = blk: {...@@ -791,6 +794,7 @@ pub const all_features = blk: {
791 .unaligned_buffer_access,794 .unaligned_buffer_access,
792 .unaligned_ds_access,795 .unaligned_ds_access,
793 .vgpr_index_mode,796 .vgpr_index_mode,
797 .vmem_write_vgpr_in_order,
794 .vop3p,798 .vop3p,
795 .wavefrontsize64,799 .wavefrontsize64,
796 .xnack_support,800 .xnack_support,
...@@ -1161,6 +1165,7 @@ pub const all_features = blk: {...@@ -1161,6 +1165,7 @@ pub const all_features = blk: {
1161 .s_memtime_inst,1165 .s_memtime_inst,
1162 .trig_reduced_range,1166 .trig_reduced_range,
1163 .unaligned_buffer_access,1167 .unaligned_buffer_access,
1168 .vmem_write_vgpr_in_order,
1164 .wavefrontsize64,1169 .wavefrontsize64,
1165 }),1170 }),
1166 };1171 };
...@@ -1209,6 +1214,7 @@ pub const all_features = blk: {...@@ -1209,6 +1214,7 @@ pub const all_features = blk: {
1209 .movrel,1214 .movrel,
1210 .s_memtime_inst,1215 .s_memtime_inst,
1211 .trig_reduced_range,1216 .trig_reduced_range,
1217 .vmem_write_vgpr_in_order,
1212 .wavefrontsize64,1218 .wavefrontsize64,
1213 }),1219 }),
1214 };1220 };
...@@ -1307,6 +1313,11 @@ pub const all_features = blk: {...@@ -1307,6 +1313,11 @@ pub const all_features = blk: {
1307 .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",1313 .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
1308 .dependencies = featureSet(&[_]Feature{}),1314 .dependencies = featureSet(&[_]Feature{}),
1309 };1315 };
1316 result[@intFromEnum(Feature.vmem_write_vgpr_in_order)] = .{
1317 .llvm_name = "vmem-write-vgpr-in-order",
1318 .description = "VMEM instructions of the same type write VGPR results in order",
1319 .dependencies = featureSet(&[_]Feature{}),
1320 };
1310 result[@intFromEnum(Feature.volcanic_islands)] = .{1321 result[@intFromEnum(Feature.volcanic_islands)] = .{
1311 .llvm_name = "volcanic-islands",1322 .llvm_name = "volcanic-islands",
1312 .description = "VOLCANIC_ISLANDS GPU generation",1323 .description = "VOLCANIC_ISLANDS GPU generation",
...@@ -1341,6 +1352,7 @@ pub const all_features = blk: {...@@ -1341,6 +1352,7 @@ pub const all_features = blk: {
1341 .trig_reduced_range,1352 .trig_reduced_range,
1342 .unaligned_buffer_access,1353 .unaligned_buffer_access,
1343 .vgpr_index_mode,1354 .vgpr_index_mode,
1355 .vmem_write_vgpr_in_order,
1344 .wavefrontsize64,1356 .wavefrontsize64,
1345 }),1357 }),
1346 };1358 };
lib/std/Target/x86.zig+77
...@@ -4819,4 +4819,81 @@ pub const cpu = struct {...@@ -4819,4 +4819,81 @@ pub const cpu = struct {
4819 .xsaves,4819 .xsaves,
4820 }),4820 }),
4821 };4821 };
4822 pub const znver5 = CpuModel{
4823 .name = "znver5",
4824 .llvm_name = "znver5",
4825 .features = featureSet(&[_]Feature{
4826 .@"64bit",
4827 .adx,
4828 .allow_light_256_bit,
4829 .avx512bf16,
4830 .avx512bitalg,
4831 .avx512cd,
4832 .avx512dq,
4833 .avx512ifma,
4834 .avx512vbmi,
4835 .avx512vbmi2,
4836 .avx512vl,
4837 .avx512vnni,
4838 .avx512vp2intersect,
4839 .avx512vpopcntdq,
4840 .avxvnni,
4841 .bmi,
4842 .bmi2,
4843 .branchfusion,
4844 .clflushopt,
4845 .clwb,
4846 .clzero,
4847 .cmov,
4848 .crc32,
4849 .cx16,
4850 .evex512,
4851 .fast_15bytenop,
4852 .fast_bextr,
4853 .fast_dpwssd,
4854 .fast_imm16,
4855 .fast_lzcnt,
4856 .fast_movbe,
4857 .fast_scalar_fsqrt,
4858 .fast_scalar_shift_masks,
4859 .fast_variable_perlane_shuffle,
4860 .fast_vector_fsqrt,
4861 .fsgsbase,
4862 .fsrm,
4863 .fxsr,
4864 .gfni,
4865 .idivq_to_divl,
4866 .invpcid,
4867 .lzcnt,
4868 .macrofusion,
4869 .mmx,
4870 .movbe,
4871 .movdir64b,
4872 .movdiri,
4873 .mwaitx,
4874 .nopl,
4875 .pku,
4876 .popcnt,
4877 .prefetchi,
4878 .prfchw,
4879 .rdpid,
4880 .rdpru,
4881 .rdrnd,
4882 .rdseed,
4883 .sahf,
4884 .sbb_dep_breaking,
4885 .sha,
4886 .shstk,
4887 .slow_shld,
4888 .sse4a,
4889 .vaes,
4890 .vpclmulqdq,
4891 .vzeroupper,
4892 .wbnoinvd,
4893 .x87,
4894 .xsavec,
4895 .xsaveopt,
4896 .xsaves,
4897 }),
4898 };
4822};4899};