Commit 936294e32ad3cb07b51d6753269f8ac7b13c5ffc | zig

author	Andrew Kelley <andrew@ziglang.org> 2022-01-26 20:51:59-05:00
committer	Andrew Kelley <andrew@ziglang.org> 2022-02-02 21:51:58-07:00
log	936294e32ad3cb07b51d6753269f8ac7b13c5ffc
tree	2e0b27497b256e1fc25c965882deacbe87e5ae6e
parent	7e61bdbaa48dcf3a280c5c9a6b10c26ef4f687d5

Merge pull request #10699 from motiejus/arm64

[linux headers] rename arm64 to aarch64

49 files changed, 1447 insertions(+), 1429 deletions(-)

lib
- libc
  - include
    aarch64-linux-any
    asm
    auxvec.h
    bitsperlong.h
    bpf_perf_event.h
    byteorder.h
    fcntl.h
    hwcap.h
    kvm.h
    mman.h
    param.h
    perf_regs.h
    posix_types.h
    ptrace.h
    setup.h
    sigcontext.h
    signal.h
    statfs.h
    sve_context.h
    ucontext.h
    unistd.h
    any-linux-any
    asm-generic
    poll.h
    drm
    virtgpu_drm.h
    linux
    byteorder
    big_endian.h
    little_endian.h
    if_ether.h
    mptcp.h
    nfc.h
    resource.h
    version.h
    arm64-linux-any
    asm
    auxvec.h
    bitsperlong.h
    bpf_perf_event.h
    byteorder.h
    fcntl.h
    hwcap.h
    kvm.h
    mman.h
    param.h
    perf_regs.h
    posix_types.h
    ptrace.h
    setup.h
    sigcontext.h
    signal.h
    statfs.h
    sve_context.h
    ucontext.h
    unistd.h
src
- target.zig
tools
- update-linux-headers.zig

lib/libc/include/aarch64-linux-any/asm/auxvec.h created+26

...	@@ -0,0 +1,26 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_AUXVEC_H
18	#define __ASM_AUXVEC_H
19
20	/* vDSO location */
21	#define AT_SYSINFO_EHDR 33
22	#define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */
23
24	#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
25
26	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/bitsperlong.h created+24

...	@@ -0,0 +1,24 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_BITSPERLONG_H
18	#define __ASM_BITSPERLONG_H
19
20	#define __BITS_PER_LONG 64
21
22	#include <asm-generic/bitsperlong.h>
23
24	#endif /* __ASM_BITSPERLONG_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/bpf_perf_event.h created+9

...	@@ -0,0 +1,9 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_BPF_PERF_EVENT_H__
3	#define __ASM_BPF_PERF_EVENT_H__
4
5	#include <asm/ptrace.h>
6
7	typedef struct user_pt_regs bpf_user_pt_regs_t;
8
9	#endif /* __ASM_BPF_PERF_EVENT_H__ */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/byteorder.h created+26

...	@@ -0,0 +1,26 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_BYTEORDER_H
18	#define __ASM_BYTEORDER_H
19
20	#ifdef __AARCH64EB__
21	#include <linux/byteorder/big_endian.h>
22	#else
23	#include <linux/byteorder/little_endian.h>
24	#endif
25
26	#endif /* __ASM_BYTEORDER_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/fcntl.h created+30

...	@@ -0,0 +1,30 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_FCNTL_H
18	#define __ASM_FCNTL_H
19
20	/*
21	* Using our own definitions for AArch32 (compat) support.
22	*/
23	#define O_DIRECTORY 040000 /* must be a directory */
24	#define O_NOFOLLOW 0100000 /* don't follow links */
25	#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
26	#define O_LARGEFILE 0400000
27
28	#include <asm-generic/fcntl.h>
29
30	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/hwcap.h created+80

...	@@ -0,0 +1,80 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_HWCAP_H
18	#define __ASM_HWCAP_H
19
20	/*
21	* HWCAP flags - for AT_HWCAP
22	*/
23	#define HWCAP_FP (1 << 0)
24	#define HWCAP_ASIMD (1 << 1)
25	#define HWCAP_EVTSTRM (1 << 2)
26	#define HWCAP_AES (1 << 3)
27	#define HWCAP_PMULL (1 << 4)
28	#define HWCAP_SHA1 (1 << 5)
29	#define HWCAP_SHA2 (1 << 6)
30	#define HWCAP_CRC32 (1 << 7)
31	#define HWCAP_ATOMICS (1 << 8)
32	#define HWCAP_FPHP (1 << 9)
33	#define HWCAP_ASIMDHP (1 << 10)
34	#define HWCAP_CPUID (1 << 11)
35	#define HWCAP_ASIMDRDM (1 << 12)
36	#define HWCAP_JSCVT (1 << 13)
37	#define HWCAP_FCMA (1 << 14)
38	#define HWCAP_LRCPC (1 << 15)
39	#define HWCAP_DCPOP (1 << 16)
40	#define HWCAP_SHA3 (1 << 17)
41	#define HWCAP_SM3 (1 << 18)
42	#define HWCAP_SM4 (1 << 19)
43	#define HWCAP_ASIMDDP (1 << 20)
44	#define HWCAP_SHA512 (1 << 21)
45	#define HWCAP_SVE (1 << 22)
46	#define HWCAP_ASIMDFHM (1 << 23)
47	#define HWCAP_DIT (1 << 24)
48	#define HWCAP_USCAT (1 << 25)
49	#define HWCAP_ILRCPC (1 << 26)
50	#define HWCAP_FLAGM (1 << 27)
51	#define HWCAP_SSBS (1 << 28)
52	#define HWCAP_SB (1 << 29)
53	#define HWCAP_PACA (1 << 30)
54	#define HWCAP_PACG (1UL << 31)
55
56	/*
57	* HWCAP2 flags - for AT_HWCAP2
58	*/
59	#define HWCAP2_DCPODP (1 << 0)
60	#define HWCAP2_SVE2 (1 << 1)
61	#define HWCAP2_SVEAES (1 << 2)
62	#define HWCAP2_SVEPMULL (1 << 3)
63	#define HWCAP2_SVEBITPERM (1 << 4)
64	#define HWCAP2_SVESHA3 (1 << 5)
65	#define HWCAP2_SVESM4 (1 << 6)
66	#define HWCAP2_FLAGM2 (1 << 7)
67	#define HWCAP2_FRINT (1 << 8)
68	#define HWCAP2_SVEI8MM (1 << 9)
69	#define HWCAP2_SVEF32MM (1 << 10)
70	#define HWCAP2_SVEF64MM (1 << 11)
71	#define HWCAP2_SVEBF16 (1 << 12)
72	#define HWCAP2_I8MM (1 << 13)
73	#define HWCAP2_BF16 (1 << 14)
74	#define HWCAP2_DGH (1 << 15)
75	#define HWCAP2_RNG (1 << 16)
76	#define HWCAP2_BTI (1 << 17)
77	#define HWCAP2_MTE (1 << 18)
78	#define HWCAP2_ECV (1 << 19)
79
80	#endif /* __ASM_HWCAP_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/kvm.h created+416

...	@@ -0,0 +1,416 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012,2013 - ARM Ltd
4	* Author: Marc Zyngier <marc.zyngier@arm.com>
5	*
6	* Derived from arch/arm/include/uapi/asm/kvm.h:
7	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
8	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
9	*
10	* This program is free software; you can redistribute it and/or modify
11	* it under the terms of the GNU General Public License version 2 as
12	* published by the Free Software Foundation.
13	*
14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
21	*/
22
23	#ifndef __ARM_KVM_H__
24	#define __ARM_KVM_H__
25
26	#define KVM_SPSR_EL1 0
27	#define KVM_SPSR_SVC KVM_SPSR_EL1
28	#define KVM_SPSR_ABT 1
29	#define KVM_SPSR_UND 2
30	#define KVM_SPSR_IRQ 3
31	#define KVM_SPSR_FIQ 4
32	#define KVM_NR_SPSR 5
33
34	#ifndef __ASSEMBLY__
35	#include <linux/psci.h>
36	#include <linux/types.h>
37	#include <asm/ptrace.h>
38	#include <asm/sve_context.h>
39
40	#define __KVM_HAVE_GUEST_DEBUG
41	#define __KVM_HAVE_IRQ_LINE
42	#define __KVM_HAVE_READONLY_MEM
43	#define __KVM_HAVE_VCPU_EVENTS
44
45	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
46
47	#define KVM_REG_SIZE(id) \
48	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
49
50	struct kvm_regs {
51	struct user_pt_regs regs; /* sp = sp_el0 */
52
53	__u64 sp_el1;
54	__u64 elr_el1;
55
56	__u64 spsr[KVM_NR_SPSR];
57
58	struct user_fpsimd_state fp_regs;
59	};
60
61	/*
62	* Supported CPU Targets - Adding a new target type is not recommended,
63	* unless there are some special registers not supported by the
64	* genericv8 syreg table.
65	*/
66	#define KVM_ARM_TARGET_AEM_V8 0
67	#define KVM_ARM_TARGET_FOUNDATION_V8 1
68	#define KVM_ARM_TARGET_CORTEX_A57 2
69	#define KVM_ARM_TARGET_XGENE_POTENZA 3
70	#define KVM_ARM_TARGET_CORTEX_A53 4
71	/* Generic ARM v8 target */
72	#define KVM_ARM_TARGET_GENERIC_V8 5
73
74	#define KVM_ARM_NUM_TARGETS 6
75
76	/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
77	#define KVM_ARM_DEVICE_TYPE_SHIFT 0
78	#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
79	#define KVM_ARM_DEVICE_ID_SHIFT 16
80	#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
81
82	/* Supported device IDs */
83	#define KVM_ARM_DEVICE_VGIC_V2 0
84
85	/* Supported VGIC address types */
86	#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
87	#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
88
89	#define KVM_VGIC_V2_DIST_SIZE 0x1000
90	#define KVM_VGIC_V2_CPU_SIZE 0x2000
91
92	/* Supported VGICv3 address types */
93	#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
94	#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
95	#define KVM_VGIC_ITS_ADDR_TYPE 4
96	#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
97
98	#define KVM_VGIC_V3_DIST_SIZE SZ_64K
99	#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
100	#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
101
102	#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
103	#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
104	#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
105	#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
106	#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
107	#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
108	#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
109
110	struct kvm_vcpu_init {
111	__u32 target;
112	__u32 features[7];
113	};
114
115	struct kvm_sregs {
116	};
117
118	struct kvm_fpu {
119	};
120
121	/*
122	* See v8 ARM ARM D7.3: Debug Registers
123	*
124	* The architectural limit is 16 debug registers of each type although
125	* in practice there are usually less (see ID_AA64DFR0_EL1).
126	*
127	* Although the control registers are architecturally defined as 32
128	* bits wide we use a 64 bit structure here to keep parity with
129	* KVM_GET/SET_ONE_REG behaviour which treats all system registers as
130	* 64 bit values. It also allows for the possibility of the
131	* architecture expanding the control registers without having to
132	* change the userspace ABI.
133	*/
134	#define KVM_ARM_MAX_DBG_REGS 16
135	struct kvm_guest_debug_arch {
136	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
137	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
138	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
139	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
140	};
141
142	struct kvm_debug_exit_arch {
143	__u32 hsr;
144	__u64 far; /* used for watchpoints */
145	};
146
147	/*
148	* Architecture specific defines for kvm_guest_debug->control
149	*/
150
151	#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
152	#define KVM_GUESTDBG_USE_HW (1 << 17)
153
154	struct kvm_sync_regs {
155	/* Used with KVM_CAP_ARM_USER_IRQ */
156	__u64 device_irq_level;
157	};
158
159	/*
160	* PMU filter structure. Describe a range of events with a particular
161	* action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
162	*/
163	struct kvm_pmu_event_filter {
164	__u16 base_event;
165	__u16 nevents;
166
167	#define KVM_PMU_EVENT_ALLOW 0
168	#define KVM_PMU_EVENT_DENY 1
169
170	__u8 action;
171	__u8 pad[3];
172	};
173
174	/* for KVM_GET/SET_VCPU_EVENTS */
175	struct kvm_vcpu_events {
176	struct {
177	__u8 serror_pending;
178	__u8 serror_has_esr;
179	__u8 ext_dabt_pending;
180	/* Align it to 8 bytes */
181	__u8 pad[5];
182	__u64 serror_esr;
183	} exception;
184	__u32 reserved[12];
185	};
186
187	struct kvm_arm_copy_mte_tags {
188	__u64 guest_ipa;
189	__u64 length;
190	void *addr;
191	__u64 flags;
192	__u64 reserved[2];
193	};
194
195	#define KVM_ARM_TAGS_TO_GUEST 0
196	#define KVM_ARM_TAGS_FROM_GUEST 1
197
198	/* If you need to interpret the index values, here is the key: */
199	#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
200	#define KVM_REG_ARM_COPROC_SHIFT 16
201
202	/* Normal registers are mapped as coprocessor 16. */
203	#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
204	#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
205
206	/* Some registers need more space to represent values. */
207	#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
208	#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
209	#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
210	#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
211	#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
212	#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
213
214	/* AArch64 system registers */
215	#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
216	#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
217	#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
218	#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
219	#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
220	#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
221	#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
222	#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
223	#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
224	#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
225	#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
226
227	#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
228	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
229	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
230
231	#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
232	(KVM_REG_ARM64 \| KVM_REG_ARM64_SYSREG \| \
233	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) \| \
234	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) \| \
235	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) \| \
236	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) \| \
237	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
238
239	#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) \| KVM_REG_SIZE_U64)
240
241	/* Physical Timer EL0 Registers */
242	#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
243	#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
244	#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
245
246	/*
247	* EL0 Virtual Timer Registers
248	*
249	* WARNING:
250	* KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
251	* with the appropriate register encodings. Their values have been
252	* accidentally swapped. As this is set API, the definitions here
253	* must be used, rather than ones derived from the encodings.
254	*/
255	#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
256	#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
257	#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
258
259	/* KVM-as-firmware specific pseudo-registers */
260	#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
261	#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
262	KVM_REG_ARM_FW \| ((r) & 0xffff))
263	#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
264	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
265	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
266	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
267	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
268
269	/*
270	* Only two states can be presented by the host kernel:
271	* - NOT_REQUIRED: the guest doesn't need to do anything
272	* - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
273	*
274	* All the other values are deprecated. The host still accepts all
275	* values (they are ABI), but will narrow them to the above two.
276	*/
277	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
278	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
279	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
280	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
281	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
282	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
283
284	/* SVE registers */
285	#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
286
287	/* Z- and P-regs occupy blocks at the following offsets within this range: */
288	#define KVM_REG_ARM64_SVE_ZREG_BASE 0
289	#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
290	#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
291
292	#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
293	#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
294
295	#define KVM_ARM64_SVE_MAX_SLICES 32
296
297	#define KVM_REG_ARM64_SVE_ZREG(n, i) \
298	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_ZREG_BASE \| \
299	KVM_REG_SIZE_U2048 \| \
300	(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) \| \
301	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
302
303	#define KVM_REG_ARM64_SVE_PREG(n, i) \
304	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_PREG_BASE \| \
305	KVM_REG_SIZE_U256 \| \
306	(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) \| \
307	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
308
309	#define KVM_REG_ARM64_SVE_FFR(i) \
310	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_FFR_BASE \| \
311	KVM_REG_SIZE_U256 \| \
312	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
313
314	/*
315	* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
316	* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
317	* invariant layout which differs from the layout used for the FPSIMD
318	* V-registers on big-endian systems: see sigcontext.h for more explanation.
319	*/
320
321	#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
322	#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
323
324	/* Vector lengths pseudo-register: */
325	#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| \
326	KVM_REG_SIZE_U512 \| 0xffff)
327	#define KVM_ARM64_SVE_VLS_WORDS \
328	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
329
330	/* Device Control API: ARM VGIC */
331	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
332	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
333	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
334	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
335	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
336	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
337	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
338	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
339	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
340	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
341	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
342	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
343	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
344	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
345	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
346	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
347	#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
348	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
349	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
350	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
351	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
352	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
353
354	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
355	#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
356	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
357	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
358	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
359
360	/* Device Control API on vcpu fd */
361	#define KVM_ARM_VCPU_PMU_V3_CTRL 0
362	#define KVM_ARM_VCPU_PMU_V3_IRQ 0
363	#define KVM_ARM_VCPU_PMU_V3_INIT 1
364	#define KVM_ARM_VCPU_PMU_V3_FILTER 2
365	#define KVM_ARM_VCPU_TIMER_CTRL 1
366	#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
367	#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
368	#define KVM_ARM_VCPU_PVTIME_CTRL 2
369	#define KVM_ARM_VCPU_PVTIME_IPA 0
370
371	/* KVM_IRQ_LINE irq field index values */
372	#define KVM_ARM_IRQ_VCPU2_SHIFT 28
373	#define KVM_ARM_IRQ_VCPU2_MASK 0xf
374	#define KVM_ARM_IRQ_TYPE_SHIFT 24
375	#define KVM_ARM_IRQ_TYPE_MASK 0xf
376	#define KVM_ARM_IRQ_VCPU_SHIFT 16
377	#define KVM_ARM_IRQ_VCPU_MASK 0xff
378	#define KVM_ARM_IRQ_NUM_SHIFT 0
379	#define KVM_ARM_IRQ_NUM_MASK 0xffff
380
381	/* irq_type field */
382	#define KVM_ARM_IRQ_TYPE_CPU 0
383	#define KVM_ARM_IRQ_TYPE_SPI 1
384	#define KVM_ARM_IRQ_TYPE_PPI 2
385
386	/* out-of-kernel GIC cpu interrupt injection irq_number field */
387	#define KVM_ARM_IRQ_CPU_IRQ 0
388	#define KVM_ARM_IRQ_CPU_FIQ 1
389
390	/*
391	* This used to hold the highest supported SPI, but it is now obsolete
392	* and only here to provide source code level compatibility with older
393	* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
394	*/
395	#define KVM_ARM_IRQ_GIC_MAX 127
396
397	/* One single KVM irqchip, ie. the VGIC */
398	#define KVM_NR_IRQCHIPS 1
399
400	/* PSCI interface */
401	#define KVM_PSCI_FN_BASE 0x95c1ba5e
402	#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
403
404	#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
405	#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
406	#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
407	#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
408
409	#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
410	#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
411	#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
412	#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
413
414	#endif
415
416	#endif /* __ARM_KVM_H__ */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/mman.h created+10

...	@@ -0,0 +1,10 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_MMAN_H
3	#define __ASM_MMAN_H
4
5	#include <asm-generic/mman.h>
6
7	#define PROT_BTI 0x10 /* BTI guarded page */
8	#define PROT_MTE 0x20 /* Normal Tagged mapping */
9
10	#endif /* ! _UAPI__ASM_MMAN_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/param.h created+24

...	@@ -0,0 +1,24 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_PARAM_H
18	#define __ASM_PARAM_H
19
20	#define EXEC_PAGESIZE 65536
21
22	#include <asm-generic/param.h>
23
24	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/perf_regs.h created+41

...	@@ -0,0 +1,41 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef _ASM_ARM64_PERF_REGS_H
3	#define _ASM_ARM64_PERF_REGS_H
4
5	enum perf_event_arm_regs {
6	PERF_REG_ARM64_X0,
7	PERF_REG_ARM64_X1,
8	PERF_REG_ARM64_X2,
9	PERF_REG_ARM64_X3,
10	PERF_REG_ARM64_X4,
11	PERF_REG_ARM64_X5,
12	PERF_REG_ARM64_X6,
13	PERF_REG_ARM64_X7,
14	PERF_REG_ARM64_X8,
15	PERF_REG_ARM64_X9,
16	PERF_REG_ARM64_X10,
17	PERF_REG_ARM64_X11,
18	PERF_REG_ARM64_X12,
19	PERF_REG_ARM64_X13,
20	PERF_REG_ARM64_X14,
21	PERF_REG_ARM64_X15,
22	PERF_REG_ARM64_X16,
23	PERF_REG_ARM64_X17,
24	PERF_REG_ARM64_X18,
25	PERF_REG_ARM64_X19,
26	PERF_REG_ARM64_X20,
27	PERF_REG_ARM64_X21,
28	PERF_REG_ARM64_X22,
29	PERF_REG_ARM64_X23,
30	PERF_REG_ARM64_X24,
31	PERF_REG_ARM64_X25,
32	PERF_REG_ARM64_X26,
33	PERF_REG_ARM64_X27,
34	PERF_REG_ARM64_X28,
35	PERF_REG_ARM64_X29,
36	PERF_REG_ARM64_LR,
37	PERF_REG_ARM64_SP,
38	PERF_REG_ARM64_PC,
39	PERF_REG_ARM64_MAX,
40	};
41	#endif /* _ASM_ARM64_PERF_REGS_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/posix_types.h created+11

...	@@ -0,0 +1,11 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_POSIX_TYPES_H
3	#define __ASM_POSIX_TYPES_H
4
5	typedef unsigned short __kernel_old_uid_t;
6	typedef unsigned short __kernel_old_gid_t;
7	#define __kernel_old_uid_t __kernel_old_uid_t
8
9	#include <asm-generic/posix_types.h>
10
11	#endif /* __ASM_POSIX_TYPES_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/ptrace.h created+270

...	@@ -0,0 +1,270 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Based on arch/arm/include/asm/ptrace.h
4	*
5	* Copyright (C) 1996-2003 Russell King
6	* Copyright (C) 2012 ARM Ltd.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License version 2 as
10	* published by the Free Software Foundation.
11	*
12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.
16	*
17	* You should have received a copy of the GNU General Public License
18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
19	*/
20	#ifndef __ASM_PTRACE_H
21	#define __ASM_PTRACE_H
22
23	#include <linux/types.h>
24
25	#include <asm/hwcap.h>
26	#include <asm/sve_context.h>
27
28
29	/*
30	* PSR bits
31	*/
32	#define PSR_MODE_EL0t 0x00000000
33	#define PSR_MODE_EL1t 0x00000004
34	#define PSR_MODE_EL1h 0x00000005
35	#define PSR_MODE_EL2t 0x00000008
36	#define PSR_MODE_EL2h 0x00000009
37	#define PSR_MODE_EL3t 0x0000000c
38	#define PSR_MODE_EL3h 0x0000000d
39	#define PSR_MODE_MASK 0x0000000f
40
41	/* AArch32 CPSR bits */
42	#define PSR_MODE32_BIT 0x00000010
43
44	/* AArch64 SPSR bits */
45	#define PSR_F_BIT 0x00000040
46	#define PSR_I_BIT 0x00000080
47	#define PSR_A_BIT 0x00000100
48	#define PSR_D_BIT 0x00000200
49	#define PSR_BTYPE_MASK 0x00000c00
50	#define PSR_SSBS_BIT 0x00001000
51	#define PSR_PAN_BIT 0x00400000
52	#define PSR_UAO_BIT 0x00800000
53	#define PSR_DIT_BIT 0x01000000
54	#define PSR_TCO_BIT 0x02000000
55	#define PSR_V_BIT 0x10000000
56	#define PSR_C_BIT 0x20000000
57	#define PSR_Z_BIT 0x40000000
58	#define PSR_N_BIT 0x80000000
59
60	#define PSR_BTYPE_SHIFT 10
61
62	/*
63	* Groups of PSR bits
64	*/
65	#define PSR_f 0xff000000 /* Flags */
66	#define PSR_s 0x00ff0000 /* Status */
67	#define PSR_x 0x0000ff00 /* Extension */
68	#define PSR_c 0x000000ff /* Control */
69
70	/* Convenience names for the values of PSTATE.BTYPE */
71	#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
72	#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
73	#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
74	#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
75
76	/* syscall emulation path in ptrace */
77	#define PTRACE_SYSEMU 31
78	#define PTRACE_SYSEMU_SINGLESTEP 32
79	/* MTE allocation tag access */
80	#define PTRACE_PEEKMTETAGS 33
81	#define PTRACE_POKEMTETAGS 34
82
83	#ifndef __ASSEMBLY__
84
85	/*
86	* User structures for general purpose, floating point and debug registers.
87	*/
88	struct user_pt_regs {
89	__u64 regs[31];
90	__u64 sp;
91	__u64 pc;
92	__u64 pstate;
93	};
94
95	struct user_fpsimd_state {
96	__uint128_t vregs[32];
97	__u32 fpsr;
98	__u32 fpcr;
99	__u32 __reserved[2];
100	};
101
102	struct user_hwdebug_state {
103	__u32 dbg_info;
104	__u32 pad;
105	struct {
106	__u64 addr;
107	__u32 ctrl;
108	__u32 pad;
109	} dbg_regs[16];
110	};
111
112	/* SVE/FP/SIMD state (NT_ARM_SVE) */
113
114	struct user_sve_header {
115	__u32 size; /* total meaningful regset content in bytes */
116	__u32 max_size; /* maxmium possible size for this thread */
117	__u16 vl; /* current vector length */
118	__u16 max_vl; /* maximum possible vector length */
119	__u16 flags;
120	__u16 __reserved;
121	};
122
123	/* Definitions for user_sve_header.flags: */
124	#define SVE_PT_REGS_MASK (1 << 0)
125
126	#define SVE_PT_REGS_FPSIMD 0
127	#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
128
129	/*
130	* Common SVE_PT_* flags:
131	* These must be kept in sync with prctl interface in <linux/prctl.h>
132	*/
133	#define SVE_PT_VL_INHERIT ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
134	#define SVE_PT_VL_ONEXEC ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
135
136
137	/*
138	* The remainder of the SVE state follows struct user_sve_header. The
139	* total size of the SVE state (including header) depends on the
140	* metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size
141	* of the state in bytes, including the header.
142	*
143	* Refer to <asm/sigcontext.h> for details of how to pass the correct
144	* "vq" argument to these macros.
145	*/
146
147	/* Offset from the start of struct user_sve_header to the register data */
148	#define SVE_PT_REGS_OFFSET \
149	((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) \
150	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
151
152	/*
153	* The register data content and layout depends on the value of the
154	* flags field.
155	*/
156
157	/*
158	* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
159	*
160	* The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
161	* struct user_fpsimd_state. Additional data might be appended in the
162	* future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
163	* SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
164	* sizeof(struct user_fpsimd_state).
165	*/
166
167	#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
168
169	#define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state))
170
171	/*
172	* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
173	*
174	* The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
175	* SVE_PT_SVE_SIZE(vq, flags).
176	*
177	* Additional macros describe the contents and layout of the payload.
178	* For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
179	* the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
180	* the size in bytes:
181	*
182	* x type description
183	* - ---- -----------
184	* ZREGS \
185	* ZREG \|
186	* PREGS \| refer to <asm/sigcontext.h>
187	* PREG \|
188	* FFR /
189	*
190	* FPSR uint32_t FPSR
191	* FPCR uint32_t FPCR
192	*
193	* Additional data might be appended in the future.
194	*
195	* The Z-, P- and FFR registers are represented in memory in an endianness-
196	* invariant layout which differs from the layout used for the FPSIMD
197	* V-registers on big-endian systems: see sigcontext.h for more explanation.
198	*/
199
200	#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
201	#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
202	#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
203	#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
204	#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
205
206	#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
207
208	#define SVE_PT_SVE_ZREGS_OFFSET \
209	(SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
210	#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
211	(SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
212	#define SVE_PT_SVE_ZREGS_SIZE(vq) \
213	(SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
214
215	#define SVE_PT_SVE_PREGS_OFFSET(vq) \
216	(SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
217	#define SVE_PT_SVE_PREG_OFFSET(vq, n) \
218	(SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
219	#define SVE_PT_SVE_PREGS_SIZE(vq) \
220	(SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
221	SVE_PT_SVE_PREGS_OFFSET(vq))
222
223	#define SVE_PT_SVE_FFR_OFFSET(vq) \
224	(SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
225
226	#define SVE_PT_SVE_FPSR_OFFSET(vq) \
227	((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \
228	(__SVE_VQ_BYTES - 1)) \
229	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
230	#define SVE_PT_SVE_FPCR_OFFSET(vq) \
231	(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
232
233	/*
234	* Any future extension appended after FPCR must be aligned to the next
235	* 128-bit boundary.
236	*/
237
238	#define SVE_PT_SVE_SIZE(vq, flags) \
239	((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \
240	- SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \
241	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
242
243	#define SVE_PT_SIZE(vq, flags) \
244	(((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \
245	SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
246	: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
247
248	/* pointer authentication masks (NT_ARM_PAC_MASK) */
249
250	struct user_pac_mask {
251	__u64 data_mask;
252	__u64 insn_mask;
253	};
254
255	/* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
256
257	struct user_pac_address_keys {
258	__uint128_t apiakey;
259	__uint128_t apibkey;
260	__uint128_t apdakey;
261	__uint128_t apdbkey;
262	};
263
264	struct user_pac_generic_keys {
265	__uint128_t apgakey;
266	};
267
268	#endif /* __ASSEMBLY__ */
269
270	#endif /* __ASM_PTRACE_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/setup.h created+27

...	@@ -0,0 +1,27 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Based on arch/arm/include/asm/setup.h
4	*
5	* Copyright (C) 1997-1999 Russell King
6	* Copyright (C) 2012 ARM Ltd.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License version 2 as
10	* published by the Free Software Foundation.
11	*
12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.
16	*
17	* You should have received a copy of the GNU General Public License
18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
19	*/
20	#ifndef __ASM_SETUP_H
21	#define __ASM_SETUP_H
22
23	#include <linux/types.h>
24
25	#define COMMAND_LINE_SIZE 2048
26
27	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/sigcontext.h created+252

...	@@ -0,0 +1,252 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_SIGCONTEXT_H
18	#define __ASM_SIGCONTEXT_H
19
20	#ifndef __ASSEMBLY__
21
22	#include <linux/types.h>
23
24	/*
25	* Signal context structure - contains all info to do with the state
26	* before the signal handler was invoked.
27	*/
28	struct sigcontext {
29	__u64 fault_address;
30	/* AArch64 registers */
31	__u64 regs[31];
32	__u64 sp;
33	__u64 pc;
34	__u64 pstate;
35	/* 4K reserved for FP/SIMD state and future expansion */
36	__u8 __reserved[4096] __attribute__((__aligned__(16)));
37	};
38
39	/*
40	* Allocation of __reserved[]:
41	* (Note: records do not necessarily occur in the order shown here.)
42	*
43	* size description
44	*
45	* 0x210 fpsimd_context
46	* 0x10 esr_context
47	* 0x8a0 sve_context (vl <= 64) (optional)
48	* 0x20 extra_context (optional)
49	* 0x10 terminator (null _aarch64_ctx)
50	*
51	* 0x510 (reserved for future allocation)
52	*
53	* New records that can exceed this space need to be opt-in for userspace, so
54	* that an expanded signal frame is not generated unexpectedly. The mechanism
55	* for opting in will depend on the extension that generates each new record.
56	* The above table documents the maximum set and sizes of records than can be
57	* generated when userspace does not opt in for any such extension.
58	*/
59
60	/*
61	* Header to be used at the beginning of structures extending the user
62	* context. Such structures must be placed after the rt_sigframe on the stack
63	* and be 16-byte aligned. The last structure must be a dummy one with the
64	* magic and size set to 0.
65	*/
66	struct _aarch64_ctx {
67	__u32 magic;
68	__u32 size;
69	};
70
71	#define FPSIMD_MAGIC 0x46508001
72
73	struct fpsimd_context {
74	struct _aarch64_ctx head;
75	__u32 fpsr;
76	__u32 fpcr;
77	__uint128_t vregs[32];
78	};
79
80	/*
81	* Note: similarly to all other integer fields, each V-register is stored in an
82	* endianness-dependent format, with the byte at offset i from the start of the
83	* in-memory representation of the register value containing
84	*
85	* bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
86	* bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
87	*/
88
89	/* ESR_EL1 context */
90	#define ESR_MAGIC 0x45535201
91
92	struct esr_context {
93	struct _aarch64_ctx head;
94	__u64 esr;
95	};
96
97	/*
98	* extra_context: describes extra space in the signal frame for
99	* additional structures that don't fit in sigcontext.__reserved[].
100	*
101	* Note:
102	*
103	* 1) fpsimd_context, esr_context and extra_context must be placed in
104	* sigcontext.__reserved[] if present. They cannot be placed in the
105	* extra space. Any other record can be placed either in the extra
106	* space or in sigcontext.__reserved[], unless otherwise specified in
107	* this file.
108	*
109	* 2) There must not be more than one extra_context.
110	*
111	* 3) If extra_context is present, it must be followed immediately in
112	* sigcontext.__reserved[] by the terminating null _aarch64_ctx.
113	*
114	* 4) The extra space to which datap points must start at the first
115	* 16-byte aligned address immediately after the terminating null
116	* _aarch64_ctx that follows the extra_context structure in
117	* __reserved[]. The extra space may overrun the end of __reserved[],
118	* as indicated by a sufficiently large value for the size field.
119	*
120	* 5) The extra space must itself be terminated with a null
121	* _aarch64_ctx.
122	*/
123	#define EXTRA_MAGIC 0x45585401
124
125	struct extra_context {
126	struct _aarch64_ctx head;
127	__u64 datap; /* 16-byte aligned pointer to extra space cast to __u64 */
128	__u32 size; /* size in bytes of the extra space */
129	__u32 __reserved[3];
130	};
131
132	#define SVE_MAGIC 0x53564501
133
134	struct sve_context {
135	struct _aarch64_ctx head;
136	__u16 vl;
137	__u16 __reserved[3];
138	};
139
140	#endif /* !__ASSEMBLY__ */
141
142	#include <asm/sve_context.h>
143
144	/*
145	* The SVE architecture leaves space for future expansion of the
146	* vector length beyond its initial architectural limit of 2048 bits
147	* (16 quadwords).
148	*
149	* See linux/Documentation/arm64/sve.rst for a description of the VL/VQ
150	* terminology.
151	*/
152	#define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */
153
154	#define SVE_VQ_MIN __SVE_VQ_MIN
155	#define SVE_VQ_MAX __SVE_VQ_MAX
156
157	#define SVE_VL_MIN __SVE_VL_MIN
158	#define SVE_VL_MAX __SVE_VL_MAX
159
160	#define SVE_NUM_ZREGS __SVE_NUM_ZREGS
161	#define SVE_NUM_PREGS __SVE_NUM_PREGS
162
163	#define sve_vl_valid(vl) __sve_vl_valid(vl)
164	#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl)
165	#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq)
166
167	/*
168	* If the SVE registers are currently live for the thread at signal delivery,
169	* sve_context.head.size >=
170	* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl))
171	* and the register data may be accessed using the SVE_SIG_*() macros.
172	*
173	* If sve_context.head.size <
174	* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)),
175	* the SVE registers were not live for the thread and no register data
176	* is included: in this case, the SVE_SIG_*() macros should not be
177	* used except for this check.
178	*
179	* The same convention applies when returning from a signal: a caller
180	* will need to remove or resize the sve_context block if it wants to
181	* make the SVE registers live when they were previously non-live or
182	* vice-versa. This may require the caller to allocate fresh
183	* memory and/or move other context blocks in the signal frame.
184	*
185	* Changing the vector length during signal return is not permitted:
186	* sve_context.vl must equal the thread's current vector length when
187	* doing a sigreturn.
188	*
189	*
190	* Note: for all these macros, the "vq" argument denotes the SVE
191	* vector length in quadwords (i.e., units of 128 bits).
192	*
193	* The correct way to obtain vq is to use sve_vq_from_vl(vl). The
194	* result is valid if and only if sve_vl_valid(vl) is true. This is
195	* guaranteed for a struct sve_context written by the kernel.
196	*
197	*
198	* Additional macros describe the contents and layout of the payload.
199	* For each, SVE_SIG_x_OFFSET(args) is the start offset relative to
200	* the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the
201	* size in bytes:
202	*
203	* x type description
204	* - ---- -----------
205	* REGS the entire SVE context
206	*
207	* ZREGS __uint128_t[SVE_NUM_ZREGS][vq] all Z-registers
208	* ZREG __uint128_t[vq] individual Z-register Zn
209	*
210	* PREGS uint16_t[SVE_NUM_PREGS][vq] all P-registers
211	* PREG uint16_t[vq] individual P-register Pn
212	*
213	* FFR uint16_t[vq] first-fault status register
214	*
215	* Additional data might be appended in the future.
216	*
217	* Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
218	* is encoded in memory in an endianness-invariant format, with the byte at
219	* offset i from the start of the in-memory representation containing bits
220	* [(7 + 8 * i) : (8 * i)] of the register value.
221	*/
222
223	#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
224	#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
225	#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
226
227	#define SVE_SIG_REGS_OFFSET \
228	((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) \
229	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
230
231	#define SVE_SIG_ZREGS_OFFSET \
232	(SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
233	#define SVE_SIG_ZREG_OFFSET(vq, n) \
234	(SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
235	#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
236
237	#define SVE_SIG_PREGS_OFFSET(vq) \
238	(SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
239	#define SVE_SIG_PREG_OFFSET(vq, n) \
240	(SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
241	#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
242
243	#define SVE_SIG_FFR_OFFSET(vq) \
244	(SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
245
246	#define SVE_SIG_REGS_SIZE(vq) \
247	(__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
248
249	#define SVE_SIG_CONTEXT_SIZE(vq) \
250	(SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
251
252	#endif /* __ASM_SIGCONTEXT_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/signal.h created+28

...	@@ -0,0 +1,28 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_SIGNAL_H
18	#define __ASM_SIGNAL_H
19
20	/* Required for AArch32 compatibility. */
21	#define SA_RESTORER 0x04000000
22
23	#define MINSIGSTKSZ 5120
24	#define SIGSTKSZ 16384
25
26	#include <asm-generic/signal.h>
27
28	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/statfs.h created+24

...	@@ -0,0 +1,24 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_STATFS_H
18	#define __ASM_STATFS_H
19
20	#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
21
22	#include <asm-generic/statfs.h>
23
24	#endif
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/sve_context.h created+53

...	@@ -0,0 +1,53 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/* Copyright (C) 2017-2018 ARM Limited */
3
4	/*
5	* For use by other UAPI headers only.
6	* Do not make direct use of header or its definitions.
7	*/
8
9	#ifndef __ASM_SVE_CONTEXT_H
10	#define __ASM_SVE_CONTEXT_H
11
12	#include <linux/types.h>
13
14	#define __SVE_VQ_BYTES 16 /* number of bytes per quadword */
15
16	#define __SVE_VQ_MIN 1
17	#define __SVE_VQ_MAX 512
18
19	#define __SVE_VL_MIN (__SVE_VQ_MIN * __SVE_VQ_BYTES)
20	#define __SVE_VL_MAX (__SVE_VQ_MAX * __SVE_VQ_BYTES)
21
22	#define __SVE_NUM_ZREGS 32
23	#define __SVE_NUM_PREGS 16
24
25	#define __sve_vl_valid(vl) \
26	((vl) % __SVE_VQ_BYTES == 0 && \
27	(vl) >= __SVE_VL_MIN && \
28	(vl) <= __SVE_VL_MAX)
29
30	#define __sve_vq_from_vl(vl) ((vl) / __SVE_VQ_BYTES)
31	#define __sve_vl_from_vq(vq) ((vq) * __SVE_VQ_BYTES)
32
33	#define __SVE_ZREG_SIZE(vq) ((__u32)(vq) * __SVE_VQ_BYTES)
34	#define __SVE_PREG_SIZE(vq) ((__u32)(vq) * (__SVE_VQ_BYTES / 8))
35	#define __SVE_FFR_SIZE(vq) __SVE_PREG_SIZE(vq)
36
37	#define __SVE_ZREGS_OFFSET 0
38	#define __SVE_ZREG_OFFSET(vq, n) \
39	(__SVE_ZREGS_OFFSET + __SVE_ZREG_SIZE(vq) * (n))
40	#define __SVE_ZREGS_SIZE(vq) \
41	(__SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - __SVE_ZREGS_OFFSET)
42
43	#define __SVE_PREGS_OFFSET(vq) \
44	(__SVE_ZREGS_OFFSET + __SVE_ZREGS_SIZE(vq))
45	#define __SVE_PREG_OFFSET(vq, n) \
46	(__SVE_PREGS_OFFSET(vq) + __SVE_PREG_SIZE(vq) * (n))
47	#define __SVE_PREGS_SIZE(vq) \
48	(__SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - __SVE_PREGS_OFFSET(vq))
49
50	#define __SVE_FFR_OFFSET(vq) \
51	(__SVE_PREGS_OFFSET(vq) + __SVE_PREGS_SIZE(vq))
52
53	#endif /* ! _UAPI__ASM_SVE_CONTEXT_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/ucontext.h created+33

...	@@ -0,0 +1,33 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_UCONTEXT_H
18	#define __ASM_UCONTEXT_H
19
20	#include <linux/types.h>
21
22	struct ucontext {
23	unsigned long uc_flags;
24	struct ucontext *uc_link;
25	stack_t uc_stack;
26	sigset_t uc_sigmask;
27	/* glibc uses a 1024-bit sigset_t */
28	__u8 __unused[1024 / 8 - sizeof(sigset_t)];
29	/* last for future expansion */
30	struct sigcontext uc_mcontext;
31	};
32
33	#endif /* __ASM_UCONTEXT_H */
	\ No newline at end of file

lib/libc/include/aarch64-linux-any/asm/unistd.h created+25

...	@@ -0,0 +1,25 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17
18	#define __ARCH_WANT_RENAMEAT
19	#define __ARCH_WANT_NEW_STAT
20	#define __ARCH_WANT_SET_GET_RLIMIT
21	#define __ARCH_WANT_TIME32_SYSCALLS
22	#define __ARCH_WANT_SYS_CLONE3
23	#define __ARCH_WANT_MEMFD_SECRET
24
25	#include <asm-generic/unistd.h>
	\ No newline at end of file

lib/libc/include/any-linux-any/asm-generic/poll.h+1-1

...	@@ -29,7 +29,7 @@	...	@@ -29,7 +29,7 @@
29	#define POLLRDHUP 0x2000	29	#define POLLRDHUP 0x2000
30	#endif	30	#endif
31		31
32	#define POLLFREE (__poll_t)0x4000 /* currently only for epoll */	32	#define POLLFREE (__poll_t)0x4000
33		33
34	#define POLL_BUSY_LOOP (__poll_t)0x8000	34	#define POLL_BUSY_LOOP (__poll_t)0x8000
35		35

lib/libc/include/any-linux-any/drm/virtgpu_drm.h+7

...	@@ -196,6 +196,13 @@ struct drm_virtgpu_context_init {	...	@@ -196,6 +196,13 @@ struct drm_virtgpu_context_init {
196	__u64 ctx_set_params;	196	__u64 ctx_set_params;
197	};	197	};
198		198
		199	/*
		200	* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
		201	* effect. The event size is sizeof(drm_event), since there is no additional
		202	* payload.
		203	*/
		204	#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
		205
199	#define DRM_IOCTL_VIRTGPU_MAP \	206	#define DRM_IOCTL_VIRTGPU_MAP \
200	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)	207	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
201		208

lib/libc/include/any-linux-any/linux/byteorder/big_endian.h+1

...	@@ -9,6 +9,7 @@	...	@@ -9,6 +9,7 @@
9	#define __BIG_ENDIAN_BITFIELD	9	#define __BIG_ENDIAN_BITFIELD
10	#endif	10	#endif
11		11
		12	#include <linux/stddef.h>
12	#include <linux/types.h>	13	#include <linux/types.h>
13	#include <linux/swab.h>	14	#include <linux/swab.h>
14		15

lib/libc/include/any-linux-any/linux/byteorder/little_endian.h+1

...	@@ -9,6 +9,7 @@	...	@@ -9,6 +9,7 @@
9	#define __LITTLE_ENDIAN_BITFIELD	9	#define __LITTLE_ENDIAN_BITFIELD
10	#endif	10	#endif
11		11
		12	#include <linux/stddef.h>
12	#include <linux/types.h>	13	#include <linux/types.h>
13	#include <linux/swab.h>	14	#include <linux/swab.h>
14		15

lib/libc/include/any-linux-any/linux/if_ether.h+1-1

...	@@ -117,7 +117,7 @@	...	@@ -117,7 +117,7 @@
117	#define ETH_P_IFE 0xED3E /* ForCES inter-FE LFB type */	117	#define ETH_P_IFE 0xED3E /* ForCES inter-FE LFB type */
118	#define ETH_P_AF_IUCV 0xFBFB /* IBM af_iucv [ NOT AN OFFICIALLY REGISTERED ID ] */	118	#define ETH_P_AF_IUCV 0xFBFB /* IBM af_iucv [ NOT AN OFFICIALLY REGISTERED ID ] */
119		119
120	#define ETH_P_802_3_MIN 0x0600 /* If the value in the ethernet type is less than this value	120	#define ETH_P_802_3_MIN 0x0600 /* If the value in the ethernet type is more than this value
121	* then the frame is Ethernet II. Else it is 802.3 */	121	* then the frame is Ethernet II. Else it is 802.3 */
122		122
123	/*	123	/*

lib/libc/include/any-linux-any/linux/mptcp.h+10-8

 @@ -134,19 +134,21 @@ struct mptcp_info {
  * MPTCP_EVENT_REMOVED: token, rem_id
  * An address has been lost by the peer.
  *
- * MPTCP_EVENT_SUB_ESTABLISHED: token, family, saddr4 | saddr6,
+ * MPTCP_EVENT_SUB_ESTABLISHED: token, family, loc_id, rem_id,
- *                              daddr4 | daddr6, sport, dport, backup,
+ *                              saddr4 | saddr6, daddr4 | daddr6, sport,
- *                              if_idx [, error]
+ *                              dport, backup, if_idx [, error]
  * A new subflow has been established. 'error' should not be set.
  *
- * MPTCP_EVENT_SUB_CLOSED: token, family, saddr4 | saddr6, daddr4 | daddr6,
+ * MPTCP_EVENT_SUB_CLOSED: token, family, loc_id, rem_id, saddr4 | saddr6,
- *                         sport, dport, backup, if_idx [, error]
+ *                         daddr4 | daddr6, sport, dport, backup, if_idx
+ *                         [, error]
  * A subflow has been closed. An error (copy of sk_err) could be set if an
  * error has been detected for this subflow.
  *
- * MPTCP_EVENT_SUB_PRIORITY: token, family, saddr4 | saddr6, daddr4 | daddr6,
+ * MPTCP_EVENT_SUB_PRIORITY: token, family, loc_id, rem_id, saddr4 | saddr6,
- *                           sport, dport, backup, if_idx [, error]
+ *                           daddr4 | daddr6, sport, dport, backup, if_idx
- *       The priority of a subflow has changed. 'error' should not be set.
+ *                           [, error]
+ * The priority of a subflow has changed. 'error' should not be set.
  */
 enum mptcp_event_type {
 	MPTCP_EVENT_UNSPEC = 0,

lib/libc/include/any-linux-any/linux/nfc.h+3-3

...	@@ -263,7 +263,7 @@ enum nfc_sdp_attr {	...	@@ -263,7 +263,7 @@ enum nfc_sdp_attr {
263	#define NFC_SE_ENABLED 0x1	263	#define NFC_SE_ENABLED 0x1
264		264
265	struct sockaddr_nfc {	265	struct sockaddr_nfc {
266	sa_family_t sa_family;	266	__kernel_sa_family_t sa_family;
267	__u32 dev_idx;	267	__u32 dev_idx;
268	__u32 target_idx;	268	__u32 target_idx;
269	__u32 nfc_protocol;	269	__u32 nfc_protocol;
...	@@ -271,14 +271,14 @@ struct sockaddr_nfc {	...	@@ -271,14 +271,14 @@ struct sockaddr_nfc {
271		271
272	#define NFC_LLCP_MAX_SERVICE_NAME 63	272	#define NFC_LLCP_MAX_SERVICE_NAME 63
273	struct sockaddr_nfc_llcp {	273	struct sockaddr_nfc_llcp {
274	sa_family_t sa_family;	274	__kernel_sa_family_t sa_family;
275	__u32 dev_idx;	275	__u32 dev_idx;
276	__u32 target_idx;	276	__u32 target_idx;
277	__u32 nfc_protocol;	277	__u32 nfc_protocol;
278	__u8 dsap; /* Destination SAP, if known */	278	__u8 dsap; /* Destination SAP, if known */
279	__u8 ssap; /* Source SAP to be bound to */	279	__u8 ssap; /* Source SAP to be bound to */
280	char service_name[NFC_LLCP_MAX_SERVICE_NAME]; /* Service name URI */;	280	char service_name[NFC_LLCP_MAX_SERVICE_NAME]; /* Service name URI */;
281	size_t service_name_len;	281	__kernel_size_t service_name_len;
282	};	282	};
283		283
284	/* NFC socket protocols */	284	/* NFC socket protocols */

lib/libc/include/any-linux-any/linux/resource.h+10-3

 @@ -66,10 +66,17 @@ struct rlimit64 {
 #define _STK_LIM	(8*1024*1024)
 /*
- * GPG2 wants 64kB of mlocked memory, to make sure pass phrases
+ * Limit the amount of locked memory by some sane default:
- * and other sensitive information are never written to disk.
+ * root can always increase this limit if needed.
+ *
+ * The main use-cases are (1) preventing sensitive memory
+ * from being swapped; (2) real-time operations; (3) via
+ * IOURING_REGISTER_BUFFERS.
+ *
+ * The first two don't need much. The latter will take as
+ * much as it can get. 8MB is a reasonably sane default.
  */
-#define MLOCK_LIMIT	((PAGE_SIZE > 64*1024) ? PAGE_SIZE : 64*1024)
+#define MLOCK_LIMIT	(8*1024*1024)
 /*
  * Due to binary compatibility, the actual resource numbers

lib/libc/include/any-linux-any/linux/version.h+2-2

...	@@ -1,5 +1,5 @@	...	@@ -1,5 +1,5 @@
1	#define LINUX_VERSION_CODE 331776	1	#define LINUX_VERSION_CODE 331778
2	#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + ((c) > 255 ? 255 : (c)))	2	#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + ((c) > 255 ? 255 : (c)))
3	#define LINUX_VERSION_MAJOR 5	3	#define LINUX_VERSION_MAJOR 5
4	#define LINUX_VERSION_PATCHLEVEL 16	4	#define LINUX_VERSION_PATCHLEVEL 16
5	#define LINUX_VERSION_SUBLEVEL 0
	\ No newline at end of file
		5	#define LINUX_VERSION_SUBLEVEL 2
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/auxvec.h deleted-26

...	@@ -1,26 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_AUXVEC_H
18	#define __ASM_AUXVEC_H
19
20	/* vDSO location */
21	#define AT_SYSINFO_EHDR 33
22	#define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */
23
24	#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
25
26	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/bitsperlong.h deleted-24

...	@@ -1,24 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_BITSPERLONG_H
18	#define __ASM_BITSPERLONG_H
19
20	#define __BITS_PER_LONG 64
21
22	#include <asm-generic/bitsperlong.h>
23
24	#endif /* __ASM_BITSPERLONG_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/bpf_perf_event.h deleted-9

...	@@ -1,9 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_BPF_PERF_EVENT_H__
3	#define __ASM_BPF_PERF_EVENT_H__
4
5	#include <asm/ptrace.h>
6
7	typedef struct user_pt_regs bpf_user_pt_regs_t;
8
9	#endif /* __ASM_BPF_PERF_EVENT_H__ */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/byteorder.h deleted-26

...	@@ -1,26 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_BYTEORDER_H
18	#define __ASM_BYTEORDER_H
19
20	#ifdef __AARCH64EB__
21	#include <linux/byteorder/big_endian.h>
22	#else
23	#include <linux/byteorder/little_endian.h>
24	#endif
25
26	#endif /* __ASM_BYTEORDER_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/fcntl.h deleted-30

...	@@ -1,30 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_FCNTL_H
18	#define __ASM_FCNTL_H
19
20	/*
21	* Using our own definitions for AArch32 (compat) support.
22	*/
23	#define O_DIRECTORY 040000 /* must be a directory */
24	#define O_NOFOLLOW 0100000 /* don't follow links */
25	#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
26	#define O_LARGEFILE 0400000
27
28	#include <asm-generic/fcntl.h>
29
30	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/hwcap.h deleted-80

...	@@ -1,80 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_HWCAP_H
18	#define __ASM_HWCAP_H
19
20	/*
21	* HWCAP flags - for AT_HWCAP
22	*/
23	#define HWCAP_FP (1 << 0)
24	#define HWCAP_ASIMD (1 << 1)
25	#define HWCAP_EVTSTRM (1 << 2)
26	#define HWCAP_AES (1 << 3)
27	#define HWCAP_PMULL (1 << 4)
28	#define HWCAP_SHA1 (1 << 5)
29	#define HWCAP_SHA2 (1 << 6)
30	#define HWCAP_CRC32 (1 << 7)
31	#define HWCAP_ATOMICS (1 << 8)
32	#define HWCAP_FPHP (1 << 9)
33	#define HWCAP_ASIMDHP (1 << 10)
34	#define HWCAP_CPUID (1 << 11)
35	#define HWCAP_ASIMDRDM (1 << 12)
36	#define HWCAP_JSCVT (1 << 13)
37	#define HWCAP_FCMA (1 << 14)
38	#define HWCAP_LRCPC (1 << 15)
39	#define HWCAP_DCPOP (1 << 16)
40	#define HWCAP_SHA3 (1 << 17)
41	#define HWCAP_SM3 (1 << 18)
42	#define HWCAP_SM4 (1 << 19)
43	#define HWCAP_ASIMDDP (1 << 20)
44	#define HWCAP_SHA512 (1 << 21)
45	#define HWCAP_SVE (1 << 22)
46	#define HWCAP_ASIMDFHM (1 << 23)
47	#define HWCAP_DIT (1 << 24)
48	#define HWCAP_USCAT (1 << 25)
49	#define HWCAP_ILRCPC (1 << 26)
50	#define HWCAP_FLAGM (1 << 27)
51	#define HWCAP_SSBS (1 << 28)
52	#define HWCAP_SB (1 << 29)
53	#define HWCAP_PACA (1 << 30)
54	#define HWCAP_PACG (1UL << 31)
55
56	/*
57	* HWCAP2 flags - for AT_HWCAP2
58	*/
59	#define HWCAP2_DCPODP (1 << 0)
60	#define HWCAP2_SVE2 (1 << 1)
61	#define HWCAP2_SVEAES (1 << 2)
62	#define HWCAP2_SVEPMULL (1 << 3)
63	#define HWCAP2_SVEBITPERM (1 << 4)
64	#define HWCAP2_SVESHA3 (1 << 5)
65	#define HWCAP2_SVESM4 (1 << 6)
66	#define HWCAP2_FLAGM2 (1 << 7)
67	#define HWCAP2_FRINT (1 << 8)
68	#define HWCAP2_SVEI8MM (1 << 9)
69	#define HWCAP2_SVEF32MM (1 << 10)
70	#define HWCAP2_SVEF64MM (1 << 11)
71	#define HWCAP2_SVEBF16 (1 << 12)
72	#define HWCAP2_I8MM (1 << 13)
73	#define HWCAP2_BF16 (1 << 14)
74	#define HWCAP2_DGH (1 << 15)
75	#define HWCAP2_RNG (1 << 16)
76	#define HWCAP2_BTI (1 << 17)
77	#define HWCAP2_MTE (1 << 18)
78	#define HWCAP2_ECV (1 << 19)
79
80	#endif /* __ASM_HWCAP_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/kvm.h deleted-416

...	@@ -1,416 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012,2013 - ARM Ltd
4	* Author: Marc Zyngier <marc.zyngier@arm.com>
5	*
6	* Derived from arch/arm/include/uapi/asm/kvm.h:
7	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
8	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
9	*
10	* This program is free software; you can redistribute it and/or modify
11	* it under the terms of the GNU General Public License version 2 as
12	* published by the Free Software Foundation.
13	*
14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
21	*/
22
23	#ifndef __ARM_KVM_H__
24	#define __ARM_KVM_H__
25
26	#define KVM_SPSR_EL1 0
27	#define KVM_SPSR_SVC KVM_SPSR_EL1
28	#define KVM_SPSR_ABT 1
29	#define KVM_SPSR_UND 2
30	#define KVM_SPSR_IRQ 3
31	#define KVM_SPSR_FIQ 4
32	#define KVM_NR_SPSR 5
33
34	#ifndef __ASSEMBLY__
35	#include <linux/psci.h>
36	#include <linux/types.h>
37	#include <asm/ptrace.h>
38	#include <asm/sve_context.h>
39
40	#define __KVM_HAVE_GUEST_DEBUG
41	#define __KVM_HAVE_IRQ_LINE
42	#define __KVM_HAVE_READONLY_MEM
43	#define __KVM_HAVE_VCPU_EVENTS
44
45	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
46
47	#define KVM_REG_SIZE(id) \
48	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
49
50	struct kvm_regs {
51	struct user_pt_regs regs; /* sp = sp_el0 */
52
53	__u64 sp_el1;
54	__u64 elr_el1;
55
56	__u64 spsr[KVM_NR_SPSR];
57
58	struct user_fpsimd_state fp_regs;
59	};
60
61	/*
62	* Supported CPU Targets - Adding a new target type is not recommended,
63	* unless there are some special registers not supported by the
64	* genericv8 syreg table.
65	*/
66	#define KVM_ARM_TARGET_AEM_V8 0
67	#define KVM_ARM_TARGET_FOUNDATION_V8 1
68	#define KVM_ARM_TARGET_CORTEX_A57 2
69	#define KVM_ARM_TARGET_XGENE_POTENZA 3
70	#define KVM_ARM_TARGET_CORTEX_A53 4
71	/* Generic ARM v8 target */
72	#define KVM_ARM_TARGET_GENERIC_V8 5
73
74	#define KVM_ARM_NUM_TARGETS 6
75
76	/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
77	#define KVM_ARM_DEVICE_TYPE_SHIFT 0
78	#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
79	#define KVM_ARM_DEVICE_ID_SHIFT 16
80	#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
81
82	/* Supported device IDs */
83	#define KVM_ARM_DEVICE_VGIC_V2 0
84
85	/* Supported VGIC address types */
86	#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
87	#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
88
89	#define KVM_VGIC_V2_DIST_SIZE 0x1000
90	#define KVM_VGIC_V2_CPU_SIZE 0x2000
91
92	/* Supported VGICv3 address types */
93	#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
94	#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
95	#define KVM_VGIC_ITS_ADDR_TYPE 4
96	#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
97
98	#define KVM_VGIC_V3_DIST_SIZE SZ_64K
99	#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
100	#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
101
102	#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
103	#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
104	#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
105	#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
106	#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
107	#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
108	#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
109
110	struct kvm_vcpu_init {
111	__u32 target;
112	__u32 features[7];
113	};
114
115	struct kvm_sregs {
116	};
117
118	struct kvm_fpu {
119	};
120
121	/*
122	* See v8 ARM ARM D7.3: Debug Registers
123	*
124	* The architectural limit is 16 debug registers of each type although
125	* in practice there are usually less (see ID_AA64DFR0_EL1).
126	*
127	* Although the control registers are architecturally defined as 32
128	* bits wide we use a 64 bit structure here to keep parity with
129	* KVM_GET/SET_ONE_REG behaviour which treats all system registers as
130	* 64 bit values. It also allows for the possibility of the
131	* architecture expanding the control registers without having to
132	* change the userspace ABI.
133	*/
134	#define KVM_ARM_MAX_DBG_REGS 16
135	struct kvm_guest_debug_arch {
136	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
137	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
138	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
139	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
140	};
141
142	struct kvm_debug_exit_arch {
143	__u32 hsr;
144	__u64 far; /* used for watchpoints */
145	};
146
147	/*
148	* Architecture specific defines for kvm_guest_debug->control
149	*/
150
151	#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
152	#define KVM_GUESTDBG_USE_HW (1 << 17)
153
154	struct kvm_sync_regs {
155	/* Used with KVM_CAP_ARM_USER_IRQ */
156	__u64 device_irq_level;
157	};
158
159	/*
160	* PMU filter structure. Describe a range of events with a particular
161	* action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
162	*/
163	struct kvm_pmu_event_filter {
164	__u16 base_event;
165	__u16 nevents;
166
167	#define KVM_PMU_EVENT_ALLOW 0
168	#define KVM_PMU_EVENT_DENY 1
169
170	__u8 action;
171	__u8 pad[3];
172	};
173
174	/* for KVM_GET/SET_VCPU_EVENTS */
175	struct kvm_vcpu_events {
176	struct {
177	__u8 serror_pending;
178	__u8 serror_has_esr;
179	__u8 ext_dabt_pending;
180	/* Align it to 8 bytes */
181	__u8 pad[5];
182	__u64 serror_esr;
183	} exception;
184	__u32 reserved[12];
185	};
186
187	struct kvm_arm_copy_mte_tags {
188	__u64 guest_ipa;
189	__u64 length;
190	void *addr;
191	__u64 flags;
192	__u64 reserved[2];
193	};
194
195	#define KVM_ARM_TAGS_TO_GUEST 0
196	#define KVM_ARM_TAGS_FROM_GUEST 1
197
198	/* If you need to interpret the index values, here is the key: */
199	#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
200	#define KVM_REG_ARM_COPROC_SHIFT 16
201
202	/* Normal registers are mapped as coprocessor 16. */
203	#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
204	#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
205
206	/* Some registers need more space to represent values. */
207	#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
208	#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
209	#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
210	#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
211	#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
212	#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
213
214	/* AArch64 system registers */
215	#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
216	#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
217	#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
218	#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
219	#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
220	#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
221	#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
222	#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
223	#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
224	#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
225	#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
226
227	#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
228	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
229	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
230
231	#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
232	(KVM_REG_ARM64 \| KVM_REG_ARM64_SYSREG \| \
233	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) \| \
234	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) \| \
235	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) \| \
236	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) \| \
237	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
238
239	#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) \| KVM_REG_SIZE_U64)
240
241	/* Physical Timer EL0 Registers */
242	#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
243	#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
244	#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
245
246	/*
247	* EL0 Virtual Timer Registers
248	*
249	* WARNING:
250	* KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
251	* with the appropriate register encodings. Their values have been
252	* accidentally swapped. As this is set API, the definitions here
253	* must be used, rather than ones derived from the encodings.
254	*/
255	#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
256	#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
257	#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
258
259	/* KVM-as-firmware specific pseudo-registers */
260	#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
261	#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
262	KVM_REG_ARM_FW \| ((r) & 0xffff))
263	#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
264	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
265	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
266	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
267	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
268
269	/*
270	* Only two states can be presented by the host kernel:
271	* - NOT_REQUIRED: the guest doesn't need to do anything
272	* - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
273	*
274	* All the other values are deprecated. The host still accepts all
275	* values (they are ABI), but will narrow them to the above two.
276	*/
277	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
278	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
279	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
280	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
281	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
282	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
283
284	/* SVE registers */
285	#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
286
287	/* Z- and P-regs occupy blocks at the following offsets within this range: */
288	#define KVM_REG_ARM64_SVE_ZREG_BASE 0
289	#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
290	#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
291
292	#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
293	#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
294
295	#define KVM_ARM64_SVE_MAX_SLICES 32
296
297	#define KVM_REG_ARM64_SVE_ZREG(n, i) \
298	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_ZREG_BASE \| \
299	KVM_REG_SIZE_U2048 \| \
300	(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) \| \
301	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
302
303	#define KVM_REG_ARM64_SVE_PREG(n, i) \
304	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_PREG_BASE \| \
305	KVM_REG_SIZE_U256 \| \
306	(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) \| \
307	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
308
309	#define KVM_REG_ARM64_SVE_FFR(i) \
310	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_FFR_BASE \| \
311	KVM_REG_SIZE_U256 \| \
312	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
313
314	/*
315	* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
316	* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
317	* invariant layout which differs from the layout used for the FPSIMD
318	* V-registers on big-endian systems: see sigcontext.h for more explanation.
319	*/
320
321	#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
322	#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
323
324	/* Vector lengths pseudo-register: */
325	#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| \
326	KVM_REG_SIZE_U512 \| 0xffff)
327	#define KVM_ARM64_SVE_VLS_WORDS \
328	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
329
330	/* Device Control API: ARM VGIC */
331	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
332	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
333	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
334	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
335	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
336	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
337	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
338	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
339	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
340	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
341	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
342	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
343	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
344	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
345	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
346	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
347	#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
348	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
349	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
350	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
351	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
352	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
353
354	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
355	#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
356	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
357	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
358	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
359
360	/* Device Control API on vcpu fd */
361	#define KVM_ARM_VCPU_PMU_V3_CTRL 0
362	#define KVM_ARM_VCPU_PMU_V3_IRQ 0
363	#define KVM_ARM_VCPU_PMU_V3_INIT 1
364	#define KVM_ARM_VCPU_PMU_V3_FILTER 2
365	#define KVM_ARM_VCPU_TIMER_CTRL 1
366	#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
367	#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
368	#define KVM_ARM_VCPU_PVTIME_CTRL 2
369	#define KVM_ARM_VCPU_PVTIME_IPA 0
370
371	/* KVM_IRQ_LINE irq field index values */
372	#define KVM_ARM_IRQ_VCPU2_SHIFT 28
373	#define KVM_ARM_IRQ_VCPU2_MASK 0xf
374	#define KVM_ARM_IRQ_TYPE_SHIFT 24
375	#define KVM_ARM_IRQ_TYPE_MASK 0xf
376	#define KVM_ARM_IRQ_VCPU_SHIFT 16
377	#define KVM_ARM_IRQ_VCPU_MASK 0xff
378	#define KVM_ARM_IRQ_NUM_SHIFT 0
379	#define KVM_ARM_IRQ_NUM_MASK 0xffff
380
381	/* irq_type field */
382	#define KVM_ARM_IRQ_TYPE_CPU 0
383	#define KVM_ARM_IRQ_TYPE_SPI 1
384	#define KVM_ARM_IRQ_TYPE_PPI 2
385
386	/* out-of-kernel GIC cpu interrupt injection irq_number field */
387	#define KVM_ARM_IRQ_CPU_IRQ 0
388	#define KVM_ARM_IRQ_CPU_FIQ 1
389
390	/*
391	* This used to hold the highest supported SPI, but it is now obsolete
392	* and only here to provide source code level compatibility with older
393	* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
394	*/
395	#define KVM_ARM_IRQ_GIC_MAX 127
396
397	/* One single KVM irqchip, ie. the VGIC */
398	#define KVM_NR_IRQCHIPS 1
399
400	/* PSCI interface */
401	#define KVM_PSCI_FN_BASE 0x95c1ba5e
402	#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
403
404	#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
405	#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
406	#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
407	#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
408
409	#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
410	#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
411	#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
412	#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
413
414	#endif
415
416	#endif /* __ARM_KVM_H__ */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/mman.h deleted-10

...	@@ -1,10 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_MMAN_H
3	#define __ASM_MMAN_H
4
5	#include <asm-generic/mman.h>
6
7	#define PROT_BTI 0x10 /* BTI guarded page */
8	#define PROT_MTE 0x20 /* Normal Tagged mapping */
9
10	#endif /* ! _UAPI__ASM_MMAN_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/param.h deleted-24

...	@@ -1,24 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_PARAM_H
18	#define __ASM_PARAM_H
19
20	#define EXEC_PAGESIZE 65536
21
22	#include <asm-generic/param.h>
23
24	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/perf_regs.h deleted-41

...	@@ -1,41 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef _ASM_ARM64_PERF_REGS_H
3	#define _ASM_ARM64_PERF_REGS_H
4
5	enum perf_event_arm_regs {
6	PERF_REG_ARM64_X0,
7	PERF_REG_ARM64_X1,
8	PERF_REG_ARM64_X2,
9	PERF_REG_ARM64_X3,
10	PERF_REG_ARM64_X4,
11	PERF_REG_ARM64_X5,
12	PERF_REG_ARM64_X6,
13	PERF_REG_ARM64_X7,
14	PERF_REG_ARM64_X8,
15	PERF_REG_ARM64_X9,
16	PERF_REG_ARM64_X10,
17	PERF_REG_ARM64_X11,
18	PERF_REG_ARM64_X12,
19	PERF_REG_ARM64_X13,
20	PERF_REG_ARM64_X14,
21	PERF_REG_ARM64_X15,
22	PERF_REG_ARM64_X16,
23	PERF_REG_ARM64_X17,
24	PERF_REG_ARM64_X18,
25	PERF_REG_ARM64_X19,
26	PERF_REG_ARM64_X20,
27	PERF_REG_ARM64_X21,
28	PERF_REG_ARM64_X22,
29	PERF_REG_ARM64_X23,
30	PERF_REG_ARM64_X24,
31	PERF_REG_ARM64_X25,
32	PERF_REG_ARM64_X26,
33	PERF_REG_ARM64_X27,
34	PERF_REG_ARM64_X28,
35	PERF_REG_ARM64_X29,
36	PERF_REG_ARM64_LR,
37	PERF_REG_ARM64_SP,
38	PERF_REG_ARM64_PC,
39	PERF_REG_ARM64_MAX,
40	};
41	#endif /* _ASM_ARM64_PERF_REGS_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/posix_types.h deleted-11

...	@@ -1,11 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	#ifndef __ASM_POSIX_TYPES_H
3	#define __ASM_POSIX_TYPES_H
4
5	typedef unsigned short __kernel_old_uid_t;
6	typedef unsigned short __kernel_old_gid_t;
7	#define __kernel_old_uid_t __kernel_old_uid_t
8
9	#include <asm-generic/posix_types.h>
10
11	#endif /* __ASM_POSIX_TYPES_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/ptrace.h deleted-270

...	@@ -1,270 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Based on arch/arm/include/asm/ptrace.h
4	*
5	* Copyright (C) 1996-2003 Russell King
6	* Copyright (C) 2012 ARM Ltd.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License version 2 as
10	* published by the Free Software Foundation.
11	*
12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.
16	*
17	* You should have received a copy of the GNU General Public License
18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
19	*/
20	#ifndef __ASM_PTRACE_H
21	#define __ASM_PTRACE_H
22
23	#include <linux/types.h>
24
25	#include <asm/hwcap.h>
26	#include <asm/sve_context.h>
27
28
29	/*
30	* PSR bits
31	*/
32	#define PSR_MODE_EL0t 0x00000000
33	#define PSR_MODE_EL1t 0x00000004
34	#define PSR_MODE_EL1h 0x00000005
35	#define PSR_MODE_EL2t 0x00000008
36	#define PSR_MODE_EL2h 0x00000009
37	#define PSR_MODE_EL3t 0x0000000c
38	#define PSR_MODE_EL3h 0x0000000d
39	#define PSR_MODE_MASK 0x0000000f
40
41	/* AArch32 CPSR bits */
42	#define PSR_MODE32_BIT 0x00000010
43
44	/* AArch64 SPSR bits */
45	#define PSR_F_BIT 0x00000040
46	#define PSR_I_BIT 0x00000080
47	#define PSR_A_BIT 0x00000100
48	#define PSR_D_BIT 0x00000200
49	#define PSR_BTYPE_MASK 0x00000c00
50	#define PSR_SSBS_BIT 0x00001000
51	#define PSR_PAN_BIT 0x00400000
52	#define PSR_UAO_BIT 0x00800000
53	#define PSR_DIT_BIT 0x01000000
54	#define PSR_TCO_BIT 0x02000000
55	#define PSR_V_BIT 0x10000000
56	#define PSR_C_BIT 0x20000000
57	#define PSR_Z_BIT 0x40000000
58	#define PSR_N_BIT 0x80000000
59
60	#define PSR_BTYPE_SHIFT 10
61
62	/*
63	* Groups of PSR bits
64	*/
65	#define PSR_f 0xff000000 /* Flags */
66	#define PSR_s 0x00ff0000 /* Status */
67	#define PSR_x 0x0000ff00 /* Extension */
68	#define PSR_c 0x000000ff /* Control */
69
70	/* Convenience names for the values of PSTATE.BTYPE */
71	#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
72	#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
73	#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
74	#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
75
76	/* syscall emulation path in ptrace */
77	#define PTRACE_SYSEMU 31
78	#define PTRACE_SYSEMU_SINGLESTEP 32
79	/* MTE allocation tag access */
80	#define PTRACE_PEEKMTETAGS 33
81	#define PTRACE_POKEMTETAGS 34
82
83	#ifndef __ASSEMBLY__
84
85	/*
86	* User structures for general purpose, floating point and debug registers.
87	*/
88	struct user_pt_regs {
89	__u64 regs[31];
90	__u64 sp;
91	__u64 pc;
92	__u64 pstate;
93	};
94
95	struct user_fpsimd_state {
96	__uint128_t vregs[32];
97	__u32 fpsr;
98	__u32 fpcr;
99	__u32 __reserved[2];
100	};
101
102	struct user_hwdebug_state {
103	__u32 dbg_info;
104	__u32 pad;
105	struct {
106	__u64 addr;
107	__u32 ctrl;
108	__u32 pad;
109	} dbg_regs[16];
110	};
111
112	/* SVE/FP/SIMD state (NT_ARM_SVE) */
113
114	struct user_sve_header {
115	__u32 size; /* total meaningful regset content in bytes */
116	__u32 max_size; /* maxmium possible size for this thread */
117	__u16 vl; /* current vector length */
118	__u16 max_vl; /* maximum possible vector length */
119	__u16 flags;
120	__u16 __reserved;
121	};
122
123	/* Definitions for user_sve_header.flags: */
124	#define SVE_PT_REGS_MASK (1 << 0)
125
126	#define SVE_PT_REGS_FPSIMD 0
127	#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
128
129	/*
130	* Common SVE_PT_* flags:
131	* These must be kept in sync with prctl interface in <linux/prctl.h>
132	*/
133	#define SVE_PT_VL_INHERIT ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
134	#define SVE_PT_VL_ONEXEC ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
135
136
137	/*
138	* The remainder of the SVE state follows struct user_sve_header. The
139	* total size of the SVE state (including header) depends on the
140	* metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size
141	* of the state in bytes, including the header.
142	*
143	* Refer to <asm/sigcontext.h> for details of how to pass the correct
144	* "vq" argument to these macros.
145	*/
146
147	/* Offset from the start of struct user_sve_header to the register data */
148	#define SVE_PT_REGS_OFFSET \
149	((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) \
150	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
151
152	/*
153	* The register data content and layout depends on the value of the
154	* flags field.
155	*/
156
157	/*
158	* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
159	*
160	* The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
161	* struct user_fpsimd_state. Additional data might be appended in the
162	* future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
163	* SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
164	* sizeof(struct user_fpsimd_state).
165	*/
166
167	#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
168
169	#define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state))
170
171	/*
172	* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
173	*
174	* The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
175	* SVE_PT_SVE_SIZE(vq, flags).
176	*
177	* Additional macros describe the contents and layout of the payload.
178	* For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
179	* the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
180	* the size in bytes:
181	*
182	* x type description
183	* - ---- -----------
184	* ZREGS \
185	* ZREG \|
186	* PREGS \| refer to <asm/sigcontext.h>
187	* PREG \|
188	* FFR /
189	*
190	* FPSR uint32_t FPSR
191	* FPCR uint32_t FPCR
192	*
193	* Additional data might be appended in the future.
194	*
195	* The Z-, P- and FFR registers are represented in memory in an endianness-
196	* invariant layout which differs from the layout used for the FPSIMD
197	* V-registers on big-endian systems: see sigcontext.h for more explanation.
198	*/
199
200	#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
201	#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
202	#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
203	#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
204	#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
205
206	#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
207
208	#define SVE_PT_SVE_ZREGS_OFFSET \
209	(SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
210	#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
211	(SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
212	#define SVE_PT_SVE_ZREGS_SIZE(vq) \
213	(SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
214
215	#define SVE_PT_SVE_PREGS_OFFSET(vq) \
216	(SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
217	#define SVE_PT_SVE_PREG_OFFSET(vq, n) \
218	(SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
219	#define SVE_PT_SVE_PREGS_SIZE(vq) \
220	(SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
221	SVE_PT_SVE_PREGS_OFFSET(vq))
222
223	#define SVE_PT_SVE_FFR_OFFSET(vq) \
224	(SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
225
226	#define SVE_PT_SVE_FPSR_OFFSET(vq) \
227	((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \
228	(__SVE_VQ_BYTES - 1)) \
229	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
230	#define SVE_PT_SVE_FPCR_OFFSET(vq) \
231	(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
232
233	/*
234	* Any future extension appended after FPCR must be aligned to the next
235	* 128-bit boundary.
236	*/
237
238	#define SVE_PT_SVE_SIZE(vq, flags) \
239	((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \
240	- SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \
241	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
242
243	#define SVE_PT_SIZE(vq, flags) \
244	(((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \
245	SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
246	: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
247
248	/* pointer authentication masks (NT_ARM_PAC_MASK) */
249
250	struct user_pac_mask {
251	__u64 data_mask;
252	__u64 insn_mask;
253	};
254
255	/* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
256
257	struct user_pac_address_keys {
258	__uint128_t apiakey;
259	__uint128_t apibkey;
260	__uint128_t apdakey;
261	__uint128_t apdbkey;
262	};
263
264	struct user_pac_generic_keys {
265	__uint128_t apgakey;
266	};
267
268	#endif /* __ASSEMBLY__ */
269
270	#endif /* __ASM_PTRACE_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/setup.h deleted-27

...	@@ -1,27 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Based on arch/arm/include/asm/setup.h
4	*
5	* Copyright (C) 1997-1999 Russell King
6	* Copyright (C) 2012 ARM Ltd.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License version 2 as
10	* published by the Free Software Foundation.
11	*
12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.
16	*
17	* You should have received a copy of the GNU General Public License
18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
19	*/
20	#ifndef __ASM_SETUP_H
21	#define __ASM_SETUP_H
22
23	#include <linux/types.h>
24
25	#define COMMAND_LINE_SIZE 2048
26
27	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/sigcontext.h deleted-252

...	@@ -1,252 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_SIGCONTEXT_H
18	#define __ASM_SIGCONTEXT_H
19
20	#ifndef __ASSEMBLY__
21
22	#include <linux/types.h>
23
24	/*
25	* Signal context structure - contains all info to do with the state
26	* before the signal handler was invoked.
27	*/
28	struct sigcontext {
29	__u64 fault_address;
30	/* AArch64 registers */
31	__u64 regs[31];
32	__u64 sp;
33	__u64 pc;
34	__u64 pstate;
35	/* 4K reserved for FP/SIMD state and future expansion */
36	__u8 __reserved[4096] __attribute__((__aligned__(16)));
37	};
38
39	/*
40	* Allocation of __reserved[]:
41	* (Note: records do not necessarily occur in the order shown here.)
42	*
43	* size description
44	*
45	* 0x210 fpsimd_context
46	* 0x10 esr_context
47	* 0x8a0 sve_context (vl <= 64) (optional)
48	* 0x20 extra_context (optional)
49	* 0x10 terminator (null _aarch64_ctx)
50	*
51	* 0x510 (reserved for future allocation)
52	*
53	* New records that can exceed this space need to be opt-in for userspace, so
54	* that an expanded signal frame is not generated unexpectedly. The mechanism
55	* for opting in will depend on the extension that generates each new record.
56	* The above table documents the maximum set and sizes of records than can be
57	* generated when userspace does not opt in for any such extension.
58	*/
59
60	/*
61	* Header to be used at the beginning of structures extending the user
62	* context. Such structures must be placed after the rt_sigframe on the stack
63	* and be 16-byte aligned. The last structure must be a dummy one with the
64	* magic and size set to 0.
65	*/
66	struct _aarch64_ctx {
67	__u32 magic;
68	__u32 size;
69	};
70
71	#define FPSIMD_MAGIC 0x46508001
72
73	struct fpsimd_context {
74	struct _aarch64_ctx head;
75	__u32 fpsr;
76	__u32 fpcr;
77	__uint128_t vregs[32];
78	};
79
80	/*
81	* Note: similarly to all other integer fields, each V-register is stored in an
82	* endianness-dependent format, with the byte at offset i from the start of the
83	* in-memory representation of the register value containing
84	*
85	* bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
86	* bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
87	*/
88
89	/* ESR_EL1 context */
90	#define ESR_MAGIC 0x45535201
91
92	struct esr_context {
93	struct _aarch64_ctx head;
94	__u64 esr;
95	};
96
97	/*
98	* extra_context: describes extra space in the signal frame for
99	* additional structures that don't fit in sigcontext.__reserved[].
100	*
101	* Note:
102	*
103	* 1) fpsimd_context, esr_context and extra_context must be placed in
104	* sigcontext.__reserved[] if present. They cannot be placed in the
105	* extra space. Any other record can be placed either in the extra
106	* space or in sigcontext.__reserved[], unless otherwise specified in
107	* this file.
108	*
109	* 2) There must not be more than one extra_context.
110	*
111	* 3) If extra_context is present, it must be followed immediately in
112	* sigcontext.__reserved[] by the terminating null _aarch64_ctx.
113	*
114	* 4) The extra space to which datap points must start at the first
115	* 16-byte aligned address immediately after the terminating null
116	* _aarch64_ctx that follows the extra_context structure in
117	* __reserved[]. The extra space may overrun the end of __reserved[],
118	* as indicated by a sufficiently large value for the size field.
119	*
120	* 5) The extra space must itself be terminated with a null
121	* _aarch64_ctx.
122	*/
123	#define EXTRA_MAGIC 0x45585401
124
125	struct extra_context {
126	struct _aarch64_ctx head;
127	__u64 datap; /* 16-byte aligned pointer to extra space cast to __u64 */
128	__u32 size; /* size in bytes of the extra space */
129	__u32 __reserved[3];
130	};
131
132	#define SVE_MAGIC 0x53564501
133
134	struct sve_context {
135	struct _aarch64_ctx head;
136	__u16 vl;
137	__u16 __reserved[3];
138	};
139
140	#endif /* !__ASSEMBLY__ */
141
142	#include <asm/sve_context.h>
143
144	/*
145	* The SVE architecture leaves space for future expansion of the
146	* vector length beyond its initial architectural limit of 2048 bits
147	* (16 quadwords).
148	*
149	* See linux/Documentation/arm64/sve.rst for a description of the VL/VQ
150	* terminology.
151	*/
152	#define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */
153
154	#define SVE_VQ_MIN __SVE_VQ_MIN
155	#define SVE_VQ_MAX __SVE_VQ_MAX
156
157	#define SVE_VL_MIN __SVE_VL_MIN
158	#define SVE_VL_MAX __SVE_VL_MAX
159
160	#define SVE_NUM_ZREGS __SVE_NUM_ZREGS
161	#define SVE_NUM_PREGS __SVE_NUM_PREGS
162
163	#define sve_vl_valid(vl) __sve_vl_valid(vl)
164	#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl)
165	#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq)
166
167	/*
168	* If the SVE registers are currently live for the thread at signal delivery,
169	* sve_context.head.size >=
170	* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl))
171	* and the register data may be accessed using the SVE_SIG_*() macros.
172	*
173	* If sve_context.head.size <
174	* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)),
175	* the SVE registers were not live for the thread and no register data
176	* is included: in this case, the SVE_SIG_*() macros should not be
177	* used except for this check.
178	*
179	* The same convention applies when returning from a signal: a caller
180	* will need to remove or resize the sve_context block if it wants to
181	* make the SVE registers live when they were previously non-live or
182	* vice-versa. This may require the caller to allocate fresh
183	* memory and/or move other context blocks in the signal frame.
184	*
185	* Changing the vector length during signal return is not permitted:
186	* sve_context.vl must equal the thread's current vector length when
187	* doing a sigreturn.
188	*
189	*
190	* Note: for all these macros, the "vq" argument denotes the SVE
191	* vector length in quadwords (i.e., units of 128 bits).
192	*
193	* The correct way to obtain vq is to use sve_vq_from_vl(vl). The
194	* result is valid if and only if sve_vl_valid(vl) is true. This is
195	* guaranteed for a struct sve_context written by the kernel.
196	*
197	*
198	* Additional macros describe the contents and layout of the payload.
199	* For each, SVE_SIG_x_OFFSET(args) is the start offset relative to
200	* the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the
201	* size in bytes:
202	*
203	* x type description
204	* - ---- -----------
205	* REGS the entire SVE context
206	*
207	* ZREGS __uint128_t[SVE_NUM_ZREGS][vq] all Z-registers
208	* ZREG __uint128_t[vq] individual Z-register Zn
209	*
210	* PREGS uint16_t[SVE_NUM_PREGS][vq] all P-registers
211	* PREG uint16_t[vq] individual P-register Pn
212	*
213	* FFR uint16_t[vq] first-fault status register
214	*
215	* Additional data might be appended in the future.
216	*
217	* Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
218	* is encoded in memory in an endianness-invariant format, with the byte at
219	* offset i from the start of the in-memory representation containing bits
220	* [(7 + 8 * i) : (8 * i)] of the register value.
221	*/
222
223	#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
224	#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
225	#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
226
227	#define SVE_SIG_REGS_OFFSET \
228	((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) \
229	/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
230
231	#define SVE_SIG_ZREGS_OFFSET \
232	(SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
233	#define SVE_SIG_ZREG_OFFSET(vq, n) \
234	(SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
235	#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
236
237	#define SVE_SIG_PREGS_OFFSET(vq) \
238	(SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
239	#define SVE_SIG_PREG_OFFSET(vq, n) \
240	(SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
241	#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
242
243	#define SVE_SIG_FFR_OFFSET(vq) \
244	(SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
245
246	#define SVE_SIG_REGS_SIZE(vq) \
247	(__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
248
249	#define SVE_SIG_CONTEXT_SIZE(vq) \
250	(SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
251
252	#endif /* __ASM_SIGCONTEXT_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/signal.h deleted-28

...	@@ -1,28 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_SIGNAL_H
18	#define __ASM_SIGNAL_H
19
20	/* Required for AArch32 compatibility. */
21	#define SA_RESTORER 0x04000000
22
23	#define MINSIGSTKSZ 5120
24	#define SIGSTKSZ 16384
25
26	#include <asm-generic/signal.h>
27
28	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/statfs.h deleted-24

...	@@ -1,24 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_STATFS_H
18	#define __ASM_STATFS_H
19
20	#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
21
22	#include <asm-generic/statfs.h>
23
24	#endif
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/sve_context.h deleted-53

...	@@ -1,53 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/* Copyright (C) 2017-2018 ARM Limited */
3
4	/*
5	* For use by other UAPI headers only.
6	* Do not make direct use of header or its definitions.
7	*/
8
9	#ifndef __ASM_SVE_CONTEXT_H
10	#define __ASM_SVE_CONTEXT_H
11
12	#include <linux/types.h>
13
14	#define __SVE_VQ_BYTES 16 /* number of bytes per quadword */
15
16	#define __SVE_VQ_MIN 1
17	#define __SVE_VQ_MAX 512
18
19	#define __SVE_VL_MIN (__SVE_VQ_MIN * __SVE_VQ_BYTES)
20	#define __SVE_VL_MAX (__SVE_VQ_MAX * __SVE_VQ_BYTES)
21
22	#define __SVE_NUM_ZREGS 32
23	#define __SVE_NUM_PREGS 16
24
25	#define __sve_vl_valid(vl) \
26	((vl) % __SVE_VQ_BYTES == 0 && \
27	(vl) >= __SVE_VL_MIN && \
28	(vl) <= __SVE_VL_MAX)
29
30	#define __sve_vq_from_vl(vl) ((vl) / __SVE_VQ_BYTES)
31	#define __sve_vl_from_vq(vq) ((vq) * __SVE_VQ_BYTES)
32
33	#define __SVE_ZREG_SIZE(vq) ((__u32)(vq) * __SVE_VQ_BYTES)
34	#define __SVE_PREG_SIZE(vq) ((__u32)(vq) * (__SVE_VQ_BYTES / 8))
35	#define __SVE_FFR_SIZE(vq) __SVE_PREG_SIZE(vq)
36
37	#define __SVE_ZREGS_OFFSET 0
38	#define __SVE_ZREG_OFFSET(vq, n) \
39	(__SVE_ZREGS_OFFSET + __SVE_ZREG_SIZE(vq) * (n))
40	#define __SVE_ZREGS_SIZE(vq) \
41	(__SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - __SVE_ZREGS_OFFSET)
42
43	#define __SVE_PREGS_OFFSET(vq) \
44	(__SVE_ZREGS_OFFSET + __SVE_ZREGS_SIZE(vq))
45	#define __SVE_PREG_OFFSET(vq, n) \
46	(__SVE_PREGS_OFFSET(vq) + __SVE_PREG_SIZE(vq) * (n))
47	#define __SVE_PREGS_SIZE(vq) \
48	(__SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - __SVE_PREGS_OFFSET(vq))
49
50	#define __SVE_FFR_OFFSET(vq) \
51	(__SVE_PREGS_OFFSET(vq) + __SVE_PREGS_SIZE(vq))
52
53	#endif /* ! _UAPI__ASM_SVE_CONTEXT_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/ucontext.h deleted-33

...	@@ -1,33 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17	#ifndef __ASM_UCONTEXT_H
18	#define __ASM_UCONTEXT_H
19
20	#include <linux/types.h>
21
22	struct ucontext {
23	unsigned long uc_flags;
24	struct ucontext *uc_link;
25	stack_t uc_stack;
26	sigset_t uc_sigmask;
27	/* glibc uses a 1024-bit sigset_t */
28	__u8 __unused[1024 / 8 - sizeof(sigset_t)];
29	/* last for future expansion */
30	struct sigcontext uc_mcontext;
31	};
32
33	#endif /* __ASM_UCONTEXT_H */
	\ No newline at end of file

lib/libc/include/arm64-linux-any/asm/unistd.h deleted-25

...	@@ -1,25 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*
3	* Copyright (C) 2012 ARM Ltd.
4	*
5	* This program is free software; you can redistribute it and/or modify
6	* it under the terms of the GNU General Public License version 2 as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful,
10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12	* GNU General Public License for more details.
13	*
14	* You should have received a copy of the GNU General Public License
15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
16	*/
17
18	#define __ARCH_WANT_RENAMEAT
19	#define __ARCH_WANT_NEW_STAT
20	#define __ARCH_WANT_SET_GET_RLIMIT
21	#define __ARCH_WANT_TIME32_SYSCALLS
22	#define __ARCH_WANT_SYS_CLONE3
23	#define __ARCH_WANT_MEMFD_SECRET
24
25	#include <asm-generic/unistd.h>
	\ No newline at end of file

src/target.zig+1-1

...	@@ -113,7 +113,7 @@ pub fn osArchName(target: std.Target) [:0]const u8 {	...	@@ -113,7 +113,7 @@ pub fn osArchName(target: std.Target) [:0]const u8 {
113	return switch (target.os.tag) {	113	return switch (target.os.tag) {
114	.linux => switch (target.cpu.arch) {	114	.linux => switch (target.cpu.arch) {
115	.arm, .armeb, .thumb, .thumbeb => "arm",	115	.arm, .armeb, .thumb, .thumbeb => "arm",
116	.aarch64, .aarch64_be, .aarch64_32 => "arm64",	116	.aarch64, .aarch64_be, .aarch64_32 => "aarch64",
117	.mips, .mipsel, .mips64, .mips64el => "mips",	117	.mips, .mipsel, .mips64, .mips64el => "mips",
118	.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",	118	.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
119	.riscv32, .riscv64 => "riscv",	119	.riscv32, .riscv64 => "riscv",

tools/update-linux-headers.zig+1-1

...	@@ -55,7 +55,7 @@ const linux_targets = [_]LibCTarget{	...	@@ -55,7 +55,7 @@ const linux_targets = [_]LibCTarget{
55	},	55	},
56	LibCTarget{	56	LibCTarget{
57	.name = "arm64",	57	.name = "arm64",
58	.arch = .arm64,	58	.arch = .{ .specific = .aarch64 },
59	},	59	},
60	LibCTarget{	60	LibCTarget{
61	.name = "csky",	61	.name = "csky",