authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2021-12-29 11:08:48+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2021-12-29 11:08:48+01:00
log96e59fd1c29ef03616bdba147cfbd896be59c202
tree18474b40ca6218ff854c9b39aac363152b8daffd
parentbe5130ec535456559497ac241ac9fa76c4bbb8ca
signaturelock-open Commit is signed but in an unrecognized format.

stage2 ARM: implement slice_elem_val for sizes > 4

1 files changed, 7 insertions(+), 8 deletions(-)

src/arch/arm/CodeGen.zig+7-8
...@@ -1202,7 +1202,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1202,7 +1202,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1202 const bin_op = self.air.instructions.items(.data)[inst].bin_op;1202 const bin_op = self.air.instructions.items(.data)[inst].bin_op;
1203 const result: MCValue = if (!is_volatile and self.liveness.isUnused(inst)) .dead else result: {1203 const result: MCValue = if (!is_volatile and self.liveness.isUnused(inst)) .dead else result: {
1204 const slice_mcv = try self.resolveInst(bin_op.lhs);1204 const slice_mcv = try self.resolveInst(bin_op.lhs);
1205 const index_mcv = try self.resolveInst(bin_op.rhs);
12061205
1207 const slice_ty = self.air.typeOf(bin_op.lhs);1206 const slice_ty = self.air.typeOf(bin_op.lhs);
1208 const elem_ty = slice_ty.childType();1207 const elem_ty = slice_ty.childType();
...@@ -1261,14 +1260,14 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1261,14 +1260,14 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12611260
1262 break :result MCValue{ .register = dst_reg };1261 break :result MCValue{ .register = dst_reg };
1263 } else {1262 } else {
1264 // const dst_mcv = try self.allocRegOrMem(inst, false);1263 const dst_mcv = try self.allocRegOrMem(inst, false);
1265 return self.fail("TODO implement slice_elem_val for elem_size >= 4", .{});1264 const addr_reg = try self.register_manager.allocReg(inst, &.{ base_mcv.register, offset_mcv.register });
1266 }1265
1266 try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
1267 try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);
12671268
1268 _ = offset_mcv;1269 break :result dst_mcv;
1269 _ = slice_mcv;1270 }
1270 _ = index_mcv;
1271 _ = offset_mcv;
1272 };1271 };
1273 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });1272 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
1274}1273}