| ... | ... | @@ -1202,7 +1202,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void { |
| 1202 | 1202 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; |
| 1203 | 1203 | const result: MCValue = if (!is_volatile and self.liveness.isUnused(inst)) .dead else result: { |
| 1204 | 1204 | const slice_mcv = try self.resolveInst(bin_op.lhs); |
| 1205 | | const index_mcv = try self.resolveInst(bin_op.rhs); |
| 1206 | 1205 | |
| 1207 | 1206 | const slice_ty = self.air.typeOf(bin_op.lhs); |
| 1208 | 1207 | const elem_ty = slice_ty.childType(); |
| ... | ... | @@ -1261,14 +1260,14 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void { |
| 1261 | 1260 | |
| 1262 | 1261 | break :result MCValue{ .register = dst_reg }; |
| 1263 | 1262 | } else { |
| 1264 | | // const dst_mcv = try self.allocRegOrMem(inst, false); |
| 1265 | | return self.fail("TODO implement slice_elem_val for elem_size >= 4", .{}); |
| 1266 | | } |
| 1263 | const dst_mcv = try self.allocRegOrMem(inst, false); |
| 1264 | const addr_reg = try self.register_manager.allocReg(inst, &.{ base_mcv.register, offset_mcv.register }); |
| 1265 | |
| 1266 | try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned); |
| 1267 | try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type); |
| 1267 | 1268 | |
| 1268 | | _ = offset_mcv; |
| 1269 | | _ = slice_mcv; |
| 1270 | | _ = index_mcv; |
| 1271 | | _ = offset_mcv; |
| 1269 | break :result dst_mcv; |
| 1270 | } |
| 1272 | 1271 | }; |
| 1273 | 1272 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); |
| 1274 | 1273 | } |