authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-01 20:36:37-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-04 14:42:35-04:00
log9748096992620a9b1a2169ed3be34616fe417a99
tree9e5d85433310efb2c3a8c887f08d672376cbe32f
parent08c24935b167b1a2c6c8dfe20acb386a57c59f3f

x86_64: fix various crashes

1 files changed, 18 insertions(+), 13 deletions(-)

src/arch/x86_64/CodeGen.zig+18-13
...@@ -9528,13 +9528,16 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -9528,13 +9528,16 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
9528 extra_i += inputs.len;9528 extra_i += inputs.len;
95299529
9530 var result: MCValue = .none;9530 var result: MCValue = .none;
9531 var args = std.StringArrayHashMap(MCValue).init(self.gpa);9531 var args = std.ArrayList(MCValue).init(self.gpa);
9532 try args.ensureTotalCapacity(outputs.len + inputs.len);9532 try args.ensureTotalCapacity(outputs.len + inputs.len);
9533 defer {9533 defer {
9534 for (args.values()) |arg| if (arg.getReg()) |reg|9534 for (args.items) |arg| if (arg.getReg()) |reg|
9535 self.register_manager.unlockReg(.{ .register = reg });9535 self.register_manager.unlockReg(.{ .register = reg });
9536 args.deinit();9536 args.deinit();
9537 }9537 }
9538 var arg_map = std.StringHashMap(u8).init(self.gpa);
9539 try arg_map.ensureTotalCapacity(@intCast(outputs.len + inputs.len));
9540 defer arg_map.deinit();
95389541
9539 var outputs_extra_i = extra_i;9542 var outputs_extra_i = extra_i;
9540 for (outputs) |output| {9543 for (outputs) |output| {
...@@ -9585,7 +9588,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -9585,7 +9588,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
9585 if (arg_mcv.getReg()) |reg| if (RegisterManager.indexOfRegIntoTracked(reg)) |_| {9588 if (arg_mcv.getReg()) |reg| if (RegisterManager.indexOfRegIntoTracked(reg)) |_| {
9586 _ = self.register_manager.lockRegAssumeUnused(reg);9589 _ = self.register_manager.lockRegAssumeUnused(reg);
9587 };9590 };
9588 args.putAssumeCapacity(name, arg_mcv);9591 if (!std.mem.eql(u8, name, "_"))
9592 arg_map.putAssumeCapacityNoClobber(name, @intCast(args.items.len));
9593 args.appendAssumeCapacity(arg_mcv);
9589 if (output == .none) result = arg_mcv;9594 if (output == .none) result = arg_mcv;
9590 }9595 }
95919596
...@@ -9643,7 +9648,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -9643,7 +9648,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
9643 if (arg_mcv.getReg()) |reg| if (RegisterManager.indexOfRegIntoTracked(reg)) |_| {9648 if (arg_mcv.getReg()) |reg| if (RegisterManager.indexOfRegIntoTracked(reg)) |_| {
9644 _ = self.register_manager.lockReg(reg);9649 _ = self.register_manager.lockReg(reg);
9645 };9650 };
9646 args.putAssumeCapacity(name, arg_mcv);9651 if (!std.mem.eql(u8, name, "_"))
9652 arg_map.putAssumeCapacityNoClobber(name, @intCast(args.items.len));
9653 args.appendAssumeCapacity(arg_mcv);
9647 }9654 }
96489655
9649 {9656 {
...@@ -9712,8 +9719,10 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -9712,8 +9719,10 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
9712 op_str[colon_pos + 1 .. op_str.len - "]".len]9719 op_str[colon_pos + 1 .. op_str.len - "]".len]
9713 else9720 else
9714 "";9721 "";
9715 op.* = switch (args.get(op_str["%[".len .. colon orelse op_str.len - "]".len]) orelse9722 op.* = switch (args.items[
9716 return self.fail("no matching constraint: '{s}'", .{op_str})) {9723 arg_map.get(op_str["%[".len .. colon orelse op_str.len - "]".len]) orelse
9724 return self.fail("no matching constraint: '{s}'", .{op_str})
9725 ]) {
9717 .register => |reg| if (std.mem.eql(u8, modifier, ""))9726 .register => |reg| if (std.mem.eql(u8, modifier, ""))
9718 .{ .reg = reg }9727 .{ .reg = reg }
9719 else9728 else
...@@ -9826,7 +9835,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -9826,7 +9835,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
9826 };9835 };
9827 }9836 }
98289837
9829 for (outputs, args.values()[0..outputs.len]) |output, mcv| {9838 for (outputs, args.items[0..outputs.len]) |output, mcv| {
9830 const extra_bytes = std.mem.sliceAsBytes(self.air.extra[outputs_extra_i..]);9839 const extra_bytes = std.mem.sliceAsBytes(self.air.extra[outputs_extra_i..]);
9831 const constraint =9840 const constraint =
9832 std.mem.sliceTo(std.mem.sliceAsBytes(self.air.extra[outputs_extra_i..]), 0);9841 std.mem.sliceTo(std.mem.sliceAsBytes(self.air.extra[outputs_extra_i..]), 0);
...@@ -10203,17 +10212,13 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -10203,17 +10212,13 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
10203 .sse => try self.asmRegisterRegister(10212 .sse => try self.asmRegisterRegister(
10204 @as(?Mir.Inst.FixedTag, switch (ty.scalarType(mod).zigTypeTag(mod)) {10213 @as(?Mir.Inst.FixedTag, switch (ty.scalarType(mod).zigTypeTag(mod)) {
10205 else => switch (abi_size) {10214 else => switch (abi_size) {
10206 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },10215 1...16 => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
10207 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
10208 9...16 => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
10209 17...32 => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else null,10216 17...32 => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else null,
10210 else => null,10217 else => null,
10211 },10218 },
10212 .Float => switch (ty.scalarType(mod).floatBits(self.target.*)) {10219 .Float => switch (ty.scalarType(mod).floatBits(self.target.*)) {
10213 16, 128 => switch (abi_size) {10220 16, 128 => switch (abi_size) {
10214 2...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },10221 2...16 => if (self.hasFeature(.avx))
10215 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
10216 9...16 => if (self.hasFeature(.avx))
10217 .{ .v_, .movdqa }10222 .{ .v_, .movdqa }
10218 else10223 else
10219 .{ ._, .movdqa },10224 .{ ._, .movdqa },