authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-04 17:38:03-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-26 04:05:38-07:00
log9766b68c475438e24885dd75cf137d51e72ccfa3
tree85096570a8f57a68f209c741c5960d7bfb036786
parentf2bf6c1b11702179329a4693cea429d550f519e1
signaturelock-open Commit is signed but in an unrecognized format.

riscv: un-cache the `avl` and `vtype` when returning from a function call

the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function. the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.

5 files changed, 24 insertions(+), 3 deletions(-)

src/arch/riscv64/CodeGen.zig+10-1
......@@ -2481,6 +2481,11 @@ fn genBinOp(
24812481 .Float => .vfsubvv,
24822482 else => unreachable,
24832483 },
2484 .mul => switch (child_ty.zigTypeTag(zcu)) {
2485 .Int => .vmulvv,
2486 .Float => .vfmulvv,
2487 else => unreachable,
2488 },
24842489 else => return func.fail("TODO: genBinOp {s} Vector", .{@tagName(tag)}),
24852490 };
24862491
......@@ -2490,7 +2495,7 @@ fn genBinOp(
24902495 16 => .@"16",
24912496 32 => .@"32",
24922497 64 => .@"64",
2493 else => unreachable,
2498 else => return func.fail("TODO: genBinOp > 64 bit elements, found {d}", .{elem_size}),
24942499 },
24952500 .vlmul = .m1,
24962501 .vma = true,
......@@ -4638,6 +4643,10 @@ fn genCall(
46384643 .lib => return func.fail("TODO: lib func calls", .{}),
46394644 }
46404645
4646 // reset the vector settings as they might have changed in the function
4647 func.avl = null;
4648 func.vtype = null;
4649
46414650 return call_info.return_value.short;
46424651}
46434652
src/arch/riscv64/Encoding.zig+7
......@@ -288,6 +288,9 @@ pub const Mnemonic = enum {
288288 vfaddvv,
289289 vfsubvv,
290290
291 vmulvv,
292 vfmulvv,
293
291294 vadcvv,
292295
293296 vmvvx,
......@@ -546,9 +549,11 @@ pub const Mnemonic = enum {
546549 .vsetvli => .{ .opcode = .OP_V, .data = .{ .f = .{ .funct3 = 0b111 } } },
547550 .vaddvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000000, .funct3 = .OPIVV } } },
548551 .vsubvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000010, .funct3 = .OPIVV } } },
552 .vmulvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b100101, .funct3 = .OPIVV } } },
549553
550554 .vfaddvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000000, .funct3 = .OPFVV } } },
551555 .vfsubvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000010, .funct3 = .OPFVV } } },
556 .vfmulvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b100100, .funct3 = .OPFVV } } },
552557
553558 .vadcvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b010000, .funct3 = .OPMVV } } },
554559 .vmvvx => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b010111, .funct3 = .OPIVX } } },
......@@ -710,8 +715,10 @@ pub const InstEnc = enum {
710715
711716 .vaddvv,
712717 .vsubvv,
718 .vmulvv,
713719 .vfaddvv,
714720 .vfsubvv,
721 .vfmulvv,
715722 .vadcvv,
716723 .vmvvx,
717724 .vslidedownvx,
src/arch/riscv64/Mir.zig+2
......@@ -145,6 +145,8 @@ pub const Inst = struct {
145145 vfaddvv,
146146 vsubvv,
147147 vfsubvv,
148 vmulvv,
149 vfmulvv,
148150 vslidedownvx,
149151
150152 /// A pseudo-instruction. Used for anything that isn't 1:1 with an
src/arch/riscv64/abi.zig+2
......@@ -200,6 +200,8 @@ pub fn classifySystem(ty: Type, pt: Zcu.PerThread) [8]SystemClass {
200200 result[0] = .integer;
201201 return result;
202202 }
203 // we should pass vector registers of size <= 128 through 2 integer registers
204 // but we haven't implemented seperating vector registers into register_pairs
203205 return memory_class;
204206 },
205207 else => |bad_ty| std.debug.panic("classifySystem {s}", .{@tagName(bad_ty)}),
test/behavior/vector.zig+3-2
......@@ -102,7 +102,6 @@ test "vector float operators" {
102102 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
103103 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
104104 if (builtin.zig_backend == .stage2_c and comptime builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
105 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
106105 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
107106
108107 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .aarch64) {
......@@ -119,7 +118,7 @@ test "vector float operators" {
119118 try expectEqual(v + x, .{ 11, 22, 33, 44 });
120119 try expectEqual(v - x, .{ 9, 18, 27, 36 });
121120 try expectEqual(v * x, .{ 10, 40, 90, 160 });
122 try expectEqual(-x, .{ -1, -2, -3, -4 });
121 if (builtin.zig_backend != .stage2_riscv64) try expectEqual(-x, .{ -1, -2, -3, -4 });
123122 }
124123 };
125124
......@@ -129,6 +128,8 @@ test "vector float operators" {
129128 try S.doTheTest(f64);
130129 try comptime S.doTheTest(f64);
131130
131 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
132
132133 try S.doTheTest(f16);
133134 try comptime S.doTheTest(f16);
134135