authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-03-11 16:11:09-04:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2025-03-11 16:11:09-04:00
log982c500be5285500a236ca01c2f66e8555647a52
tree070417adb81d973df463dd7f4adb40d175af453f
parentf66067546775a04ca0cda1c74cb9002d02dc49d5
parentcff90e3ae0b14da5163ea0c3283557f402001c67
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #23188 from jacobly0/fix-23143

x86_64: fix crashes with symbols

3 files changed, 212 insertions(+), 71 deletions(-)

src/arch/x86_64/CodeGen.zig+159-45
...@@ -97980,16 +97980,150 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -97980,16 +97980,150 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
97980 switch (pred_mcv) {97980 switch (pred_mcv) {
97981 .register => |pred_reg| switch (pred_reg.class()) {97981 .register => |pred_reg| switch (pred_reg.class()) {
97982 .general_purpose => {},97982 .general_purpose => {},
97983 .sse => if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {97983 .sse => if (elem_ty.toIntern() == .bool_type)
97984 try self.register_manager.getKnownReg(.xmm0, null);97984 if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {
97985 try self.genSetReg(.xmm0, pred_ty, pred_mcv, .{});97985 try self.register_manager.getKnownReg(.xmm0, null);
97986 break :mask .xmm0;97986 try self.genSetReg(.xmm0, pred_ty, pred_mcv, .{});
97987 } else break :mask if (has_blend)97987 break :mask .xmm0;
97988 pred_reg97988 } else break :mask if (has_blend)
97989 pred_reg
97990 else
97991 try self.copyToTmpRegister(pred_ty, pred_mcv)
97989 else97992 else
97990 try self.copyToTmpRegister(pred_ty, pred_mcv),97993 return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)}),
97991 else => unreachable,97994 else => unreachable,
97992 },97995 },
97996 .register_mask => |pred_reg_mask| {
97997 if (pred_reg_mask.info.scalar.bitSize(self.target) != 8 * elem_abi_size)
97998 return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
97999
98000 const mask_reg: Register = if (need_xmm0 and pred_reg_mask.reg.id() != comptime Register.xmm0.id()) mask_reg: {
98001 try self.register_manager.getKnownReg(.xmm0, null);
98002 try self.genSetReg(.xmm0, ty, .{ .register = pred_reg_mask.reg }, .{});
98003 break :mask_reg .xmm0;
98004 } else pred_reg_mask.reg;
98005 const mask_alias = registerAlias(mask_reg, abi_size);
98006 const mask_lock = self.register_manager.lockRegAssumeUnused(mask_reg);
98007 defer self.register_manager.unlockReg(mask_lock);
98008
98009 const lhs_mcv = try self.resolveInst(extra.lhs);
98010 const lhs_lock = switch (lhs_mcv) {
98011 .register => |lhs_reg| self.register_manager.lockRegAssumeUnused(lhs_reg),
98012 else => null,
98013 };
98014 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
98015
98016 const rhs_mcv = try self.resolveInst(extra.rhs);
98017 const rhs_lock = switch (rhs_mcv) {
98018 .register => |rhs_reg| self.register_manager.lockReg(rhs_reg),
98019 else => null,
98020 };
98021 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
98022
98023 const order = has_blend != pred_reg_mask.info.inverted;
98024 const reuse_mcv, const other_mcv = if (order)
98025 .{ rhs_mcv, lhs_mcv }
98026 else
98027 .{ lhs_mcv, rhs_mcv };
98028 const dst_mcv: MCValue = if (reuse_mcv.isRegister() and self.reuseOperand(
98029 inst,
98030 if (order) extra.rhs else extra.lhs,
98031 @intFromBool(order),
98032 reuse_mcv,
98033 )) reuse_mcv else if (has_avx)
98034 .{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.sse) }
98035 else
98036 try self.copyToRegisterWithInstTracking(inst, ty, reuse_mcv);
98037 const dst_reg = dst_mcv.getReg().?;
98038 const dst_alias = registerAlias(dst_reg, abi_size);
98039 const dst_lock = self.register_manager.lockReg(dst_reg);
98040 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
98041
98042 const mir_tag = @as(?Mir.Inst.FixedTag, if ((pred_reg_mask.info.kind == .all and
98043 elem_ty.toIntern() != .f32_type and elem_ty.toIntern() != .f64_type) or pred_reg_mask.info.scalar == .byte)
98044 if (has_avx)
98045 .{ .vp_b, .blendv }
98046 else if (has_blend)
98047 .{ .p_b, .blendv }
98048 else if (pred_reg_mask.info.kind == .all)
98049 .{ .p_, undefined }
98050 else
98051 null
98052 else if ((pred_reg_mask.info.kind == .all and (elem_ty.toIntern() != .f64_type or !self.hasFeature(.sse2))) or
98053 pred_reg_mask.info.scalar == .dword)
98054 if (has_avx)
98055 .{ .v_ps, .blendv }
98056 else if (has_blend)
98057 .{ ._ps, .blendv }
98058 else if (pred_reg_mask.info.kind == .all)
98059 .{ ._ps, undefined }
98060 else
98061 null
98062 else if (pred_reg_mask.info.kind == .all or pred_reg_mask.info.scalar == .qword)
98063 if (has_avx)
98064 .{ .v_pd, .blendv }
98065 else if (has_blend)
98066 .{ ._pd, .blendv }
98067 else if (pred_reg_mask.info.kind == .all)
98068 .{ ._pd, undefined }
98069 else
98070 null
98071 else
98072 null) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
98073 if (has_avx) {
98074 const rhs_alias = if (reuse_mcv.isRegister())
98075 registerAlias(reuse_mcv.getReg().?, abi_size)
98076 else rhs: {
98077 try self.genSetReg(dst_reg, ty, reuse_mcv, .{});
98078 break :rhs dst_alias;
98079 };
98080 if (other_mcv.isBase()) try self.asmRegisterRegisterMemoryRegister(
98081 mir_tag,
98082 dst_alias,
98083 rhs_alias,
98084 try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
98085 mask_alias,
98086 ) else try self.asmRegisterRegisterRegisterRegister(
98087 mir_tag,
98088 dst_alias,
98089 rhs_alias,
98090 registerAlias(if (other_mcv.isRegister())
98091 other_mcv.getReg().?
98092 else
98093 try self.copyToTmpRegister(ty, other_mcv), abi_size),
98094 mask_alias,
98095 );
98096 } else if (has_blend) if (other_mcv.isBase()) try self.asmRegisterMemoryRegister(
98097 mir_tag,
98098 dst_alias,
98099 try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
98100 mask_alias,
98101 ) else try self.asmRegisterRegisterRegister(
98102 mir_tag,
98103 dst_alias,
98104 registerAlias(if (other_mcv.isRegister())
98105 other_mcv.getReg().?
98106 else
98107 try self.copyToTmpRegister(ty, other_mcv), abi_size),
98108 mask_alias,
98109 ) else {
98110 try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
98111 if (other_mcv.isBase()) try self.asmRegisterMemory(
98112 .{ mir_tag[0], .andn },
98113 mask_alias,
98114 try other_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
98115 ) else try self.asmRegisterRegister(
98116 .{ mir_tag[0], .andn },
98117 mask_alias,
98118 if (other_mcv.isRegister())
98119 other_mcv.getReg().?
98120 else
98121 try self.copyToTmpRegister(ty, other_mcv),
98122 );
98123 try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
98124 }
98125 break :result dst_mcv;
98126 },
97993 else => {},98127 else => {},
97994 }98128 }
97995 const mask_reg: Register = if (need_xmm0) mask_reg: {98129 const mask_reg: Register = if (need_xmm0) mask_reg: {
...@@ -98192,7 +98326,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -98192,7 +98326,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
98192 const dst_lock = self.register_manager.lockReg(dst_reg);98326 const dst_lock = self.register_manager.lockReg(dst_reg);
98193 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);98327 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
9819498328
98195 const mir_tag = @as(?Mir.Inst.FixedTag, switch (ty.childType(zcu).zigTypeTag(zcu)) {98329 const mir_tag = @as(?Mir.Inst.FixedTag, switch (elem_ty.zigTypeTag(zcu)) {
98196 else => null,98330 else => null,
98197 .int => switch (abi_size) {98331 .int => switch (abi_size) {
98198 0 => unreachable,98332 0 => unreachable,
...@@ -98208,7 +98342,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -98208,7 +98342,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
98208 null,98342 null,
98209 else => null,98343 else => null,
98210 },98344 },
98211 .float => switch (ty.childType(zcu).floatBits(self.target.*)) {98345 .float => switch (elem_ty.floatBits(self.target.*)) {
98212 else => unreachable,98346 else => unreachable,
98213 16, 80, 128 => null,98347 16, 80, 128 => null,
98214 32 => switch (vec_len) {98348 32 => switch (vec_len) {
...@@ -98262,30 +98396,20 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -98262,30 +98396,20 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
98262 try self.copyToTmpRegister(ty, lhs_mcv), abi_size),98396 try self.copyToTmpRegister(ty, lhs_mcv), abi_size),
98263 mask_alias,98397 mask_alias,
98264 ) else {98398 ) else {
98265 const mir_fixes = @as(?Mir.Inst.Fixes, switch (elem_ty.zigTypeTag(zcu)) {98399 try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
98266 else => null,
98267 .int => .p_,
98268 .float => switch (elem_ty.floatBits(self.target.*)) {
98269 32 => ._ps,
98270 64 => ._pd,
98271 16, 80, 128 => null,
98272 else => unreachable,
98273 },
98274 }) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
98275 try self.asmRegisterRegister(.{ mir_fixes, .@"and" }, dst_alias, mask_alias);
98276 if (rhs_mcv.isBase()) try self.asmRegisterMemory(98400 if (rhs_mcv.isBase()) try self.asmRegisterMemory(
98277 .{ mir_fixes, .andn },98401 .{ mir_tag[0], .andn },
98278 mask_alias,98402 mask_alias,
98279 try rhs_mcv.mem(self, .{ .size = .fromSize(abi_size) }),98403 try rhs_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
98280 ) else try self.asmRegisterRegister(98404 ) else try self.asmRegisterRegister(
98281 .{ mir_fixes, .andn },98405 .{ mir_tag[0], .andn },
98282 mask_alias,98406 mask_alias,
98283 if (rhs_mcv.isRegister())98407 if (rhs_mcv.isRegister())
98284 rhs_mcv.getReg().?98408 rhs_mcv.getReg().?
98285 else98409 else
98286 try self.copyToTmpRegister(ty, rhs_mcv),98410 try self.copyToTmpRegister(ty, rhs_mcv),
98287 );98411 );
98288 try self.asmRegisterRegister(.{ mir_fixes, .@"or" }, dst_alias, mask_alias);98412 try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
98289 }98413 }
98290 break :result dst_mcv;98414 break :result dst_mcv;
98291 };98415 };
...@@ -100824,11 +100948,11 @@ const Temp = struct {...@@ -100824,11 +100948,11 @@ const Temp = struct {
100824 const new_temp_index = cg.next_temp_index;100948 const new_temp_index = cg.next_temp_index;
100825 cg.temp_type[@intFromEnum(new_temp_index)] = .usize;100949 cg.temp_type[@intFromEnum(new_temp_index)] = .usize;
100826 cg.next_temp_index = @enumFromInt(@intFromEnum(new_temp_index) + 1);100950 cg.next_temp_index = @enumFromInt(@intFromEnum(new_temp_index) + 1);
100827 switch (temp.tracking(cg).short) {100951 const mcv = temp.tracking(cg).short;
100828 else => |mcv| std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),100952 switch (mcv) {
100953 else => std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
100829 .register => |reg| {100954 .register => |reg| {
100830 const new_reg =100955 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100831 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100832 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });100956 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
100833 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{100957 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
100834 .base = .{ .reg = reg.to64() },100958 .base = .{ .reg = reg.to64() },
...@@ -100836,33 +100960,22 @@ const Temp = struct {...@@ -100836,33 +100960,22 @@ const Temp = struct {
100836 });100960 });
100837 },100961 },
100838 .register_offset => |reg_off| {100962 .register_offset => |reg_off| {
100839 const new_reg =100963 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100840 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100841 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });100964 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
100842 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{100965 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
100843 .base = .{ .reg = reg_off.reg.to64() },100966 .base = .{ .reg = reg_off.reg.to64() },
100844 .mod = .{ .rm = .{ .disp = reg_off.off + off } },100967 .mod = .{ .rm = .{ .disp = reg_off.off + off } },
100845 });100968 });
100846 },100969 },
100970 .load_symbol, .load_frame => {
100971 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100972 new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{ .reg = new_reg, .off = off } });
100973 try cg.genSetReg(new_reg, .usize, mcv, .{});
100974 },
100847 .lea_symbol => |sym_off| new_temp_index.tracking(cg).* = .init(.{ .lea_symbol = .{100975 .lea_symbol => |sym_off| new_temp_index.tracking(cg).* = .init(.{ .lea_symbol = .{
100848 .sym_index = sym_off.sym_index,100976 .sym_index = sym_off.sym_index,
100849 .off = sym_off.off + off,100977 .off = sym_off.off + off,
100850 } }),100978 } }),
100851 .load_frame => |frame_addr| {
100852 const new_reg =
100853 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100854 new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{
100855 .reg = new_reg,
100856 .off = off,
100857 } });
100858 try cg.asmRegisterMemory(.{ ._, .mov }, new_reg.to64(), .{
100859 .base = .{ .frame = frame_addr.index },
100860 .mod = .{ .rm = .{
100861 .size = .qword,
100862 .disp = frame_addr.off,
100863 } },
100864 });
100865 },
100866 .lea_frame => |frame_addr| new_temp_index.tracking(cg).* = .init(.{ .lea_frame = .{100979 .lea_frame => |frame_addr| new_temp_index.tracking(cg).* = .init(.{ .lea_frame = .{
100867 .index = frame_addr.index,100980 .index = frame_addr.index,
100868 .off = frame_addr.off + off,100981 .off = frame_addr.off + off,
...@@ -101179,7 +101292,8 @@ const Temp = struct {...@@ -101179,7 +101292,8 @@ const Temp = struct {
101179 => return temp.toRegClass(true, .general_purpose, cg),101292 => return temp.toRegClass(true, .general_purpose, cg),
101180 .lea_symbol => |sym_off| {101293 .lea_symbol => |sym_off| {
101181 const off = sym_off.off;101294 const off = sym_off.off;
101182 if (off == 0) return false;101295 // hack around linker relocation bugs
101296 if (false and off == 0) return false;
101183 try temp.toOffset(-off, cg);101297 try temp.toOffset(-off, cg);
101184 while (try temp.toRegClass(true, .general_purpose, cg)) {}101298 while (try temp.toRegClass(true, .general_purpose, cg)) {}
101185 try temp.toOffset(off, cg);101299 try temp.toOffset(off, cg);
src/link/Dwarf.zig+33-26
...@@ -2008,9 +2008,9 @@ pub const WipNav = struct {...@@ -2008,9 +2008,9 @@ pub const WipNav = struct {
2008 .decl_const_runtime_bits,2008 .decl_const_runtime_bits,
2009 .decl_const_comptime_state,2009 .decl_const_comptime_state,
2010 .decl_const_runtime_bits_comptime_state,2010 .decl_const_runtime_bits_comptime_state,
2011 .decl_empty_func,2011 .decl_nullary_func,
2012 .decl_func,2012 .decl_func,
2013 .decl_empty_func_generic,2013 .decl_nullary_func_generic,
2014 .decl_func_generic,2014 .decl_func_generic,
2015 => false,2015 => false,
2016 .generic_decl_var,2016 .generic_decl_var,
...@@ -2626,8 +2626,8 @@ pub fn finishWipNavFunc(...@@ -2626,8 +2626,8 @@ pub fn finishWipNavFunc(
2626 abbrev_code_buf,2626 abbrev_code_buf,
2627 try dwarf.refAbbrevCode(switch (abbrev_code) {2627 try dwarf.refAbbrevCode(switch (abbrev_code) {
2628 else => unreachable,2628 else => unreachable,
2629 .decl_func => .decl_empty_func,2629 .decl_func => .decl_nullary_func,
2630 .decl_instance_func => .decl_instance_empty_func,2630 .decl_instance_func => .decl_instance_nullary_func,
2631 }),2631 }),
2632 );2632 );
2633 }2633 }
...@@ -3012,29 +3012,34 @@ fn updateComptimeNavInner(dwarf: *Dwarf, pt: Zcu.PerThread, nav_index: InternPoo...@@ -3012,29 +3012,34 @@ fn updateComptimeNavInner(dwarf: *Dwarf, pt: Zcu.PerThread, nav_index: InternPoo
3012 if (nav_gop.found_existing) switch (try dwarf.debug_info.declAbbrevCode(wip_nav.unit, nav_gop.value_ptr.*)) {3012 if (nav_gop.found_existing) switch (try dwarf.debug_info.declAbbrevCode(wip_nav.unit, nav_gop.value_ptr.*)) {
3013 .null => {},3013 .null => {},
3014 else => unreachable,3014 else => unreachable,
3015 .decl_empty_func, .decl_func, .decl_instance_empty_func, .decl_instance_func => return,3015 .decl_nullary_func, .decl_func, .decl_instance_nullary_func, .decl_instance_func => return,
3016 .decl_empty_func_generic,3016 .decl_nullary_func_generic,
3017 .decl_func_generic,3017 .decl_func_generic,
3018 .decl_instance_empty_func_generic,3018 .decl_instance_nullary_func_generic,
3019 .decl_instance_func_generic,3019 .decl_instance_func_generic,
3020 => dwarf.debug_info.section.getUnit(wip_nav.unit).getEntry(nav_gop.value_ptr.*).clear(),3020 => dwarf.debug_info.section.getUnit(wip_nav.unit).getEntry(nav_gop.value_ptr.*).clear(),
3021 } else nav_gop.value_ptr.* = try dwarf.addCommonEntry(wip_nav.unit);3021 } else nav_gop.value_ptr.* = try dwarf.addCommonEntry(wip_nav.unit);
3022 wip_nav.entry = nav_gop.value_ptr.*;3022 wip_nav.entry = nav_gop.value_ptr.*;
30233023
3024 const func_type = ip.indexToKey(func.ty).func_type;3024 const func_type = ip.indexToKey(func.ty).func_type;
3025 const is_nullary = !func_type.is_var_args and for (0..func_type.param_types.len) |param_index| {
3026 if (!func_type.paramIsComptime(std.math.cast(u5, param_index) orelse break false)) break false;
3027 } else true;
3025 const diw = wip_nav.debug_info.writer(dwarf.gpa);3028 const diw = wip_nav.debug_info.writer(dwarf.gpa);
3026 try wip_nav.declCommon(if (func_type.param_types.len > 0 or func_type.is_var_args) .{3029 try wip_nav.declCommon(if (is_nullary) .{
3027 .decl = .decl_func_generic,3030 .decl = .decl_nullary_func_generic,
3028 .generic_decl = .generic_decl_func,3031 .generic_decl = .generic_decl_func,
3029 .decl_instance = .decl_instance_func_generic,3032 .decl_instance = .decl_instance_nullary_func_generic,
3030 } else .{3033 } else .{
3031 .decl = .decl_empty_func_generic,3034 .decl = .decl_func_generic,
3032 .generic_decl = .generic_decl_func,3035 .generic_decl = .generic_decl_func,
3033 .decl_instance = .decl_instance_empty_func_generic,3036 .decl_instance = .decl_instance_func_generic,
3034 }, &nav, inst_info.file, &decl);3037 }, &nav, inst_info.file, &decl);
3035 try wip_nav.refType(.fromInterned(func_type.return_type));3038 try wip_nav.refType(.fromInterned(func_type.return_type));
3036 if (func_type.param_types.len > 0 or func_type.is_var_args) {3039 if (!is_nullary) {
3037 for (0..func_type.param_types.len) |param_index| {3040 for (0..func_type.param_types.len) |param_index| {
3041 if (std.math.cast(u5, param_index)) |small_param_index|
3042 if (func_type.paramIsComptime(small_param_index)) continue;
3038 try wip_nav.abbrevCode(.func_type_param);3043 try wip_nav.abbrevCode(.func_type_param);
3039 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));3044 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
3040 }3045 }
...@@ -3568,12 +3573,14 @@ fn updateLazyType(...@@ -3568,12 +3573,14 @@ fn updateLazyType(
3568 };3573 };
3569 try diw.writeByte(@intFromEnum(cc));3574 try diw.writeByte(@intFromEnum(cc));
3570 try wip_nav.refType(.fromInterned(func_type.return_type));3575 try wip_nav.refType(.fromInterned(func_type.return_type));
3571 for (0..func_type.param_types.len) |param_index| {3576 if (!is_nullary) {
3572 try wip_nav.abbrevCode(.func_type_param);3577 for (0..func_type.param_types.len) |param_index| {
3573 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));3578 try wip_nav.abbrevCode(.func_type_param);
3579 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
3580 }
3581 if (func_type.is_var_args) try wip_nav.abbrevCode(.is_var_args);
3582 try uleb128(diw, @intFromEnum(AbbrevCode.null));
3574 }3583 }
3575 if (func_type.is_var_args) try wip_nav.abbrevCode(.is_var_args);
3576 if (!is_nullary) try uleb128(diw, @intFromEnum(AbbrevCode.null));
3577 },3584 },
3578 .error_set_type => |error_set_type| {3585 .error_set_type => |error_set_type| {
3579 try wip_nav.abbrevCode(if (error_set_type.names.len == 0) .generated_empty_enum_type else .generated_enum_type);3586 try wip_nav.abbrevCode(if (error_set_type.names.len == 0) .generated_empty_enum_type else .generated_enum_type);
...@@ -4787,9 +4794,9 @@ const AbbrevCode = enum {...@@ -4787,9 +4794,9 @@ const AbbrevCode = enum {
4787 decl_const_runtime_bits,4794 decl_const_runtime_bits,
4788 decl_const_comptime_state,4795 decl_const_comptime_state,
4789 decl_const_runtime_bits_comptime_state,4796 decl_const_runtime_bits_comptime_state,
4790 decl_empty_func,4797 decl_nullary_func,
4791 decl_func,4798 decl_func,
4792 decl_empty_func_generic,4799 decl_nullary_func_generic,
4793 decl_func_generic,4800 decl_func_generic,
4794 generic_decl_var,4801 generic_decl_var,
4795 generic_decl_const,4802 generic_decl_const,
...@@ -4806,9 +4813,9 @@ const AbbrevCode = enum {...@@ -4806,9 +4813,9 @@ const AbbrevCode = enum {
4806 decl_instance_const_runtime_bits,4813 decl_instance_const_runtime_bits,
4807 decl_instance_const_comptime_state,4814 decl_instance_const_comptime_state,
4808 decl_instance_const_runtime_bits_comptime_state,4815 decl_instance_const_runtime_bits_comptime_state,
4809 decl_instance_empty_func,4816 decl_instance_nullary_func,
4810 decl_instance_func,4817 decl_instance_func,
4811 decl_instance_empty_func_generic,4818 decl_instance_nullary_func_generic,
4812 decl_instance_func_generic,4819 decl_instance_func_generic,
4813 // the rest are unrestricted other than empty variants must not be longer4820 // the rest are unrestricted other than empty variants must not be longer
4814 // than the non-empty variant, and so should appear first4821 // than the non-empty variant, and so should appear first
...@@ -5019,7 +5026,7 @@ const AbbrevCode = enum {...@@ -5019,7 +5026,7 @@ const AbbrevCode = enum {
5019 .{ .ZIG_comptime_value, .ref_addr },5026 .{ .ZIG_comptime_value, .ref_addr },
5020 },5027 },
5021 },5028 },
5022 .decl_empty_func = .{5029 .decl_nullary_func = .{
5023 .tag = .subprogram,5030 .tag = .subprogram,
5024 .attrs = decl_abbrev_common_attrs ++ .{5031 .attrs = decl_abbrev_common_attrs ++ .{
5025 .{ .linkage_name, .strp },5032 .{ .linkage_name, .strp },
...@@ -5044,7 +5051,7 @@ const AbbrevCode = enum {...@@ -5044,7 +5051,7 @@ const AbbrevCode = enum {
5044 .{ .noreturn, .flag },5051 .{ .noreturn, .flag },
5045 },5052 },
5046 },5053 },
5047 .decl_empty_func_generic = .{5054 .decl_nullary_func_generic = .{
5048 .tag = .subprogram,5055 .tag = .subprogram,
5049 .attrs = decl_abbrev_common_attrs ++ .{5056 .attrs = decl_abbrev_common_attrs ++ .{
5050 .{ .type, .ref_addr },5057 .{ .type, .ref_addr },
...@@ -5167,7 +5174,7 @@ const AbbrevCode = enum {...@@ -5167,7 +5174,7 @@ const AbbrevCode = enum {
5167 .{ .ZIG_comptime_value, .ref_addr },5174 .{ .ZIG_comptime_value, .ref_addr },
5168 },5175 },
5169 },5176 },
5170 .decl_instance_empty_func = .{5177 .decl_instance_nullary_func = .{
5171 .tag = .subprogram,5178 .tag = .subprogram,
5172 .attrs = decl_instance_abbrev_common_attrs ++ .{5179 .attrs = decl_instance_abbrev_common_attrs ++ .{
5173 .{ .linkage_name, .strp },5180 .{ .linkage_name, .strp },
...@@ -5192,7 +5199,7 @@ const AbbrevCode = enum {...@@ -5192,7 +5199,7 @@ const AbbrevCode = enum {
5192 .{ .noreturn, .flag },5199 .{ .noreturn, .flag },
5193 },5200 },
5194 },5201 },
5195 .decl_instance_empty_func_generic = .{5202 .decl_instance_nullary_func_generic = .{
5196 .tag = .subprogram,5203 .tag = .subprogram,
5197 .attrs = decl_instance_abbrev_common_attrs ++ .{5204 .attrs = decl_instance_abbrev_common_attrs ++ .{
5198 .{ .type, .ref_addr },5205 .{ .type, .ref_addr },
test/behavior/select.zig+20
...@@ -66,3 +66,23 @@ fn selectArrays() !void {...@@ -66,3 +66,23 @@ fn selectArrays() !void {
66 const xyz = @select(f32, x, y, z);66 const xyz = @select(f32, x, y, z);
67 try expect(mem.eql(f32, &@as([4]f32, xyz), &[4]f32{ 0.0, 312.1, -145.9, -3381.233 }));67 try expect(mem.eql(f32, &@as([4]f32, xyz), &[4]f32{ 0.0, 312.1, -145.9, -3381.233 }));
68}68}
69
70test "@select compare result" {
71 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
72 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
73 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
74
75 const S = struct {
76 fn min(comptime V: type, lhs: V, rhs: V) V {
77 return @select(@typeInfo(V).vector.child, lhs < rhs, lhs, rhs);
78 }
79
80 fn doTheTest() !void {
81 try expect(@reduce(.And, min(@Vector(4, f32), .{ -1, 2, -3, 4 }, .{ 1, -2, 3, -4 }) == @Vector(4, f32){ -1, -2, -3, -4 }));
82 try expect(@reduce(.And, min(@Vector(2, f64), .{ -1, 2 }, .{ 1, -2 }) == @Vector(2, f64){ -1, -2 }));
83 }
84 };
85
86 try S.doTheTest();
87 try comptime S.doTheTest();
88}