| author |  David Rubin <david@vortan.dev> 2024-07-31 11:43:47-07:00 |
| committer | David Rubin <david@vortan.dev> 2024-07-31 13:39:57-07:00 |
| log | 9c7aade488c94ddd84477a6d29162ba6b03ce800 |
| tree | 6664e840cb716cbc847731ee66d98edc5c7af291 |
| parent | 00089347458b4c2544871666cc09570642b0d5b1 |
| signature |  Commit is signed but in an unrecognized format. |
riscv: fix `.got` symbol loading
4 files changed, 55 insertions(+), 3 deletions(-)
src- arch
- riscv64
src/arch/riscv64/Emit.zig+3
| ... | ... | @@ -63,6 +63,9 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 63 | 63 | |
| 64 | 64 | hi_r_type = Elf.R_ZIG_GOT_HI20; |
| 65 | 65 | lo_r_type = Elf.R_ZIG_GOT_LO12; |
| 66 | } else if (sym.flags.needs_got) { | |
| 67 | hi_r_type = Elf.R_GOT_HI20_STATIC; // TODO: rework this #20887 | |
| 68 | lo_r_type = Elf.R_GOT_LO12_I_STATIC; // TODO: rework this #20887 | |
| 66 | 69 | } |
| 67 | 70 | |
| 68 | 71 | try atom_ptr.addReloc(elf_file, .{ |
src/link/Elf.zig+30-1
| ... | ... | @@ -6059,11 +6059,40 @@ const RelaSection = struct { |
| 6059 | 6059 | }; |
| 6060 | 6060 | const RelaSectionTable = std.AutoArrayHashMapUnmanaged(u32, RelaSection); |
| 6061 | 6061 | |
| 6062 | // TODO: add comptime check we don't clobber any reloc for any ISA | |
| 6063 | 6062 | pub const R_ZIG_GOT32: u32 = 0xff00; |
| 6064 | 6063 | pub const R_ZIG_GOTPCREL: u32 = 0xff01; |
| 6065 | 6064 | pub const R_ZIG_GOT_HI20: u32 = 0xff02; |
| 6066 | 6065 | pub const R_ZIG_GOT_LO12: u32 = 0xff03; |
| 6066 | pub const R_GOT_HI20_STATIC: u32 = 0xff04; | |
| 6067 | pub const R_GOT_LO12_I_STATIC: u32 = 0xff05; | |
| 6068 | ||
| 6069 | // Comptime asserts that no Zig relocs overlap with another ISA's reloc number | |
| 6070 | comptime { | |
| 6071 | const zig_relocs = .{ | |
| 6072 | R_ZIG_GOT32, | |
| 6073 | R_ZIG_GOT_HI20, | |
| 6074 | R_ZIG_GOT_LO12, | |
| 6075 | R_ZIG_GOTPCREL, | |
| 6076 | R_GOT_HI20_STATIC, | |
| 6077 | R_GOT_LO12_I_STATIC, | |
| 6078 | }; | |
| 6079 | ||
| 6080 | const other_relocs = .{ | |
| 6081 | elf.R_X86_64, | |
| 6082 | elf.R_AARCH64, | |
| 6083 | elf.R_RISCV, | |
| 6084 | elf.R_PPC64, | |
| 6085 | }; | |
| 6086 | ||
| 6087 | @setEvalBranchQuota(@min(other_relocs.len * zig_relocs.len * 256, 6200)); | |
| 6088 | for (other_relocs) |relocs| { | |
| 6089 | for (@typeInfo(relocs).Enum.fields) |reloc| { | |
| 6090 | for (zig_relocs) |zig_reloc| { | |
| 6091 | assert(reloc.value != zig_reloc); | |
| 6092 | } | |
| 6093 | } | |
| 6094 | } | |
| 6095 | } | |
| 6067 | 6096 | |
| 6068 | 6097 | fn defaultEntrySymbolName(cpu_arch: std.Target.Cpu.Arch) []const u8 { |
| 6069 | 6098 | return switch (cpu_arch) { |
src/link/Elf/Atom.zig+18-2
| ... | ... | @@ -2016,6 +2016,10 @@ const riscv = struct { |
| 2016 | 2016 | assert(symbol.flags.has_zig_got); |
| 2017 | 2017 | }, |
| 2018 | 2018 | |
| 2019 | Elf.R_GOT_HI20_STATIC, | |
| 2020 | Elf.R_GOT_LO12_I_STATIC, | |
| 2021 | => symbol.flags.needs_got = true, | |
| 2022 | ||
| 2019 | 2023 | else => try atom.reportUnhandledRelocError(rel, elf_file), |
| 2020 | 2024 | }, |
| 2021 | 2025 | } |
| ... | ... | @@ -2161,16 +2165,28 @@ const riscv = struct { |
| 2161 | 2165 | // Zig custom relocations |
| 2162 | 2166 | Elf.R_ZIG_GOT_HI20 => { |
| 2163 | 2167 | assert(target.flags.has_zig_got); |
| 2164 | const disp: u32 = @bitCast(math.cast(i32, G + ZIG_GOT + A) orelse return error.Overflow); | |
| 2168 | const disp: u32 = @bitCast(math.cast(i32, ZIG_GOT + A) orelse return error.Overflow); | |
| 2165 | 2169 | riscv_util.writeInstU(code[r_offset..][0..4], disp); |
| 2166 | 2170 | }, |
| 2167 | 2171 | |
| 2168 | 2172 | Elf.R_ZIG_GOT_LO12 => { |
| 2169 | 2173 | assert(target.flags.has_zig_got); |
| 2170 | const value: u32 = @bitCast(math.cast(i32, G + ZIG_GOT + A) orelse return error.Overflow); | |
| 2174 | const value: u32 = @bitCast(math.cast(i32, ZIG_GOT + A) orelse return error.Overflow); | |
| 2171 | 2175 | riscv_util.writeInstI(code[r_offset..][0..4], value); |
| 2172 | 2176 | }, |
| 2173 | 2177 | |
| 2178 | Elf.R_GOT_HI20_STATIC => { | |
| 2179 | assert(target.flags.has_got); | |
| 2180 | const disp: u32 = @bitCast(math.cast(i32, G + GOT + A) orelse return error.Overflow); | |
| 2181 | riscv_util.writeInstU(code[r_offset..][0..4], disp); | |
| 2182 | }, | |
| 2183 | ||
| 2184 | Elf.R_GOT_LO12_I_STATIC => { | |
| 2185 | assert(target.flags.has_got); | |
| 2186 | const disp: u32 = @bitCast(math.cast(i32, G + GOT + A) orelse return error.Overflow); | |
| 2187 | riscv_util.writeInstI(code[r_offset..][0..4], disp); | |
| 2188 | }, | |
| 2189 | ||
| 2174 | 2190 | else => try atom.reportUnhandledRelocError(rel, elf_file), |
| 2175 | 2191 | }, |
| 2176 | 2192 | } |
src/link/Elf/relocation.zig+4
| ... | ... | @@ -115,6 +115,10 @@ fn formatRelocType( |
| 115 | 115 | switch (r_type) { |
| 116 | 116 | Elf.R_ZIG_GOT32 => try writer.writeAll("R_ZIG_GOT32"), |
| 117 | 117 | Elf.R_ZIG_GOTPCREL => try writer.writeAll("R_ZIG_GOTPCREL"), |
| 118 | Elf.R_ZIG_GOT_HI20 => try writer.writeAll("R_ZIG_GOT_HI20"), | |
| 119 | Elf.R_ZIG_GOT_LO12 => try writer.writeAll("R_ZIG_GOT_LO12"), | |
| 120 | Elf.R_GOT_HI20_STATIC => try writer.writeAll("R_GOT_HI20_STATIC"), | |
| 121 | Elf.R_GOT_LO12_I_STATIC => try writer.writeAll("R_GOT_LO12_I_STATIC"), | |
| 118 | 122 | else => switch (ctx.cpu_arch) { |
| 119 | 123 | .x86_64 => try writer.print("R_X86_64_{s}", .{@tagName(@as(elf.R_X86_64, @enumFromInt(r_type)))}), |
| 120 | 124 | .aarch64 => try writer.print("R_AARCH64_{s}", .{@tagName(@as(elf.R_AARCH64, @enumFromInt(r_type)))}), |