| author | |
| committer | |
| log | 9ccdbca635a3b5a26b65ab8e52533d3acc8f2f5e |
| tree | da608c7ad4fc308a7707863d7cc917e4af41b02f |
| parent | 31429a4e8649961624878d11e1bb330107013086 |
6 files changed, 52 insertions(+), 7 deletions(-)
src/arch/x86_64/CodeGen.zig+14-6| ... | @@ -1458,14 +1458,13 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void { | ... | @@ -1458,14 +1458,13 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void { |
| 1458 | .log, | 1458 | .log, |
| 1459 | .log2, | 1459 | .log2, |
| 1460 | .log10, | 1460 | .log10, |
| 1461 | .fabs, | ||
| 1462 | .floor, | 1461 | .floor, |
| 1463 | .ceil, | 1462 | .ceil, |
| 1464 | .round, | 1463 | .round, |
| 1465 | .trunc_float, | 1464 | .trunc_float, |
| 1466 | => try self.airUnaryMath(inst), | 1465 | => try self.airUnaryMath(inst), |
| 1467 | 1466 | ||
| 1468 | .neg => try self.airNeg(inst), | 1467 | .neg, .fabs => try self.airFloatSign(inst), |
| 1469 | 1468 | ||
| 1470 | .add_with_overflow => try self.airAddSubWithOverflow(inst), | 1469 | .add_with_overflow => try self.airAddSubWithOverflow(inst), |
| 1471 | .sub_with_overflow => try self.airAddSubWithOverflow(inst), | 1470 | .sub_with_overflow => try self.airAddSubWithOverflow(inst), |
| ... | @@ -4185,7 +4184,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4185,7 +4184,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { |
| 4185 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); | 4184 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); |
| 4186 | } | 4185 | } |
| 4187 | 4186 | ||
| 4188 | fn airNeg(self: *Self, inst: Air.Inst.Index) !void { | 4187 | fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void { |
| 4189 | const un_op = self.air.instructions.items(.data)[inst].un_op; | 4188 | const un_op = self.air.instructions.items(.data)[inst].un_op; |
| 4190 | const ty = self.air.typeOf(un_op); | 4189 | const ty = self.air.typeOf(un_op); |
| 4191 | const ty_bits = ty.floatBits(self.target.*); | 4190 | const ty_bits = ty.floatBits(self.target.*); |
| ... | @@ -4228,10 +4227,19 @@ fn airNeg(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4228,10 +4227,19 @@ fn airNeg(self: *Self, inst: Air.Inst.Index) !void { |
| 4228 | const dst_lock = self.register_manager.lockReg(dst_mcv.register); | 4227 | const dst_lock = self.register_manager.lockReg(dst_mcv.register); |
| 4229 | defer if (dst_lock) |lock| self.register_manager.unlockReg(lock); | 4228 | defer if (dst_lock) |lock| self.register_manager.unlockReg(lock); |
| 4230 | 4229 | ||
| 4230 | const tag = self.air.instructions.items(.tag)[inst]; | ||
| 4231 | try self.genBinOpMir(switch (ty_bits) { | 4231 | try self.genBinOpMir(switch (ty_bits) { |
| 4232 | 32 => .xorps, | 4232 | 32 => switch (tag) { |
| 4233 | 64 => .xorpd, | 4233 | .neg => .xorps, |
| 4234 | else => return self.fail("TODO implement airNeg for {}", .{ | 4234 | .fabs => .andnps, |
| 4235 | else => unreachable, | ||
| 4236 | }, | ||
| 4237 | 64 => switch (tag) { | ||
| 4238 | .neg => .xorpd, | ||
| 4239 | .fabs => .andnpd, | ||
| 4240 | else => unreachable, | ||
| 4241 | }, | ||
| 4242 | else => return self.fail("TODO implement airFloatSign for {}", .{ | ||
| 4235 | ty.fmt(self.bin_file.options.module.?), | 4243 | ty.fmt(self.bin_file.options.module.?), |
| 4236 | }), | 4244 | }), |
| 4237 | }, vec_ty, dst_mcv, sign_mcv); | 4245 | }, vec_ty, dst_mcv, sign_mcv); |
src/arch/x86_64/Encoding.zig+6| ... | @@ -268,23 +268,29 @@ pub const Mnemonic = enum { | ... | @@ -268,23 +268,29 @@ pub const Mnemonic = enum { |
| 268 | movd, | 268 | movd, |
| 269 | // SSE | 269 | // SSE |
| 270 | addss, | 270 | addss, |
| 271 | andps, | ||
| 272 | andnps, | ||
| 271 | cmpss, | 273 | cmpss, |
| 272 | cvtsi2ss, | 274 | cvtsi2ss, |
| 273 | divss, | 275 | divss, |
| 274 | maxss, minss, | 276 | maxss, minss, |
| 275 | movss, | 277 | movss, |
| 276 | mulss, | 278 | mulss, |
| 279 | orps, | ||
| 277 | subss, | 280 | subss, |
| 278 | ucomiss, | 281 | ucomiss, |
| 279 | xorps, | 282 | xorps, |
| 280 | // SSE2 | 283 | // SSE2 |
| 281 | addsd, | 284 | addsd, |
| 285 | andpd, | ||
| 286 | andnpd, | ||
| 282 | //cmpsd, | 287 | //cmpsd, |
| 283 | cvtsd2ss, cvtsi2sd, cvtss2sd, | 288 | cvtsd2ss, cvtsi2sd, cvtss2sd, |
| 284 | divsd, | 289 | divsd, |
| 285 | maxsd, minsd, | 290 | maxsd, minsd, |
| 286 | movq, //movd, movsd, | 291 | movq, //movd, movsd, |
| 287 | mulsd, | 292 | mulsd, |
| 293 | orpd, | ||
| 288 | subsd, | 294 | subsd, |
| 289 | ucomisd, | 295 | ucomisd, |
| 290 | xorpd, | 296 | xorpd, |
src/arch/x86_64/Lower.zig+6| ... | @@ -94,6 +94,8 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { | ... | @@ -94,6 +94,8 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { |
| 94 | .xor, | 94 | .xor, |
| 95 | 95 | ||
| 96 | .addss, | 96 | .addss, |
| 97 | .andnps, | ||
| 98 | .andps, | ||
| 97 | .cmpss, | 99 | .cmpss, |
| 98 | .cvtsi2ss, | 100 | .cvtsi2ss, |
| 99 | .divss, | 101 | .divss, |
| ... | @@ -101,11 +103,14 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { | ... | @@ -101,11 +103,14 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { |
| 101 | .minss, | 103 | .minss, |
| 102 | .movss, | 104 | .movss, |
| 103 | .mulss, | 105 | .mulss, |
| 106 | .orps, | ||
| 104 | .roundss, | 107 | .roundss, |
| 105 | .subss, | 108 | .subss, |
| 106 | .ucomiss, | 109 | .ucomiss, |
| 107 | .xorps, | 110 | .xorps, |
| 108 | .addsd, | 111 | .addsd, |
| 112 | .andnpd, | ||
| 113 | .andpd, | ||
| 109 | .cmpsd, | 114 | .cmpsd, |
| 110 | .cvtsd2ss, | 115 | .cvtsd2ss, |
| 111 | .cvtsi2sd, | 116 | .cvtsi2sd, |
| ... | @@ -115,6 +120,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { | ... | @@ -115,6 +120,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction { |
| 115 | .minsd, | 120 | .minsd, |
| 116 | .movsd, | 121 | .movsd, |
| 117 | .mulsd, | 122 | .mulsd, |
| 123 | .orpd, | ||
| 118 | .roundsd, | 124 | .roundsd, |
| 119 | .subsd, | 125 | .subsd, |
| 120 | .ucomisd, | 126 | .ucomisd, |
src/arch/x86_64/Mir.zig+12| ... | @@ -168,6 +168,10 @@ pub const Inst = struct { | ... | @@ -168,6 +168,10 @@ pub const Inst = struct { |
| 168 | 168 | ||
| 169 | /// Add single precision floating point values | 169 | /// Add single precision floating point values |
| 170 | addss, | 170 | addss, |
| 171 | /// Bitwise logical and of packed single precision floating-point values | ||
| 172 | andps, | ||
| 173 | /// Bitwise logical and not of packed single precision floating-point values | ||
| 174 | andnps, | ||
| 171 | /// Compare scalar single-precision floating-point values | 175 | /// Compare scalar single-precision floating-point values |
| 172 | cmpss, | 176 | cmpss, |
| 173 | /// Convert doubleword integer to scalar single-precision floating-point value | 177 | /// Convert doubleword integer to scalar single-precision floating-point value |
| ... | @@ -182,6 +186,8 @@ pub const Inst = struct { | ... | @@ -182,6 +186,8 @@ pub const Inst = struct { |
| 182 | movss, | 186 | movss, |
| 183 | /// Multiply scalar single-precision floating-point values | 187 | /// Multiply scalar single-precision floating-point values |
| 184 | mulss, | 188 | mulss, |
| 189 | /// Bitwise logical or of packed single precision floating-point values | ||
| 190 | orps, | ||
| 185 | /// Round scalar single-precision floating-point values | 191 | /// Round scalar single-precision floating-point values |
| 186 | roundss, | 192 | roundss, |
| 187 | /// Subtract scalar single-precision floating-point values | 193 | /// Subtract scalar single-precision floating-point values |
| ... | @@ -192,6 +198,10 @@ pub const Inst = struct { | ... | @@ -192,6 +198,10 @@ pub const Inst = struct { |
| 192 | xorps, | 198 | xorps, |
| 193 | /// Add double precision floating point values | 199 | /// Add double precision floating point values |
| 194 | addsd, | 200 | addsd, |
| 201 | /// Bitwise logical and not of packed double precision floating-point values | ||
| 202 | andnpd, | ||
| 203 | /// Bitwise logical and of packed double precision floating-point values | ||
| 204 | andpd, | ||
| 195 | /// Compare scalar double-precision floating-point values | 205 | /// Compare scalar double-precision floating-point values |
| 196 | cmpsd, | 206 | cmpsd, |
| 197 | /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value | 207 | /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value |
| ... | @@ -210,6 +220,8 @@ pub const Inst = struct { | ... | @@ -210,6 +220,8 @@ pub const Inst = struct { |
| 210 | movsd, | 220 | movsd, |
| 211 | /// Multiply scalar double-precision floating-point values | 221 | /// Multiply scalar double-precision floating-point values |
| 212 | mulsd, | 222 | mulsd, |
| 223 | /// Bitwise logical or of packed double precision floating-point values | ||
| 224 | orpd, | ||
| 213 | /// Round scalar double-precision floating-point values | 225 | /// Round scalar double-precision floating-point values |
| 214 | roundsd, | 226 | roundsd, |
| 215 | /// Subtract scalar double-precision floating-point values | 227 | /// Subtract scalar double-precision floating-point values |
src/arch/x86_64/encodings.zig+12| ... | @@ -832,6 +832,10 @@ pub const table = [_]Entry{ | ... | @@ -832,6 +832,10 @@ pub const table = [_]Entry{ |
| 832 | // SSE | 832 | // SSE |
| 833 | .{ .addss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .sse }, | 833 | .{ .addss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .sse }, |
| 834 | 834 | ||
| 835 | .{ .andnps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x55 }, 0, .sse }, | ||
| 836 | |||
| 837 | .{ .andps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .sse }, | ||
| 838 | |||
| 835 | .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse }, | 839 | .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse }, |
| 836 | 840 | ||
| 837 | .{ .cvtsi2ss, .rm, &.{ .xmm, .rm32 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse }, | 841 | .{ .cvtsi2ss, .rm, &.{ .xmm, .rm32 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse }, |
| ... | @@ -848,6 +852,8 @@ pub const table = [_]Entry{ | ... | @@ -848,6 +852,8 @@ pub const table = [_]Entry{ |
| 848 | 852 | ||
| 849 | .{ .mulss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .sse }, | 853 | .{ .mulss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .sse }, |
| 850 | 854 | ||
| 855 | .{ .orps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .sse }, | ||
| 856 | |||
| 851 | .{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .sse }, | 857 | .{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .sse }, |
| 852 | 858 | ||
| 853 | .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse }, | 859 | .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse }, |
| ... | @@ -857,6 +863,10 @@ pub const table = [_]Entry{ | ... | @@ -857,6 +863,10 @@ pub const table = [_]Entry{ |
| 857 | // SSE2 | 863 | // SSE2 |
| 858 | .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 }, | 864 | .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 }, |
| 859 | 865 | ||
| 866 | .{ .andnpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x55 }, 0, .sse2 }, | ||
| 867 | |||
| 868 | .{ .andpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x54 }, 0, .sse2 }, | ||
| 869 | |||
| 860 | .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 }, | 870 | .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 }, |
| 861 | 871 | ||
| 862 | .{ .cvtsd2ss, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .sse2 }, | 872 | .{ .cvtsd2ss, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .sse2 }, |
| ... | @@ -883,6 +893,8 @@ pub const table = [_]Entry{ | ... | @@ -883,6 +893,8 @@ pub const table = [_]Entry{ |
| 883 | 893 | ||
| 884 | .{ .mulsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x59 }, 0, .sse2 }, | 894 | .{ .mulsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x59 }, 0, .sse2 }, |
| 885 | 895 | ||
| 896 | .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .sse2 }, | ||
| 897 | |||
| 886 | .{ .subsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5c }, 0, .sse2 }, | 898 | .{ .subsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5c }, 0, .sse2 }, |
| 887 | 899 | ||
| 888 | .{ .movsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .sse2 }, | 900 | .{ .movsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .sse2 }, |
test/behavior/floatop.zig+2-1| ... | @@ -96,7 +96,8 @@ test "negative f128 floatToInt at compile-time" { | ... | @@ -96,7 +96,8 @@ test "negative f128 floatToInt at compile-time" { |
| 96 | } | 96 | } |
| 97 | 97 | ||
| 98 | test "@sqrt" { | 98 | test "@sqrt" { |
| 99 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO | 99 | if (builtin.zig_backend == .stage2_x86_64 and |
| 100 | comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO | ||
| 100 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO | 101 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO |
| 101 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO | 102 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO |
| 102 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO | 103 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO |