| ... | ... | @@ -4194,13 +4194,63 @@ fn airTagName(self: *Self, inst: Air.Inst.Index) !void { |
| 4194 | 4194 | } |
| 4195 | 4195 | |
| 4196 | 4196 | fn airErrorName(self: *Self, inst: Air.Inst.Index) !void { |
| 4197 | const mod = self.bin_file.comp.module.?; |
| 4197 | 4198 | const un_op = self.air.instructions.items(.data)[@intFromEnum(inst)].un_op; |
| 4198 | | const operand = try self.resolveInst(un_op); |
| 4199 | | const result: MCValue = if (self.liveness.isUnused(inst)) .dead else { |
| 4200 | | _ = operand; |
| 4201 | | return self.fail("TODO implement airErrorName for riscv64", .{}); |
| 4202 | | }; |
| 4203 | | return self.finishAir(inst, result, .{ un_op, .none, .none }); |
| 4199 | |
| 4200 | const err_ty = self.typeOf(un_op); |
| 4201 | const err_mcv = try self.resolveInst(un_op); |
| 4202 | |
| 4203 | const err_reg = try self.copyToTmpRegister(err_ty, err_mcv); |
| 4204 | const err_lock = self.register_manager.lockRegAssumeUnused(err_reg); |
| 4205 | defer self.register_manager.unlockReg(err_lock); |
| 4206 | |
| 4207 | const addr_reg, const addr_lock = try self.allocReg(); |
| 4208 | defer self.register_manager.unlockReg(addr_lock); |
| 4209 | |
| 4210 | const lazy_sym = link.File.LazySymbol.initDecl(.const_data, null, mod); |
| 4211 | if (self.bin_file.cast(link.File.Elf)) |elf_file| { |
| 4212 | const sym_index = elf_file.zigObjectPtr().?.getOrCreateMetadataForLazySymbol(elf_file, lazy_sym) catch |err| |
| 4213 | return self.fail("{s} creating lazy symbol", .{@errorName(err)}); |
| 4214 | const sym = elf_file.symbol(sym_index); |
| 4215 | try self.genSetReg(Type.usize, addr_reg, .{ .load_symbol = .{ .sym = sym.esym_index } }); |
| 4216 | } else { |
| 4217 | return self.fail("TODO: riscv non-elf", .{}); |
| 4218 | } |
| 4219 | |
| 4220 | const start_reg, const start_lock = try self.allocReg(); |
| 4221 | defer self.register_manager.unlockReg(start_lock); |
| 4222 | |
| 4223 | const end_reg, const end_lock = try self.allocReg(); |
| 4224 | defer self.register_manager.unlockReg(end_lock); |
| 4225 | |
| 4226 | _ = try self.addInst(.{ |
| 4227 | .tag = .slli, |
| 4228 | .data = .{ |
| 4229 | .i_type = .{ |
| 4230 | .rd = err_reg, |
| 4231 | .rs1 = err_reg, |
| 4232 | .imm12 = 4, |
| 4233 | }, |
| 4234 | }, |
| 4235 | }); |
| 4236 | |
| 4237 | try self.binOpMir( |
| 4238 | .add, |
| 4239 | null, |
| 4240 | Type.usize, |
| 4241 | .{ .register = err_reg }, |
| 4242 | .{ .register = addr_reg }, |
| 4243 | ); |
| 4244 | |
| 4245 | try self.genSetReg(Type.usize, start_reg, .{ .indirect = .{ .reg = err_reg } }); |
| 4246 | try self.genSetReg(Type.usize, end_reg, .{ .indirect = .{ .reg = err_reg, .off = 8 } }); |
| 4247 | |
| 4248 | const dst_mcv = try self.allocRegOrMem(inst, false); |
| 4249 | |
| 4250 | try self.genSetStack(Type.usize, dst_mcv.stack_offset, .{ .register = start_reg }); |
| 4251 | try self.genSetStack(Type.usize, dst_mcv.stack_offset + 8, .{ .register = end_reg }); |
| 4252 | |
| 4253 | return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none }); |
| 4204 | 4254 | } |
| 4205 | 4255 | |
| 4206 | 4256 | fn airSplat(self: *Self, inst: Air.Inst.Index) !void { |
David Rubin <david@vortan.dev> 2024-03-30 06:43:13-07:00
src