| ... | ... | @@ -2884,6 +2884,8 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { |
| 2884 | 2884 | break :blk dst_mcv; |
| 2885 | 2885 | } |
| 2886 | 2886 | }; |
| 2887 | dst_mcv.freezeIfRegister(&self.register_manager); |
| 2888 | defer dst_mcv.unfreezeIfRegister(&self.register_manager); |
| 2887 | 2889 | |
| 2888 | 2890 | // Shift by struct_field_offset. |
| 2889 | 2891 | const shift = @intCast(u8, struct_field_offset * @sizeOf(usize)); |
| ... | ... | @@ -2893,7 +2895,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { |
| 2893 | 2895 | const max_reg_bit_width = Register.rax.size(); |
| 2894 | 2896 | const mask_shift = @intCast(u6, (max_reg_bit_width - struct_field_ty.bitSize(self.target.*))); |
| 2895 | 2897 | const mask = (~@as(u64, 0)) >> mask_shift; |
| 2896 | | try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .immediate = mask }); |
| 2898 | |
| 2899 | const tmp_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = mask }); |
| 2900 | try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .register = tmp_reg }); |
| 2897 | 2901 | |
| 2898 | 2902 | break :result dst_mcv; |
| 2899 | 2903 | }, |