| ... | @@ -74,6 +74,9 @@ | ... | @@ -74,6 +74,9 @@ |
| 74 | #elif defined (__x86_64__) || (defined(zig_msvc) && defined(_M_X64)) | 74 | #elif defined (__x86_64__) || (defined(zig_msvc) && defined(_M_X64)) |
| 75 | #define zig_x86_64 | 75 | #define zig_x86_64 |
| 76 | #define zig_x86 | 76 | #define zig_x86 |
| | 77 | #elif defined(__I86__) |
| | 78 | #define zig_x86_16 |
| | 79 | #define zig_x86 |
| 77 | #endif | 80 | #endif |
| 78 | | 81 | |
| 79 | #if defined(zig_msvc) || __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ | 82 | #if defined(zig_msvc) || __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| ... | @@ -400,6 +403,8 @@ | ... | @@ -400,6 +403,8 @@ |
| 400 | #define zig_trap() __asm__ volatile("j 0x2") | 403 | #define zig_trap() __asm__ volatile("j 0x2") |
| 401 | #elif defined(zig_sparc) | 404 | #elif defined(zig_sparc) |
| 402 | #define zig_trap() __asm__ volatile("illtrap") | 405 | #define zig_trap() __asm__ volatile("illtrap") |
| | 406 | #elif defined(zig_x86_16) |
| | 407 | #define zig_trap() __asm__ volatile("int $0x3") |
| 403 | #elif defined(zig_x86) | 408 | #elif defined(zig_x86) |
| 404 | #define zig_trap() __asm__ volatile("ud2") | 409 | #define zig_trap() __asm__ volatile("ud2") |
| 405 | #else | 410 | #else |
| ... | @@ -4219,7 +4224,7 @@ static inline void zig_loongarch_cpucfg(uint32_t word, uint32_t* result) { | ... | @@ -4219,7 +4224,7 @@ static inline void zig_loongarch_cpucfg(uint32_t word, uint32_t* result) { |
| 4219 | #endif | 4224 | #endif |
| 4220 | } | 4225 | } |
| 4221 | | 4226 | |
| 4222 | #elif defined(zig_x86) | 4227 | #elif defined(zig_x86) && !defined(zig_x86_16) |
| 4223 | | 4228 | |
| 4224 | static inline void zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) { | 4229 | static inline void zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) { |
| 4225 | #if defined(zig_msvc) | 4230 | #if defined(zig_msvc) |