Commit 9d534790ebc869ec933e932abe4be8b9e3593bbc | zig

lib/compiler/aro/aro/target.zig+8-8

...	...	@@ -162,7 +162,7 @@ pub fn ignoreNonZeroSizedBitfieldTypeAlignment(target: std.Target) bool {
162	162	switch (target.cpu.arch) {
163	163	.avr => return true,
164	164	.arm => {
165		if (std.Target.arm.featureSetHas(target.cpu.features, .has_v7)) {
	165	if (target.cpu.has(.arm, .has_v7)) {
166	166	switch (target.os.tag) {
167	167	.ios => return true,
168	168	else => return false,
...	...	@@ -185,7 +185,7 @@ pub fn minZeroWidthBitfieldAlignment(target: std.Target) ?u29 {
185	185	switch (target.cpu.arch) {
186	186	.avr => return 8,
187	187	.arm => {
188		if (std.Target.arm.featureSetHas(target.cpu.features, .has_v7)) {
	188	if (target.cpu.has(.arm, .has_v7)) {
189	189	switch (target.os.tag) {
190	190	.ios => return 32,
191	191	else => return null,
...	...	@@ -203,7 +203,7 @@ pub fn unnamedFieldAffectsAlignment(target: std.Target) bool {
203	203	return true;
204	204	},
205	205	.armeb => {
206		if (std.Target.arm.featureSetHas(target.cpu.features, .has_v7)) {
	206	if (target.cpu.has(.arm, .has_v7)) {
207	207	if (std.Target.Abi.default(target.cpu.arch, target.os.tag) == .eabi) return true;
208	208	}
209	209	},
...	...	@@ -230,7 +230,7 @@ pub fn defaultAlignment(target: std.Target) u29 {
230	230	switch (target.cpu.arch) {
231	231	.avr => return 1,
232	232	.arm => if (target.abi.isAndroid() or target.os.tag == .ios) return 16 else return 8,
233		.sparc => if (std.Target.sparc.featureSetHas(target.cpu.features, .v9)) return 16 else return 8,
	233	.sparc => if (target.cpu.has(.sparc, .v9)) return 16 else return 8,
234	234	.mips, .mipsel => switch (target.abi) {
235	235	.none, .gnuabi64 => return 16,
236	236	else => return 8,
...	...	@@ -268,7 +268,7 @@ pub fn systemCompiler(target: std.Target) LangOpts.Compiler {
268	268	pub fn hasFloat128(target: std.Target) bool {
269	269	if (target.cpu.arch.isWasm()) return true;
270	270	if (target.os.tag.isDarwin()) return false;
271		if (target.cpu.arch.isPowerPC()) return std.Target.powerpc.featureSetHas(target.cpu.features, .float128);
	271	if (target.cpu.arch.isPowerPC()) return target.cpu.has(.powerpc, .float128);
272	272	return switch (target.os.tag) {
273	273	.dragonfly,
274	274	.haiku,
...	...	@@ -334,7 +334,7 @@ pub const FPSemantics = enum {
334	334	.spirv32,
335	335	.spirv64,
336	336	=> return .IEEEHalf,
337		.x86, .x86_64 => if (std.Target.x86.featureSetHas(target.cpu.features, .sse2)) return .IEEEHalf,
	337	.x86, .x86_64 => if (target.cpu.has(.x86, .sse2)) return .IEEEHalf,
338	338	else => {},
339	339	}
340	340	return null;
...	...	@@ -399,7 +399,7 @@ pub fn defaultFpEvalMethod(target: std.Target) LangOpts.FPEvalMethod {
399	399	return .double;
400	400	}
401	401	}
402		if (std.Target.x86.featureSetHas(target.cpu.features, .sse)) {
	402	if (target.cpu.has(.x86, .sse)) {
403	403	return .source;
404	404	}
405	405	return .extended;
...	...	@@ -765,7 +765,7 @@ test "target size/align tests" {
765	765	.specifier = .char,
766	766	};
767	767
768		try std.testing.expectEqual(true, std.Target.arm.featureSetHas(comp.target.cpu.features, .has_v7));
	768	try std.testing.expectEqual(true, comp.target.cpu.has(.arm, .has_v7));
769	769	try std.testing.expectEqual(@as(u64, 1), ct.sizeof(&comp).?);
770	770	try std.testing.expectEqual(@as(u64, 1), ct.alignof(&comp));
771	771	try std.testing.expectEqual(true, ignoreNonZeroSizedBitfieldTypeAlignment(comp.target));

lib/compiler/aro/aro/toolchains/Linux.zig+1-1

...	...	@@ -318,7 +318,7 @@ pub fn buildLinkerArgs(self: const Linux, tc: const Toolchain, argv: *std.Arra
318	318
319	319	fn getMultiarchTriple(target: std.Target) ?[]const u8 {
320	320	const is_android = target.abi.isAndroid();
321		const is_mips_r6 = std.Target.mips.featureSetHas(target.cpu.features, .mips32r6);
	321	const is_mips_r6 = target.cpu.has(.mips, .mips32r6);
322	322	return switch (target.cpu.arch) {
323	323	.arm, .thumb => if (is_android) "arm-linux-androideabi" else if (target.abi == .gnueabihf) "arm-linux-gnueabihf" else "arm-linux-gnueabi",
324	324	.armeb, .thumbeb => if (target.abi == .gnueabihf) "armeb-linux-gnueabihf" else "armeb-linux-gnueabi",

lib/compiler_rt/aarch64_outline_atomics.zig+1-1

...	...	@@ -2,7 +2,7 @@
2	2	const builtin = @import("builtin");
3	3	const std = @import("std");
4	4	const common = @import("common.zig");
5		const always_has_lse = std.Target.aarch64.featureSetHas(builtin.cpu.features, .lse);
	5	const always_has_lse = builtin.cpu.has(.aarch64, .lse);
6	6
7	7	/// This default is overridden at runtime after inspecting CPU properties.
8	8	/// It is intentionally not exported in order to make the machine code that

lib/compiler_rt/atomics.zig+2-2

...	...	@@ -19,7 +19,7 @@ const supports_atomic_ops = switch (arch) {
19	19	// operations (unless we're targeting Linux, the kernel provides a way to
20	20	// perform CAS operations).
21	21	// XXX: The Linux code path is not implemented yet.
22		!std.Target.arm.featureSetHas(builtin.cpu.features, .has_v6m),
	22	!builtin.cpu.has(.arm, .has_v6m),
23	23	else => true,
24	24	};
25	25
...	...	@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
30	30	// On SPARC systems that lacks CAS and/or swap instructions, the only
31	31	// available atomic operation is a test-and-set (`ldstub`), so we force
32	32	// every atomic memory access to go through the lock.
33		.sparc => if (std.Target.sparc.featureSetHas(builtin.cpu.features, .hasleoncasa)) @sizeOf(usize) else 0,
	33	.sparc => if (builtin.cpu.has(.sparc, .hasleoncasa)) @sizeOf(usize) else 0,
34	34
35	35	// XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
36	36	// and set this parameter accordingly.

lib/compiler_rt/common.zig+1-1

...	...	@@ -124,7 +124,7 @@ pub fn F16T(comptime OtherType: type) type {
124	124	.spirv32,
125	125	.spirv64,
126	126	=> f16,
127		.hexagon => if (std.Target.hexagon.featureSetHas(builtin.target.cpu.features, .v68)) f16 else u16,
	127	.hexagon => if (builtin.target.cpu.has(.hexagon, .v68)) f16 else u16,
128	128	.x86, .x86_64 => if (builtin.target.os.tag.isDarwin()) switch (OtherType) {
129	129	// Starting with LLVM 16, Darwin uses different abi for f16
130	130	// depending on the type of the other return/argument..???

lib/compiler_rt/count0bits.zig+1-3

...	...	@@ -142,9 +142,7 @@ fn clzsi2_generic(a: i32) callconv(.c) i32 {
142	142	pub const __clzsi2 = switch (builtin.cpu.arch) {
143	143	.arm, .armeb, .thumb, .thumbeb => impl: {
144	144	const use_thumb1 =
145		(builtin.cpu.arch.isThumb() or
146		std.Target.arm.featureSetHas(builtin.cpu.features, .noarm)) and
147		!std.Target.arm.featureSetHas(builtin.cpu.features, .thumb2);
	145	(builtin.cpu.arch.isThumb() or builtin.cpu.has(.arm, .noarm)) and !builtin.cpu.has(.arm, .thumb2);
148	146
149	147	if (use_thumb1) {
150	148	break :impl __clzsi2_thumb1;

lib/std/Target.zig+113-117

...	...	@@ -767,25 +767,27 @@ pub const Os = struct {
767	767	};
768	768
769	769	pub const aarch64 = @import("Target/aarch64.zig");
770		pub const arc = @import("Target/arc.zig");
771	770	pub const amdgcn = @import("Target/amdgcn.zig");
	771	pub const arc = @import("Target/arc.zig");
772	772	pub const arm = @import("Target/arm.zig");
773	773	pub const avr = @import("Target/avr.zig");
774	774	pub const bpf = @import("Target/bpf.zig");
775	775	pub const csky = @import("Target/csky.zig");
776	776	pub const hexagon = @import("Target/hexagon.zig");
	777	pub const kalimba = @import("Target/generic.zig");
777	778	pub const lanai = @import("Target/lanai.zig");
778	779	pub const loongarch = @import("Target/loongarch.zig");
779	780	pub const m68k = @import("Target/m68k.zig");
780	781	pub const mips = @import("Target/mips.zig");
781	782	pub const msp430 = @import("Target/msp430.zig");
782	783	pub const nvptx = @import("Target/nvptx.zig");
	784	pub const or1k = @import("Target/generic.zig");
783	785	pub const powerpc = @import("Target/powerpc.zig");
784	786	pub const propeller = @import("Target/propeller.zig");
785	787	pub const riscv = @import("Target/riscv.zig");
	788	pub const s390x = @import("Target/s390x.zig");
786	789	pub const sparc = @import("Target/sparc.zig");
787	790	pub const spirv = @import("Target/spirv.zig");
788		pub const s390x = @import("Target/s390x.zig");
789	791	pub const ve = @import("Target/ve.zig");
790	792	pub const wasm = @import("Target/wasm.zig");
791	793	pub const x86 = @import("Target/x86.zig");
...	...	@@ -1094,7 +1096,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {
1094	1096	.propeller => .PROPELLER,
1095	1097	.riscv32, .riscv64 => .RISCV,
1096	1098	.s390x => .S390,
1097		.sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
	1099	.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1098	1100	.sparc64 => .SPARCV9,
1099	1101	.ve => .VE,
1100	1102	.x86 => .@"386",
...	...	@@ -1396,6 +1398,71 @@ pub const Cpu = struct {
1396	1398	// - tce
1397	1399	// - tcele
1398	1400
	1401	/// An architecture family can encompass multiple architectures as represented by `Arch`.
	1402	/// For a given family tag, it is guaranteed that an `std.Target.<tag>` namespace exists
	1403	/// containing CPU model and feature data.
	1404	pub const Family = enum {
	1405	amdgcn,
	1406	arc,
	1407	arm,
	1408	aarch64,
	1409	avr,
	1410	bpf,
	1411	csky,
	1412	hexagon,
	1413	kalimba,
	1414	lanai,
	1415	loongarch,
	1416	m68k,
	1417	mips,
	1418	msp430,
	1419	nvptx,
	1420	or1k,
	1421	powerpc,
	1422	propeller,
	1423	riscv,
	1424	s390x,
	1425	sparc,
	1426	spirv,
	1427	ve,
	1428	wasm,
	1429	x86,
	1430	xcore,
	1431	xtensa,
	1432	};
	1433
	1434	pub inline fn family(arch: Arch) Family {
	1435	return switch (arch) {
	1436	.amdgcn => .amdgcn,
	1437	.arc => .arc,
	1438	.arm, .armeb, .thumb, .thumbeb => .arm,
	1439	.aarch64, .aarch64_be => .aarch64,
	1440	.avr => .avr,
	1441	.bpfel, .bpfeb => .bpf,
	1442	.csky => .csky,
	1443	.hexagon => .hexagon,
	1444	.kalimba => .kalimba,
	1445	.lanai => .lanai,
	1446	.loongarch32, .loongarch64 => .loongarch,
	1447	.m68k => .m68k,
	1448	.mips, .mipsel, .mips64, .mips64el => .mips,
	1449	.msp430 => .msp430,
	1450	.or1k => .or1k,
	1451	.nvptx, .nvptx64 => .nvptx,
	1452	.powerpc, .powerpcle, .powerpc64, .powerpc64le => .powerpc,
	1453	.propeller => .propeller,
	1454	.riscv32, .riscv64 => .riscv,
	1455	.s390x => .s390x,
	1456	.sparc, .sparc64 => .sparc,
	1457	.spirv, .spirv32, .spirv64 => .spirv,
	1458	.ve => .ve,
	1459	.wasm32, .wasm64 => .wasm,
	1460	.x86, .x86_64 => .x86,
	1461	.xcore => .xcore,
	1462	.xtensa => .xtensa,
	1463	};
	1464	}
	1465
1399	1466	pub inline fn isX86(arch: Arch) bool {
1400	1467	return switch (arch) {
1401	1468	.x86, .x86_64 => true,
...	...	@@ -1574,88 +1641,17 @@ pub const Cpu = struct {
1574	1641	};
1575	1642	}
1576	1643
1577		/// Returns a name that matches the lib/std/target/* source file name.
1578		pub fn genericName(arch: Arch) [:0]const u8 {
1579		return switch (arch) {
1580		.arm, .armeb, .thumb, .thumbeb => "arm",
1581		.aarch64, .aarch64_be => "aarch64",
1582		.bpfel, .bpfeb => "bpf",
1583		.loongarch32, .loongarch64 => "loongarch",
1584		.mips, .mipsel, .mips64, .mips64el => "mips",
1585		.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1586		.propeller => "propeller",
1587		.riscv32, .riscv64 => "riscv",
1588		.sparc, .sparc64 => "sparc",
1589		.s390x => "s390x",
1590		.x86, .x86_64 => "x86",
1591		.nvptx, .nvptx64 => "nvptx",
1592		.wasm32, .wasm64 => "wasm",
1593		.spirv, .spirv32, .spirv64 => "spirv",
1594		else => @tagName(arch),
1595		};
1596		}
1597
1598	1644	/// All CPU features Zig is aware of, sorted lexicographically by name.
1599	1645	pub fn allFeaturesList(arch: Arch) []const Cpu.Feature {
1600		return switch (arch) {
1601		.arm, .armeb, .thumb, .thumbeb => &arm.all_features,
1602		.aarch64, .aarch64_be => &aarch64.all_features,
1603		.arc => &arc.all_features,
1604		.avr => &avr.all_features,
1605		.bpfel, .bpfeb => &bpf.all_features,
1606		.csky => &csky.all_features,
1607		.hexagon => &hexagon.all_features,
1608		.lanai => &lanai.all_features,
1609		.loongarch32, .loongarch64 => &loongarch.all_features,
1610		.m68k => &m68k.all_features,
1611		.mips, .mipsel, .mips64, .mips64el => &mips.all_features,
1612		.msp430 => &msp430.all_features,
1613		.powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
1614		.amdgcn => &amdgcn.all_features,
1615		.riscv32, .riscv64 => &riscv.all_features,
1616		.sparc, .sparc64 => &sparc.all_features,
1617		.spirv, .spirv32, .spirv64 => &spirv.all_features,
1618		.s390x => &s390x.all_features,
1619		.x86, .x86_64 => &x86.all_features,
1620		.xcore => &xcore.all_features,
1621		.xtensa => &xtensa.all_features,
1622		.nvptx, .nvptx64 => &nvptx.all_features,
1623		.ve => &ve.all_features,
1624		.wasm32, .wasm64 => &wasm.all_features,
1625
1626		else => &[0]Cpu.Feature{},
	1646	return switch (arch.family()) {
	1647	inline else => \|f\| &@field(Target, @tagName(f)).all_features,
1627	1648	};
1628	1649	}
1629	1650
1630	1651	/// All processors Zig is aware of, sorted lexicographically by name.
1631	1652	pub fn allCpuModels(arch: Arch) []const *const Cpu.Model {
1632		return switch (arch) {
1633		.arc => comptime allCpusFromDecls(arc.cpu),
1634		.arm, .armeb, .thumb, .thumbeb => comptime allCpusFromDecls(arm.cpu),
1635		.aarch64, .aarch64_be => comptime allCpusFromDecls(aarch64.cpu),
1636		.avr => comptime allCpusFromDecls(avr.cpu),
1637		.bpfel, .bpfeb => comptime allCpusFromDecls(bpf.cpu),
1638		.csky => comptime allCpusFromDecls(csky.cpu),
1639		.hexagon => comptime allCpusFromDecls(hexagon.cpu),
1640		.lanai => comptime allCpusFromDecls(lanai.cpu),
1641		.loongarch32, .loongarch64 => comptime allCpusFromDecls(loongarch.cpu),
1642		.m68k => comptime allCpusFromDecls(m68k.cpu),
1643		.mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
1644		.msp430 => comptime allCpusFromDecls(msp430.cpu),
1645		.powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1646		.amdgcn => comptime allCpusFromDecls(amdgcn.cpu),
1647		.riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1648		.sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
1649		.spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
1650		.s390x => comptime allCpusFromDecls(s390x.cpu),
1651		.x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
1652		.xcore => comptime allCpusFromDecls(xcore.cpu),
1653		.xtensa => comptime allCpusFromDecls(xtensa.cpu),
1654		.nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
1655		.ve => comptime allCpusFromDecls(ve.cpu),
1656		.wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
1657
1658		else => &[0]*const Model{},
	1653	return switch (arch.family()) {
	1654	inline else => \|f\| comptime allCpusFromDecls(@field(Target, @tagName(f)).cpu),
1659	1655	};
1660	1656	}
1661	1657
...	...	@@ -1871,49 +1867,24 @@ pub const Cpu = struct {
1871	1867	/// can return CPU models that are understood by LLVM, but not understood by Clang. If
1872	1868	/// Clang compatibility is important, consider using `baseline` instead.
1873	1869	pub fn generic(arch: Arch) *const Model {
1874		const S = struct {
1875		const generic_model = Model{
1876		.name = "generic",
1877		.llvm_name = null,
1878		.features = Cpu.Feature.Set.empty,
1879		};
1880		};
1881	1870	return switch (arch) {
1882	1871	.amdgcn => &amdgcn.cpu.gfx600,
1883		.arc => &arc.cpu.generic,
1884		.arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
1885		.aarch64, .aarch64_be => &aarch64.cpu.generic,
1886	1872	.avr => &avr.cpu.avr1,
1887		.bpfel, .bpfeb => &bpf.cpu.generic,
1888		.csky => &csky.cpu.generic,
1889		.hexagon => &hexagon.cpu.generic,
1890		.lanai => &lanai.cpu.generic,
1891	1873	.loongarch32 => &loongarch.cpu.generic_la32,
1892	1874	.loongarch64 => &loongarch.cpu.generic_la64,
1893		.m68k => &m68k.cpu.generic,
1894	1875	.mips, .mipsel => &mips.cpu.mips32,
1895	1876	.mips64, .mips64el => &mips.cpu.mips64,
1896		.msp430 => &msp430.cpu.generic,
	1877	.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1897	1878	.powerpc, .powerpcle => &powerpc.cpu.ppc,
1898	1879	.powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
1899	1880	.propeller => &propeller.cpu.p1,
1900	1881	.riscv32 => &riscv.cpu.generic_rv32,
1901	1882	.riscv64 => &riscv.cpu.generic_rv64,
1902		.spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
1903		.sparc => &sparc.cpu.generic,
1904		.sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
1905		.s390x => &s390x.cpu.generic,
	1883	.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
	1884	.wasm32, .wasm64 => &wasm.cpu.mvp,
1906	1885	.x86 => &x86.cpu.i386,
1907	1886	.x86_64 => &x86.cpu.x86_64,
1908		.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1909		.ve => &ve.cpu.generic,
1910		.wasm32, .wasm64 => &wasm.cpu.mvp,
1911		.xcore => &xcore.cpu.generic,
1912		.xtensa => &xtensa.cpu.generic,
1913
1914		.kalimba,
1915		.or1k,
1916		=> &S.generic_model,
	1887	inline else => \|a\| &@field(Target, @tagName(a.family())).cpu.generic,
1917	1888	};
1918	1889	}
1919	1890
...	...	@@ -1994,7 +1965,7 @@ pub const Cpu = struct {
1994	1965	.fs, .gs, .ss => (arch == .x86_64 or arch == .x86) and (context == null or context == .pointer),
1995	1966	.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has
1996	1967	.cog, .hub => arch == .propeller,
1997		.lut => arch == .propeller and std.Target.propeller.featureSetHas(cpu.features, .p2),
	1968	.lut => arch == .propeller and cpu.has(.propeller, .p2),
1998	1969
1999	1970	.global, .local, .shared => is_gpu,
2000	1971	.constant => is_gpu and (context == null or context == .constant),
...	...	@@ -2002,6 +1973,30 @@ pub const Cpu = struct {
2002	1973	.input, .output, .uniform, .push_constant, .storage_buffer, .physical_storage_buffer => is_spirv,
2003	1974	};
2004	1975	}
	1976
	1977	/// Returns true if `feature` is enabled.
	1978	pub fn has(cpu: Cpu, comptime family: Arch.Family, feature: @field(Target, @tagName(family)).Feature) bool {
	1979	if (family != cpu.arch.family()) return false;
	1980	return cpu.features.isEnabled(@intFromEnum(feature));
	1981	}
	1982
	1983	/// Returns true if any feature in `features` is enabled.
	1984	pub fn hasAny(cpu: Cpu, comptime family: Arch.Family, features: []const @field(Target, @tagName(family)).Feature) bool {
	1985	if (family != cpu.arch.family()) return false;
	1986	for (features) \|feature\| {
	1987	if (cpu.features.isEnabled(@intFromEnum(feature))) return true;
	1988	}
	1989	return false;
	1990	}
	1991
	1992	/// Returns true if all features in `features` are enabled.
	1993	pub fn hasAll(cpu: Cpu, comptime family: Arch.Family, features: []const @field(Target, @tagName(family)).Feature) bool {
	1994	if (family != cpu.arch.family()) return false;
	1995	for (features) \|feature\| {
	1996	if (!cpu.features.isEnabled(@intFromEnum(feature))) return false;
	1997	}
	1998	return true;
	1999	}
2005	2000	};
2006	2001
2007	2002	pub fn zigTriple(target: Target, allocator: Allocator) Allocator.Error![]u8 {
...	...	@@ -2295,7 +2290,7 @@ pub const DynamicLinker = struct {
2295	2290	.mips,
2296	2291	.mipsel,
2297	2292	=> \|arch\| initFmt("/lib/ld-musl-mips{s}{s}{s}.so.1", .{
2298		if (mips.featureSetHas(cpu.features, .mips32r6)) "r6" else "",
	2293	if (cpu.has(.mips, .mips32r6)) "r6" else "",
2299	2294	if (arch == .mipsel) "el" else "",
2300	2295	switch (abi) {
2301	2296	.musleabi => "-sf",
...	...	@@ -2312,7 +2307,7 @@ pub const DynamicLinker = struct {
2312	2307	.muslabin32 => "n32",
2313	2308	else => return none,
2314	2309	},
2315		if (mips.featureSetHas(cpu.features, .mips64r6)) "r6" else "",
	2310	if (cpu.has(.mips, .mips64r6)) "r6" else "",
2316	2311	if (arch == .mips64el) "el" else "",
2317	2312	}),
2318	2313
...	...	@@ -2326,9 +2321,9 @@ pub const DynamicLinker = struct {
2326	2321	.riscv64,
2327	2322	=> \|arch\| if (abi == .musl) initFmt("/lib/ld-musl-{s}{s}.so.1", .{
2328	2323	@tagName(arch),
2329		if (riscv.featureSetHas(cpu.features, .d))
	2324	if (cpu.has(.riscv, .d))
2330	2325	""
2331		else if (riscv.featureSetHas(cpu.features, .f))
	2326	else if (cpu.has(.riscv, .f))
2332	2327	"-sp"
2333	2328	else
2334	2329	"-sf",
...	...	@@ -2385,7 +2380,7 @@ pub const DynamicLinker = struct {
2385	2380	.gnueabi,
2386	2381	.gnueabihf,
2387	2382	=> initFmt("/lib/ld{s}.so.1", .{
2388		if (mips.featureSetHas(cpu.features, .nan2008)) "-linux-mipsn8" else "",
	2383	if (cpu.has(.mips, .nan2008)) "-linux-mipsn8" else "",
2389	2384	}),
2390	2385	else => none,
2391	2386	},
...	...	@@ -2398,7 +2393,7 @@ pub const DynamicLinker = struct {
2398	2393	.gnuabin32 => "32",
2399	2394	else => return none,
2400	2395	},
2401		if (mips.featureSetHas(cpu.features, .nan2008)) "-linux-mipsn8" else "",
	2396	if (cpu.has(.mips, .nan2008)) "-linux-mipsn8" else "",
2402	2397	}),
2403	2398
2404	2399	.powerpc => switch (abi) {
...	...	@@ -2419,9 +2414,9 @@ pub const DynamicLinker = struct {
2419	2414	.riscv64 => "riscv64-lp64",
2420	2415	else => unreachable,
2421	2416	},
2422		if (riscv.featureSetHas(cpu.features, .d))
	2417	if (cpu.has(.riscv, .d))
2423	2418	"d"
2424		else if (riscv.featureSetHas(cpu.features, .f))
	2419	else if (cpu.has(.riscv, .f))
2425	2420	"f"
2426	2421	else
2427	2422	"",
...	...	@@ -2686,7 +2681,7 @@ pub fn stackAlignment(target: Target) u16 {
2686	2681	=> if (target.os.tag == .linux or target.os.tag == .aix) return 16,
2687	2682	.riscv32,
2688	2683	.riscv64,
2689		=> if (!Target.riscv.featureSetHas(target.cpu.features, .e)) return 16,
	2684	=> if (!target.cpu.has(.riscv, .e)) return 16,
2690	2685	.x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
2691	2686	.x86_64 => return 16,
2692	2687	else => {},
...	...	@@ -3398,6 +3393,7 @@ const Target = @This();
3398	3393	const std = @import("std.zig");
3399	3394	const builtin = @import("builtin");
3400	3395	const Allocator = std.mem.Allocator;
	3396	const assert = std.debug.assert;
3401	3397
3402	3398	test {
3403	3399	std.testing.refAllDecls(Cpu.Arch);

lib/std/Target/Query.zig+10-10

...	...	@@ -653,16 +653,16 @@ test parse {
653	653	try std.testing.expect(target.os.tag == .linux);
654	654	try std.testing.expect(target.abi == .gnu);
655	655	try std.testing.expect(target.cpu.arch == .x86_64);
656		try std.testing.expect(!Target.x86.featureSetHas(target.cpu.features, .sse));
657		try std.testing.expect(!Target.x86.featureSetHas(target.cpu.features, .avx));
658		try std.testing.expect(!Target.x86.featureSetHas(target.cpu.features, .cx8));
659		try std.testing.expect(Target.x86.featureSetHas(target.cpu.features, .cmov));
660		try std.testing.expect(Target.x86.featureSetHas(target.cpu.features, .fxsr));
	656	try std.testing.expect(!target.cpu.has(.x86, .sse));
	657	try std.testing.expect(!target.cpu.has(.x86, .avx));
	658	try std.testing.expect(!target.cpu.has(.x86, .cx8));
	659	try std.testing.expect(target.cpu.has(.x86, .cmov));
	660	try std.testing.expect(target.cpu.has(.x86, .fxsr));
661	661
662		try std.testing.expect(Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov }));
663		try std.testing.expect(!Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx }));
664		try std.testing.expect(Target.x86.featureSetHasAll(target.cpu.features, .{ .mmx, .x87 }));
665		try std.testing.expect(!Target.x86.featureSetHasAll(target.cpu.features, .{ .mmx, .x87, .sse }));
	662	try std.testing.expect(target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov }));
	663	try std.testing.expect(!target.cpu.hasAny(.x86, &.{ .sse, .avx }));
	664	try std.testing.expect(target.cpu.hasAll(.x86, &.{ .mmx, .x87 }));
	665	try std.testing.expect(!target.cpu.hasAll(.x86, &.{ .mmx, .x87, .sse }));
666	666
667	667	const text = try query.zigTriple(std.testing.allocator);
668	668	defer std.testing.allocator.free(text);
...	...	@@ -679,7 +679,7 @@ test parse {
679	679	try std.testing.expect(target.abi == .musleabihf);
680	680	try std.testing.expect(target.cpu.arch == .arm);
681	681	try std.testing.expect(target.cpu.model == &Target.arm.cpu.generic);
682		try std.testing.expect(Target.arm.featureSetHas(target.cpu.features, .v8a));
	682	try std.testing.expect(target.cpu.has(.arm, .v8a));
683	683
684	684	const text = try query.zigTriple(std.testing.allocator);
685	685	defer std.testing.allocator.free(text);

lib/std/Target/generic.zig created+20

...	...	@@ -0,0 +1,20 @@
	1	const std = @import("../std.zig");
	2	const CpuFeature = std.Target.Cpu.Feature;
	3	const CpuModel = std.Target.Cpu.Model;
	4
	5	pub const Feature = enum {};
	6
	7	pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
	8	pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
	9	pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
	10	pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
	11
	12	pub const all_features: [0]CpuFeature = .{};
	13
	14	pub const cpu = struct {
	15	pub const generic: CpuModel = .{
	16	.name = "generic",
	17	.llvm_name = null,
	18	.features = featureSet(&.{}),
	19	};
	20	};

lib/std/Thread/Futex.zig+4-6

...	...	@@ -461,9 +461,8 @@ const DragonflyImpl = struct {
461	461
462	462	const WasmImpl = struct {
463	463	fn wait(ptr: *const atomic.Value(u32), expect: u32, timeout: ?u64) error{Timeout}!void {
464		if (!comptime std.Target.wasm.featureSetHas(builtin.target.cpu.features, .atomics)) {
465		@compileError("WASI target missing cpu feature 'atomics'");
466		}
	464	if (!comptime builtin.cpu.has(.wasm, .atomics)) @compileError("WASI target missing cpu feature 'atomics'");
	465
467	466	const to: i64 = if (timeout) \|to\| @intCast(to) else -1;
468	467	const result = asm volatile (
469	468	\\local.get %[ptr]
...	...	@@ -485,9 +484,8 @@ const WasmImpl = struct {
485	484	}
486	485
487	486	fn wake(ptr: *const atomic.Value(u32), max_waiters: u32) void {
488		if (!comptime std.Target.wasm.featureSetHas(builtin.target.cpu.features, .atomics)) {
489		@compileError("WASI target missing cpu feature 'atomics'");
490		}
	487	if (!comptime builtin.cpu.has(.wasm, .atomics)) @compileError("WASI target missing cpu feature 'atomics'");
	488
491	489	assert(max_waiters != 0);
492	490	const woken_count = asm volatile (
493	491	\\local.get %[ptr]

lib/std/atomic.zig+4-9

...	...	@@ -378,13 +378,8 @@ pub inline fn spinLoopHint() void {
378	378	.armeb,
379	379	.thumb,
380	380	.thumbeb,
381		=> {
382		const can_yield = comptime std.Target.arm.featureSetHasAny(builtin.target.cpu.features, .{
383		.has_v6k, .has_v6m,
384		});
385		if (can_yield) {
386		asm volatile ("yield");
387		}
	381	=> if (comptime builtin.cpu.hasAny(.arm, &.{ .has_v6k, .has_v6m })) {
	382	asm volatile ("yield");
388	383	},
389	384
390	385	// The 8-bit immediate specifies the amount of cycles to pause for. We can't really be too
...	...	@@ -394,7 +389,7 @@ pub inline fn spinLoopHint() void {
394	389
395	390	.riscv32,
396	391	.riscv64,
397		=> if (comptime std.Target.riscv.featureSetHas(builtin.target.cpu.features, .zihintpause)) {
	392	=> if (comptime builtin.cpu.has(.riscv, .zihintpause)) {
398	393	asm volatile ("pause");
399	394	},
400	395
...	...	@@ -430,7 +425,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
430	425
431	426	// https://github.com/llvm/llvm-project/blob/e379094328e49731a606304f7e3559d4f1fa96f9/clang/lib/Basic/Targets/Hexagon.h#L145-L151
432	427	.hexagon,
433		=> if (std.Target.hexagon.featureSetHas(cpu.features, .v73)) 64 else 32,
	428	=> if (cpu.has(.hexagon, .v73)) 64 else 32,
434	429
435	430	// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
436	431	// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7

lib/std/crypto/aes.zig+3-3

...	...	@@ -2,9 +2,9 @@ const std = @import("../std.zig");
2	2	const builtin = @import("builtin");
3	3	const testing = std.testing;
4	4
5		const has_aesni = std.Target.x86.featureSetHas(builtin.cpu.features, .aes);
6		const has_avx = std.Target.x86.featureSetHas(builtin.cpu.features, .avx);
7		const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes);
	5	const has_aesni = builtin.cpu.has(.x86, .aes);
	6	const has_avx = builtin.cpu.has(.x86, .avx);
	7	const has_armaes = builtin.cpu.has(.aarch64, .aes);
8	8	// C backend doesn't currently support passing vectors to inline asm.
9	9	const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_aesni and has_avx) impl: {
10	10	break :impl @import("aes/aesni.zig");

lib/std/crypto/aes/aesni.zig+2-2

...	...	@@ -3,8 +3,8 @@ const builtin = @import("builtin");
3	3	const mem = std.mem;
4	4	const debug = std.debug;
5	5
6		const has_vaes = builtin.cpu.arch == .x86_64 and std.Target.x86.featureSetHas(builtin.cpu.features, .vaes);
7		const has_avx512f = builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_x86_64 and std.Target.x86.featureSetHas(builtin.cpu.features, .avx512f);
	6	const has_vaes = builtin.cpu.arch == .x86_64 and builtin.cpu.has(.x86, .vaes);
	7	const has_avx512f = builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_x86_64 and builtin.cpu.has(.x86, .avx512f);
8	8
9	9	/// A single AES block.
10	10	pub const Block = struct {

lib/std/crypto/aes_ocb.zig+2-2

...	...	@@ -101,8 +101,8 @@ fn AesOcb(comptime Aes: anytype) type {
101	101	return offset;
102	102	}
103	103
104		const has_aesni = std.Target.x86.featureSetHas(builtin.cpu.features, .aes);
105		const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes);
	104	const has_aesni = builtin.cpu.has(.x86, .aes);
	105	const has_armaes = builtin.cpu.has(.aarch64, .aes);
106	106	const wb: usize = if ((builtin.cpu.arch == .x86_64 and has_aesni) or (builtin.cpu.arch == .aarch64 and has_armaes)) 4 else 0;
107	107
108	108	/// c: ciphertext: output buffer should be of size m.len

lib/std/crypto/chacha20.zig+3-3

...	...	@@ -499,12 +499,12 @@ fn ChaChaNonVecImpl(comptime rounds_nb: usize) type {
499	499	fn ChaChaImpl(comptime rounds_nb: usize) type {
500	500	switch (builtin.cpu.arch) {
501	501	.x86_64 => {
502		if (builtin.zig_backend != .stage2_x86_64 and std.Target.x86.featureSetHas(builtin.cpu.features, .avx512f)) return ChaChaVecImpl(rounds_nb, 4);
503		if (std.Target.x86.featureSetHas(builtin.cpu.features, .avx2)) return ChaChaVecImpl(rounds_nb, 2);
	502	if (builtin.zig_backend != .stage2_x86_64 and builtin.cpu.has(.x86, .avx512f)) return ChaChaVecImpl(rounds_nb, 4);
	503	if (builtin.cpu.has(.x86, .avx2)) return ChaChaVecImpl(rounds_nb, 2);
504	504	return ChaChaVecImpl(rounds_nb, 1);
505	505	},
506	506	.aarch64 => {
507		if (builtin.zig_backend != .stage2_aarch64 and std.Target.aarch64.featureSetHas(builtin.cpu.features, .neon)) return ChaChaVecImpl(rounds_nb, 4);
	507	if (builtin.zig_backend != .stage2_aarch64 and builtin.cpu.has(.aarch64, .neon)) return ChaChaVecImpl(rounds_nb, 4);
508	508	return ChaChaNonVecImpl(rounds_nb);
509	509	},
510	510	else => return ChaChaNonVecImpl(rounds_nb),

lib/std/crypto/ghash_polyval.zig+3-3

...	...	@@ -284,9 +284,9 @@ fn Hash(comptime endian: std.builtin.Endian, comptime shift_key: bool) type {
284	284	return d ^ hi;
285	285	}
286	286
287		const has_pclmul = std.Target.x86.featureSetHas(builtin.cpu.features, .pclmul);
288		const has_avx = std.Target.x86.featureSetHas(builtin.cpu.features, .avx);
289		const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes);
	287	const has_pclmul = builtin.cpu.has(.x86, .pclmul);
	288	const has_avx = builtin.cpu.has(.x86, .avx);
	289	const has_armaes = builtin.cpu.has(.aarch64, .aes);
290	290	// C backend doesn't currently support passing vectors to inline asm.
291	291	const clmul = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_pclmul and has_avx) impl: {
292	292	break :impl clmulPclmul;

lib/std/crypto/sha2.zig+2-2

...	...	@@ -200,7 +200,7 @@ fn Sha2x32(comptime iv: Iv32, digest_bits: comptime_int) type {
200	200	if (!@inComptime()) {
201	201	const V4u32 = @Vector(4, u32);
202	202	switch (builtin.cpu.arch) {
203		.aarch64 => if (builtin.zig_backend != .stage2_c and comptime std.Target.aarch64.featureSetHas(builtin.cpu.features, .sha2)) {
	203	.aarch64 => if (builtin.zig_backend != .stage2_c and comptime builtin.cpu.has(.aarch64, .sha2)) {
204	204	var x: V4u32 = d.s[0..4].*;
205	205	var y: V4u32 = d.s[4..8].*;
206	206	const s_v = @as(*[16]V4u32, @ptrCast(&s));
...	...	@@ -238,7 +238,7 @@ fn Sha2x32(comptime iv: Iv32, digest_bits: comptime_int) type {
238	238	return;
239	239	},
240	240	// C backend doesn't currently support passing vectors to inline asm.
241		.x86_64 => if (builtin.zig_backend != .stage2_c and comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sha, .avx2 })) {
	241	.x86_64 => if (builtin.zig_backend != .stage2_c and comptime builtin.cpu.hasAll(.x86, &.{ .sha, .avx2 })) {
242	242	var x: V4u32 = [_]u32{ d.s[5], d.s[4], d.s[1], d.s[0] };
243	243	var y: V4u32 = [_]u32{ d.s[7], d.s[6], d.s[3], d.s[2] };
244	244	const s_v = @as(*[16]V4u32, @ptrCast(&s));

lib/std/debug.zig+1-1

...	...	@@ -773,7 +773,7 @@ pub const StackIterator = struct {
773	773	pub fn init(first_address: ?usize, fp: ?usize) StackIterator {
774	774	if (native_arch.isSPARC()) {
775	775	// Flush all the register windows on stack.
776		asm volatile (if (std.Target.sparc.featureSetHas(builtin.cpu.features, .v9))
	776	asm volatile (if (builtin.cpu.has(.sparc, .v9))
777	777	"flushw"
778	778	else
779	779	"ta 3" // ST_FLUSH_WINDOWS

lib/std/math.zig+1-2

...	...	@@ -1365,8 +1365,7 @@ pub fn lerp(a: anytype, b: anytype, t: anytype) @TypeOf(a, b, t) {
1365	1365
1366	1366	test lerp {
1367	1367	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/17884
1368		if (builtin.zig_backend == .stage2_x86_64 and
1369		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .fma)) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/17884
	1368	if (builtin.zig_backend == .stage2_x86_64 and !comptime builtin.cpu.has(.x86, .fma)) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/17884
1370	1369
1371	1370	try testing.expectEqual(@as(f64, 75), lerp(50, 100, 0.5));
1372	1371	try testing.expectEqual(@as(f32, 43.75), lerp(50, 25, 0.25));

lib/std/simd.zig+31-40

...	...	@@ -13,68 +13,59 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
13	13	const element_bit_size = @max(8, std.math.ceilPowerOfTwo(u16, @bitSizeOf(T)) catch unreachable);
14	14	const vector_bit_size: u16 = blk: {
15	15	if (cpu.arch.isX86()) {
16		if (T == bool and std.Target.x86.featureSetHas(cpu.features, .prefer_mask_registers)) return 64;
17		if (builtin.zig_backend != .stage2_x86_64 and std.Target.x86.featureSetHas(cpu.features, .avx512f) and !std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .prefer_128_bit })) break :blk 512;
18		if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;
19		if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;
20		if (std.Target.x86.featureSetHasAny(cpu.features, .{ .mmx, .@"3dnow" })) break :blk 64;
	16	if (T == bool and cpu.has(.x86, .prefer_mask_registers)) return 64;
	17	if (builtin.zig_backend != .stage2_x86_64 and cpu.has(.x86, .avx512f) and !cpu.hasAny(.x86, &.{ .prefer_256_bit, .prefer_128_bit })) break :blk 512;
	18	if (cpu.hasAny(.x86, &.{ .prefer_256_bit, .avx2 }) and !cpu.has(.x86, .prefer_128_bit)) break :blk 256;
	19	if (cpu.has(.x86, .sse)) break :blk 128;
	20	if (cpu.hasAny(.x86, &.{ .mmx, .@"3dnow" })) break :blk 64;
21	21	} else if (cpu.arch.isArm()) {
22		if (std.Target.arm.featureSetHas(cpu.features, .neon)) break :blk 128;
	22	if (cpu.has(.arm, .neon)) break :blk 128;
23	23	} else if (cpu.arch.isAARCH64()) {
24	24	// SVE allows up to 2048 bits in the specification, as of 2022 the most powerful machine has implemented 512-bit
25	25	// I think is safer to just be on 128 until is more common
26	26	// TODO: Check on this return when bigger values are more common
27		if (std.Target.aarch64.featureSetHas(cpu.features, .sve)) break :blk 128;
28		if (std.Target.aarch64.featureSetHas(cpu.features, .neon)) break :blk 128;
	27	if (cpu.has(.aarch64, .sve)) break :blk 128;
	28	if (cpu.has(.aarch64, .neon)) break :blk 128;
29	29	} else if (cpu.arch.isPowerPC()) {
30		if (std.Target.powerpc.featureSetHas(cpu.features, .altivec)) break :blk 128;
	30	if (cpu.has(.powerpc, .altivec)) break :blk 128;
31	31	} else if (cpu.arch.isMIPS()) {
32		if (std.Target.mips.featureSetHas(cpu.features, .msa)) break :blk 128;
	32	if (cpu.has(.mips, .msa)) break :blk 128;
33	33	// TODO: Test MIPS capability to handle bigger vectors
34	34	// In theory MDMX and by extension mips3d have 32 registers of 64 bits which can use in parallel
35	35	// for multiple processing, but I don't know what's optimal here, if using
36	36	// the 2048 bits or using just 64 per vector or something in between
37		if (std.Target.mips.featureSetHas(cpu.features, std.Target.mips.Feature.mips3d)) break :blk 64;
	37	if (cpu.has(.mips, .mips3d)) break :blk 64;
38	38	} else if (cpu.arch.isRISCV()) {
39	39	// In RISC-V Vector Registers are length agnostic so there's no good way to determine the best size.
40	40	// The usual vector length in most RISC-V cpus is 256 bits, however it can get to multiple kB.
41		if (std.Target.riscv.featureSetHas(cpu.features, .v)) {
42		var vec_bit_length: u32 = 256;
43		if (std.Target.riscv.featureSetHas(cpu.features, .zvl32b)) {
44		vec_bit_length = 32;
45		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl64b)) {
46		vec_bit_length = 64;
47		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl128b)) {
48		vec_bit_length = 128;
49		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl256b)) {
50		vec_bit_length = 256;
51		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl512b)) {
52		vec_bit_length = 512;
53		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl1024b)) {
54		vec_bit_length = 1024;
55		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl2048b)) {
56		vec_bit_length = 2048;
57		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl4096b)) {
58		vec_bit_length = 4096;
59		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl8192b)) {
60		vec_bit_length = 8192;
61		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl16384b)) {
62		vec_bit_length = 16384;
63		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl32768b)) {
64		vec_bit_length = 32768;
65		} else if (std.Target.riscv.featureSetHas(cpu.features, .zvl65536b)) {
66		vec_bit_length = 65536;
	41	if (cpu.has(.riscv, .v)) {
	42	inline for (.{
	43	.{ .zvl65536b, 65536 },
	44	.{ .zvl32768b, 32768 },
	45	.{ .zvl16384b, 16384 },
	46	.{ .zvl8192b, 8192 },
	47	.{ .zvl4096b, 4096 },
	48	.{ .zvl2048b, 2048 },
	49	.{ .zvl1024b, 1024 },
	50	.{ .zvl512b, 512 },
	51	.{ .zvl256b, 256 },
	52	.{ .zvl128b, 128 },
	53	.{ .zvl64b, 64 },
	54	.{ .zvl32b, 32 },
	55	}) \|mapping\| {
	56	if (cpu.has(.riscv, mapping[0])) break :blk mapping[1];
67	57	}
68		break :blk vec_bit_length;
	58
	59	break :blk 256;
69	60	}
70	61	} else if (cpu.arch.isSPARC()) {
71	62	// TODO: Test Sparc capability to handle bigger vectors
72	63	// In theory Sparc have 32 registers of 64 bits which can use in parallel
73	64	// for multiple processing, but I don't know what's optimal here, if using
74	65	// the 2048 bits or using just 64 per vector or something in between
75		if (std.Target.sparc.featureSetHasAny(cpu.features, .{ .vis, .vis2, .vis3 })) break :blk 64;
	66	if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;
76	67	} else if (cpu.arch.isWasm()) {
77		if (std.Target.wasm.featureSetHas(cpu.features, .simd128)) break :blk 128;
	68	if (cpu.has(.wasm, .simd128)) break :blk 128;
78	69	}
79	70	return null;
80	71	};

lib/std/zig/system.zig+1-1

...	...	@@ -109,7 +109,7 @@ pub fn getExternalExecutor(
109	109	.riscv64 => Executor{ .qemu = "qemu-riscv64" },
110	110	.s390x => Executor{ .qemu = "qemu-s390x" },
111	111	.sparc => Executor{
112		.qemu = if (std.Target.sparc.featureSetHas(candidate.cpu.features, .v9))
	112	.qemu = if (candidate.cpu.has(.sparc, .v9))
113	113	"qemu-sparc32plus"
114	114	else
115	115	"qemu-sparc",

lib/std/zig/system/x86.zig+9-9

...	...	@@ -77,7 +77,7 @@ pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, os: Target.Os, query: T
77	77	detectIntelProcessor(&cpu, family, model, brand_id);
78	78	},
79	79	0x68747541 => {
80		if (detectAMDProcessor(cpu.features, family, model)) \|m\| cpu.model = m;
	80	if (detectAMDProcessor(cpu, family, model)) \|m\| cpu.model = m;
81	81	},
82	82	else => {},
83	83	}
...	...	@@ -107,7 +107,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
107	107	return;
108	108	},
109	109	5 => {
110		if (Target.x86.featureSetHas(cpu.features, .mmx)) {
	110	if (cpu.has(.x86, .mmx)) {
111	111	cpu.model = &Target.x86.cpu.pentium_mmx;
112	112	return;
113	113	}
...	...	@@ -177,10 +177,10 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
177	177	return;
178	178	},
179	179	0x55 => {
180		if (Target.x86.featureSetHas(cpu.features, .avx512bf16)) {
	180	if (cpu.has(.x86, .avx512bf16)) {
181	181	cpu.model = &Target.x86.cpu.cooperlake;
182	182	return;
183		} else if (Target.x86.featureSetHas(cpu.features, .avx512vnni)) {
	183	} else if (cpu.has(.x86, .avx512vnni)) {
184	184	cpu.model = &Target.x86.cpu.cascadelake;
185	185	return;
186	186	} else {
...	...	@@ -296,11 +296,11 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
296	296	}
297	297	},
298	298	15 => {
299		if (Target.x86.featureSetHas(cpu.features, .@"64bit")) {
	299	if (cpu.has(.x86, .@"64bit")) {
300	300	cpu.model = &Target.x86.cpu.nocona;
301	301	return;
302	302	}
303		if (Target.x86.featureSetHas(cpu.features, .sse3)) {
	303	if (cpu.has(.x86, .sse3)) {
304	304	cpu.model = &Target.x86.cpu.prescott;
305	305	return;
306	306	}
...	...	@@ -311,7 +311,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
311	311	}
312	312	}
313	313
314		fn detectAMDProcessor(features: Target.Cpu.Feature.Set, family: u32, model: u32) ?*const Target.Cpu.Model {
	314	fn detectAMDProcessor(cpu: Target.Cpu, family: u32, model: u32) ?*const Target.Cpu.Model {
315	315	return switch (family) {
316	316	4 => &Target.x86.cpu.i486,
317	317	5 => switch (model) {
...	...	@@ -321,11 +321,11 @@ fn detectAMDProcessor(features: Target.Cpu.Feature.Set, family: u32, model: u32)
321	321	10 => &Target.x86.cpu.geode,
322	322	else => &Target.x86.cpu.pentium,
323	323	},
324		6 => if (Target.x86.featureSetHas(features, .sse))
	324	6 => if (cpu.has(.x86, .sse))
325	325	&Target.x86.cpu.athlon_xp
326	326	else
327	327	&Target.x86.cpu.athlon,
328		15 => if (Target.x86.featureSetHas(features, .sse3))
	328	15 => if (cpu.has(.x86, .sse3))
329	329	&Target.x86.cpu.k8_sse3
330	330	else
331	331	&Target.x86.cpu.k8,

src/Builtin.zig+3-3

...	...	@@ -47,7 +47,7 @@ pub fn generate(opts: @This(), allocator: Allocator) Allocator.Error![:0]u8 {
47	47
48	48	pub fn append(opts: @This(), buffer: *std.ArrayList(u8)) Allocator.Error!void {
49	49	const target = opts.target;
50		const generic_arch_name = target.cpu.arch.genericName();
	50	const arch_family_name = @tagName(target.cpu.arch.family());
51	51	const zig_backend = opts.zig_backend;
52	52
53	53	@setEvalBranchQuota(4000);
...	...	@@ -80,9 +80,9 @@ pub fn append(opts: @This(), buffer: *std.ArrayList(u8)) Allocator.Error!void {
80	80	opts.single_threaded,
81	81	std.zig.fmtId(@tagName(target.abi)),
82	82	std.zig.fmtId(@tagName(target.cpu.arch)),
83		std.zig.fmtId(generic_arch_name),
	83	std.zig.fmtId(arch_family_name),
84	84	std.zig.fmtId(target.cpu.model.name),
85		std.zig.fmtId(generic_arch_name),
	85	std.zig.fmtId(arch_family_name),
86	86	});
87	87
88	88	for (target.cpu.arch.allFeaturesList(), 0..) \|feature, index_usize\| {

src/Compilation.zig+4-4

...	...	@@ -6469,7 +6469,7 @@ pub fn addCCArgs(
6469	6469	var march_index: usize = prefix_len;
6470	6470	@memcpy(march_buf[0..prefix.len], prefix);
6471	6471
6472		if (std.Target.riscv.featureSetHas(target.cpu.features, .e)) {
	6472	if (target.cpu.has(.riscv, .e)) {
6473	6473	march_buf[march_index] = 'e';
6474	6474	} else {
6475	6475	march_buf[march_index] = 'i';
...	...	@@ -6477,7 +6477,7 @@ pub fn addCCArgs(
6477	6477	march_index += 1;
6478	6478
6479	6479	for (letters) \|letter\| {
6480		if (std.Target.riscv.featureSetHas(target.cpu.features, letter.feat)) {
	6480	if (target.cpu.has(.riscv, letter.feat)) {
6481	6481	march_buf[march_index] = letter.char;
6482	6482	march_index += 1;
6483	6483	}
...	...	@@ -6488,12 +6488,12 @@ pub fn addCCArgs(
6488	6488	});
6489	6489	try argv.append(march_arg);
6490	6490
6491		if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) {
	6491	if (target.cpu.has(.riscv, .relax)) {
6492	6492	try argv.append("-mrelax");
6493	6493	} else {
6494	6494	try argv.append("-mno-relax");
6495	6495	}
6496		if (std.Target.riscv.featureSetHas(target.cpu.features, .save_restore)) {
	6496	if (target.cpu.has(.riscv, .save_restore)) {
6497	6497	try argv.append("-msave-restore");
6498	6498	} else {
6499	6499	try argv.append("-mno-save-restore");

src/Compilation/Config.zig+1-1

...	...	@@ -166,7 +166,7 @@ pub fn resolve(options: Options) ResolveError!Config {
166	166	if (options.shared_memory == true) return error.ObjectFilesCannotShareMemory;
167	167	break :b false;
168	168	}
169		if (!std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })) {
	169	if (!target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })) {
170	170	if (options.shared_memory == true)
171	171	return error.SharedMemoryRequiresAtomicsAndBulkMemory;
172	172	break :b false;

src/Sema.zig+3-3

...	...	@@ -9594,7 +9594,7 @@ fn checkMergeAllowed(sema: Sema, block: Block, src: LazySrcLoc, peer_ty: Type)
9594	9594	const backend = target_util.zigBackend(target, zcu.comp.config.use_llvm);
9595	9595	try sema.errNote(src, msg, "pointers with address space '{s}' cannot be returned from a branch on target {s}-{s} by compiler backend {s}", .{
9596	9596	@tagName(as),
9597		target.cpu.arch.genericName(),
	9597	@tagName(target.cpu.arch.family()),
9598	9598	@tagName(target.os.tag),
9599	9599	@tagName(backend),
9600	9600	});
...	...	@@ -23604,7 +23604,7 @@ fn checkLogicalPtrOperation(sema: Sema, block: Block, src: LazySrcLoc, ty: Typ
23604	23604	"cannot perform arithmetic on pointers with address space '{s}' on target {s}-{s}",
23605	23605	.{
23606	23606	@tagName(as),
23607		target.cpu.arch.genericName(),
	23607	@tagName(target.cpu.arch.family()),
23608	23608	@tagName(target.os.tag),
23609	23609	},
23610	23610	);
...	...	@@ -36719,7 +36719,7 @@ pub fn analyzeAsAddressSpace(
36719	36719	block,
36720	36720	src,
36721	36721	"{s} with address space '{s}' are not supported on {s}",
36722		.{ entity, @tagName(address_space), target.cpu.arch.genericName() },
	36722	.{ entity, @tagName(address_space), @tagName(target.cpu.arch.family()) },
36723	36723	);
36724	36724	}
36725	36725

src/Type.zig+4-4

...	...	@@ -993,8 +993,8 @@ pub fn abiAlignmentInner(
993	993	},
994	994	.stage2_x86_64 => {
995	995	if (vector_type.child == .bool_type) {
996		if (vector_type.len > 256 and std.Target.x86.featureSetHas(target.cpu.features, .avx512f)) return .{ .scalar = .@"64" };
997		if (vector_type.len > 128 and std.Target.x86.featureSetHas(target.cpu.features, .avx)) return .{ .scalar = .@"32" };
	996	if (vector_type.len > 256 and target.cpu.has(.x86, .avx512f)) return .{ .scalar = .@"64" };
	997	if (vector_type.len > 128 and target.cpu.has(.x86, .avx)) return .{ .scalar = .@"32" };
998	998	if (vector_type.len > 64) return .{ .scalar = .@"16" };
999	999	const bytes = std.math.divCeil(u32, vector_type.len, 8) catch unreachable;
1000	1000	const alignment = std.math.ceilPowerOfTwoAssert(u32, bytes);
...	...	@@ -1003,8 +1003,8 @@ pub fn abiAlignmentInner(
1003	1003	const elem_bytes: u32 = @intCast((try Type.fromInterned(vector_type.child).abiSizeInner(strat, zcu, tid)).scalar);
1004	1004	if (elem_bytes == 0) return .{ .scalar = .@"1" };
1005	1005	const bytes = elem_bytes * vector_type.len;
1006		if (bytes > 32 and std.Target.x86.featureSetHas(target.cpu.features, .avx512f)) return .{ .scalar = .@"64" };
1007		if (bytes > 16 and std.Target.x86.featureSetHas(target.cpu.features, .avx)) return .{ .scalar = .@"32" };
	1006	if (bytes > 32 and target.cpu.has(.x86, .avx512f)) return .{ .scalar = .@"64" };
	1007	if (bytes > 16 and target.cpu.has(.x86, .avx)) return .{ .scalar = .@"32" };
1008	1008	return .{ .scalar = .@"16" };
1009	1009	},
1010	1010	}

src/Zcu.zig+2-2

...	...	@@ -3741,7 +3741,7 @@ pub fn errorSetBits(zcu: *const Zcu) u16 {
3741	3741
3742	3742	if (zcu.error_limit == 0) return 0;
3743	3743	if (target.cpu.arch.isSpirV()) {
3744		if (!std.Target.spirv.featureSetHas(target.cpu.features, .storage_push_constant16)) {
	3744	if (!target.cpu.has(.spirv, .storage_push_constant16)) {
3745	3745	return 32;
3746	3746	}
3747	3747	}
...	...	@@ -3911,7 +3911,7 @@ pub fn atomicPtrAlignment(
3911	3911	.aarch64_be,
3912	3912	=> 128,
3913	3913
3914		.x86_64 => if (std.Target.x86.featureSetHas(target.cpu.features, .cx16)) 128 else 64,
	3914	.x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64,
3915	3915	};
3916	3916
3917	3917	if (ty.toIntern() == .bool_type) return .none;

src/arch/arm/CodeGen.zig+3-3

...	...	@@ -4344,7 +4344,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallModifier
4344	4344
4345	4345	// TODO: add Instruction.supportedOn
4346	4346	// function for ARM
4347		if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
	4347	if (self.target.cpu.has(.arm, .has_v5t)) {
4348	4348	_ = try self.addInst(.{
4349	4349	.tag = .blx,
4350	4350	.data = .{ .reg = .lr },
...	...	@@ -5578,7 +5578,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5578	5578	} },
5579	5579	});
5580	5580	} else if (x <= math.maxInt(u16)) {
5581		if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
	5581	if (self.target.cpu.has(.arm, .has_v7)) {
5582	5582	_ = try self.addInst(.{
5583	5583	.tag = .movw,
5584	5584	.data = .{ .r_imm16 = .{
...	...	@@ -5606,7 +5606,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5606	5606	} else {
5607	5607	// TODO write constant to code and load
5608	5608	// relative to pc
5609		if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
	5609	if (self.target.cpu.has(.arm, .has_v7)) {
5610	5610	// immediate: 0xaaaabbbb
5611	5611	// movw reg, #0xbbbb
5612	5612	// movt reg, #0xaaaa

src/arch/arm/Emit.zig+2-2

...	...	@@ -203,7 +203,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
203	203	} else if (Instruction.Operand.fromU32(imm32) != null) {
204	204	// sub
205	205	return 1 * 4;
206		} else if (Target.arm.featureSetHas(emit.target.cpu.features, .has_v7)) {
	206	} else if (emit.target.cpu.has(.arm, .has_v7)) {
207	207	// movw; movt; sub
208	208	return 3 * 4;
209	209	} else {
...	...	@@ -452,7 +452,7 @@ fn mirSubStackPointer(emit: *Emit, inst: Mir.Inst.Index) !void {
452	452	const operand = Instruction.Operand.fromU32(imm32) orelse blk: {
453	453	const scratch: Register = .r4;
454	454
455		if (Target.arm.featureSetHas(emit.target.cpu.features, .has_v7)) {
	455	if (emit.target.cpu.has(.arm, .has_v7)) {
456	456	try emit.writeInstruction(Instruction.movw(cond, scratch, @as(u16, @truncate(imm32))));
457	457	try emit.writeInstruction(Instruction.movt(cond, scratch, @as(u16, @truncate(imm32 >> 16))));
458	458	} else {

src/arch/riscv64/CodeGen.zig+1-1

...	...	@@ -8455,7 +8455,7 @@ fn typeOfIndex(func: *Func, inst: Air.Inst.Index) Type {
8455	8455	}
8456	8456
8457	8457	fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool {
8458		return Target.riscv.featureSetHas(func.target.cpu.features, feature);
	8458	return func.target.cpu.has(.riscv, feature);
8459	8459	}
8460	8460
8461	8461	pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Zcu) u64 {

src/arch/riscv64/Lower.zig+1-3

...	...	@@ -590,9 +590,7 @@ pub fn fail(lower: *Lower, comptime format: []const u8, args: anytype) Error {
590	590	}
591	591
592	592	fn hasFeature(lower: *Lower, feature: std.Target.riscv.Feature) bool {
593		const target = lower.pt.zcu.getTarget();
594		const features = target.cpu.features;
595		return std.Target.riscv.featureSetHas(features, feature);
	593	return lower.pt.zcu.getTarget().cpu.has(.riscv, feature);
596	594	}
597	595
598	596	const Lower = @This();

src/arch/riscv64/abi.zig+3-4

...	...	@@ -22,7 +22,7 @@ pub fn classifyType(ty: Type, zcu: *Zcu) Class {
22	22	return .byval;
23	23	}
24	24
25		if (std.Target.riscv.featureSetHas(target.cpu.features, .d)) fields: {
	25	if (target.cpu.has(.riscv, .d)) fields: {
26	26	var any_fp = false;
27	27	var field_count: usize = 0;
28	28	for (0..ty.structFieldCount(zcu)) \|field_index\| {
...	...	@@ -141,10 +141,9 @@ pub fn classifySystem(ty: Type, zcu: *Zcu) [8]SystemClass {
141	141	},
142	142	.float => {
143	143	const target = zcu.getTarget();
144		const features = target.cpu.features;
145	144
146		const float_bits = ty.floatBits(zcu.getTarget());
147		const float_reg_size: u32 = if (std.Target.riscv.featureSetHas(features, .d)) 64 else 32;
	145	const float_bits = ty.floatBits(target);
	146	const float_reg_size: u32 = if (target.cpu.has(.riscv, .d)) 64 else 32;
148	147	if (float_bits <= float_reg_size) {
149	148	result[0] = .float;
150	149	return result;

src/arch/riscv64/bits.zig+6-8

...	...	@@ -164,12 +164,12 @@ pub const Register = enum(u8) {
164	164	ft8, ft9, ft10, ft11, // foat temporaries. calller saved.
165	165
166	166	// this register is accessed only through API instructions instead of directly
167		// fcsr,
	167	// fcsr,
168	168
169		f0, f1, f2, f3, f4, f5, f6, f7,
170		f8, f9, f10, f11, f12, f13, f14, f15,
171		f16, f17, f18, f19, f20, f21, f22, f23,
172		f24, f25, f26, f27, f28, f29, f30, f31,
	169	f0, f1, f2, f3, f4, f5, f6, f7,
	170	f8, f9, f10, f11, f12, f13, f14, f15,
	171	f16, f17, f18, f19, f20, f21, f22, f23,
	172	f24, f25, f26, f27, f28, f29, f30, f31,
173	173
174	174
175	175	// V extension registers
...	...	@@ -211,12 +211,10 @@ pub const Register = enum(u8) {
211	211	}
212	212
213	213	pub fn bitSize(reg: Register, zcu: *const Zcu) u32 {
214		const features = zcu.getTarget().cpu.features;
215
216	214	return switch (@intFromEnum(reg)) {
217	215	// zig fmt: off
218	216	@intFromEnum(Register.zero) ... @intFromEnum(Register.x31) => 64,
219		@intFromEnum(Register.ft0) ... @intFromEnum(Register.f31) => if (Target.riscv.featureSetHas(features, .d)) 64 else 32,
	217	@intFromEnum(Register.ft0) ... @intFromEnum(Register.f31) => if (zcu.getTarget().cpu.has(.riscv, .d)) 64 else 32,
220	218	@intFromEnum(Register.v0) ... @intFromEnum(Register.v31) => 256, // TODO: look at suggestVectorSize
221	219	else => unreachable,
222	220	// zig fmt: on

src/arch/wasm/CodeGen.zig+6-8

...	...	@@ -1616,8 +1616,8 @@ fn memcpy(cg: *CodeGen, dst: WValue, src: WValue, len: WValue) !void {
1616	1616	};
1617	1617	// When bulk_memory is enabled, we lower it to wasm's memcpy instruction.
1618	1618	// If not, we lower it ourselves manually
1619		if (std.Target.wasm.featureSetHas(cg.target.cpu.features, .bulk_memory)) {
1620		const len0_ok = std.Target.wasm.featureSetHas(cg.target.cpu.features, .nontrapping_bulk_memory_len0);
	1619	if (cg.target.cpu.has(.wasm, .bulk_memory)) {
	1620	const len0_ok = cg.target.cpu.has(.wasm, .nontrapping_bulk_memory_len0);
1621	1621	const emit_check = !(len0_ok or len_known_neq_0);
1622	1622
1623	1623	if (emit_check) {
...	...	@@ -1839,9 +1839,7 @@ const SimdStoreStrategy = enum {
1839	1839	pub fn determineSimdStoreStrategy(ty: Type, zcu: const Zcu, target: const std.Target) SimdStoreStrategy {
1840	1840	assert(ty.zigTypeTag(zcu) == .vector);
1841	1841	if (ty.bitSize(zcu) != 128) return .unrolled;
1842		const hasFeature = std.Target.wasm.featureSetHas;
1843		const features = target.cpu.features;
1844		if (hasFeature(features, .relaxed_simd) or hasFeature(features, .simd128)) {
	1842	if (target.cpu.has(.wasm, .relaxed_simd) or target.cpu.has(.wasm, .simd128)) {
1845	1843	return .direct;
1846	1844	}
1847	1845	return .unrolled;
...	...	@@ -4838,8 +4836,8 @@ fn memset(cg: *CodeGen, elem_ty: Type, ptr: WValue, len: WValue, value: WValue)
4838	4836
4839	4837	// When bulk_memory is enabled, we lower it to wasm's memset instruction.
4840	4838	// If not, we lower it ourselves.
4841		if (std.Target.wasm.featureSetHas(cg.target.cpu.features, .bulk_memory) and abi_size == 1) {
4842		const len0_ok = std.Target.wasm.featureSetHas(cg.target.cpu.features, .nontrapping_bulk_memory_len0);
	4839	if (cg.target.cpu.has(.wasm, .bulk_memory) and abi_size == 1) {
	4840	const len0_ok = cg.target.cpu.has(.wasm, .nontrapping_bulk_memory_len0);
4843	4841
4844	4842	if (!len0_ok) {
4845	4843	try cg.startBlock(.block, .empty);
...	...	@@ -7304,7 +7302,7 @@ fn airErrorSetHasValue(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
7304	7302	}
7305	7303
7306	7304	inline fn useAtomicFeature(cg: *const CodeGen) bool {
7307		return std.Target.wasm.featureSetHas(cg.target.cpu.features, .atomics);
	7305	return cg.target.cpu.has(.wasm, .atomics);
7308	7306	}
7309	7307
7310	7308	fn airCmpxchg(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {

src/arch/x86_64/CodeGen.zig+1-1

...	...	@@ -182035,7 +182035,7 @@ fn hasFeature(cg: *CodeGen, feature: std.Target.x86.Feature) bool {
182035	182035	.x86_64 => null,
182036	182036	},
182037	182037	else => null,
182038		} orelse std.Target.x86.featureSetHas(cg.target.cpu.features, feature);
	182038	} orelse cg.target.cpu.has(.x86, feature);
182039	182039	}
182040	182040
182041	182041	fn typeOf(self: *CodeGen, inst: Air.Inst.Ref) Type {

src/arch/x86_64/Encoding.zig+6-6

...	...	@@ -72,8 +72,8 @@ pub fn findByMnemonic(
72	72	},
73	73	inline .@"invpcid 32bit", .@"rdpid 32bit" => \|tag\| switch (target.cpu.arch) {
74	74	else => unreachable,
75		.x86 => std.Target.x86.featureSetHas(
76		target.cpu.features,
	75	.x86 => target.cpu.has(
	76	.x86,
77	77	@field(std.Target.x86.Feature, @tagName(tag)[0 .. @tagName(tag).len - " 32bit".len]),
78	78	),
79	79	.x86_64 => false,
...	...	@@ -81,17 +81,17 @@ pub fn findByMnemonic(
81	81	inline .@"invpcid 64bit", .@"rdpid 64bit", .@"prefetchi 64bit" => \|tag\| switch (target.cpu.arch) {
82	82	else => unreachable,
83	83	.x86 => false,
84		.x86_64 => std.Target.x86.featureSetHas(
85		target.cpu.features,
	84	.x86_64 => target.cpu.has(
	85	.x86,
86	86	@field(std.Target.x86.Feature, @tagName(tag)[0 .. @tagName(tag).len - " 64bit".len]),
87	87	),
88	88	},
89		.prefetch => std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .prfchw, .prefetchi, .prefetchwt1 }),
	89	.prefetch => target.cpu.hasAny(.x86, &.{ .sse, .prfchw, .prefetchi, .prefetchwt1 }),
90	90	inline else => \|tag\| has_features: {
91	91	comptime var feature_it = std.mem.splitScalar(u8, @tagName(tag), ' ');
92	92	comptime var features: []const std.Target.x86.Feature = &.{};
93	93	inline while (comptime feature_it.next()) \|feature\| features = features ++ .{@field(std.Target.x86.Feature, feature)};
94		break :has_features std.Target.x86.featureSetHasAll(target.cpu.features, features[0..].*);
	94	break :has_features target.cpu.hasAll(.x86, features);
95	95	},
96	96	}) continue;
97	97

src/arch/x86_64/abi.zig+6-6

...	...	@@ -201,11 +201,11 @@ pub fn classifySystemV(ty: Type, zcu: Zcu, target: const std.Target, ctx: Cont
201	201	.integer_per_element, .none, .none, .none,
202	202	.none, .none, .none, .none,
203	203	};
204		if (bits <= 256 and std.Target.x86.featureSetHas(target.cpu.features, .avx)) return .{
	204	if (bits <= 256 and target.cpu.has(.x86, .avx)) return .{
205	205	.integer_per_element, .none, .none, .none,
206	206	.none, .none, .none, .none,
207	207	};
208		if (bits <= 512 and std.Target.x86.featureSetHas(target.cpu.features, .avx512f)) return .{
	208	if (bits <= 512 and target.cpu.has(.x86, .avx512f)) return .{
209	209	.integer_per_element, .none, .none, .none,
210	210	.none, .none, .none, .none,
211	211	};
...	...	@@ -220,7 +220,7 @@ pub fn classifySystemV(ty: Type, zcu: Zcu, target: const std.Target, ctx: Cont
220	220	.sse, .sseup, .none, .none,
221	221	.none, .none, .none, .none,
222	222	};
223		if (ctx == .arg and !std.Target.x86.featureSetHas(target.cpu.features, .avx)) return memory_class;
	223	if (ctx == .arg and !target.cpu.has(.x86, .avx)) return memory_class;
224	224	if (bits <= 192) return .{
225	225	.sse, .sseup, .sseup, .none,
226	226	.none, .none, .none, .none,
...	...	@@ -229,7 +229,7 @@ pub fn classifySystemV(ty: Type, zcu: Zcu, target: const std.Target, ctx: Cont
229	229	.sse, .sseup, .sseup, .sseup,
230	230	.none, .none, .none, .none,
231	231	};
232		if (ctx == .arg and !std.Target.x86.featureSetHas(target.cpu.features, .avx512f)) return memory_class;
	232	if (ctx == .arg and !target.cpu.has(.x86, .avx512f)) return memory_class;
233	233	if (bits <= 320) return .{
234	234	.sse, .sseup, .sseup, .sseup,
235	235	.sseup, .none, .none, .none,
...	...	@@ -242,9 +242,9 @@ pub fn classifySystemV(ty: Type, zcu: Zcu, target: const std.Target, ctx: Cont
242	242	.sse, .sseup, .sseup, .sseup,
243	243	.sseup, .sseup, .sseup, .none,
244	244	};
245		if (bits <= 512 or (ctx == .ret and bits <= @as(u64, if (std.Target.x86.featureSetHas(target.cpu.features, .avx512f))
	245	if (bits <= 512 or (ctx == .ret and bits <= @as(u64, if (target.cpu.has(.x86, .avx512f))
246	246	2048
247		else if (std.Target.x86.featureSetHas(target.cpu.features, .avx))
	247	else if (target.cpu.has(.x86, .avx))
248	248	1024
249	249	else
250	250	512))) return .{

src/codegen/llvm.zig+24-26

...	...	@@ -40,9 +40,9 @@ pub fn legalizeFeatures(_: const std.Target) ?const Air.Legalize.Features {
40	40	return null;
41	41	}
42	42
43		fn subArchName(features: std.Target.Cpu.Feature.Set, arch: anytype, mappings: anytype) ?[]const u8 {
	43	fn subArchName(target: std.Target, comptime family: std.Target.Cpu.Arch.Family, mappings: anytype) ?[]const u8 {
44	44	inline for (mappings) \|mapping\| {
45		if (arch.featureSetHas(features, mapping[0])) return mapping[1];
	45	if (target.cpu.has(family, mapping[0])) return mapping[1];
46	46	}
47	47
48	48	return null;
...	...	@@ -52,8 +52,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
52	52	var llvm_triple = std.ArrayList(u8).init(allocator);
53	53	defer llvm_triple.deinit();
54	54
55		const features = target.cpu.features;
56
57	55	const llvm_arch = switch (target.cpu.arch) {
58	56	.arm => "arm",
59	57	.armeb => "armeb",
...	...	@@ -69,10 +67,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
69	67	.loongarch64 => "loongarch64",
70	68	.m68k => "m68k",
71	69	// MIPS sub-architectures are a bit irregular, so we handle them manually here.
72		.mips => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6" else "mips",
73		.mipsel => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6el" else "mipsel",
74		.mips64 => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6" else "mips64",
75		.mips64el => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6el" else "mips64el",
	70	.mips => if (target.cpu.has(.mips, .mips32r6)) "mipsisa32r6" else "mips",
	71	.mipsel => if (target.cpu.has(.mips, .mips32r6)) "mipsisa32r6el" else "mipsel",
	72	.mips64 => if (target.cpu.has(.mips, .mips64r6)) "mipsisa64r6" else "mips64",
	73	.mips64el => if (target.cpu.has(.mips, .mips64r6)) "mipsisa64r6el" else "mips64el",
76	74	.msp430 => "msp430",
77	75	.powerpc => "powerpc",
78	76	.powerpcle => "powerpcle",
...	...	@@ -109,7 +107,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
109	107	try llvm_triple.appendSlice(llvm_arch);
110	108
111	109	const llvm_sub_arch: ?[]const u8 = switch (target.cpu.arch) {
112		.arm, .armeb, .thumb, .thumbeb => subArchName(features, std.Target.arm, .{
	110	.arm, .armeb, .thumb, .thumbeb => subArchName(target, .arm, .{
113	111	.{ .v4t, "v4t" },
114	112	.{ .v5t, "v5t" },
115	113	.{ .v5te, "v5te" },
...	...	@@ -146,13 +144,13 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
146	144	.{ .v9_5a, "v9.5a" },
147	145	.{ .v9_6a, "v9.6a" },
148	146	}),
149		.powerpc => subArchName(features, std.Target.powerpc, .{
	147	.powerpc => subArchName(target, .powerpc, .{
150	148	.{ .spe, "spe" },
151	149	}),
152		.spirv => subArchName(features, std.Target.spirv, .{
	150	.spirv => subArchName(target, .spirv, .{
153	151	.{ .v1_5, "1.5" },
154	152	}),
155		.spirv32, .spirv64 => subArchName(features, std.Target.spirv, .{
	153	.spirv32, .spirv64 => subArchName(target, .spirv, .{
156	154	.{ .v1_5, "1.5" },
157	155	.{ .v1_4, "1.4" },
158	156	.{ .v1_3, "1.3" },
...	...	@@ -309,13 +307,13 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
309	307	}
310	308
311	309	pub fn supportsTailCall(target: std.Target) bool {
312		switch (target.cpu.arch) {
313		.wasm32, .wasm64 => return std.Target.wasm.featureSetHas(target.cpu.features, .tail_call),
	310	return switch (target.cpu.arch) {
	311	.wasm32, .wasm64 => target.cpu.has(.wasm, .tail_call),
314	312	// Although these ISAs support tail calls, LLVM does not support tail calls on them.
315		.mips, .mipsel, .mips64, .mips64el => return false,
316		.powerpc, .powerpcle, .powerpc64, .powerpc64le => return false,
317		else => return true,
318		}
	313	.mips, .mipsel, .mips64, .mips64el => false,
	314	.powerpc, .powerpcle, .powerpc64, .powerpc64le => false,
	315	else => true,
	316	};
319	317	}
320	318
321	319	pub fn dataLayout(target: std.Target) []const u8 {
...	...	@@ -391,11 +389,11 @@ pub fn dataLayout(target: std.Target) []const u8 {
391	389	.nvptx => "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64",
392	390	.nvptx64 => "e-i64:64-i128:128-v16:16-v32:32-n16:32:64",
393	391	.amdgcn => "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9",
394		.riscv32 => if (std.Target.riscv.featureSetHas(target.cpu.features, .e))
	392	.riscv32 => if (target.cpu.has(.riscv, .e))
395	393	"e-m:e-p:32:32-i64:64-n32-S32"
396	394	else
397	395	"e-m:e-p:32:32-i64:64-n32-S128",
398		.riscv64 => if (std.Target.riscv.featureSetHas(target.cpu.features, .e))
	396	.riscv64 => if (target.cpu.has(.riscv, .e))
399	397	"e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"
400	398	else
401	399	"e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
...	...	@@ -12047,7 +12045,7 @@ fn returnTypeByRef(zcu: *Zcu, target: std.Target, ty: Type) bool {
12047	12045	if (isByRef(ty, zcu)) {
12048	12046	return true;
12049	12047	} else if (target.cpu.arch.isX86() and
12050		!std.Target.x86.featureSetHas(target.cpu.features, .evex512) and
	12048	!target.cpu.has(.x86, .evex512) and
12051	12049	ty.totalVectorBits(zcu) >= 512)
12052	12050	{
12053	12051	// As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
...	...	@@ -12322,7 +12320,7 @@ const ParamTypeIterator = struct {
12322	12320	} else if (isByRef(ty, zcu)) {
12323	12321	return .byref;
12324	12322	} else if (target.cpu.arch.isX86() and
12325		!std.Target.x86.featureSetHas(target.cpu.features, .evex512) and
	12323	!target.cpu.has(.x86, .evex512) and
12326	12324	ty.totalVectorBits(zcu) >= 512)
12327	12325	{
12328	12326	// As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
...	...	@@ -12746,7 +12744,7 @@ fn isScalar(zcu: *Zcu, ty: Type) bool {
12746	12744	/// or if it produces miscompilations.
12747	12745	fn backendSupportsF80(target: std.Target) bool {
12748	12746	return switch (target.cpu.arch) {
12749		.x86_64, .x86 => !std.Target.x86.featureSetHas(target.cpu.features, .soft_float),
	12747	.x86, .x86_64 => !target.cpu.has(.x86, .soft_float),
12750	12748	else => false,
12751	12749	};
12752	12750	}
...	...	@@ -12778,11 +12776,11 @@ fn backendSupportsF16(target: std.Target) bool {
12778	12776	.armeb,
12779	12777	.thumb,
12780	12778	.thumbeb,
12781		=> target.abi.float() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fullfp16),
	12779	=> target.abi.float() == .soft or target.cpu.has(.arm, .fullfp16),
12782	12780	// https://github.com/llvm/llvm-project/issues/129394
12783	12781	.aarch64,
12784	12782	.aarch64_be,
12785		=> std.Target.aarch64.featureSetHas(target.cpu.features, .fp_armv8),
	12783	=> target.cpu.has(.aarch64, .fp_armv8),
12786	12784	else => true,
12787	12785	};
12788	12786	}
...	...	@@ -12813,7 +12811,7 @@ fn backendSupportsF128(target: std.Target) bool {
12813	12811	.armeb,
12814	12812	.thumb,
12815	12813	.thumbeb,
12816		=> target.abi.float() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8),
	12814	=> target.abi.float() == .soft or target.cpu.has(.arm, .fp_armv8),
12817	12815	else => true,
12818	12816	};
12819	12817	}

src/codegen/spirv/Module.zig+7-7

...	...	@@ -190,12 +190,12 @@ entry_points: std.AutoArrayHashMapUnmanaged(IdRef, EntryPoint) = .empty,
190	190	pub fn init(gpa: Allocator, target: std.Target) Module {
191	191	const version_minor: u8 = blk: {
192	192	// Prefer higher versions
193		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_6)) break :blk 6;
194		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_5)) break :blk 5;
195		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_4)) break :blk 4;
196		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_3)) break :blk 3;
197		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_2)) break :blk 2;
198		if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_1)) break :blk 1;
	193	if (target.cpu.has(.spirv, .v1_6)) break :blk 6;
	194	if (target.cpu.has(.spirv, .v1_5)) break :blk 5;
	195	if (target.cpu.has(.spirv, .v1_4)) break :blk 4;
	196	if (target.cpu.has(.spirv, .v1_3)) break :blk 3;
	197	if (target.cpu.has(.spirv, .v1_2)) break :blk 2;
	198	if (target.cpu.has(.spirv, .v1_1)) break :blk 1;
199	199	break :blk 0;
200	200	};
201	201
...	...	@@ -268,7 +268,7 @@ pub fn idBound(self: Module) Word {
268	268	}
269	269
270	270	pub fn hasFeature(self: *Module, feature: std.Target.spirv.Feature) bool {
271		return std.Target.spirv.featureSetHas(self.target.cpu.features, feature);
	271	return self.target.cpu.has(.spirv, feature);
272	272	}
273	273
274	274	fn addEntryPointDeps(

src/link/Elf/Object.zig+5-6

...	...	@@ -187,7 +187,6 @@ pub fn validateEFlags(
187	187	) !void {
188	188	switch (target.cpu.arch) {
189	189	.riscv64 => {
190		const features = target.cpu.features;
191	190	const flags: riscv.Eflags = @bitCast(e_flags);
192	191	var any_errors: bool = false;
193	192
...	...	@@ -196,7 +195,7 @@ pub fn validateEFlags(
196	195
197	196	// Invalid when
198	197	// 1. The input uses C and we do not.
199		if (flags.rvc and !std.Target.riscv.featureSetHas(features, .c)) {
	198	if (flags.rvc and !target.cpu.has(.riscv, .c)) {
200	199	any_errors = true;
201	200	diags.addParseError(
202	201	path,
...	...	@@ -208,7 +207,7 @@ pub fn validateEFlags(
208	207	// Invalid when
209	208	// 1. We use E and the input does not.
210	209	// 2. The input uses E and we do not.
211		if (std.Target.riscv.featureSetHas(features, .e) != flags.rve) {
	210	if (target.cpu.has(.riscv, .e) != flags.rve) {
212	211	any_errors = true;
213	212	diags.addParseError(
214	213	path,
...	...	@@ -225,7 +224,7 @@ pub fn validateEFlags(
225	224	// Invalid when
226	225	// 1. We use total store order and the input does not.
227	226	// 2. The input uses total store order and we do not.
228		if (flags.tso != std.Target.riscv.featureSetHas(features, .ztso)) {
	227	if (flags.tso != target.cpu.has(.riscv, .ztso)) {
229	228	any_errors = true;
230	229	diags.addParseError(
231	230	path,
...	...	@@ -235,9 +234,9 @@ pub fn validateEFlags(
235	234	}
236	235
237	236	const fabi: riscv.Eflags.FloatAbi =
238		if (std.Target.riscv.featureSetHas(features, .d))
	237	if (target.cpu.has(.riscv, .d))
239	238	.double
240		else if (std.Target.riscv.featureSetHas(features, .f))
	239	else if (target.cpu.has(.riscv, .f))
241	240	.single
242	241	else
243	242	.soft;

src/link/Wasm/Flush.zig+1-1

...	...	@@ -1159,7 +1159,7 @@ fn emitFeaturesSection(
1159	1159
1160	1160	var safety_count = feature_count;
1161	1161	for (target.cpu.arch.allFeaturesList(), 0..) \|*feature, i\| {
1162		if (!std.Target.wasm.featureSetHas(target.cpu.features, @enumFromInt(i))) continue;
	1162	if (!target.cpu.has(.wasm, @as(std.Target.wasm.Feature, @enumFromInt(i)))) continue;
1163	1163	safety_count -= 1;
1164	1164
1165	1165	try leb.writeUleb128(writer, @as(u32, '+'));

src/link/Wasm/Object.zig+5-5

...	...	@@ -917,12 +917,12 @@ pub fn parse(
917	917	}
918	918	if (!saw_linking_section) return error.MissingLinkingSection;
919	919
920		const target_features = comp.root_mod.resolved_target.result.cpu.features;
	920	const cpu = comp.root_mod.resolved_target.result.cpu;
921	921
922	922	if (has_tls) {
923		if (!std.Target.wasm.featureSetHas(target_features, .atomics))
	923	if (!cpu.has(.wasm, .atomics))
924	924	return diags.failParse(path, "object has TLS segment but target CPU feature atomics is disabled", .{});
925		if (!std.Target.wasm.featureSetHas(target_features, .bulk_memory))
	925	if (!cpu.has(.wasm, .bulk_memory))
926	926	return diags.failParse(path, "object has TLS segment but target CPU feature bulk_memory is disabled", .{});
927	927	}
928	928
...	...	@@ -937,7 +937,7 @@ pub fn parse(
937	937	},
938	938	else => {
939	939	const f = feat.tag.toCpuFeature().?;
940		if (std.Target.wasm.featureSetHas(target_features, f)) {
	940	if (cpu.has(.wasm, f)) {
941	941	return diags.failParse(
942	942	path,
943	943	"object forbids {s} but specified target features include {s}",
...	...	@@ -952,7 +952,7 @@ pub fn parse(
952	952	},
953	953	else => {
954	954	const f = feat.tag.toCpuFeature().?;
955		if (!std.Target.wasm.featureSetHas(target_features, f)) {
	955	if (!cpu.has(.wasm, f)) {
956	956	return diags.failParse(
957	957	path,
958	958	"object requires {s} but specified target features exclude {s}",

src/target.zig+32-35

...	...	@@ -297,18 +297,21 @@ pub fn classifyCompilerRtLibName(name: []const u8) CompilerRtClassification {
297	297
298	298	pub fn hasDebugInfo(target: std.Target) bool {
299	299	return switch (target.cpu.arch) {
300		.nvptx, .nvptx64 => std.Target.nvptx.featureSetHas(target.cpu.features, .ptx75) or
301		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx76) or
302		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx77) or
303		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx78) or
304		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx80) or
305		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx81) or
306		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx82) or
307		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx83) or
308		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx84) or
309		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx85) or
310		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx86) or
311		std.Target.nvptx.featureSetHas(target.cpu.features, .ptx87),
	300	// TODO: We should make newer PTX versions depend on older ones so we'd just check `ptx75`.
	301	.nvptx, .nvptx64 => target.cpu.hasAny(.nvptx, &.{
	302	.ptx75,
	303	.ptx76,
	304	.ptx77,
	305	.ptx78,
	306	.ptx80,
	307	.ptx81,
	308	.ptx82,
	309	.ptx83,
	310	.ptx84,
	311	.ptx85,
	312	.ptx86,
	313	.ptx87,
	314	}),
312	315	.bpfel, .bpfeb => false,
313	316	else => true,
314	317	};
...	...	@@ -613,28 +616,22 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 {
613	616	else => if (target.abi.isMusl()) "elfv2" else "elfv1",
614	617	},
615	618	.powerpc64le => "elfv2",
616		.riscv64 => b: {
617		const featureSetHas = std.Target.riscv.featureSetHas;
618		break :b if (featureSetHas(target.cpu.features, .e))
619		"lp64e"
620		else if (featureSetHas(target.cpu.features, .d))
621		"lp64d"
622		else if (featureSetHas(target.cpu.features, .f))
623		"lp64f"
624		else
625		"lp64";
626		},
627		.riscv32 => b: {
628		const featureSetHas = std.Target.riscv.featureSetHas;
629		break :b if (featureSetHas(target.cpu.features, .e))
630		"ilp32e"
631		else if (featureSetHas(target.cpu.features, .d))
632		"ilp32d"
633		else if (featureSetHas(target.cpu.features, .f))
634		"ilp32f"
635		else
636		"ilp32";
637		},
	619	.riscv64 => if (target.cpu.has(.riscv, .e))
	620	"lp64e"
	621	else if (target.cpu.has(.riscv, .d))
	622	"lp64d"
	623	else if (target.cpu.has(.riscv, .f))
	624	"lp64f"
	625	else
	626	"lp64",
	627	.riscv32 => if (target.cpu.has(.riscv, .e))
	628	"ilp32e"
	629	else if (target.cpu.has(.riscv, .d))
	630	"ilp32d"
	631	else if (target.cpu.has(.riscv, .f))
	632	"ilp32f"
	633	else
	634	"ilp32",
638	635	else => null,
639	636	};
640	637	}
...	...	@@ -672,7 +669,7 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
672	669	return switch (target.cpu.arch) {
673	670	.riscv32,
674	671	.riscv64,
675		=> if (std.Target.riscv.featureSetHasAny(target.cpu.features, .{ .c, .zca })) .@"2" else .@"4",
	672	=> if (target.cpu.hasAny(.riscv, &.{ .c, .zca })) .@"2" else .@"4",
676	673	.thumb,
677	674	.thumbeb,
678	675	.csky,

test/behavior/atomics.zig+1-1

...	...	@@ -7,7 +7,7 @@ const supports_128_bit_atomics = switch (builtin.cpu.arch) {
7	7	// TODO: Ideally this could be sync'd with the logic in Sema.
8	8	.aarch64 => true,
9	9	.aarch64_be => false, // Fails due to LLVM issues.
10		.x86_64 => std.Target.x86.featureSetHas(builtin.cpu.features, .cx16),
	10	.x86_64 => builtin.cpu.has(.x86, .cx16),
11	11	else => false,
12	12	};
13	13

test/behavior/floatop.zig+12-12

...	...	@@ -17,7 +17,7 @@ test "add f16" {
17	17	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
18	18
19	19	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
20		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	20	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
21	21
22	22	try testAdd(f16);
23	23	try comptime testAdd(f16);
...	...	@@ -129,7 +129,7 @@ test "cmp f16" {
129	129	if (builtin.cpu.arch.isArm() and builtin.target.abi.float() == .soft) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21234
130	130
131	131	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
132		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	132	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
133	133
134	134	try testCmp(f16);
135	135	try comptime testCmp(f16);
...	...	@@ -345,7 +345,7 @@ test "different sized float comparisons" {
345	345	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
346	346
347	347	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
348		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	348	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
349	349
350	350	try testDifferentSizedFloatComparisons();
351	351	try comptime testDifferentSizedFloatComparisons();
...	...	@@ -396,7 +396,7 @@ test "@sqrt f16" {
396	396	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
397	397
398	398	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
399		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	399	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
400	400
401	401	try testSqrt(f16);
402	402	try comptime testSqrt(f16);
...	...	@@ -1140,7 +1140,7 @@ test "@abs f16" {
1140	1140	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1141	1141
1142	1142	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1143		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	1143	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
1144	1144
1145	1145	try testFabs(f16);
1146	1146	try comptime testFabs(f16);
...	...	@@ -1276,7 +1276,7 @@ test "@floor f32/f64" {
1276	1276	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1277	1277
1278	1278	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1279		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1279	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1280	1280
1281	1281	try testFloor(f32);
1282	1282	try comptime testFloor(f32);
...	...	@@ -1343,7 +1343,7 @@ test "@floor with vectors" {
1343	1343	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1344	1344
1345	1345	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1346		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1346	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1347	1347
1348	1348	try testFloorWithVectors();
1349	1349	try comptime testFloorWithVectors();
...	...	@@ -1377,7 +1377,7 @@ test "@ceil f32/f64" {
1377	1377	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1378	1378
1379	1379	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1380		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1380	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1381	1381
1382	1382	try testCeil(f32);
1383	1383	try comptime testCeil(f32);
...	...	@@ -1444,7 +1444,7 @@ test "@ceil with vectors" {
1444	1444	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1445	1445
1446	1446	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1447		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1447	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1448	1448
1449	1449	try testCeilWithVectors();
1450	1450	try comptime testCeilWithVectors();
...	...	@@ -1478,7 +1478,7 @@ test "@trunc f32/f64" {
1478	1478	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1479	1479
1480	1480	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1481		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1481	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1482	1482
1483	1483	try testTrunc(f32);
1484	1484	try comptime testTrunc(f32);
...	...	@@ -1545,7 +1545,7 @@ test "@trunc with vectors" {
1545	1545	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1546	1546
1547	1547	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1548		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1548	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1549	1549
1550	1550	try testTruncWithVectors();
1551	1551	try comptime testTruncWithVectors();
...	...	@@ -1568,7 +1568,7 @@ test "neg f16" {
1568	1568	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1569	1569
1570	1570	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1571		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	1571	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
1572	1572
1573	1573	if (builtin.os.tag == .freebsd) {
1574	1574	// TODO file issue to track this failure

test/behavior/math.zig+2-2

...	...	@@ -475,7 +475,7 @@ test "division" {
475	475	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
476	476
477	477	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
478		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	478	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
479	479
480	480	try testIntDivision();
481	481	try comptime testIntDivision();
...	...	@@ -1930,7 +1930,7 @@ test "float vector division of comptime zero by runtime nan is nan" {
1930	1930	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
1931	1931
1932	1932	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
1933		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
	1933	!comptime builtin.cpu.has(.x86, .sse4_1)) return error.SkipZigTest;
1934	1934
1935	1935	const ct_zero: @Vector(1, f32) = .{0};
1936	1936	var rt_nan: @Vector(1, f32) = .{math.nan(f32)};

test/behavior/muladd.zig+3-3

...	...	@@ -10,7 +10,7 @@ test "@mulAdd" {
10	10	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
11	11
12	12	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
13		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .fma)) return error.SkipZigTest;
	13	!comptime builtin.cpu.has(.x86, .fma)) return error.SkipZigTest;
14	14
15	15	try comptime testMulAdd();
16	16	try testMulAdd();
...	...	@@ -143,7 +143,7 @@ test "vector f32" {
143	143	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
144	144
145	145	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
146		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .fma)) return error.SkipZigTest;
	146	!comptime builtin.cpu.has(.x86, .fma)) return error.SkipZigTest;
147	147
148	148	try comptime vector32();
149	149	try vector32();
...	...	@@ -171,7 +171,7 @@ test "vector f64" {
171	171	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
172	172
173	173	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
174		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .fma)) return error.SkipZigTest;
	174	!comptime builtin.cpu.has(.x86, .fma)) return error.SkipZigTest;
175	175
176	176	try comptime vector64();
177	177	try vector64();

test/behavior/vector.zig+2-4

...	...	@@ -251,7 +251,7 @@ test "array to vector with element type coercion" {
251	251	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
252	252
253	253	if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt == .coff and
254		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
	254	!comptime builtin.cpu.has(.x86, .f16c)) return error.SkipZigTest;
255	255
256	256	const S = struct {
257	257	fn doTheTest() !void {
...	...	@@ -1259,9 +1259,7 @@ test "byte vector initialized in inline function" {
1259	1259	if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1260	1260	if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
1261	1261
1262		if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and
1263		std.Target.x86.featureSetHas(builtin.cpu.features, .avx512f))
1264		{
	1262	if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and comptime builtin.cpu.has(.x86, .avx512f)) {
1265	1263	// TODO https://github.com/ziglang/zig/issues/13279
1266	1264	return error.SkipZigTest;
1267	1265	}

test/behavior/x86_64/build.zig+1-1

...	...	@@ -133,7 +133,7 @@ pub fn build(b: *std.Build) void {
133	133	.use_lld = false,
134	134	.root_module = test_mod,
135	135	});
136		if (!std.Target.x86.featureSetHas(target.result.cpu.features, .sse2)) {
	136	if (!target.result.cpu.has(.x86, .sse2)) {
137	137	test_exe.bundle_compiler_rt = false;
138	138	test_mod.linkLibrary(compiler_rt_lib);
139	139	}

test/behavior/x86_64/math.zig+1-1

...	...	@@ -17,7 +17,7 @@ pub const Gpr = switch (builtin.cpu.arch) {
17	17	.x86 => u32,
18	18	.x86_64 => u64,
19	19	};
20		pub const Sse = if (std.Target.x86.featureSetHas(builtin.cpu.features, .avx))
	20	pub const Sse = if (builtin.cpu.has(.x86, .avx))
21	21	@Vector(32, u8)
22	22	else
23	23	@Vector(16, u8);

test/c_abi/main.zig+1-3

...	...	@@ -1087,9 +1087,7 @@ extern fn c_medium_vec(MediumVec) void;
1087	1087	extern fn c_ret_medium_vec() MediumVec;
1088	1088
1089	1089	test "medium simd vector" {
1090		if (builtin.zig_backend == .stage2_x86_64 and
1091		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .avx)) return error.SkipZigTest;
1092
	1090	if (builtin.zig_backend == .stage2_x86_64 and !comptime builtin.cpu.has(.x86, .avx)) return error.SkipZigTest;
1093	1091	if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
1094	1092
1095	1093	c_medium_vec(.{ 1, 2, 3, 4 });

tools/gen_outline_atomics.zig+1-1

...	...	@@ -25,7 +25,7 @@ pub fn main() !void {
25	25	\\const builtin = @import("builtin");
26	26	\\const std = @import("std");
27	27	\\const common = @import("common.zig");
28		\\const always_has_lse = std.Target.aarch64.featureSetHas(builtin.cpu.features, .lse);
	28	\\const always_has_lse = builtin.cpu.has(.aarch64, .lse);
29	29	\\
30	30	\\/// This default is overridden at runtime after inspecting CPU properties.
31	31	\\/// It is intentionally not exported in order to make the machine code that

author	Alex Rønne Petersen <alex@alexrp.com> 2025-02-18 05:25:36+01:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2025-06-05 06:12:00+02:00
log	9d534790ebc869ec933e932abe4be8b9e3593bbc
tree	70652dde381fd0c0d536d8e7665e725e0924bb51
parent	14873f9a3434a0d753ca8438f389a7931956cf26

std.Target: Introduce Cpu convenience functions for feature tests.