authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-07-31 09:43:29-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2023-08-01 19:20:22-07:00
log9e0a34f329caec5711e1a1492ff7c78caf5da10b
treee521c1e835bcade83e34f7b99de6ba607dd177c8
parent4f6013bf50e1b99b5c9ea238a2165bfe41fc57d4

llvm: fix data layout calculation for experimental llvm targets

Closes #16616

8 files changed, 133 insertions(+), 229 deletions(-)

build.zig+7-1
...@@ -435,7 +435,13 @@ pub fn build(b: *std.Build) !void {...@@ -435,7 +435,13 @@ pub fn build(b: *std.Build) !void {
435 }).step);435 }).step);
436436
437 const test_cases_step = b.step("test-cases", "Run the main compiler test cases");437 const test_cases_step = b.step("test-cases", "Run the main compiler test cases");
438 try tests.addCases(b, test_cases_step, test_filter, check_case_exe);438 try tests.addCases(b, test_cases_step, test_filter, check_case_exe, .{
439 .enable_llvm = enable_llvm,
440 .llvm_has_m68k = llvm_has_m68k,
441 .llvm_has_csky = llvm_has_csky,
442 .llvm_has_arc = llvm_has_arc,
443 .llvm_has_xtensa = llvm_has_xtensa,
444 });
439 test_step.dependOn(test_cases_step);445 test_step.dependOn(test_cases_step);
440446
441 test_step.dependOn(tests.addModuleTests(b, .{447 test_step.dependOn(tests.addModuleTests(b, .{
lib/std/target.zig+2-1
...@@ -1154,9 +1154,9 @@ pub const Target = struct {...@@ -1154,9 +1154,9 @@ pub const Target = struct {
1154 .dxil,1154 .dxil,
1155 .loongarch32,1155 .loongarch32,
1156 .loongarch64,1156 .loongarch64,
1157 .arc,
1157 => .Little,1158 => .Little,
11581159
1159 .arc,
1160 .armeb,1160 .armeb,
1161 .aarch64_be,1161 .aarch64_be,
1162 .bpfeb,1162 .bpfeb,
...@@ -1911,6 +1911,7 @@ pub const Target = struct {...@@ -1911,6 +1911,7 @@ pub const Target = struct {
19111911
1912 pub fn stackAlignment(target: Target) u16 {1912 pub fn stackAlignment(target: Target) u16 {
1913 return switch (target.cpu.arch) {1913 return switch (target.cpu.arch) {
1914 .m68k => 2,
1914 .amdgcn => 4,1915 .amdgcn => 4,
1915 .x86 => switch (target.os.tag) {1916 .x86 => switch (target.os.tag) {
1916 .windows, .uefi => 4,1917 .windows, .uefi => 4,
src/codegen/llvm.zig+94-221
...@@ -374,6 +374,8 @@ const DataLayoutBuilder = struct {...@@ -374,6 +374,8 @@ const DataLayoutBuilder = struct {
374 },374 },
375 })}),375 })}),
376 }376 }
377 const stack_abi = self.target.stackAlignment() * 8;
378 if (self.target.cpu.arch == .csky) try writer.print("-S{d}", .{stack_abi});
377 var any_non_integral = false;379 var any_non_integral = false;
378 const ptr_bit_width = self.target.ptrBitWidth();380 const ptr_bit_width = self.target.ptrBitWidth();
379 var default_info = struct { size: u16, abi: u16, pref: u16, idx: u16 }{381 var default_info = struct { size: u16, abi: u16, pref: u16, idx: u16 }{
...@@ -420,14 +422,19 @@ const DataLayoutBuilder = struct {...@@ -420,14 +422,19 @@ const DataLayoutBuilder = struct {
420 if (self.target.cpu.arch.isArmOrThumb())422 if (self.target.cpu.arch.isArmOrThumb())
421 try writer.writeAll("-Fi8"); // for thumb interwork423 try writer.writeAll("-Fi8"); // for thumb interwork
422 if (self.target.cpu.arch != .hexagon) {424 if (self.target.cpu.arch != .hexagon) {
423 if (self.target.cpu.arch == .s390x) try self.typeAlignment(.integer, 1, 8, 8, false, writer);425 if (self.target.cpu.arch == .arc or self.target.cpu.arch == .s390x)
426 try self.typeAlignment(.integer, 1, 8, 8, false, writer);
424 try self.typeAlignment(.integer, 8, 8, 8, false, writer);427 try self.typeAlignment(.integer, 8, 8, 8, false, writer);
425 try self.typeAlignment(.integer, 16, 16, 16, false, writer);428 try self.typeAlignment(.integer, 16, 16, 16, false, writer);
426 try self.typeAlignment(.integer, 32, 32, 32, false, writer);429 try self.typeAlignment(.integer, 32, 32, 32, false, writer);
430 if (self.target.cpu.arch == .arc)
431 try self.typeAlignment(.float, 32, 32, 32, false, writer);
427 try self.typeAlignment(.integer, 64, 32, 64, false, writer);432 try self.typeAlignment(.integer, 64, 32, 64, false, writer);
428 try self.typeAlignment(.integer, 128, 32, 64, false, writer);433 try self.typeAlignment(.integer, 128, 32, 64, false, writer);
429 if (backendSupportsF16(self.target)) try self.typeAlignment(.float, 16, 16, 16, false, writer);434 if (backendSupportsF16(self.target))
430 try self.typeAlignment(.float, 32, 32, 32, false, writer);435 try self.typeAlignment(.float, 16, 16, 16, false, writer);
436 if (self.target.cpu.arch != .arc)
437 try self.typeAlignment(.float, 32, 32, 32, false, writer);
431 try self.typeAlignment(.float, 64, 64, 64, false, writer);438 try self.typeAlignment(.float, 64, 64, 64, false, writer);
432 if (self.target.cpu.arch.isX86()) try self.typeAlignment(.float, 80, 0, 0, false, writer);439 if (self.target.cpu.arch.isX86()) try self.typeAlignment(.float, 80, 0, 0, false, writer);
433 try self.typeAlignment(.float, 128, 128, 128, false, writer);440 try self.typeAlignment(.float, 128, 128, 128, false, writer);
...@@ -458,15 +465,18 @@ const DataLayoutBuilder = struct {...@@ -458,15 +465,18 @@ const DataLayoutBuilder = struct {
458 .uefi, .windows => true,465 .uefi, .windows => true,
459 else => false,466 else => false,
460 },467 },
461 .avr => true,468 .avr, .m68k => true,
462 else => false,469 else => false,
463 };470 };
464 if (!swap_agg_nat) try self.typeAlignment(.aggregate, 0, 0, 64, false, writer);471 if (!swap_agg_nat) try self.typeAlignment(.aggregate, 0, 0, 64, false, writer);
472 if (self.target.cpu.arch == .csky) try writer.writeAll("-Fi32");
465 for (@as([]const u24, switch (self.target.cpu.arch) {473 for (@as([]const u24, switch (self.target.cpu.arch) {
466 .avr => &.{8},474 .avr => &.{8},
467 .msp430 => &.{ 8, 16 },475 .msp430 => &.{ 8, 16 },
476 .arc,
468 .arm,477 .arm,
469 .armeb,478 .armeb,
479 .csky,
470 .mips,480 .mips,
471 .mipsel,481 .mipsel,
472 .powerpc,482 .powerpc,
...@@ -476,6 +486,7 @@ const DataLayoutBuilder = struct {...@@ -476,6 +486,7 @@ const DataLayoutBuilder = struct {
476 .sparcel,486 .sparcel,
477 .thumb,487 .thumb,
478 .thumbeb,488 .thumbeb,
489 .xtensa,
479 => &.{32},490 => &.{32},
480 .aarch64,491 .aarch64,
481 .aarch64_be,492 .aarch64_be,
...@@ -495,7 +506,9 @@ const DataLayoutBuilder = struct {...@@ -495,7 +506,9 @@ const DataLayoutBuilder = struct {
495 .wasm64,506 .wasm64,
496 => &.{ 32, 64 },507 => &.{ 32, 64 },
497 .hexagon => &.{ 16, 32 },508 .hexagon => &.{ 16, 32 },
498 .x86 => &.{ 8, 16, 32 },509 .m68k,
510 .x86,
511 => &.{ 8, 16, 32 },
499 .nvptx,512 .nvptx,
500 .nvptx64,513 .nvptx64,
501 => &.{ 16, 32, 64 },514 => &.{ 16, 32, 64 },
...@@ -514,9 +527,8 @@ const DataLayoutBuilder = struct {...@@ -514,9 +527,8 @@ const DataLayoutBuilder = struct {
514 try self.typeAlignment(.float, 32, 32, 32, true, writer);527 try self.typeAlignment(.float, 32, 32, 32, true, writer);
515 try self.typeAlignment(.float, 64, 64, 64, true, writer);528 try self.typeAlignment(.float, 64, 64, 64, true, writer);
516 }529 }
517 const stack_abi = self.target.stackAlignment() * 8;530 if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or
518 if (self.target.os.tag == .uefi or self.target.os.tag == .windows or531 self.target.os.tag == .uefi or self.target.os.tag == .windows)
519 self.target.cpu.arch == .msp430 or stack_abi != ptr_bit_width)
520 try writer.print("-S{d}", .{stack_abi});532 try writer.print("-S{d}", .{stack_abi});
521 switch (self.target.cpu.arch) {533 switch (self.target.cpu.arch) {
522 .hexagon, .ve => {534 .hexagon, .ve => {
...@@ -592,6 +604,12 @@ const DataLayoutBuilder = struct {...@@ -592,6 +604,12 @@ const DataLayoutBuilder = struct {
592 },604 },
593 else => pref = @max(pref, 32),605 else => pref = @max(pref, 32),
594 },606 },
607 .arc => if (size <= 64) {
608 abi = @min((std.math.divCeil(u24, size, 8) catch unreachable) * 8, 32);
609 pref = 32;
610 force_abi = true;
611 force_pref = size <= 32;
612 },
595 .bpfeb,613 .bpfeb,
596 .bpfel,614 .bpfel,
597 .nvptx,615 .nvptx,
...@@ -601,22 +619,37 @@ const DataLayoutBuilder = struct {...@@ -601,22 +619,37 @@ const DataLayoutBuilder = struct {
601 abi = size;619 abi = size;
602 pref = size;620 pref = size;
603 },621 },
622 .csky => if (size == 32 or size == 64) {
623 abi = 32;
624 pref = 32;
625 force_abi = true;
626 force_pref = true;
627 },
604 .hexagon => force_abi = true,628 .hexagon => force_abi = true,
629 .m68k => if (size <= 32) {
630 abi = @min(size, 16);
631 pref = size;
632 force_abi = true;
633 force_pref = true;
634 } else if (size == 64) {
635 abi = 32;
636 pref = size;
637 },
605 .mips,638 .mips,
606 .mipsel,639 .mipsel,
607 => pref = @max(pref, 32),
608 .mips64,640 .mips64,
609 .mips64el,641 .mips64el,
610 => if (size <= 32) {642 => pref = @max(pref, 32),
611 pref = 32;643 .s390x => pref = @max(pref, 16),
612 },
613 .s390x => if (size <= 16) {
614 pref = 16;
615 },
616 .ve => if (size == 64) {644 .ve => if (size == 64) {
617 abi = size;645 abi = size;
618 pref = size;646 pref = size;
619 },647 },
648 .xtensa => if (size <= 64) {
649 pref = @max(size, 32);
650 abi = size;
651 force_abi = size == 64;
652 },
620 else => {},653 else => {},
621 }654 }
622 },655 },
...@@ -634,6 +667,10 @@ const DataLayoutBuilder = struct {...@@ -634,6 +667,10 @@ const DataLayoutBuilder = struct {
634 pref = size;667 pref = size;
635 } else if (self.target.cpu.arch == .amdgcn and size <= 2048) {668 } else if (self.target.cpu.arch == .amdgcn and size <= 2048) {
636 force_abi = true;669 force_abi = true;
670 } else if (self.target.cpu.arch == .csky and (size == 64 or size == 128)) {
671 abi = 32;
672 pref = 32;
673 force_pref = true;
637 } else if (self.target.cpu.arch == .hexagon and674 } else if (self.target.cpu.arch == .hexagon and
638 ((size >= 32 and size <= 64) or (size >= 512 and size <= 2048)))675 ((size >= 32 and size <= 64) or (size >= 512 and size <= 2048)))
639 {676 {
...@@ -651,11 +688,27 @@ const DataLayoutBuilder = struct {...@@ -651,11 +688,27 @@ const DataLayoutBuilder = struct {
651 force_pref = true;688 force_pref = true;
652 },689 },
653 .float => switch (self.target.cpu.arch) {690 .float => switch (self.target.cpu.arch) {
691 .aarch64_32, .amdgcn => if (size == 128) {
692 abi = size;
693 pref = size;
694 },
695 .arc => if (size == 32 or size == 64) {
696 abi = 32;
697 pref = 32;
698 force_abi = true;
699 force_pref = size == 32;
700 },
654 .avr, .msp430, .sparc64 => if (size != 32 and size != 64) return,701 .avr, .msp430, .sparc64 => if (size != 32 and size != 64) return,
702 .csky => if (size == 32 or size == 64) {
703 abi = 32;
704 pref = 32;
705 force_abi = true;
706 force_pref = true;
707 },
655 .hexagon => if (size == 32 or size == 64) {708 .hexagon => if (size == 32 or size == 64) {
656 force_abi = true;709 force_abi = true;
657 },710 },
658 .aarch64_32, .amdgcn => if (size == 128) {711 .ve, .xtensa => if (size == 64) {
659 abi = size;712 abi = size;
660 pref = size;713 pref = size;
661 },714 },
...@@ -663,25 +716,34 @@ const DataLayoutBuilder = struct {...@@ -663,25 +716,34 @@ const DataLayoutBuilder = struct {
663 abi = 64;716 abi = 64;
664 pref = 64;717 pref = 64;
665 },718 },
666 .ve => if (size == 64) {
667 abi = size;
668 pref = size;
669 },
670 else => {},719 else => {},
671 },720 },
672 .aggregate => if (self.target.os.tag == .uefi or self.target.os.tag == .windows or721 .aggregate => if (self.target.os.tag == .uefi or self.target.os.tag == .windows or
673 self.target.cpu.arch.isArmOrThumb())722 self.target.cpu.arch.isArmOrThumb())
674 {723 {
675 pref = @min(pref, self.target.ptrBitWidth());724 pref = @min(pref, self.target.ptrBitWidth());
676 } else if (self.target.cpu.arch == .hexagon) {725 } else switch (self.target.cpu.arch) {
677 abi = 0;726 .arc, .csky => {
678 pref = 0;727 abi = 0;
679 } else if (self.target.cpu.arch == .s390x) {728 pref = 32;
680 abi = 8;729 },
681 pref = 16;730 .hexagon => {
682 } else if (self.target.cpu.arch == .msp430) {731 abi = 0;
683 abi = 8;732 pref = 0;
684 pref = 8;733 },
734 .m68k => {
735 abi = 0;
736 pref = 16;
737 },
738 .msp430 => {
739 abi = 8;
740 pref = 8;
741 },
742 .s390x => {
743 abi = 8;
744 pref = 16;
745 },
746 else => {},
685 },747 },
686 }748 }
687 if (kind != .vector and self.target.cpu.arch == .avr) {749 if (kind != .vector and self.target.cpu.arch == .avr) {
...@@ -11005,198 +11067,6 @@ pub const FuncGen = struct {...@@ -11005,198 +11067,6 @@ pub const FuncGen = struct {
11005 }11067 }
11006};11068};
1100711069
11008fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
11009 switch (arch) {
11010 .aarch64, .aarch64_be, .aarch64_32 => {
11011 llvm.LLVMInitializeAArch64Target();
11012 llvm.LLVMInitializeAArch64TargetInfo();
11013 llvm.LLVMInitializeAArch64TargetMC();
11014 llvm.LLVMInitializeAArch64AsmPrinter();
11015 llvm.LLVMInitializeAArch64AsmParser();
11016 },
11017 .amdgcn => {
11018 llvm.LLVMInitializeAMDGPUTarget();
11019 llvm.LLVMInitializeAMDGPUTargetInfo();
11020 llvm.LLVMInitializeAMDGPUTargetMC();
11021 llvm.LLVMInitializeAMDGPUAsmPrinter();
11022 llvm.LLVMInitializeAMDGPUAsmParser();
11023 },
11024 .thumb, .thumbeb, .arm, .armeb => {
11025 llvm.LLVMInitializeARMTarget();
11026 llvm.LLVMInitializeARMTargetInfo();
11027 llvm.LLVMInitializeARMTargetMC();
11028 llvm.LLVMInitializeARMAsmPrinter();
11029 llvm.LLVMInitializeARMAsmParser();
11030 },
11031 .avr => {
11032 llvm.LLVMInitializeAVRTarget();
11033 llvm.LLVMInitializeAVRTargetInfo();
11034 llvm.LLVMInitializeAVRTargetMC();
11035 llvm.LLVMInitializeAVRAsmPrinter();
11036 llvm.LLVMInitializeAVRAsmParser();
11037 },
11038 .bpfel, .bpfeb => {
11039 llvm.LLVMInitializeBPFTarget();
11040 llvm.LLVMInitializeBPFTargetInfo();
11041 llvm.LLVMInitializeBPFTargetMC();
11042 llvm.LLVMInitializeBPFAsmPrinter();
11043 llvm.LLVMInitializeBPFAsmParser();
11044 },
11045 .hexagon => {
11046 llvm.LLVMInitializeHexagonTarget();
11047 llvm.LLVMInitializeHexagonTargetInfo();
11048 llvm.LLVMInitializeHexagonTargetMC();
11049 llvm.LLVMInitializeHexagonAsmPrinter();
11050 llvm.LLVMInitializeHexagonAsmParser();
11051 },
11052 .lanai => {
11053 llvm.LLVMInitializeLanaiTarget();
11054 llvm.LLVMInitializeLanaiTargetInfo();
11055 llvm.LLVMInitializeLanaiTargetMC();
11056 llvm.LLVMInitializeLanaiAsmPrinter();
11057 llvm.LLVMInitializeLanaiAsmParser();
11058 },
11059 .mips, .mipsel, .mips64, .mips64el => {
11060 llvm.LLVMInitializeMipsTarget();
11061 llvm.LLVMInitializeMipsTargetInfo();
11062 llvm.LLVMInitializeMipsTargetMC();
11063 llvm.LLVMInitializeMipsAsmPrinter();
11064 llvm.LLVMInitializeMipsAsmParser();
11065 },
11066 .msp430 => {
11067 llvm.LLVMInitializeMSP430Target();
11068 llvm.LLVMInitializeMSP430TargetInfo();
11069 llvm.LLVMInitializeMSP430TargetMC();
11070 llvm.LLVMInitializeMSP430AsmPrinter();
11071 llvm.LLVMInitializeMSP430AsmParser();
11072 },
11073 .nvptx, .nvptx64 => {
11074 llvm.LLVMInitializeNVPTXTarget();
11075 llvm.LLVMInitializeNVPTXTargetInfo();
11076 llvm.LLVMInitializeNVPTXTargetMC();
11077 llvm.LLVMInitializeNVPTXAsmPrinter();
11078 // There is no LLVMInitializeNVPTXAsmParser function available.
11079 },
11080 .powerpc, .powerpcle, .powerpc64, .powerpc64le => {
11081 llvm.LLVMInitializePowerPCTarget();
11082 llvm.LLVMInitializePowerPCTargetInfo();
11083 llvm.LLVMInitializePowerPCTargetMC();
11084 llvm.LLVMInitializePowerPCAsmPrinter();
11085 llvm.LLVMInitializePowerPCAsmParser();
11086 },
11087 .riscv32, .riscv64 => {
11088 llvm.LLVMInitializeRISCVTarget();
11089 llvm.LLVMInitializeRISCVTargetInfo();
11090 llvm.LLVMInitializeRISCVTargetMC();
11091 llvm.LLVMInitializeRISCVAsmPrinter();
11092 llvm.LLVMInitializeRISCVAsmParser();
11093 },
11094 .sparc, .sparc64, .sparcel => {
11095 llvm.LLVMInitializeSparcTarget();
11096 llvm.LLVMInitializeSparcTargetInfo();
11097 llvm.LLVMInitializeSparcTargetMC();
11098 llvm.LLVMInitializeSparcAsmPrinter();
11099 llvm.LLVMInitializeSparcAsmParser();
11100 },
11101 .s390x => {
11102 llvm.LLVMInitializeSystemZTarget();
11103 llvm.LLVMInitializeSystemZTargetInfo();
11104 llvm.LLVMInitializeSystemZTargetMC();
11105 llvm.LLVMInitializeSystemZAsmPrinter();
11106 llvm.LLVMInitializeSystemZAsmParser();
11107 },
11108 .wasm32, .wasm64 => {
11109 llvm.LLVMInitializeWebAssemblyTarget();
11110 llvm.LLVMInitializeWebAssemblyTargetInfo();
11111 llvm.LLVMInitializeWebAssemblyTargetMC();
11112 llvm.LLVMInitializeWebAssemblyAsmPrinter();
11113 llvm.LLVMInitializeWebAssemblyAsmParser();
11114 },
11115 .x86, .x86_64 => {
11116 llvm.LLVMInitializeX86Target();
11117 llvm.LLVMInitializeX86TargetInfo();
11118 llvm.LLVMInitializeX86TargetMC();
11119 llvm.LLVMInitializeX86AsmPrinter();
11120 llvm.LLVMInitializeX86AsmParser();
11121 },
11122 .xtensa => {
11123 if (build_options.llvm_has_xtensa) {
11124 llvm.LLVMInitializeXtensaTarget();
11125 llvm.LLVMInitializeXtensaTargetInfo();
11126 llvm.LLVMInitializeXtensaTargetMC();
11127 llvm.LLVMInitializeXtensaAsmPrinter();
11128 llvm.LLVMInitializeXtensaAsmParser();
11129 }
11130 },
11131 .xcore => {
11132 llvm.LLVMInitializeXCoreTarget();
11133 llvm.LLVMInitializeXCoreTargetInfo();
11134 llvm.LLVMInitializeXCoreTargetMC();
11135 llvm.LLVMInitializeXCoreAsmPrinter();
11136 // There is no LLVMInitializeXCoreAsmParser function.
11137 },
11138 .m68k => {
11139 if (build_options.llvm_has_m68k) {
11140 llvm.LLVMInitializeM68kTarget();
11141 llvm.LLVMInitializeM68kTargetInfo();
11142 llvm.LLVMInitializeM68kTargetMC();
11143 llvm.LLVMInitializeM68kAsmPrinter();
11144 llvm.LLVMInitializeM68kAsmParser();
11145 }
11146 },
11147 .csky => {
11148 if (build_options.llvm_has_csky) {
11149 llvm.LLVMInitializeCSKYTarget();
11150 llvm.LLVMInitializeCSKYTargetInfo();
11151 llvm.LLVMInitializeCSKYTargetMC();
11152 // There is no LLVMInitializeCSKYAsmPrinter function.
11153 llvm.LLVMInitializeCSKYAsmParser();
11154 }
11155 },
11156 .ve => {
11157 llvm.LLVMInitializeVETarget();
11158 llvm.LLVMInitializeVETargetInfo();
11159 llvm.LLVMInitializeVETargetMC();
11160 llvm.LLVMInitializeVEAsmPrinter();
11161 llvm.LLVMInitializeVEAsmParser();
11162 },
11163 .arc => {
11164 if (build_options.llvm_has_arc) {
11165 llvm.LLVMInitializeARCTarget();
11166 llvm.LLVMInitializeARCTargetInfo();
11167 llvm.LLVMInitializeARCTargetMC();
11168 llvm.LLVMInitializeARCAsmPrinter();
11169 // There is no LLVMInitializeARCAsmParser function.
11170 }
11171 },
11172
11173 // LLVM backends that have no initialization functions.
11174 .tce,
11175 .tcele,
11176 .r600,
11177 .le32,
11178 .le64,
11179 .amdil,
11180 .amdil64,
11181 .hsail,
11182 .hsail64,
11183 .shave,
11184 .spir,
11185 .spir64,
11186 .kalimba,
11187 .renderscript32,
11188 .renderscript64,
11189 .dxil,
11190 .loongarch32,
11191 .loongarch64,
11192 => {},
11193
11194 .spu_2 => unreachable, // LLVM does not support this backend
11195 .spirv32 => unreachable, // LLVM does not support this backend
11196 .spirv64 => unreachable, // LLVM does not support this backend
11197 }
11198}
11199
11200fn toLlvmAtomicOrdering(atomic_order: std.builtin.AtomicOrder) Builder.AtomicOrdering {11070fn toLlvmAtomicOrdering(atomic_order: std.builtin.AtomicOrder) Builder.AtomicOrdering {
11201 return switch (atomic_order) {11071 return switch (atomic_order) {
11202 .Unordered => .unordered,11072 .Unordered => .unordered,
...@@ -11318,6 +11188,9 @@ fn llvmAddrSpaceInfo(target: std.Target) []const AddrSpaceInfo {...@@ -11318,6 +11188,9 @@ fn llvmAddrSpaceInfo(target: std.Target) []const AddrSpaceInfo {
11318 .{ .zig = null, .llvm = Builder.AddrSpace.wasm.externref, .non_integral = true, .size = 8, .abi = 8 },11188 .{ .zig = null, .llvm = Builder.AddrSpace.wasm.externref, .non_integral = true, .size = 8, .abi = 8 },
11319 .{ .zig = null, .llvm = Builder.AddrSpace.wasm.funcref, .non_integral = true, .size = 8, .abi = 8 },11189 .{ .zig = null, .llvm = Builder.AddrSpace.wasm.funcref, .non_integral = true, .size = 8, .abi = 8 },
11320 },11190 },
11191 .m68k => &.{
11192 .{ .zig = .generic, .llvm = .default, .abi = 16, .pref = 32 },
11193 },
11321 else => &.{11194 else => &.{
11322 .{ .zig = .generic, .llvm = .default },11195 .{ .zig = .generic, .llvm = .default },
11323 },11196 },
src/codegen/llvm/Builder.zig+1-1
...@@ -6366,7 +6366,7 @@ pub fn initializeLLVMTarget(self: *const Builder, arch: std.Target.Cpu.Arch) voi...@@ -6366,7 +6366,7 @@ pub fn initializeLLVMTarget(self: *const Builder, arch: std.Target.Cpu.Arch) voi
6366 llvm.LLVMInitializeXtensaTarget();6366 llvm.LLVMInitializeXtensaTarget();
6367 llvm.LLVMInitializeXtensaTargetInfo();6367 llvm.LLVMInitializeXtensaTargetInfo();
6368 llvm.LLVMInitializeXtensaTargetMC();6368 llvm.LLVMInitializeXtensaTargetMC();
6369 llvm.LLVMInitializeXtensaAsmPrinter();6369 // There is no LLVMInitializeXtensaAsmPrinter function.
6370 llvm.LLVMInitializeXtensaAsmParser();6370 llvm.LLVMInitializeXtensaAsmParser();
6371 }6371 }
6372 },6372 },
src/codegen/llvm/bindings.zig-1
...@@ -1337,7 +1337,6 @@ pub extern fn LLVMInitializeSystemZAsmPrinter() void;...@@ -1337,7 +1337,6 @@ pub extern fn LLVMInitializeSystemZAsmPrinter() void;
1337pub extern fn LLVMInitializeWebAssemblyAsmPrinter() void;1337pub extern fn LLVMInitializeWebAssemblyAsmPrinter() void;
1338pub extern fn LLVMInitializeX86AsmPrinter() void;1338pub extern fn LLVMInitializeX86AsmPrinter() void;
1339pub extern fn LLVMInitializeXCoreAsmPrinter() void;1339pub extern fn LLVMInitializeXCoreAsmPrinter() void;
1340pub extern fn LLVMInitializeXtensaAsmPrinter() void;
1341pub extern fn LLVMInitializeM68kAsmPrinter() void;1340pub extern fn LLVMInitializeM68kAsmPrinter() void;
1342pub extern fn LLVMInitializeVEAsmPrinter() void;1341pub extern fn LLVMInitializeVEAsmPrinter() void;
1343pub extern fn LLVMInitializeARCAsmPrinter() void;1342pub extern fn LLVMInitializeARCAsmPrinter() void;
test/cases.zig+10-2
...@@ -1,9 +1,17 @@...@@ -1,9 +1,17 @@
1const std = @import("std");1const std = @import("std");
2const Cases = @import("src/Cases.zig");2const Cases = @import("src/Cases.zig");
33
4pub fn addCases(cases: *Cases) !void {4pub const BuildOptions = struct {
5 enable_llvm: bool,
6 llvm_has_m68k: bool,
7 llvm_has_csky: bool,
8 llvm_has_arc: bool,
9 llvm_has_xtensa: bool,
10};
11
12pub fn addCases(cases: *Cases, build_options: BuildOptions) !void {
5 try @import("compile_errors.zig").addCases(cases);13 try @import("compile_errors.zig").addCases(cases);
6 try @import("cbe.zig").addCases(cases);14 try @import("cbe.zig").addCases(cases);
7 try @import("llvm_targets.zig").addCases(cases);15 try @import("llvm_targets.zig").addCases(cases, build_options);
8 try @import("nvptx.zig").addCases(cases);16 try @import("nvptx.zig").addCases(cases);
9}17}
test/llvm_targets.zig+17-1
...@@ -18,6 +18,8 @@ const targets = [_]std.zig.CrossTarget{...@@ -18,6 +18,8 @@ const targets = [_]std.zig.CrossTarget{
18 .{ .cpu_arch = .amdgcn, .os_tag = .amdpal, .abi = .none },18 .{ .cpu_arch = .amdgcn, .os_tag = .amdpal, .abi = .none },
19 .{ .cpu_arch = .amdgcn, .os_tag = .linux, .abi = .none },19 .{ .cpu_arch = .amdgcn, .os_tag = .linux, .abi = .none },
20 //.{ .cpu_arch = .amdgcn, .os_tag = .mesa3d, .abi = .none },20 //.{ .cpu_arch = .amdgcn, .os_tag = .mesa3d, .abi = .none },
21 .{ .cpu_arch = .arc, .os_tag = .freestanding, .abi = .none },
22 .{ .cpu_arch = .arc, .os_tag = .linux, .abi = .none },
21 .{ .cpu_arch = .arm, .os_tag = .freestanding, .abi = .none },23 .{ .cpu_arch = .arm, .os_tag = .freestanding, .abi = .none },
22 .{ .cpu_arch = .arm, .os_tag = .linux, .abi = .none },24 .{ .cpu_arch = .arm, .os_tag = .linux, .abi = .none },
23 .{ .cpu_arch = .arm, .os_tag = .uefi, .abi = .none },25 .{ .cpu_arch = .arm, .os_tag = .uefi, .abi = .none },
...@@ -30,7 +32,11 @@ const targets = [_]std.zig.CrossTarget{...@@ -30,7 +32,11 @@ const targets = [_]std.zig.CrossTarget{
30 .{ .cpu_arch = .bpfel, .os_tag = .linux, .abi = .none },32 .{ .cpu_arch = .bpfel, .os_tag = .linux, .abi = .none },
31 .{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .gnu },33 .{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .gnu },
32 .{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .none },34 .{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .none },
35 .{ .cpu_arch = .csky, .os_tag = .freestanding, .abi = .none },
36 .{ .cpu_arch = .csky, .os_tag = .linux, .abi = .none },
33 .{ .cpu_arch = .hexagon, .os_tag = .linux, .abi = .none },37 .{ .cpu_arch = .hexagon, .os_tag = .linux, .abi = .none },
38 .{ .cpu_arch = .m68k, .os_tag = .freestanding, .abi = .none },
39 .{ .cpu_arch = .m68k, .os_tag = .linux, .abi = .none },
34 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .gnueabihf },40 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .gnueabihf },
35 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .musl },41 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .musl },
36 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .none },42 .{ .cpu_arch = .mips, .os_tag = .linux, .abi = .none },
...@@ -117,10 +123,20 @@ const targets = [_]std.zig.CrossTarget{...@@ -117,10 +123,20 @@ const targets = [_]std.zig.CrossTarget{
117 .{ .cpu_arch = .x86_64, .os_tag = .uefi, .abi = .none },123 .{ .cpu_arch = .x86_64, .os_tag = .uefi, .abi = .none },
118 .{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .gnu },124 .{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .gnu },
119 .{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .msvc },125 .{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .msvc },
126 .{ .cpu_arch = .xtensa, .os_tag = .freestanding, .abi = .none },
127 .{ .cpu_arch = .xtensa, .os_tag = .linux, .abi = .none },
120};128};
121129
122pub fn addCases(ctx: *Cases) !void {130pub fn addCases(ctx: *Cases, build_options: @import("cases.zig").BuildOptions) !void {
131 if (!build_options.enable_llvm) return;
123 for (targets) |target| {132 for (targets) |target| {
133 if (target.cpu_arch) |arch| switch (arch) {
134 .m68k => if (!build_options.llvm_has_m68k) continue,
135 .csky => if (!build_options.llvm_has_csky) continue,
136 .arc => if (!build_options.llvm_has_arc) continue,
137 .xtensa => if (!build_options.llvm_has_xtensa) continue,
138 else => {},
139 };
124 var case = ctx.noEmitUsingLlvmBackend("llvm_targets", target);140 var case = ctx.noEmitUsingLlvmBackend("llvm_targets", target);
125 case.addCompile("");141 case.addCompile("");
126 }142 }
test/tests.zig+2-1
...@@ -1156,6 +1156,7 @@ pub fn addCases(...@@ -1156,6 +1156,7 @@ pub fn addCases(
1156 parent_step: *Step,1156 parent_step: *Step,
1157 opt_test_filter: ?[]const u8,1157 opt_test_filter: ?[]const u8,
1158 check_case_exe: *std.Build.Step.Compile,1158 check_case_exe: *std.Build.Step.Compile,
1159 build_options: @import("cases.zig").BuildOptions,
1159) !void {1160) !void {
1160 const arena = b.allocator;1161 const arena = b.allocator;
1161 const gpa = b.allocator;1162 const gpa = b.allocator;
...@@ -1166,7 +1167,7 @@ pub fn addCases(...@@ -1166,7 +1167,7 @@ pub fn addCases(
1166 defer dir.close();1167 defer dir.close();
11671168
1168 cases.addFromDir(dir);1169 cases.addFromDir(dir);
1169 try @import("cases.zig").addCases(&cases);1170 try @import("cases.zig").addCases(&cases, build_options);
11701171
1171 const cases_dir_path = try b.build_root.join(b.allocator, &.{ "test", "cases" });1172 const cases_dir_path = try b.build_root.join(b.allocator, &.{ "test", "cases" });
1172 cases.lowerToBuildSteps(1173 cases.lowerToBuildSteps(