authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-08 01:28:17-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-08 04:41:55-04:00
log9fc9235ac815f8b0ad88445216407a0a9f747d5f
tree4b1d2fb68a1c982ec23010d09e35950f1f7a9c15
parentf6e027da32caabdea57bae9ee806abe1d9e3ac68

x86_64: fix undersized vector binary operations

2 files changed, 10 insertions(+), 3 deletions(-)

src/arch/x86_64/CodeGen.zig+8-2
...@@ -7733,7 +7733,10 @@ fn genBinOp(...@@ -7733,7 +7733,10 @@ fn genBinOp(
7733 mir_tag,7733 mir_tag,
7734 dst_reg,7734 dst_reg,
7735 lhs_reg,7735 lhs_reg,
7736 src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),7736 src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
7737 else => Memory.PtrSize.fromSize(abi_size),
7738 .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
7739 }),
7737 ) else try self.asmRegisterRegisterRegister(7740 ) else try self.asmRegisterRegisterRegister(
7738 mir_tag,7741 mir_tag,
7739 dst_reg,7742 dst_reg,
...@@ -7748,7 +7751,10 @@ fn genBinOp(...@@ -7748,7 +7751,10 @@ fn genBinOp(
7748 if (src_mcv.isMemory()) try self.asmRegisterMemory(7751 if (src_mcv.isMemory()) try self.asmRegisterMemory(
7749 mir_tag,7752 mir_tag,
7750 dst_reg,7753 dst_reg,
7751 src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),7754 src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
7755 else => Memory.PtrSize.fromSize(abi_size),
7756 .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
7757 }),
7752 ) else try self.asmRegisterRegister(7758 ) else try self.asmRegisterRegister(
7753 mir_tag,7759 mir_tag,
7754 dst_reg,7760 dst_reg,
test/behavior/maximum_minimum.zig+2-1
...@@ -276,7 +276,8 @@ test "@min/@max notices bounds from vector types when element of comptime-known...@@ -276,7 +276,8 @@ test "@min/@max notices bounds from vector types when element of comptime-known
276 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO276 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
277 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO277 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
278 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;278 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
279 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;279 if (builtin.zig_backend == .stage2_x86_64 and
280 !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
280281
281 var x: @Vector(2, u32) = .{ 1_000_000, 12345 };282 var x: @Vector(2, u32) = .{ 1_000_000, 12345 };
282 const y: @Vector(2, u16) = .{ 10, undefined };283 const y: @Vector(2, u16) = .{ 10, undefined };