| ... | ... | @@ -9,6 +9,7 @@ else switch (native_arch) { |
| 9 | 9 | .hexagon => Hexagon, |
| 10 | 10 | .loongarch32, .loongarch64 => LoongArch, |
| 11 | 11 | .mips, .mipsel, .mips64, .mips64el => Mips, |
| 12 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc, |
| 12 | 13 | .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv, |
| 13 | 14 | .s390x => S390x, |
| 14 | 15 | .x86 => X86, |
| ... | ... | @@ -216,6 +217,14 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native { |
| 216 | 217 | }, |
| 217 | 218 | else => null, |
| 218 | 219 | }, |
| 220 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => switch (builtin.os.tag) { |
| 221 | .linux => .{ |
| 222 | .r = uc.mcontext.gp_regs[0..32].*, |
| 223 | .pc = uc.mcontext.gp_regs[32], |
| 224 | .lr = uc.mcontext.gp_regs[36], |
| 225 | }, |
| 226 | else => null, |
| 227 | }, |
| 219 | 228 | .riscv32, .riscv64 => switch (builtin.os.tag) { |
| 220 | 229 | .linux => .{ |
| 221 | 230 | .r = [1]usize{0} ++ uc.mcontext.gregs[1..].*, // r0 position is used for pc; replace with zero |
| ... | ... | @@ -808,6 +817,114 @@ pub const Mips = extern struct { |
| 808 | 817 | } |
| 809 | 818 | }; |
| 810 | 819 | |
| 820 | /// This is an `extern struct` so that inline assembly in `current` can use field offsets. |
| 821 | pub const Powerpc = extern struct { |
| 822 | /// The numbered general-purpose registers r0 - r31. |
| 823 | r: [32]Gpr, |
| 824 | pc: Gpr, |
| 825 | lr: Gpr, |
| 826 | |
| 827 | pub const Gpr = if (builtin.target.cpu.arch.isPowerPC64()) u64 else u32; |
| 828 | |
| 829 | pub inline fn current() Powerpc { |
| 830 | var ctx: Powerpc = undefined; |
| 831 | asm volatile (if (Gpr == u64) |
| 832 | \\ std 0, 0(10) |
| 833 | \\ std 1, 8(10) |
| 834 | \\ std 2, 16(10) |
| 835 | \\ std 3, 24(10) |
| 836 | \\ std 4, 32(10) |
| 837 | \\ std 5, 40(10) |
| 838 | \\ std 6, 48(10) |
| 839 | \\ std 7, 56(10) |
| 840 | \\ std 8, 64(10) |
| 841 | \\ std 9, 72(10) |
| 842 | \\ std 10, 80(10) |
| 843 | \\ std 11, 88(10) |
| 844 | \\ std 12, 96(10) |
| 845 | \\ std 13, 104(10) |
| 846 | \\ std 14, 112(10) |
| 847 | \\ std 15, 120(10) |
| 848 | \\ std 16, 128(10) |
| 849 | \\ std 17, 136(10) |
| 850 | \\ std 18, 144(10) |
| 851 | \\ std 19, 152(10) |
| 852 | \\ std 20, 160(10) |
| 853 | \\ std 21, 168(10) |
| 854 | \\ std 22, 176(10) |
| 855 | \\ std 23, 184(10) |
| 856 | \\ std 24, 192(10) |
| 857 | \\ std 25, 200(10) |
| 858 | \\ std 26, 208(10) |
| 859 | \\ std 27, 216(10) |
| 860 | \\ std 28, 224(10) |
| 861 | \\ std 29, 232(10) |
| 862 | \\ std 30, 240(10) |
| 863 | \\ std 31, 248(10) |
| 864 | \\ mflr 8 |
| 865 | \\ std 8, 264(10) |
| 866 | \\ bl 1f |
| 867 | \\1: |
| 868 | \\ mflr 8 |
| 869 | \\ std 8, 256(10) |
| 870 | \\ ld 8, 64(10) |
| 871 | else |
| 872 | \\ stw 0, 0(10) |
| 873 | \\ stw 1, 4(10) |
| 874 | \\ stw 2, 8(10) |
| 875 | \\ stw 3, 12(10) |
| 876 | \\ stw 4, 16(10) |
| 877 | \\ stw 5, 20(10) |
| 878 | \\ stw 6, 24(10) |
| 879 | \\ stw 7, 28(10) |
| 880 | \\ stw 8, 32(10) |
| 881 | \\ stw 9, 36(10) |
| 882 | \\ stw 10, 40(10) |
| 883 | \\ stw 11, 44(10) |
| 884 | \\ stw 12, 48(10) |
| 885 | \\ stw 13, 52(10) |
| 886 | \\ stw 14, 56(10) |
| 887 | \\ stw 15, 60(10) |
| 888 | \\ stw 16, 64(10) |
| 889 | \\ stw 17, 68(10) |
| 890 | \\ stw 18, 72(10) |
| 891 | \\ stw 19, 76(10) |
| 892 | \\ stw 20, 80(10) |
| 893 | \\ stw 21, 84(10) |
| 894 | \\ stw 22, 88(10) |
| 895 | \\ stw 23, 92(10) |
| 896 | \\ stw 24, 96(10) |
| 897 | \\ stw 25, 100(10) |
| 898 | \\ stw 26, 104(10) |
| 899 | \\ stw 27, 108(10) |
| 900 | \\ stw 28, 112(10) |
| 901 | \\ stw 29, 116(10) |
| 902 | \\ stw 30, 120(10) |
| 903 | \\ stw 31, 124(10) |
| 904 | \\ mflr 8 |
| 905 | \\ stw 8, 132(10) |
| 906 | \\ bl 1f |
| 907 | \\1: |
| 908 | \\ mflr 8 |
| 909 | \\ stw 8, 128(10) |
| 910 | \\ lwz 8, 32(10) |
| 911 | : |
| 912 | : [gprs] "{r10}" (&ctx), |
| 913 | : .{ .lr = true, .memory = true }); |
| 914 | return ctx; |
| 915 | } |
| 916 | |
| 917 | pub fn dwarfRegisterBytes(ctx: *Powerpc, register_num: u16) DwarfRegisterError![]u8 { |
| 918 | switch (register_num) { |
| 919 | 0...31 => return @ptrCast(&ctx.r[register_num]), |
| 920 | 65 => return @ptrCast(&ctx.lr), |
| 921 | 357 => return @ptrCast(&ctx.pc), |
| 922 | |
| 923 | else => return error.InvalidRegister, |
| 924 | } |
| 925 | } |
| 926 | }; |
| 927 | |
| 811 | 928 | /// This is an `extern struct` so that inline assembly in `current` can use field offsets. |
| 812 | 929 | pub const Riscv = extern struct { |
| 813 | 930 | /// The numbered general-purpose registers r0 - r31. r0 must be zero. |
Alex Rønne Petersen <alex@alexrp.com> 2025-10-07 00:05:39+02:00
Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM
lib