| author | |
| committer | |
| log | ad176b319d810da7755b9a1ec39e68210df8d807 |
| tree | c82c32c3462dd221bcd25dac644f6f7f1f9db0fd |
| parent | 65c5ef52e94323e15005cb943cd98b929119ce39 |
2 files changed, 29 insertions(+), 1 deletions(-)
src/arch/sparc64/Emit.zig+21-1| ... | ... | @@ -102,7 +102,7 @@ pub fn emitMir( |
| 102 | 102 | |
| 103 | 103 | .movcc => try emit.mirConditionalMove(inst), |
| 104 | 104 | |
| 105 | .movr => @panic("TODO implement sparc64 movr"), | |
| 105 | .movr => try emit.mirConditionalMove(inst), | |
| 106 | 106 | |
| 107 | 107 | .mulx => try emit.mirArithmetic3Op(inst), |
| 108 | 108 | .sdivx => try emit.mirArithmetic3Op(inst), |
| ... | ... | @@ -346,6 +346,26 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void { |
| 346 | 346 | )); |
| 347 | 347 | } |
| 348 | 348 | }, |
| 349 | .movr => { | |
| 350 | const data = emit.mir.instructions.items(.data)[inst].conditional_move_reg; | |
| 351 | if (data.is_imm) { | |
| 352 | try emit.writeInstruction(Instruction.movr( | |
| 353 | i10, | |
| 354 | data.cond, | |
| 355 | data.rs1, | |
| 356 | data.rs2_or_imm.imm, | |
| 357 | data.rd, | |
| 358 | )); | |
| 359 | } else { | |
| 360 | try emit.writeInstruction(Instruction.movr( | |
| 361 | Register, | |
| 362 | data.cond, | |
| 363 | data.rs1, | |
| 364 | data.rs2_or_imm.rs2, | |
| 365 | data.rd, | |
| 366 | )); | |
| 367 | } | |
| 368 | }, | |
| 349 | 369 | else => unreachable, |
| 350 | 370 | } |
| 351 | 371 | } |
src/arch/sparc64/bits.zig+8| ... | ... | @@ -1273,6 +1273,14 @@ pub const Instruction = union(enum) { |
| 1273 | 1273 | }; |
| 1274 | 1274 | } |
| 1275 | 1275 | |
| 1276 | pub fn movr(comptime s2: type, cond: RCondition, rs1: Register, rs2: s2, rd: Register) Instruction { | |
| 1277 | return switch (s2) { | |
| 1278 | Register => format3e(0b10, 0b10_1111, cond, rs1, rs2, rd), | |
| 1279 | i10 => format3f(0b10, 0b10_1111, cond, rs1, rs2, rd), | |
| 1280 | else => unreachable, | |
| 1281 | }; | |
| 1282 | } | |
| 1283 | ||
| 1276 | 1284 | pub fn mulx(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction { |
| 1277 | 1285 | return switch (s2) { |
| 1278 | 1286 | Register => format3a(0b10, 0b00_1001, rs1, rs2, rd), |