| ... | @@ -1185,48 +1185,17 @@ fn genLoad(self: *Self, value_reg: Register, addr_reg: Register, comptime off_ty | ... | @@ -1185,48 +1185,17 @@ fn genLoad(self: *Self, value_reg: Register, addr_reg: Register, comptime off_ty |
| 1185 | const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; | 1185 | const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; |
| 1186 | | 1186 | |
| 1187 | switch (abi_size) { | 1187 | switch (abi_size) { |
| 1188 | 1 => { | 1188 | 1, 2, 4, 8 => { |
| 1189 | _ = try self.addInst(.{ | 1189 | const tag: Mir.Inst.Tag = switch (abi_size) { |
| 1190 | .tag = .ldub, | 1190 | 1 => .ldub, |
| 1191 | .data = .{ | 1191 | 2 => .lduh, |
| 1192 | .arithmetic_3op = .{ | 1192 | 4 => .lduw, |
| 1193 | .is_imm = is_imm, | 1193 | 8 => .ldx, |
| 1194 | .rd = value_reg, | 1194 | else => unreachable, // unexpected abi size |
| 1195 | .rs1 = addr_reg, | 1195 | }; |
| 1196 | .rs2_or_imm = rs2_or_imm, | 1196 | |
| 1197 | }, | | |
| 1198 | }, | | |
| 1199 | }); | | |
| 1200 | }, | | |
| 1201 | 2 => { | | |
| 1202 | _ = try self.addInst(.{ | | |
| 1203 | .tag = .lduh, | | |
| 1204 | .data = .{ | | |
| 1205 | .arithmetic_3op = .{ | | |
| 1206 | .is_imm = is_imm, | | |
| 1207 | .rd = value_reg, | | |
| 1208 | .rs1 = addr_reg, | | |
| 1209 | .rs2_or_imm = rs2_or_imm, | | |
| 1210 | }, | | |
| 1211 | }, | | |
| 1212 | }); | | |
| 1213 | }, | | |
| 1214 | 4 => { | | |
| 1215 | _ = try self.addInst(.{ | | |
| 1216 | .tag = .lduw, | | |
| 1217 | .data = .{ | | |
| 1218 | .arithmetic_3op = .{ | | |
| 1219 | .is_imm = is_imm, | | |
| 1220 | .rd = value_reg, | | |
| 1221 | .rs1 = addr_reg, | | |
| 1222 | .rs2_or_imm = rs2_or_imm, | | |
| 1223 | }, | | |
| 1224 | }, | | |
| 1225 | }); | | |
| 1226 | }, | | |
| 1227 | 8 => { | | |
| 1228 | _ = try self.addInst(.{ | 1197 | _ = try self.addInst(.{ |
| 1229 | .tag = .ldx, | 1198 | .tag = tag, |
| 1230 | .data = .{ | 1199 | .data = .{ |
| 1231 | .arithmetic_3op = .{ | 1200 | .arithmetic_3op = .{ |
| 1232 | .is_imm = is_imm, | 1201 | .is_imm = is_imm, |
| ... | @@ -1436,48 +1405,17 @@ fn genStore(self: *Self, value_reg: Register, addr_reg: Register, comptime off_t | ... | @@ -1436,48 +1405,17 @@ fn genStore(self: *Self, value_reg: Register, addr_reg: Register, comptime off_t |
| 1436 | const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; | 1405 | const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; |
| 1437 | | 1406 | |
| 1438 | switch (abi_size) { | 1407 | switch (abi_size) { |
| 1439 | 1 => { | 1408 | 1, 2, 4, 8 => { |
| 1440 | _ = try self.addInst(.{ | 1409 | const tag: Mir.Inst.Tag = switch (abi_size) { |
| 1441 | .tag = .stb, | 1410 | 1 => .stb, |
| 1442 | .data = .{ | 1411 | 2 => .sth, |
| 1443 | .arithmetic_3op = .{ | 1412 | 4 => .stw, |
| 1444 | .is_imm = is_imm, | 1413 | 8 => .stx, |
| 1445 | .rd = value_reg, | 1414 | else => unreachable, // unexpected abi size |
| 1446 | .rs1 = addr_reg, | 1415 | }; |
| 1447 | .rs2_or_imm = rs2_or_imm, | 1416 | |
| 1448 | }, | | |
| 1449 | }, | | |
| 1450 | }); | | |
| 1451 | }, | | |
| 1452 | 2 => { | | |
| 1453 | _ = try self.addInst(.{ | | |
| 1454 | .tag = .sth, | | |
| 1455 | .data = .{ | | |
| 1456 | .arithmetic_3op = .{ | | |
| 1457 | .is_imm = is_imm, | | |
| 1458 | .rd = value_reg, | | |
| 1459 | .rs1 = addr_reg, | | |
| 1460 | .rs2_or_imm = rs2_or_imm, | | |
| 1461 | }, | | |
| 1462 | }, | | |
| 1463 | }); | | |
| 1464 | }, | | |
| 1465 | 4 => { | | |
| 1466 | _ = try self.addInst(.{ | | |
| 1467 | .tag = .stw, | | |
| 1468 | .data = .{ | | |
| 1469 | .arithmetic_3op = .{ | | |
| 1470 | .is_imm = is_imm, | | |
| 1471 | .rd = value_reg, | | |
| 1472 | .rs1 = addr_reg, | | |
| 1473 | .rs2_or_imm = rs2_or_imm, | | |
| 1474 | }, | | |
| 1475 | }, | | |
| 1476 | }); | | |
| 1477 | }, | | |
| 1478 | 8 => { | | |
| 1479 | _ = try self.addInst(.{ | 1417 | _ = try self.addInst(.{ |
| 1480 | .tag = .stx, | 1418 | .tag = tag, |
| 1481 | .data = .{ | 1419 | .data = .{ |
| 1482 | .arithmetic_3op = .{ | 1420 | .arithmetic_3op = .{ |
| 1483 | .is_imm = is_imm, | 1421 | .is_imm = is_imm, |
Koakuma <koachan@protonmail.com> 2022-04-21 06:06:58+07:00
Jakub Konka <kubkon@jakubkonka.com> 2022-05-05 19:34:05+02:00
src