authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-06-23 17:44:56+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-20 05:08:16+02:00
logaf8205e25ee1781e3747246a45e8c30b65486ab3
tree4b6c7da13c863540f049ee36394f7c7d1cfc007c
parent5a2f6acb447abef01088c0030ca41a5e0e036114
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `nacl` OS specifier and `le32`/`le64` arch specifiers.

Native Client is dead. https://developer.chrome.com/docs/native-client

6 files changed, 0 insertions(+), 45 deletions(-)

lib/compiler/aro/aro/target.zig-8
......@@ -39,7 +39,6 @@ pub fn intMaxType(target: std.Target) Type {
3939pub fn intPtrType(target: std.Target) Type {
4040 switch (target.os.tag) {
4141 .haiku => return .{ .specifier = .long },
42 .nacl => return .{ .specifier = .int },
4342 else => {},
4443 }
4544
......@@ -467,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
467466 .csky,
468467 .hexagon,
469468 .m68k,
470 .le32,
471469 .mips,
472470 .mipsel,
473471 .powerpc,
......@@ -500,7 +498,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
500498
501499 .aarch64 => copy.cpu.arch = .arm,
502500 .aarch64_be => copy.cpu.arch = .armeb,
503 .le64 => copy.cpu.arch = .le32,
504501 .amdil64 => copy.cpu.arch = .amdil,
505502 .nvptx64 => copy.cpu.arch = .nvptx,
506503 .wasm64 => copy.cpu.arch = .wasm32,
......@@ -547,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
547544 .amdgcn,
548545 .bpfeb,
549546 .bpfel,
550 .le64,
551547 .amdil64,
552548 .nvptx64,
553549 .wasm64,
......@@ -572,7 +568,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
572568 .arm => copy.cpu.arch = .aarch64,
573569 .armeb => copy.cpu.arch = .aarch64_be,
574570 .hsail => copy.cpu.arch = .hsail64,
575 .le32 => copy.cpu.arch = .le64,
576571 .loongarch32 => copy.cpu.arch = .loongarch64,
577572 .mips => copy.cpu.arch = .mips64,
578573 .mipsel => copy.cpu.arch = .mips64el,
......@@ -643,8 +638,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
643638 .xtensa => "xtensa",
644639 .nvptx => "nvptx",
645640 .nvptx64 => "nvptx64",
646 .le32 => "le32",
647 .le64 => "le64",
648641 .amdil => "amdil",
649642 .amdil64 => "amdil64",
650643 .hsail => "hsail",
......@@ -685,7 +678,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
685678 .haiku => "haiku",
686679 .minix => "minix",
687680 .rtems => "rtems",
688 .nacl => "nacl",
689681 .aix => "aix",
690682 .cuda => "cuda",
691683 .nvcl => "nvcl",
lib/std/Target.zig-23
......@@ -35,7 +35,6 @@ pub const Os = struct {
3535 haiku,
3636 minix,
3737 rtems,
38 nacl,
3938 aix,
4039 cuda,
4140 nvcl,
......@@ -144,7 +143,6 @@ pub const Os = struct {
144143 .haiku,
145144 .minix,
146145 .rtems,
147 .nacl,
148146 .aix,
149147 .cuda,
150148 .nvcl,
......@@ -377,7 +375,6 @@ pub const Os = struct {
377375 .haiku,
378376 .minix,
379377 .rtems,
380 .nacl,
381378 .aix,
382379 .cuda,
383380 .nvcl,
......@@ -564,7 +561,6 @@ pub const Os = struct {
564561 .zos,
565562 .minix,
566563 .rtems,
567 .nacl,
568564 .aix,
569565 .cuda,
570566 .nvcl,
......@@ -668,7 +664,6 @@ pub const Abi = enum {
668664 .zos,
669665 .minix,
670666 .rtems,
671 .nacl,
672667 .aix,
673668 .cuda,
674669 .nvcl,
......@@ -1018,8 +1013,6 @@ pub const Cpu = struct {
10181013 xtensa,
10191014 nvptx,
10201015 nvptx64,
1021 le32,
1022 le64,
10231016 amdil,
10241017 amdil64,
10251018 hsail,
......@@ -1153,7 +1146,6 @@ pub const Cpu = struct {
11531146 .hexagon => .HEXAGON,
11541147 .dxil => .NONE,
11551148 .m68k => .@"68K",
1156 .le32 => .NONE,
11571149 .mips => .MIPS,
11581150 .mipsel => .MIPS_RS3_LE,
11591151 .powerpc, .powerpcle => .PPC,
......@@ -1187,7 +1179,6 @@ pub const Cpu = struct {
11871179 .riscv64 => .RISCV,
11881180 .x86_64 => .X86_64,
11891181 .nvptx64 => .NONE,
1190 .le64 => .NONE,
11911182 .amdil64 => .NONE,
11921183 .hsail64 => .NONE,
11931184 .spir64 => .NONE,
......@@ -1219,7 +1210,6 @@ pub const Cpu = struct {
12191210 .dxil => .Unknown,
12201211 .hexagon => .Unknown,
12211212 .m68k => .Unknown,
1222 .le32 => .Unknown,
12231213 .mips => .Unknown,
12241214 .mipsel => .Unknown,
12251215 .powerpc, .powerpcle => .POWERPC,
......@@ -1253,7 +1243,6 @@ pub const Cpu = struct {
12531243 .riscv64 => .RISCV64,
12541244 .x86_64 => .X64,
12551245 .nvptx64 => .Unknown,
1256 .le64 => .Unknown,
12571246 .amdil64 => .Unknown,
12581247 .hsail64 => .Unknown,
12591248 .spir64 => .Unknown,
......@@ -1291,8 +1280,6 @@ pub const Cpu = struct {
12911280 .hsail,
12921281 .hsail64,
12931282 .kalimba,
1294 .le32,
1295 .le64,
12961283 .mipsel,
12971284 .mips64el,
12981285 .msp430,
......@@ -1799,8 +1786,6 @@ pub const DynamicLinker = struct {
17991786 .tce,
18001787 .tcele,
18011788 .xcore,
1802 .le32,
1803 .le64,
18041789 .amdil,
18051790 .amdil64,
18061791 .hsail,
......@@ -1854,7 +1839,6 @@ pub const DynamicLinker = struct {
18541839 .zos,
18551840 .minix,
18561841 .rtems,
1857 .nacl,
18581842 .aix,
18591843 .cuda,
18601844 .nvcl,
......@@ -1897,7 +1881,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18971881 .csky,
18981882 .hexagon,
18991883 .m68k,
1900 .le32,
19011884 .mips,
19021885 .mipsel,
19031886 .powerpc,
......@@ -1936,7 +1919,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
19361919 .riscv64,
19371920 .x86_64,
19381921 .nvptx64,
1939 .le64,
19401922 .amdil64,
19411923 .hsail64,
19421924 .spir64,
......@@ -2372,7 +2354,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
23722354 .lv2,
23732355 .zos,
23742356 .rtems,
2375 .nacl,
23762357 .aix,
23772358 .elfiamcu,
23782359 .mesa3d,
......@@ -2439,7 +2420,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24392420 .loongarch32,
24402421 .tce,
24412422 .tcele,
2442 .le32,
24432423 .amdil,
24442424 .hsail,
24452425 .spir,
......@@ -2467,7 +2447,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24672447 .sparcel,
24682448 .sparc64,
24692449 .lanai,
2470 .le64,
24712450 .nvptx,
24722451 .nvptx64,
24732452 .r600,
......@@ -2560,7 +2539,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25602539 .loongarch32,
25612540 .tce,
25622541 .tcele,
2563 .le32,
25642542 .amdil,
25652543 .hsail,
25662544 .spir,
......@@ -2595,7 +2573,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25952573 .sparcel,
25962574 .sparc64,
25972575 .lanai,
2598 .le64,
25992576 .nvptx,
26002577 .nvptx64,
26012578 .r600,
src/Type.zig-2
......@@ -1651,7 +1651,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16511651 .m68k,
16521652 .tce,
16531653 .tcele,
1654 .le32,
16551654 .amdil,
16561655 .hsail,
16571656 .spir,
......@@ -1660,7 +1659,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16601659 .spirv,
16611660 .spirv32,
16621661 .shave,
1663 .le64,
16641662 .amdil64,
16651663 .hsail64,
16661664 .spir64,
src/Zcu.zig-2
......@@ -3243,7 +3243,6 @@ pub fn atomicPtrAlignment(
32433243 .armeb,
32443244 .hexagon,
32453245 .m68k,
3246 .le32,
32473246 .mips,
32483247 .mipsel,
32493248 .nvptx,
......@@ -3277,7 +3276,6 @@ pub fn atomicPtrAlignment(
32773276 .amdgcn,
32783277 .bpfel,
32793278 .bpfeb,
3280 .le64,
32813279 .mips64,
32823280 .mips64el,
32833281 .nvptx64,
src/codegen/llvm.zig-8
......@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
8282 .xtensa => "xtensa",
8383 .nvptx => "nvptx",
8484 .nvptx64 => "nvptx64",
85 .le32 => "le32",
86 .le64 => "le64",
8785 .amdil => "amdil",
8886 .amdil64 => "amdil64",
8987 .hsail => "hsail",
......@@ -120,7 +118,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
120118 .zos => "zos",
121119 .haiku => "haiku",
122120 .rtems => "rtems",
123 .nacl => "nacl",
124121 .aix => "aix",
125122 .cuda => "cuda",
126123 .nvcl => "nvcl",
......@@ -242,7 +239,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType {
242239 .zos => .ZOS,
243240 .haiku => .Haiku,
244241 .rtems => .RTEMS,
245 .nacl => .NaCl,
246242 .aix => .AIX,
247243 .cuda => .CUDA,
248244 .nvcl => .NVCL,
......@@ -311,8 +307,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
311307 .xtensa => .xtensa,
312308 .nvptx => .nvptx,
313309 .nvptx64 => .nvptx64,
314 .le32 => .le32,
315 .le64 => .le64,
316310 .amdil => .amdil,
317311 .amdil64 => .amdil64,
318312 .hsail => .hsail,
......@@ -12098,8 +12092,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1209812092 .tce,
1209912093 .tcele,
1210012094 .r600,
12101 .le32,
12102 .le64,
1210312095 .amdil,
1210412096 .amdil64,
1210512097 .hsail,
src/target.zig-2
......@@ -153,8 +153,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
153153 .xtensa,
154154 .nvptx,
155155 .nvptx64,
156 .le32,
157 .le64,
158156 .amdil,
159157 .amdil64,
160158 .hsail,