| author |  Alex Rønne Petersen <alex@alexrp.com> 2024-06-23 17:44:56+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2024-07-20 05:08:16+02:00 |
| log | af8205e25ee1781e3747246a45e8c30b65486ab3 |
| tree | 4b6c7da13c863540f049ee36394f7c7d1cfc007c |
| parent | 5a2f6acb447abef01088c0030ca41a5e0e036114 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.Target: Remove `nacl` OS specifier and `le32`/`le64` arch specifiers.
Native Client is dead.
https://developer.chrome.com/docs/native-client6 files changed, 0 insertions(+), 45 deletions(-)
lib- compiler
- aro
- aro
- std
- src
lib/compiler/aro/aro/target.zig-8
| ... | @@ -39,7 +39,6 @@ pub fn intMaxType(target: std.Target) Type { | ... | @@ -39,7 +39,6 @@ pub fn intMaxType(target: std.Target) Type { |
| 39 | pub fn intPtrType(target: std.Target) Type { | 39 | pub fn intPtrType(target: std.Target) Type { |
| 40 | switch (target.os.tag) { | 40 | switch (target.os.tag) { |
| 41 | .haiku => return .{ .specifier = .long }, | 41 | .haiku => return .{ .specifier = .long }, |
| 42 | .nacl => return .{ .specifier = .int }, | ||
| 43 | else => {}, | 42 | else => {}, |
| 44 | } | 43 | } |
| 45 | 44 | ||
| ... | @@ -467,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -467,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { |
| 467 | .csky, | 466 | .csky, |
| 468 | .hexagon, | 467 | .hexagon, |
| 469 | .m68k, | 468 | .m68k, |
| 470 | .le32, | ||
| 471 | .mips, | 469 | .mips, |
| 472 | .mipsel, | 470 | .mipsel, |
| 473 | .powerpc, | 471 | .powerpc, |
| ... | @@ -500,7 +498,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -500,7 +498,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { |
| 500 | 498 | ||
| 501 | .aarch64 => copy.cpu.arch = .arm, | 499 | .aarch64 => copy.cpu.arch = .arm, |
| 502 | .aarch64_be => copy.cpu.arch = .armeb, | 500 | .aarch64_be => copy.cpu.arch = .armeb, |
| 503 | .le64 => copy.cpu.arch = .le32, | ||
| 504 | .amdil64 => copy.cpu.arch = .amdil, | 501 | .amdil64 => copy.cpu.arch = .amdil, |
| 505 | .nvptx64 => copy.cpu.arch = .nvptx, | 502 | .nvptx64 => copy.cpu.arch = .nvptx, |
| 506 | .wasm64 => copy.cpu.arch = .wasm32, | 503 | .wasm64 => copy.cpu.arch = .wasm32, |
| ... | @@ -547,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -547,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { |
| 547 | .amdgcn, | 544 | .amdgcn, |
| 548 | .bpfeb, | 545 | .bpfeb, |
| 549 | .bpfel, | 546 | .bpfel, |
| 550 | .le64, | ||
| 551 | .amdil64, | 547 | .amdil64, |
| 552 | .nvptx64, | 548 | .nvptx64, |
| 553 | .wasm64, | 549 | .wasm64, |
| ... | @@ -572,7 +568,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -572,7 +568,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { |
| 572 | .arm => copy.cpu.arch = .aarch64, | 568 | .arm => copy.cpu.arch = .aarch64, |
| 573 | .armeb => copy.cpu.arch = .aarch64_be, | 569 | .armeb => copy.cpu.arch = .aarch64_be, |
| 574 | .hsail => copy.cpu.arch = .hsail64, | 570 | .hsail => copy.cpu.arch = .hsail64, |
| 575 | .le32 => copy.cpu.arch = .le64, | ||
| 576 | .loongarch32 => copy.cpu.arch = .loongarch64, | 571 | .loongarch32 => copy.cpu.arch = .loongarch64, |
| 577 | .mips => copy.cpu.arch = .mips64, | 572 | .mips => copy.cpu.arch = .mips64, |
| 578 | .mipsel => copy.cpu.arch = .mips64el, | 573 | .mipsel => copy.cpu.arch = .mips64el, |
| ... | @@ -643,8 +638,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { | ... | @@ -643,8 +638,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { |
| 643 | .xtensa => "xtensa", | 638 | .xtensa => "xtensa", |
| 644 | .nvptx => "nvptx", | 639 | .nvptx => "nvptx", |
| 645 | .nvptx64 => "nvptx64", | 640 | .nvptx64 => "nvptx64", |
| 646 | .le32 => "le32", | ||
| 647 | .le64 => "le64", | ||
| 648 | .amdil => "amdil", | 641 | .amdil => "amdil", |
| 649 | .amdil64 => "amdil64", | 642 | .amdil64 => "amdil64", |
| 650 | .hsail => "hsail", | 643 | .hsail => "hsail", |
| ... | @@ -685,7 +678,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { | ... | @@ -685,7 +678,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { |
| 685 | .haiku => "haiku", | 678 | .haiku => "haiku", |
| 686 | .minix => "minix", | 679 | .minix => "minix", |
| 687 | .rtems => "rtems", | 680 | .rtems => "rtems", |
| 688 | .nacl => "nacl", | ||
| 689 | .aix => "aix", | 681 | .aix => "aix", |
| 690 | .cuda => "cuda", | 682 | .cuda => "cuda", |
| 691 | .nvcl => "nvcl", | 683 | .nvcl => "nvcl", |
lib/std/Target.zig-23
| ... | @@ -35,7 +35,6 @@ pub const Os = struct { | ... | @@ -35,7 +35,6 @@ pub const Os = struct { |
| 35 | haiku, | 35 | haiku, |
| 36 | minix, | 36 | minix, |
| 37 | rtems, | 37 | rtems, |
| 38 | nacl, | ||
| 39 | aix, | 38 | aix, |
| 40 | cuda, | 39 | cuda, |
| 41 | nvcl, | 40 | nvcl, |
| ... | @@ -144,7 +143,6 @@ pub const Os = struct { | ... | @@ -144,7 +143,6 @@ pub const Os = struct { |
| 144 | .haiku, | 143 | .haiku, |
| 145 | .minix, | 144 | .minix, |
| 146 | .rtems, | 145 | .rtems, |
| 147 | .nacl, | ||
| 148 | .aix, | 146 | .aix, |
| 149 | .cuda, | 147 | .cuda, |
| 150 | .nvcl, | 148 | .nvcl, |
| ... | @@ -377,7 +375,6 @@ pub const Os = struct { | ... | @@ -377,7 +375,6 @@ pub const Os = struct { |
| 377 | .haiku, | 375 | .haiku, |
| 378 | .minix, | 376 | .minix, |
| 379 | .rtems, | 377 | .rtems, |
| 380 | .nacl, | ||
| 381 | .aix, | 378 | .aix, |
| 382 | .cuda, | 379 | .cuda, |
| 383 | .nvcl, | 380 | .nvcl, |
| ... | @@ -564,7 +561,6 @@ pub const Os = struct { | ... | @@ -564,7 +561,6 @@ pub const Os = struct { |
| 564 | .zos, | 561 | .zos, |
| 565 | .minix, | 562 | .minix, |
| 566 | .rtems, | 563 | .rtems, |
| 567 | .nacl, | ||
| 568 | .aix, | 564 | .aix, |
| 569 | .cuda, | 565 | .cuda, |
| 570 | .nvcl, | 566 | .nvcl, |
| ... | @@ -668,7 +664,6 @@ pub const Abi = enum { | ... | @@ -668,7 +664,6 @@ pub const Abi = enum { |
| 668 | .zos, | 664 | .zos, |
| 669 | .minix, | 665 | .minix, |
| 670 | .rtems, | 666 | .rtems, |
| 671 | .nacl, | ||
| 672 | .aix, | 667 | .aix, |
| 673 | .cuda, | 668 | .cuda, |
| 674 | .nvcl, | 669 | .nvcl, |
| ... | @@ -1018,8 +1013,6 @@ pub const Cpu = struct { | ... | @@ -1018,8 +1013,6 @@ pub const Cpu = struct { |
| 1018 | xtensa, | 1013 | xtensa, |
| 1019 | nvptx, | 1014 | nvptx, |
| 1020 | nvptx64, | 1015 | nvptx64, |
| 1021 | le32, | ||
| 1022 | le64, | ||
| 1023 | amdil, | 1016 | amdil, |
| 1024 | amdil64, | 1017 | amdil64, |
| 1025 | hsail, | 1018 | hsail, |
| ... | @@ -1153,7 +1146,6 @@ pub const Cpu = struct { | ... | @@ -1153,7 +1146,6 @@ pub const Cpu = struct { |
| 1153 | .hexagon => .HEXAGON, | 1146 | .hexagon => .HEXAGON, |
| 1154 | .dxil => .NONE, | 1147 | .dxil => .NONE, |
| 1155 | .m68k => .@"68K", | 1148 | .m68k => .@"68K", |
| 1156 | .le32 => .NONE, | ||
| 1157 | .mips => .MIPS, | 1149 | .mips => .MIPS, |
| 1158 | .mipsel => .MIPS_RS3_LE, | 1150 | .mipsel => .MIPS_RS3_LE, |
| 1159 | .powerpc, .powerpcle => .PPC, | 1151 | .powerpc, .powerpcle => .PPC, |
| ... | @@ -1187,7 +1179,6 @@ pub const Cpu = struct { | ... | @@ -1187,7 +1179,6 @@ pub const Cpu = struct { |
| 1187 | .riscv64 => .RISCV, | 1179 | .riscv64 => .RISCV, |
| 1188 | .x86_64 => .X86_64, | 1180 | .x86_64 => .X86_64, |
| 1189 | .nvptx64 => .NONE, | 1181 | .nvptx64 => .NONE, |
| 1190 | .le64 => .NONE, | ||
| 1191 | .amdil64 => .NONE, | 1182 | .amdil64 => .NONE, |
| 1192 | .hsail64 => .NONE, | 1183 | .hsail64 => .NONE, |
| 1193 | .spir64 => .NONE, | 1184 | .spir64 => .NONE, |
| ... | @@ -1219,7 +1210,6 @@ pub const Cpu = struct { | ... | @@ -1219,7 +1210,6 @@ pub const Cpu = struct { |
| 1219 | .dxil => .Unknown, | 1210 | .dxil => .Unknown, |
| 1220 | .hexagon => .Unknown, | 1211 | .hexagon => .Unknown, |
| 1221 | .m68k => .Unknown, | 1212 | .m68k => .Unknown, |
| 1222 | .le32 => .Unknown, | ||
| 1223 | .mips => .Unknown, | 1213 | .mips => .Unknown, |
| 1224 | .mipsel => .Unknown, | 1214 | .mipsel => .Unknown, |
| 1225 | .powerpc, .powerpcle => .POWERPC, | 1215 | .powerpc, .powerpcle => .POWERPC, |
| ... | @@ -1253,7 +1243,6 @@ pub const Cpu = struct { | ... | @@ -1253,7 +1243,6 @@ pub const Cpu = struct { |
| 1253 | .riscv64 => .RISCV64, | 1243 | .riscv64 => .RISCV64, |
| 1254 | .x86_64 => .X64, | 1244 | .x86_64 => .X64, |
| 1255 | .nvptx64 => .Unknown, | 1245 | .nvptx64 => .Unknown, |
| 1256 | .le64 => .Unknown, | ||
| 1257 | .amdil64 => .Unknown, | 1246 | .amdil64 => .Unknown, |
| 1258 | .hsail64 => .Unknown, | 1247 | .hsail64 => .Unknown, |
| 1259 | .spir64 => .Unknown, | 1248 | .spir64 => .Unknown, |
| ... | @@ -1291,8 +1280,6 @@ pub const Cpu = struct { | ... | @@ -1291,8 +1280,6 @@ pub const Cpu = struct { |
| 1291 | .hsail, | 1280 | .hsail, |
| 1292 | .hsail64, | 1281 | .hsail64, |
| 1293 | .kalimba, | 1282 | .kalimba, |
| 1294 | .le32, | ||
| 1295 | .le64, | ||
| 1296 | .mipsel, | 1283 | .mipsel, |
| 1297 | .mips64el, | 1284 | .mips64el, |
| 1298 | .msp430, | 1285 | .msp430, |
| ... | @@ -1799,8 +1786,6 @@ pub const DynamicLinker = struct { | ... | @@ -1799,8 +1786,6 @@ pub const DynamicLinker = struct { |
| 1799 | .tce, | 1786 | .tce, |
| 1800 | .tcele, | 1787 | .tcele, |
| 1801 | .xcore, | 1788 | .xcore, |
| 1802 | .le32, | ||
| 1803 | .le64, | ||
| 1804 | .amdil, | 1789 | .amdil, |
| 1805 | .amdil64, | 1790 | .amdil64, |
| 1806 | .hsail, | 1791 | .hsail, |
| ... | @@ -1854,7 +1839,6 @@ pub const DynamicLinker = struct { | ... | @@ -1854,7 +1839,6 @@ pub const DynamicLinker = struct { |
| 1854 | .zos, | 1839 | .zos, |
| 1855 | .minix, | 1840 | .minix, |
| 1856 | .rtems, | 1841 | .rtems, |
| 1857 | .nacl, | ||
| 1858 | .aix, | 1842 | .aix, |
| 1859 | .cuda, | 1843 | .cuda, |
| 1860 | .nvcl, | 1844 | .nvcl, |
| ... | @@ -1897,7 +1881,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { | ... | @@ -1897,7 +1881,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { |
| 1897 | .csky, | 1881 | .csky, |
| 1898 | .hexagon, | 1882 | .hexagon, |
| 1899 | .m68k, | 1883 | .m68k, |
| 1900 | .le32, | ||
| 1901 | .mips, | 1884 | .mips, |
| 1902 | .mipsel, | 1885 | .mipsel, |
| 1903 | .powerpc, | 1886 | .powerpc, |
| ... | @@ -1936,7 +1919,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { | ... | @@ -1936,7 +1919,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { |
| 1936 | .riscv64, | 1919 | .riscv64, |
| 1937 | .x86_64, | 1920 | .x86_64, |
| 1938 | .nvptx64, | 1921 | .nvptx64, |
| 1939 | .le64, | ||
| 1940 | .amdil64, | 1922 | .amdil64, |
| 1941 | .hsail64, | 1923 | .hsail64, |
| 1942 | .spir64, | 1924 | .spir64, |
| ... | @@ -2372,7 +2354,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { | ... | @@ -2372,7 +2354,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { |
| 2372 | .lv2, | 2354 | .lv2, |
| 2373 | .zos, | 2355 | .zos, |
| 2374 | .rtems, | 2356 | .rtems, |
| 2375 | .nacl, | ||
| 2376 | .aix, | 2357 | .aix, |
| 2377 | .elfiamcu, | 2358 | .elfiamcu, |
| 2378 | .mesa3d, | 2359 | .mesa3d, |
| ... | @@ -2439,7 +2420,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2439,7 +2420,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { |
| 2439 | .loongarch32, | 2420 | .loongarch32, |
| 2440 | .tce, | 2421 | .tce, |
| 2441 | .tcele, | 2422 | .tcele, |
| 2442 | .le32, | ||
| 2443 | .amdil, | 2423 | .amdil, |
| 2444 | .hsail, | 2424 | .hsail, |
| 2445 | .spir, | 2425 | .spir, |
| ... | @@ -2467,7 +2447,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2467,7 +2447,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { |
| 2467 | .sparcel, | 2447 | .sparcel, |
| 2468 | .sparc64, | 2448 | .sparc64, |
| 2469 | .lanai, | 2449 | .lanai, |
| 2470 | .le64, | ||
| 2471 | .nvptx, | 2450 | .nvptx, |
| 2472 | .nvptx64, | 2451 | .nvptx64, |
| 2473 | .r600, | 2452 | .r600, |
| ... | @@ -2560,7 +2539,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2560,7 +2539,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { |
| 2560 | .loongarch32, | 2539 | .loongarch32, |
| 2561 | .tce, | 2540 | .tce, |
| 2562 | .tcele, | 2541 | .tcele, |
| 2563 | .le32, | ||
| 2564 | .amdil, | 2542 | .amdil, |
| 2565 | .hsail, | 2543 | .hsail, |
| 2566 | .spir, | 2544 | .spir, |
| ... | @@ -2595,7 +2573,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2595,7 +2573,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { |
| 2595 | .sparcel, | 2573 | .sparcel, |
| 2596 | .sparc64, | 2574 | .sparc64, |
| 2597 | .lanai, | 2575 | .lanai, |
| 2598 | .le64, | ||
| 2599 | .nvptx, | 2576 | .nvptx, |
| 2600 | .nvptx64, | 2577 | .nvptx64, |
| 2601 | .r600, | 2578 | .r600, |
src/Type.zig-2
| ... | @@ -1651,7 +1651,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { | ... | @@ -1651,7 +1651,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { |
| 1651 | .m68k, | 1651 | .m68k, |
| 1652 | .tce, | 1652 | .tce, |
| 1653 | .tcele, | 1653 | .tcele, |
| 1654 | .le32, | ||
| 1655 | .amdil, | 1654 | .amdil, |
| 1656 | .hsail, | 1655 | .hsail, |
| 1657 | .spir, | 1656 | .spir, |
| ... | @@ -1660,7 +1659,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { | ... | @@ -1660,7 +1659,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { |
| 1660 | .spirv, | 1659 | .spirv, |
| 1661 | .spirv32, | 1660 | .spirv32, |
| 1662 | .shave, | 1661 | .shave, |
| 1663 | .le64, | ||
| 1664 | .amdil64, | 1662 | .amdil64, |
| 1665 | .hsail64, | 1663 | .hsail64, |
| 1666 | .spir64, | 1664 | .spir64, |
src/Zcu.zig-2
| ... | @@ -3243,7 +3243,6 @@ pub fn atomicPtrAlignment( | ... | @@ -3243,7 +3243,6 @@ pub fn atomicPtrAlignment( |
| 3243 | .armeb, | 3243 | .armeb, |
| 3244 | .hexagon, | 3244 | .hexagon, |
| 3245 | .m68k, | 3245 | .m68k, |
| 3246 | .le32, | ||
| 3247 | .mips, | 3246 | .mips, |
| 3248 | .mipsel, | 3247 | .mipsel, |
| 3249 | .nvptx, | 3248 | .nvptx, |
| ... | @@ -3277,7 +3276,6 @@ pub fn atomicPtrAlignment( | ... | @@ -3277,7 +3276,6 @@ pub fn atomicPtrAlignment( |
| 3277 | .amdgcn, | 3276 | .amdgcn, |
| 3278 | .bpfel, | 3277 | .bpfel, |
| 3279 | .bpfeb, | 3278 | .bpfeb, |
| 3280 | .le64, | ||
| 3281 | .mips64, | 3279 | .mips64, |
| 3282 | .mips64el, | 3280 | .mips64el, |
| 3283 | .nvptx64, | 3281 | .nvptx64, |
src/codegen/llvm.zig-8
| ... | @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { | ... | @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { |
| 82 | .xtensa => "xtensa", | 82 | .xtensa => "xtensa", |
| 83 | .nvptx => "nvptx", | 83 | .nvptx => "nvptx", |
| 84 | .nvptx64 => "nvptx64", | 84 | .nvptx64 => "nvptx64", |
| 85 | .le32 => "le32", | ||
| 86 | .le64 => "le64", | ||
| 87 | .amdil => "amdil", | 85 | .amdil => "amdil", |
| 88 | .amdil64 => "amdil64", | 86 | .amdil64 => "amdil64", |
| 89 | .hsail => "hsail", | 87 | .hsail => "hsail", |
| ... | @@ -120,7 +118,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { | ... | @@ -120,7 +118,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { |
| 120 | .zos => "zos", | 118 | .zos => "zos", |
| 121 | .haiku => "haiku", | 119 | .haiku => "haiku", |
| 122 | .rtems => "rtems", | 120 | .rtems => "rtems", |
| 123 | .nacl => "nacl", | ||
| 124 | .aix => "aix", | 121 | .aix => "aix", |
| 125 | .cuda => "cuda", | 122 | .cuda => "cuda", |
| 126 | .nvcl => "nvcl", | 123 | .nvcl => "nvcl", |
| ... | @@ -242,7 +239,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { | ... | @@ -242,7 +239,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { |
| 242 | .zos => .ZOS, | 239 | .zos => .ZOS, |
| 243 | .haiku => .Haiku, | 240 | .haiku => .Haiku, |
| 244 | .rtems => .RTEMS, | 241 | .rtems => .RTEMS, |
| 245 | .nacl => .NaCl, | ||
| 246 | .aix => .AIX, | 242 | .aix => .AIX, |
| 247 | .cuda => .CUDA, | 243 | .cuda => .CUDA, |
| 248 | .nvcl => .NVCL, | 244 | .nvcl => .NVCL, |
| ... | @@ -311,8 +307,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { | ... | @@ -311,8 +307,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { |
| 311 | .xtensa => .xtensa, | 307 | .xtensa => .xtensa, |
| 312 | .nvptx => .nvptx, | 308 | .nvptx => .nvptx, |
| 313 | .nvptx64 => .nvptx64, | 309 | .nvptx64 => .nvptx64, |
| 314 | .le32 => .le32, | ||
| 315 | .le64 => .le64, | ||
| 316 | .amdil => .amdil, | 310 | .amdil => .amdil, |
| 317 | .amdil64 => .amdil64, | 311 | .amdil64 => .amdil64, |
| 318 | .hsail => .hsail, | 312 | .hsail => .hsail, |
| ... | @@ -12098,8 +12092,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { | ... | @@ -12098,8 +12092,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { |
| 12098 | .tce, | 12092 | .tce, |
| 12099 | .tcele, | 12093 | .tcele, |
| 12100 | .r600, | 12094 | .r600, |
| 12101 | .le32, | ||
| 12102 | .le64, | ||
| 12103 | .amdil, | 12095 | .amdil, |
| 12104 | .amdil64, | 12096 | .amdil64, |
| 12105 | .hsail, | 12097 | .hsail, |
src/target.zig-2
| ... | @@ -153,8 +153,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { | ... | @@ -153,8 +153,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { |
| 153 | .xtensa, | 153 | .xtensa, |
| 154 | .nvptx, | 154 | .nvptx, |
| 155 | .nvptx64, | 155 | .nvptx64, |
| 156 | .le32, | ||
| 157 | .le64, | ||
| 158 | .amdil, | 156 | .amdil, |
| 159 | .amdil64, | 157 | .amdil64, |
| 160 | .hsail, | 158 | .hsail, |