authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 01:56:57+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:03:09+02:00
logaf967572446945a0754e7b0756caa2f28bd42070
treef0975bc6571e703fc05fb63115d96c74a4e2ddfc
parente4c7fc58a54d8ca25db92846f09c089bc58e1f04
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

compiler_rt.atomics: lanai does not support atomic instructions

1 files changed, 1 insertions(+), 1 deletions(-)

lib/compiler_rt/atomics.zig+1-1
...@@ -13,7 +13,7 @@ const symbol = compiler_rt.symbol;...@@ -13,7 +13,7 @@ const symbol = compiler_rt.symbol;
13// detail to keep the export logic clean and because we need some kind of CAS to13// detail to keep the export logic clean and because we need some kind of CAS to
14// implement the spinlocks.14// implement the spinlocks.
15const supports_atomic_ops = switch (arch) {15const supports_atomic_ops = switch (arch) {
16 .msp430, .avr, .bpfel, .bpfeb => false,16 .msp430, .avr, .bpfel, .bpfeb, .lanai => false,
17 .arm, .armeb, .thumb, .thumbeb =>17 .arm, .armeb, .thumb, .thumbeb =>
18 // The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS18 // The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS
19 // operations (unless we're targeting Linux, the kernel provides a way to19 // operations (unless we're targeting Linux, the kernel provides a way to