authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2019-07-18 12:28:24-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2019-07-18 12:28:24-04:00
logafbf99c84671992acb4129a6a7bc70d604c4d00d
tree4d74b5d7817845f4ea68f0ce2c0466573ac71253
parentd4ca337e6b8d0c268ebce5c4b5fbe9015f3d8ab6
signaturelock-open Commit is signed but in an unrecognized format.

riscv musl: only add the +a feature

1 files changed, 5 insertions(+), 10 deletions(-)

src/codegen.cpp+5-10
...@@ -8409,16 +8409,11 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa...@@ -8409,16 +8409,11 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa
8409 if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) {8409 if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) {
8410 // Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's8410 // Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's
8411 // cross compilation CPU info for RISCV.8411 // cross compilation CPU info for RISCV.
8412 switch (g->zig_target->arch) {8412 // TODO: https://github.com/ziglang/zig/issues/2883
8413 case ZigLLVM_riscv32:8413 args.append("-Xclang");
8414 args.append("-march=rv32ia");8414 args.append("-target-feature");
8415 break;8415 args.append("-Xclang");
8416 case ZigLLVM_riscv64:8416 args.append("+a");
8417 args.append("-march=rv64ia");
8418 break;
8419 default:
8420 zig_unreachable();
8421 }
8422 }8417 }
8423 }8418 }
8424 if (g->zig_target->os == OsFreestanding) {8419 if (g->zig_target->os == OsFreestanding) {