| ... | ... | @@ -4341,6 +4341,9 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void { |
| 4341 | 4341 | const result = result: { |
| 4342 | 4342 | const dst_ty = self.typeOfIndex(inst); |
| 4343 | 4343 | const src_ty = self.typeOf(ty_op.operand); |
| 4344 | if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{ |
| 4345 | src_ty.fmt(mod), |
| 4346 | }); |
| 4344 | 4347 | |
| 4345 | 4348 | const src_mcv = try self.resolveInst(ty_op.operand); |
| 4346 | 4349 | const mat_src_mcv = switch (src_mcv) { |
| ... | ... | @@ -4691,7 +4694,9 @@ fn byteSwap(self: *Self, inst: Air.Inst.Index, src_ty: Type, src_mcv: MCValue, m |
| 4691 | 4694 | defer if (src_lock) |lock| self.register_manager.unlockReg(lock); |
| 4692 | 4695 | |
| 4693 | 4696 | switch (src_bits) { |
| 4694 | | else => unreachable, |
| 4697 | else => return self.fail("TODO implement byteSwap for {}", .{ |
| 4698 | src_ty.fmt(mod), |
| 4699 | }), |
| 4695 | 4700 | 8 => return if ((mem_ok or src_mcv.isRegister()) and |
| 4696 | 4701 | self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) |
| 4697 | 4702 | src_mcv |
| ... | ... | @@ -6093,16 +6098,16 @@ fn genShiftBinOp( |
| 6093 | 6098 | rhs_ty: Type, |
| 6094 | 6099 | ) !MCValue { |
| 6095 | 6100 | const mod = self.bin_file.options.module.?; |
| 6096 | | if (lhs_ty.zigTypeTag(mod) == .Vector) { |
| 6097 | | return self.fail("TODO implement genShiftBinOp for {}", .{lhs_ty.fmtDebug()}); |
| 6098 | | } |
| 6101 | if (lhs_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement genShiftBinOp for {}", .{ |
| 6102 | lhs_ty.fmt(mod), |
| 6103 | }); |
| 6099 | 6104 | |
| 6100 | 6105 | assert(rhs_ty.abiSize(mod) == 1); |
| 6101 | 6106 | |
| 6102 | 6107 | const lhs_abi_size = lhs_ty.abiSize(mod); |
| 6103 | | if (lhs_abi_size > 16) { |
| 6104 | | return self.fail("TODO implement genShiftBinOp for {}", .{lhs_ty.fmtDebug()}); |
| 6105 | | } |
| 6108 | if (lhs_abi_size > 16) return self.fail("TODO implement genShiftBinOp for {}", .{ |
| 6109 | lhs_ty.fmt(mod), |
| 6110 | }); |
| 6106 | 6111 | |
| 6107 | 6112 | try self.register_manager.getReg(.rcx, null); |
| 6108 | 6113 | const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx); |
| ... | ... | @@ -6158,11 +6163,12 @@ fn genMulDivBinOp( |
| 6158 | 6163 | rhs: MCValue, |
| 6159 | 6164 | ) !MCValue { |
| 6160 | 6165 | const mod = self.bin_file.options.module.?; |
| 6161 | | if (dst_ty.zigTypeTag(mod) == .Vector or dst_ty.zigTypeTag(mod) == .Float) { |
| 6162 | | return self.fail("TODO implement genMulDivBinOp for {}", .{dst_ty.fmtDebug()}); |
| 6163 | | } |
| 6164 | | const dst_abi_size = @as(u32, @intCast(dst_ty.abiSize(mod))); |
| 6165 | | const src_abi_size = @as(u32, @intCast(src_ty.abiSize(mod))); |
| 6166 | if (dst_ty.zigTypeTag(mod) == .Vector or dst_ty.zigTypeTag(mod) == .Float) return self.fail( |
| 6167 | "TODO implement genMulDivBinOp for {}", |
| 6168 | .{dst_ty.fmt(mod)}, |
| 6169 | ); |
| 6170 | const dst_abi_size: u32 = @intCast(dst_ty.abiSize(mod)); |
| 6171 | const src_abi_size: u32 = @intCast(src_ty.abiSize(mod)); |
| 6166 | 6172 | if (switch (tag) { |
| 6167 | 6173 | else => unreachable, |
| 6168 | 6174 | .mul, .mul_wrap => dst_abi_size != src_abi_size and dst_abi_size != src_abi_size * 2, |