| ... | ... | @@ -1841,7 +1841,7 @@ fn finishAir( |
| 1841 | 1841 | } |
| 1842 | 1842 | |
| 1843 | 1843 | const FrameLayout = struct { |
| 1844 | | stack_adjust: u32, |
| 1844 | stack_adjust: i12, |
| 1845 | 1845 | save_reg_list: Mir.RegisterList, |
| 1846 | 1846 | }; |
| 1847 | 1847 | |
| ... | ... | @@ -1855,10 +1855,7 @@ fn setFrameLoc( |
| 1855 | 1855 | const frame_i = @intFromEnum(frame_index); |
| 1856 | 1856 | if (aligned) { |
| 1857 | 1857 | const alignment: InternPool.Alignment = func.frame_allocs.items(.abi_align)[frame_i]; |
| 1858 | | offset.* = if (math.sign(offset.*) < 0) |
| 1859 | | -1 * @as(i32, @intCast(alignment.backward(@intCast(@abs(offset.*))))) |
| 1860 | | else |
| 1861 | | @intCast(alignment.forward(@intCast(@abs(offset.*)))); |
| 1858 | offset.* = math.sign(offset.*) * @as(i32, @intCast(alignment.backward(@intCast(@abs(offset.*))))); |
| 1862 | 1859 | } |
| 1863 | 1860 | func.frame_locs.set(frame_i, .{ .base = base, .disp = offset.* }); |
| 1864 | 1861 | offset.* += func.frame_allocs.items(.abi_size)[frame_i]; |
| ... | ... | @@ -6216,7 +6213,7 @@ fn airAsm(func: *Func, inst: Air.Inst.Index) !void { |
| 6216 | 6213 | .jalr => try func.addInst(.{ |
| 6217 | 6214 | .tag = mnem, |
| 6218 | 6215 | .data = .{ .i_type = .{ |
| 6219 | | .rd = .zero, |
| 6216 | .rd = .ra, |
| 6220 | 6217 | .rs1 = reg1, |
| 6221 | 6218 | .imm12 = Immediate.s(0), |
| 6222 | 6219 | } }, |
| ... | ... | @@ -7337,15 +7334,34 @@ fn airCmpxchg(func: *Func, inst: Air.Inst.Index, strength: enum { weak, strong } |
| 7337 | 7334 | else => return func.fail("TODO: airCmpxchg Int size {}", .{val_abi_size}), |
| 7338 | 7335 | } |
| 7339 | 7336 | |
| 7340 | | const succ_order: struct { aq: Mir.Barrier, rl: Mir.Barrier } = switch (extra.successOrder()) { |
| 7337 | const lr_order: struct { aq: Mir.Barrier, rl: Mir.Barrier } = switch (extra.successOrder()) { |
| 7338 | .unordered, |
| 7339 | => unreachable, |
| 7340 | |
| 7341 | .monotonic, |
| 7342 | .release, |
| 7343 | => .{ .aq = .none, .rl = .none }, |
| 7344 | .acquire, |
| 7345 | .acq_rel, |
| 7346 | => .{ .aq = .aq, .rl = .none }, |
| 7347 | .seq_cst => .{ .aq = .aq, .rl = .rl }, |
| 7348 | }; |
| 7349 | |
| 7350 | const sc_order: struct { aq: Mir.Barrier, rl: Mir.Barrier } = switch (extra.failureOrder()) { |
| 7341 | 7351 | .unordered, |
| 7342 | 7352 | .release, |
| 7343 | 7353 | .acq_rel, |
| 7344 | 7354 | => unreachable, |
| 7345 | 7355 | |
| 7346 | | .monotonic => .{ .aq = .none, .rl = .none }, |
| 7347 | | .acquire => .{ .aq = .aq, .rl = .none }, |
| 7348 | | .seq_cst => .{ .aq = .aq, .rl = .rl }, |
| 7356 | .monotonic, |
| 7357 | .acquire, |
| 7358 | .seq_cst, |
| 7359 | => switch (extra.successOrder()) { |
| 7360 | .release, |
| 7361 | .seq_cst, |
| 7362 | => .{ .aq = .none, .rl = .rl }, |
| 7363 | else => .{ .aq = .none, .rl = .none }, |
| 7364 | }, |
| 7349 | 7365 | }; |
| 7350 | 7366 | |
| 7351 | 7367 | const ptr_mcv = try func.resolveInst(extra.ptr); |
| ... | ... | @@ -7371,8 +7387,8 @@ fn airCmpxchg(func: *Func, inst: Air.Inst.Index, strength: enum { weak, strong } |
| 7371 | 7387 | const jump_back = try func.addInst(.{ |
| 7372 | 7388 | .tag = if (val_ty.bitSize(pt) <= 32) .lrw else .lrd, |
| 7373 | 7389 | .data = .{ .amo = .{ |
| 7374 | | .aq = succ_order.aq, |
| 7375 | | .rl = succ_order.rl, |
| 7390 | .aq = lr_order.aq, |
| 7391 | .rl = lr_order.rl, |
| 7376 | 7392 | .rd = branch_reg, |
| 7377 | 7393 | .rs1 = ptr_reg, |
| 7378 | 7394 | .rs2 = .zero, |
| ... | ... | @@ -7392,8 +7408,8 @@ fn airCmpxchg(func: *Func, inst: Air.Inst.Index, strength: enum { weak, strong } |
| 7392 | 7408 | _ = try func.addInst(.{ |
| 7393 | 7409 | .tag = if (val_ty.bitSize(pt) <= 32) .scw else .scd, |
| 7394 | 7410 | .data = .{ .amo = .{ |
| 7395 | | .aq = .none, |
| 7396 | | .rl = succ_order.rl, |
| 7411 | .aq = sc_order.aq, |
| 7412 | .rl = sc_order.rl, |
| 7397 | 7413 | .rd = fallthrough_reg, |
| 7398 | 7414 | .rs1 = ptr_reg, |
| 7399 | 7415 | .rs2 = new_reg, |
David Rubin <david@vortan.dev> 2024-07-27 08:14:09-07:00
Commit is signed but in an unrecognized format.
src