authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-16 17:09:30+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 00:36:52+02:00
logba9ab3fb6720ff5894ac07741eccaaca44122eb0
treeb2dd557ed57b265647849588f32e22bc1167623d
parenteb36a45ed9fbdf5ab92c3cdb650375a13eaaa648
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.debug: add CPU context and DWARF mappings for m68k

3 files changed, 49 insertions(+), 3 deletions(-)

lib/std/debug/Dwarf.zig+3
...@@ -1435,6 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {...@@ -1435,6 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1435 .hexagon => 76,1435 .hexagon => 76,
1436 .lanai => 2,1436 .lanai => 2,
1437 .loongarch32, .loongarch64 => 64,1437 .loongarch32, .loongarch64 => 64,
1438 .m68k => 26,
1438 .mips, .mipsel, .mips64, .mips64el => 66,1439 .mips, .mipsel, .mips64, .mips64el => 66,
1439 .or1k => 35,1440 .or1k => 35,
1440 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,1441 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
...@@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1456 .hexagon => 30,1457 .hexagon => 30,
1457 .lanai => 5,1458 .lanai => 5,
1458 .loongarch32, .loongarch64 => 22,1459 .loongarch32, .loongarch64 => 22,
1460 .m68k => 14,
1459 .mips, .mipsel, .mips64, .mips64el => 30,1461 .mips, .mipsel, .mips64, .mips64el => 30,
1460 .or1k => 2,1462 .or1k => 2,
1461 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,1463 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
...@@ -1477,6 +1479,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1477,6 +1479,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
1477 .hexagon => 29,1479 .hexagon => 29,
1478 .lanai => 4,1480 .lanai => 4,
1479 .loongarch32, .loongarch64 => 3,1481 .loongarch32, .loongarch64 => 3,
1482 .m68k => 15,
1480 .mips, .mipsel, .mips64, .mips64el => 29,1483 .mips, .mipsel, .mips64, .mips64el => 29,
1481 .or1k => 1,1484 .or1k => 1,
1482 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,1485 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
lib/std/debug/SelfInfo/Elf.zig+6-3
...@@ -94,19 +94,21 @@ pub const can_unwind: bool = s: {...@@ -94,19 +94,21 @@ pub const can_unwind: bool = s: {
94 // Notably, we are yet to support unwinding on ARM. There, unwinding is not done through94 // Notably, we are yet to support unwinding on ARM. There, unwinding is not done through
95 // `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.95 // `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.
96 const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {96 const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {
97 // Not supported yet: arm, m68k97 // Not supported yet: arm
98 .haiku => &.{98 .haiku => &.{
99 .aarch64,99 .aarch64,
100 .m68k,
100 .riscv64,101 .riscv64,
101 .x86,102 .x86,
102 .x86_64,103 .x86_64,
103 },104 },
104 // Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, xtensa105 // Not supported yet: arc, arm/armeb/thumb/thumbeb, xtensa
105 .linux => &.{106 .linux => &.{
106 .aarch64,107 .aarch64,
107 .aarch64_be,108 .aarch64_be,
108 .csky,109 .csky,
109 .loongarch64,110 .loongarch64,
111 .m68k,
110 .mips,112 .mips,
111 .mipsel,113 .mipsel,
112 .mips64,114 .mips64,
...@@ -133,10 +135,11 @@ pub const can_unwind: bool = s: {...@@ -133,10 +135,11 @@ pub const can_unwind: bool = s: {
133 .riscv64,135 .riscv64,
134 .x86_64,136 .x86_64,
135 },137 },
136 // Not supported yet: arm/armeb, m68k, mips64/mips64el138 // Not supported yet: arm/armeb, mips64/mips64el
137 .netbsd => &.{139 .netbsd => &.{
138 .aarch64,140 .aarch64,
139 .aarch64_be,141 .aarch64_be,
142 .m68k,
140 .mips,143 .mips,
141 .mipsel,144 .mipsel,
142 .x86,145 .x86,
lib/std/debug/cpu_context.zig+40
...@@ -10,6 +10,7 @@ else switch (native_arch) {...@@ -10,6 +10,7 @@ else switch (native_arch) {
10 .hexagon => Hexagon,10 .hexagon => Hexagon,
11 .lanai => Lanai,11 .lanai => Lanai,
12 .loongarch32, .loongarch64 => LoongArch,12 .loongarch32, .loongarch64 => LoongArch,
13 .m68k => M68k,
13 .mips, .mipsel, .mips64, .mips64el => Mips,14 .mips, .mipsel, .mips64, .mips64el => Mips,
14 .or1k => Or1k,15 .or1k => Or1k,
15 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,16 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
...@@ -87,6 +88,11 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {...@@ -87,6 +88,11 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
87 .r = uc.mcontext.r,88 .r = uc.mcontext.r,
88 .pc = uc.mcontext.pc,89 .pc = uc.mcontext.pc,
89 },90 },
91 .m68k => .{
92 .d = uc.mcontext.d,
93 .a = uc.mcontext.a,
94 .pc = uc.mcontext.pc,
95 },
90 .powerpc, .powerpcle, .powerpc64, .powerpc64le => .{96 .powerpc, .powerpcle, .powerpc64, .powerpc64le => .{
91 .r = uc.mcontext.r,97 .r = uc.mcontext.r,
92 .pc = uc.mcontext.pc,98 .pc = uc.mcontext.pc,
...@@ -697,6 +703,40 @@ const LoongArch = extern struct {...@@ -697,6 +703,40 @@ const LoongArch = extern struct {
697 }703 }
698};704};
699705
706/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
707const M68k = extern struct {
708 /// The numbered data registers d0 - d7.
709 d: [8]u32,
710 /// The numbered address registers a0 - a7.
711 a: [8]u32,
712 pc: u32,
713
714 pub inline fn current() M68k {
715 var ctx: M68k = undefined;
716 asm volatile (
717 \\ movem.l %%d0 - %%a7, (%%a0)
718 \\ lea.l (%%pc), %%a1
719 \\ move.l %%a1, (%%a0, 64)
720 :
721 : [ctx] "{a0}" (&ctx),
722 : .{ .a1 = true, .memory = true });
723 return ctx;
724 }
725
726 pub fn dwarfRegisterBytes(ctx: *M68k, register_num: u16) DwarfRegisterError![]u8 {
727 switch (register_num) {
728 0...7 => return @ptrCast(&ctx.d[register_num]),
729 8...15 => return @ptrCast(&ctx.a[register_num - 8]),
730 26 => return @ptrCast(&ctx.pc),
731
732 16...23 => return error.UnsupportedRegister, // fp0 - fp7
733 24...25 => return error.UnsupportedRegister, // Return columns in GCC...?
734
735 else => return error.InvalidRegister,
736 }
737 }
738};
739
700/// This is an `extern struct` so that inline assembly in `current` can use field offsets.740/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
701const Mips = extern struct {741const Mips = extern struct {
702 /// The numbered general-purpose registers r0 - r31. r0 must be zero.742 /// The numbered general-purpose registers r0 - r31. r0 must be zero.