authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-10-28 23:42:47+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-11-02 10:44:14+01:00
logbaf60426d48adbd938406f07bbbd0dfdf012943b
treed91eeacf951e05e95b166f19e878eadee35df1b6
parent20cdfe9fb6e5f54623e170b59781001dcc7e1d75
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Rename amdgpu module to amdgcn.

This was an inconsistency left over from c825b567b26c475e058e074e5d22af006854fab6.

7 files changed, 2737 insertions(+), 2738 deletions(-)

CMakeLists.txt+1-1
...@@ -376,7 +376,7 @@ set(ZIG_STAGE2_SOURCES...@@ -376,7 +376,7 @@ set(ZIG_STAGE2_SOURCES
376 lib/std/Target.zig376 lib/std/Target.zig
377 lib/std/Target/Query.zig377 lib/std/Target/Query.zig
378 lib/std/Target/aarch64.zig378 lib/std/Target/aarch64.zig
379 lib/std/Target/amdgpu.zig379 lib/std/Target/amdgcn.zig
380 lib/std/Target/arm.zig380 lib/std/Target/arm.zig
381 lib/std/Target/avr.zig381 lib/std/Target/avr.zig
382 lib/std/Target/bpf.zig382 lib/std/Target/bpf.zig
lib/compiler_rt/atomics.zig+1-1
...@@ -42,7 +42,7 @@ const largest_atomic_size = switch (arch) {...@@ -42,7 +42,7 @@ const largest_atomic_size = switch (arch) {
42// Objects smaller than this threshold are implemented in terms of compare-exchange42// Objects smaller than this threshold are implemented in terms of compare-exchange
43// of a larger value.43// of a larger value.
44const smallest_atomic_fetch_exch_size = switch (arch) {44const smallest_atomic_fetch_exch_size = switch (arch) {
45 // On AMDGPU, there are no instructions for atomic operations other than load and store45 // On AMDGCN, there are no instructions for atomic operations other than load and store
46 // (as of LLVM 15), and so these need to be implemented in terms of atomic CAS.46 // (as of LLVM 15), and so these need to be implemented in terms of atomic CAS.
47 .amdgcn => @sizeOf(u32),47 .amdgcn => @sizeOf(u32),
48 else => @sizeOf(u8),48 else => @sizeOf(u8),
lib/std/Target.zig+5-6
...@@ -719,7 +719,7 @@ pub const Os = struct {...@@ -719,7 +719,7 @@ pub const Os = struct {
719719
720pub const aarch64 = @import("Target/aarch64.zig");720pub const aarch64 = @import("Target/aarch64.zig");
721pub const arc = @import("Target/arc.zig");721pub const arc = @import("Target/arc.zig");
722pub const amdgpu = @import("Target/amdgpu.zig");722pub const amdgcn = @import("Target/amdgcn.zig");
723pub const arm = @import("Target/arm.zig");723pub const arm = @import("Target/arm.zig");
724pub const avr = @import("Target/avr.zig");724pub const avr = @import("Target/avr.zig");
725pub const bpf = @import("Target/bpf.zig");725pub const bpf = @import("Target/bpf.zig");
...@@ -1591,7 +1591,6 @@ pub const Cpu = struct {...@@ -1591,7 +1591,6 @@ pub const Cpu = struct {
1591 .loongarch32, .loongarch64 => "loongarch",1591 .loongarch32, .loongarch64 => "loongarch",
1592 .mips, .mipsel, .mips64, .mips64el => "mips",1592 .mips, .mipsel, .mips64, .mips64el => "mips",
1593 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",1593 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1594 .amdgcn => "amdgpu",
1595 .riscv32, .riscv64 => "riscv",1594 .riscv32, .riscv64 => "riscv",
1596 .sparc, .sparc64 => "sparc",1595 .sparc, .sparc64 => "sparc",
1597 .s390x => "s390x",1596 .s390x => "s390x",
...@@ -1620,7 +1619,7 @@ pub const Cpu = struct {...@@ -1620,7 +1619,7 @@ pub const Cpu = struct {
1620 .mips, .mipsel, .mips64, .mips64el => &mips.all_features,1619 .mips, .mipsel, .mips64, .mips64el => &mips.all_features,
1621 .msp430 => &msp430.all_features,1620 .msp430 => &msp430.all_features,
1622 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,1621 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
1623 .amdgcn => &amdgpu.all_features,1622 .amdgcn => &amdgcn.all_features,
1624 .riscv32, .riscv64 => &riscv.all_features,1623 .riscv32, .riscv64 => &riscv.all_features,
1625 .sparc, .sparc64 => &sparc.all_features,1624 .sparc, .sparc64 => &sparc.all_features,
1626 .spirv, .spirv32, .spirv64 => &spirv.all_features,1625 .spirv, .spirv32, .spirv64 => &spirv.all_features,
...@@ -1652,7 +1651,7 @@ pub const Cpu = struct {...@@ -1652,7 +1651,7 @@ pub const Cpu = struct {
1652 .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),1651 .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
1653 .msp430 => comptime allCpusFromDecls(msp430.cpu),1652 .msp430 => comptime allCpusFromDecls(msp430.cpu),
1654 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),1653 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1655 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),1654 .amdgcn => comptime allCpusFromDecls(amdgcn.cpu),
1656 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),1655 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1657 .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),1656 .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
1658 .spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),1657 .spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
...@@ -1890,7 +1889,7 @@ pub const Cpu = struct {...@@ -1890,7 +1889,7 @@ pub const Cpu = struct {
1890 };1889 };
1891 };1890 };
1892 return switch (arch) {1891 return switch (arch) {
1893 .amdgcn => &amdgpu.cpu.gfx600,1892 .amdgcn => &amdgcn.cpu.gfx600,
1894 .arc => &arc.cpu.generic,1893 .arc => &arc.cpu.generic,
1895 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,1894 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
1896 .aarch64, .aarch64_be => &aarch64.cpu.generic,1895 .aarch64, .aarch64_be => &aarch64.cpu.generic,
...@@ -1939,7 +1938,7 @@ pub const Cpu = struct {...@@ -1939,7 +1938,7 @@ pub const Cpu = struct {
1939 /// `Os.Tag.freestanding`.1938 /// `Os.Tag.freestanding`.
1940 pub fn baseline(arch: Arch, os: Os) *const Model {1939 pub fn baseline(arch: Arch, os: Os) *const Model {
1941 return switch (arch) {1940 return switch (arch) {
1942 .amdgcn => &amdgpu.cpu.gfx906,1941 .amdgcn => &amdgcn.cpu.gfx906,
1943 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,1942 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
1944 .aarch64 => switch (os.tag) {1943 .aarch64 => switch (os.tag) {
1945 .bridgeos, .driverkit, .macos => &aarch64.cpu.apple_m1,1944 .bridgeos, .driverkit, .macos => &aarch64.cpu.apple_m1,
lib/std/Target/amdgcn.zig created+2728
...@@ -0,0 +1,2728 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"16_bit_insts",
9 a16,
10 add_no_carry_insts,
11 agent_scope_fine_grained_remote_memory_atomics,
12 allocate1_5xvgprs,
13 aperture_regs,
14 architected_flat_scratch,
15 architected_sgprs,
16 atomic_buffer_global_pk_add_f16_insts,
17 atomic_buffer_global_pk_add_f16_no_rtn_insts,
18 atomic_buffer_pk_add_bf16_inst,
19 atomic_csub_no_rtn_insts,
20 atomic_ds_pk_add_16_insts,
21 atomic_fadd_no_rtn_insts,
22 atomic_fadd_rtn_insts,
23 atomic_flat_pk_add_16_insts,
24 atomic_fmin_fmax_flat_f32,
25 atomic_fmin_fmax_flat_f64,
26 atomic_fmin_fmax_global_f32,
27 atomic_fmin_fmax_global_f64,
28 atomic_global_pk_add_bf16_inst,
29 auto_waitcnt_before_barrier,
30 back_off_barrier,
31 ci_insts,
32 cumode,
33 default_component_broadcast,
34 default_component_zero,
35 dl_insts,
36 dot10_insts,
37 dot11_insts,
38 dot1_insts,
39 dot2_insts,
40 dot3_insts,
41 dot4_insts,
42 dot5_insts,
43 dot6_insts,
44 dot7_insts,
45 dot8_insts,
46 dot9_insts,
47 dpp,
48 dpp8,
49 dpp_64bit,
50 dpp_src1_sgpr,
51 ds128,
52 ds_src2_insts,
53 extended_image_insts,
54 fast_denormal_f32,
55 fast_fmaf,
56 flat_address_space,
57 flat_atomic_fadd_f32_inst,
58 flat_buffer_global_fadd_f64_inst,
59 flat_for_global,
60 flat_global_insts,
61 flat_inst_offsets,
62 flat_scratch,
63 flat_scratch_insts,
64 flat_segment_offset_bug,
65 fma_mix_insts,
66 fmacf64_inst,
67 fmaf,
68 force_store_sc0_sc1,
69 fp64,
70 fp8_conversion_insts,
71 fp8_insts,
72 full_rate_64_ops,
73 g16,
74 gcn3_encoding,
75 gds,
76 get_wave_id_inst,
77 gfx10,
78 gfx10_3_insts,
79 gfx10_a_encoding,
80 gfx10_b_encoding,
81 gfx10_insts,
82 gfx11,
83 gfx11_insts,
84 gfx12,
85 gfx12_insts,
86 gfx7_gfx8_gfx9_insts,
87 gfx8_insts,
88 gfx9,
89 gfx90a_insts,
90 gfx940_insts,
91 gfx9_insts,
92 gws,
93 half_rate_64_ops,
94 image_gather4_d16_bug,
95 image_insts,
96 image_store_d16_bug,
97 inst_fwd_prefetch_bug,
98 int_clamp_insts,
99 inv_2pi_inline_imm,
100 kernarg_preload,
101 lds_branch_vmem_war_hazard,
102 lds_misaligned_bug,
103 ldsbankcount16,
104 ldsbankcount32,
105 load_store_opt,
106 localmemorysize32768,
107 localmemorysize65536,
108 mad_intra_fwd_bug,
109 mad_mac_f32_insts,
110 mad_mix_insts,
111 mai_insts,
112 max_hard_clause_length_32,
113 max_hard_clause_length_63,
114 max_private_element_size_16,
115 max_private_element_size_4,
116 max_private_element_size_8,
117 memory_atomic_fadd_f32_denormal_support,
118 mfma_inline_literal_bug,
119 mimg_r128,
120 movrel,
121 msaa_load_dst_sel_bug,
122 negative_scratch_offset_bug,
123 negative_unaligned_scratch_offset_bug,
124 no_data_dep_hazard,
125 no_sdst_cmpx,
126 nsa_clause_bug,
127 nsa_encoding,
128 nsa_to_vmem_bug,
129 offset_3f_bug,
130 packed_fp32_ops,
131 packed_tid,
132 partial_nsa_encoding,
133 pk_fmac_f16_inst,
134 precise_memory,
135 priv_enabled_trap2_nop_bug,
136 promote_alloca,
137 prt_strict_null,
138 pseudo_scalar_trans,
139 r128_a16,
140 real_true16,
141 required_export_priority,
142 requires_cov6,
143 restricted_soffset,
144 s_memrealtime,
145 s_memtime_inst,
146 salu_float,
147 scalar_atomics,
148 scalar_dwordx3_loads,
149 scalar_flat_scratch_insts,
150 scalar_stores,
151 sdwa,
152 sdwa_mav,
153 sdwa_omod,
154 sdwa_out_mods_vopc,
155 sdwa_scalar,
156 sdwa_sdst,
157 sea_islands,
158 sgpr_init_bug,
159 shader_cycles_hi_lo_registers,
160 shader_cycles_register,
161 si_scheduler,
162 smem_to_vector_write_hazard,
163 southern_islands,
164 sramecc,
165 sramecc_support,
166 tgsplit,
167 trap_handler,
168 trig_reduced_range,
169 true16,
170 unaligned_access_mode,
171 unaligned_buffer_access,
172 unaligned_ds_access,
173 unaligned_scratch_access,
174 unpacked_d16_vmem,
175 unsafe_ds_offset_folding,
176 user_sgpr_init16_bug,
177 valu_trans_use_hazard,
178 vcmpx_exec_war_hazard,
179 vcmpx_permlane_hazard,
180 vgpr_index_mode,
181 vgpr_singleuse_hint,
182 vmem_to_scalar_write_hazard,
183 vmem_write_vgpr_in_order,
184 volcanic_islands,
185 vop3_literal,
186 vop3p,
187 vopd,
188 vscnt,
189 wavefrontsize16,
190 wavefrontsize32,
191 wavefrontsize64,
192 xnack,
193 xnack_support,
194};
195
196pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
197pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
198pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
199pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
200
201pub const all_features = blk: {
202 const len = @typeInfo(Feature).@"enum".fields.len;
203 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
204 var result: [len]CpuFeature = undefined;
205 result[@intFromEnum(Feature.@"16_bit_insts")] = .{
206 .llvm_name = "16-bit-insts",
207 .description = "Has i16/f16 instructions",
208 .dependencies = featureSet(&[_]Feature{}),
209 };
210 result[@intFromEnum(Feature.a16)] = .{
211 .llvm_name = "a16",
212 .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
213 .dependencies = featureSet(&[_]Feature{}),
214 };
215 result[@intFromEnum(Feature.add_no_carry_insts)] = .{
216 .llvm_name = "add-no-carry-insts",
217 .description = "Have VALU add/sub instructions without carry out",
218 .dependencies = featureSet(&[_]Feature{}),
219 };
220 result[@intFromEnum(Feature.agent_scope_fine_grained_remote_memory_atomics)] = .{
221 .llvm_name = "agent-scope-fine-grained-remote-memory-atomics",
222 .description = "Agent (device) scoped atomic operations, excluding those directly supported by PCIe (i.e. integer atomic add, exchange, and compare-and-swap), are functional for allocations in host or peer device memory.",
223 .dependencies = featureSet(&[_]Feature{}),
224 };
225 result[@intFromEnum(Feature.allocate1_5xvgprs)] = .{
226 .llvm_name = "allocate1_5xvgprs",
227 .description = "Has 50% more physical VGPRs and 50% larger allocation granule",
228 .dependencies = featureSet(&[_]Feature{}),
229 };
230 result[@intFromEnum(Feature.aperture_regs)] = .{
231 .llvm_name = "aperture-regs",
232 .description = "Has Memory Aperture Base and Size Registers",
233 .dependencies = featureSet(&[_]Feature{}),
234 };
235 result[@intFromEnum(Feature.architected_flat_scratch)] = .{
236 .llvm_name = "architected-flat-scratch",
237 .description = "Flat Scratch register is a readonly SPI initialized architected register",
238 .dependencies = featureSet(&[_]Feature{}),
239 };
240 result[@intFromEnum(Feature.architected_sgprs)] = .{
241 .llvm_name = "architected-sgprs",
242 .description = "Enable the architected SGPRs",
243 .dependencies = featureSet(&[_]Feature{}),
244 };
245 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
246 .llvm_name = "atomic-buffer-global-pk-add-f16-insts",
247 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
248 .dependencies = featureSet(&[_]Feature{
249 .flat_global_insts,
250 }),
251 };
252 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_no_rtn_insts)] = .{
253 .llvm_name = "atomic-buffer-global-pk-add-f16-no-rtn-insts",
254 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
255 .dependencies = featureSet(&[_]Feature{
256 .flat_global_insts,
257 }),
258 };
259 result[@intFromEnum(Feature.atomic_buffer_pk_add_bf16_inst)] = .{
260 .llvm_name = "atomic-buffer-pk-add-bf16-inst",
261 .description = "Has buffer_atomic_pk_add_bf16 instruction",
262 .dependencies = featureSet(&[_]Feature{}),
263 };
264 result[@intFromEnum(Feature.atomic_csub_no_rtn_insts)] = .{
265 .llvm_name = "atomic-csub-no-rtn-insts",
266 .description = "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value",
267 .dependencies = featureSet(&[_]Feature{}),
268 };
269 result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{
270 .llvm_name = "atomic-ds-pk-add-16-insts",
271 .description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions",
272 .dependencies = featureSet(&[_]Feature{}),
273 };
274 result[@intFromEnum(Feature.atomic_fadd_no_rtn_insts)] = .{
275 .llvm_name = "atomic-fadd-no-rtn-insts",
276 .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value",
277 .dependencies = featureSet(&[_]Feature{
278 .flat_global_insts,
279 }),
280 };
281 result[@intFromEnum(Feature.atomic_fadd_rtn_insts)] = .{
282 .llvm_name = "atomic-fadd-rtn-insts",
283 .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that return original value",
284 .dependencies = featureSet(&[_]Feature{
285 .flat_global_insts,
286 }),
287 };
288 result[@intFromEnum(Feature.atomic_flat_pk_add_16_insts)] = .{
289 .llvm_name = "atomic-flat-pk-add-16-insts",
290 .description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions",
291 .dependencies = featureSet(&[_]Feature{}),
292 };
293 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{
294 .llvm_name = "atomic-fmin-fmax-flat-f32",
295 .description = "Has flat memory instructions for atomicrmw fmin/fmax for float",
296 .dependencies = featureSet(&[_]Feature{}),
297 };
298 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{
299 .llvm_name = "atomic-fmin-fmax-flat-f64",
300 .description = "Has flat memory instructions for atomicrmw fmin/fmax for double",
301 .dependencies = featureSet(&[_]Feature{}),
302 };
303 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{
304 .llvm_name = "atomic-fmin-fmax-global-f32",
305 .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float",
306 .dependencies = featureSet(&[_]Feature{}),
307 };
308 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f64)] = .{
309 .llvm_name = "atomic-fmin-fmax-global-f64",
310 .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float",
311 .dependencies = featureSet(&[_]Feature{}),
312 };
313 result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{
314 .llvm_name = "atomic-global-pk-add-bf16-inst",
315 .description = "Has global_atomic_pk_add_bf16 instruction",
316 .dependencies = featureSet(&[_]Feature{
317 .flat_global_insts,
318 }),
319 };
320 result[@intFromEnum(Feature.auto_waitcnt_before_barrier)] = .{
321 .llvm_name = "auto-waitcnt-before-barrier",
322 .description = "Hardware automatically inserts waitcnt before barrier",
323 .dependencies = featureSet(&[_]Feature{}),
324 };
325 result[@intFromEnum(Feature.back_off_barrier)] = .{
326 .llvm_name = "back-off-barrier",
327 .description = "Hardware supports backing off s_barrier if an exception occurs",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
330 result[@intFromEnum(Feature.ci_insts)] = .{
331 .llvm_name = "ci-insts",
332 .description = "Additional instructions for CI+",
333 .dependencies = featureSet(&[_]Feature{}),
334 };
335 result[@intFromEnum(Feature.cumode)] = .{
336 .llvm_name = "cumode",
337 .description = "Enable CU wavefront execution mode",
338 .dependencies = featureSet(&[_]Feature{}),
339 };
340 result[@intFromEnum(Feature.default_component_broadcast)] = .{
341 .llvm_name = "default-component-broadcast",
342 .description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",
343 .dependencies = featureSet(&[_]Feature{}),
344 };
345 result[@intFromEnum(Feature.default_component_zero)] = .{
346 .llvm_name = "default-component-zero",
347 .description = "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)",
348 .dependencies = featureSet(&[_]Feature{}),
349 };
350 result[@intFromEnum(Feature.dl_insts)] = .{
351 .llvm_name = "dl-insts",
352 .description = "Has v_fmac_f32 and v_xnor_b32 instructions",
353 .dependencies = featureSet(&[_]Feature{}),
354 };
355 result[@intFromEnum(Feature.dot10_insts)] = .{
356 .llvm_name = "dot10-insts",
357 .description = "Has v_dot2_f32_f16 instruction",
358 .dependencies = featureSet(&[_]Feature{}),
359 };
360 result[@intFromEnum(Feature.dot11_insts)] = .{
361 .llvm_name = "dot11-insts",
362 .description = "Has v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8, v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8 instructions",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@intFromEnum(Feature.dot1_insts)] = .{
366 .llvm_name = "dot1-insts",
367 .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
368 .dependencies = featureSet(&[_]Feature{}),
369 };
370 result[@intFromEnum(Feature.dot2_insts)] = .{
371 .llvm_name = "dot2-insts",
372 .description = "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions",
373 .dependencies = featureSet(&[_]Feature{}),
374 };
375 result[@intFromEnum(Feature.dot3_insts)] = .{
376 .llvm_name = "dot3-insts",
377 .description = "Has v_dot8c_i32_i4 instruction",
378 .dependencies = featureSet(&[_]Feature{}),
379 };
380 result[@intFromEnum(Feature.dot4_insts)] = .{
381 .llvm_name = "dot4-insts",
382 .description = "Has v_dot2c_i32_i16 instruction",
383 .dependencies = featureSet(&[_]Feature{}),
384 };
385 result[@intFromEnum(Feature.dot5_insts)] = .{
386 .llvm_name = "dot5-insts",
387 .description = "Has v_dot2c_f32_f16 instruction",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@intFromEnum(Feature.dot6_insts)] = .{
391 .llvm_name = "dot6-insts",
392 .description = "Has v_dot4c_i32_i8 instruction",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
395 result[@intFromEnum(Feature.dot7_insts)] = .{
396 .llvm_name = "dot7-insts",
397 .description = "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
400 result[@intFromEnum(Feature.dot8_insts)] = .{
401 .llvm_name = "dot8-insts",
402 .description = "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions",
403 .dependencies = featureSet(&[_]Feature{}),
404 };
405 result[@intFromEnum(Feature.dot9_insts)] = .{
406 .llvm_name = "dot9-insts",
407 .description = "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@intFromEnum(Feature.dpp)] = .{
411 .llvm_name = "dpp",
412 .description = "Support DPP (Data Parallel Primitives) extension",
413 .dependencies = featureSet(&[_]Feature{}),
414 };
415 result[@intFromEnum(Feature.dpp8)] = .{
416 .llvm_name = "dpp8",
417 .description = "Support DPP8 (Data Parallel Primitives) extension",
418 .dependencies = featureSet(&[_]Feature{}),
419 };
420 result[@intFromEnum(Feature.dpp_64bit)] = .{
421 .llvm_name = "dpp-64bit",
422 .description = "Support DPP (Data Parallel Primitives) extension in DP ALU",
423 .dependencies = featureSet(&[_]Feature{}),
424 };
425 result[@intFromEnum(Feature.dpp_src1_sgpr)] = .{
426 .llvm_name = "dpp-src1-sgpr",
427 .description = "Support SGPR for Src1 of DPP instructions",
428 .dependencies = featureSet(&[_]Feature{}),
429 };
430 result[@intFromEnum(Feature.ds128)] = .{
431 .llvm_name = "enable-ds128",
432 .description = "Use ds_{read|write}_b128",
433 .dependencies = featureSet(&[_]Feature{}),
434 };
435 result[@intFromEnum(Feature.ds_src2_insts)] = .{
436 .llvm_name = "ds-src2-insts",
437 .description = "Has ds_*_src2 instructions",
438 .dependencies = featureSet(&[_]Feature{}),
439 };
440 result[@intFromEnum(Feature.extended_image_insts)] = .{
441 .llvm_name = "extended-image-insts",
442 .description = "Support mips != 0, lod != 0, gather4, and get_lod",
443 .dependencies = featureSet(&[_]Feature{}),
444 };
445 result[@intFromEnum(Feature.fast_denormal_f32)] = .{
446 .llvm_name = "fast-denormal-f32",
447 .description = "Enabling denormals does not cause f32 instructions to run at f64 rates",
448 .dependencies = featureSet(&[_]Feature{}),
449 };
450 result[@intFromEnum(Feature.fast_fmaf)] = .{
451 .llvm_name = "fast-fmaf",
452 .description = "Assuming f32 fma is at least as fast as mul + add",
453 .dependencies = featureSet(&[_]Feature{}),
454 };
455 result[@intFromEnum(Feature.flat_address_space)] = .{
456 .llvm_name = "flat-address-space",
457 .description = "Support flat address space",
458 .dependencies = featureSet(&[_]Feature{}),
459 };
460 result[@intFromEnum(Feature.flat_atomic_fadd_f32_inst)] = .{
461 .llvm_name = "flat-atomic-fadd-f32-inst",
462 .description = "Has flat_atomic_add_f32 instruction",
463 .dependencies = featureSet(&[_]Feature{}),
464 };
465 result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{
466 .llvm_name = "flat-buffer-global-fadd-f64-inst",
467 .description = "Has flat, buffer, and global instructions for f64 atomic fadd",
468 .dependencies = featureSet(&[_]Feature{}),
469 };
470 result[@intFromEnum(Feature.flat_for_global)] = .{
471 .llvm_name = "flat-for-global",
472 .description = "Force to generate flat instruction for global",
473 .dependencies = featureSet(&[_]Feature{}),
474 };
475 result[@intFromEnum(Feature.flat_global_insts)] = .{
476 .llvm_name = "flat-global-insts",
477 .description = "Have global_* flat memory instructions",
478 .dependencies = featureSet(&[_]Feature{}),
479 };
480 result[@intFromEnum(Feature.flat_inst_offsets)] = .{
481 .llvm_name = "flat-inst-offsets",
482 .description = "Flat instructions have immediate offset addressing mode",
483 .dependencies = featureSet(&[_]Feature{}),
484 };
485 result[@intFromEnum(Feature.flat_scratch)] = .{
486 .llvm_name = "enable-flat-scratch",
487 .description = "Use scratch_* flat memory instructions to access scratch",
488 .dependencies = featureSet(&[_]Feature{}),
489 };
490 result[@intFromEnum(Feature.flat_scratch_insts)] = .{
491 .llvm_name = "flat-scratch-insts",
492 .description = "Have scratch_* flat memory instructions",
493 .dependencies = featureSet(&[_]Feature{}),
494 };
495 result[@intFromEnum(Feature.flat_segment_offset_bug)] = .{
496 .llvm_name = "flat-segment-offset-bug",
497 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
498 .dependencies = featureSet(&[_]Feature{}),
499 };
500 result[@intFromEnum(Feature.fma_mix_insts)] = .{
501 .llvm_name = "fma-mix-insts",
502 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
503 .dependencies = featureSet(&[_]Feature{}),
504 };
505 result[@intFromEnum(Feature.fmacf64_inst)] = .{
506 .llvm_name = "fmacf64-inst",
507 .description = "Has v_fmac_f64 instruction",
508 .dependencies = featureSet(&[_]Feature{}),
509 };
510 result[@intFromEnum(Feature.fmaf)] = .{
511 .llvm_name = "fmaf",
512 .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
513 .dependencies = featureSet(&[_]Feature{}),
514 };
515 result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
516 .llvm_name = "force-store-sc0-sc1",
517 .description = "Has SC0 and SC1 on stores",
518 .dependencies = featureSet(&[_]Feature{}),
519 };
520 result[@intFromEnum(Feature.fp64)] = .{
521 .llvm_name = "fp64",
522 .description = "Enable double precision operations",
523 .dependencies = featureSet(&[_]Feature{}),
524 };
525 result[@intFromEnum(Feature.fp8_conversion_insts)] = .{
526 .llvm_name = "fp8-conversion-insts",
527 .description = "Has fp8 and bf8 conversion instructions",
528 .dependencies = featureSet(&[_]Feature{}),
529 };
530 result[@intFromEnum(Feature.fp8_insts)] = .{
531 .llvm_name = "fp8-insts",
532 .description = "Has fp8 and bf8 instructions",
533 .dependencies = featureSet(&[_]Feature{}),
534 };
535 result[@intFromEnum(Feature.full_rate_64_ops)] = .{
536 .llvm_name = "full-rate-64-ops",
537 .description = "Most fp64 instructions are full rate",
538 .dependencies = featureSet(&[_]Feature{}),
539 };
540 result[@intFromEnum(Feature.g16)] = .{
541 .llvm_name = "g16",
542 .description = "Support G16 for 16-bit gradient image operands",
543 .dependencies = featureSet(&[_]Feature{}),
544 };
545 result[@intFromEnum(Feature.gcn3_encoding)] = .{
546 .llvm_name = "gcn3-encoding",
547 .description = "Encoding format for VI",
548 .dependencies = featureSet(&[_]Feature{}),
549 };
550 result[@intFromEnum(Feature.gds)] = .{
551 .llvm_name = "gds",
552 .description = "Has Global Data Share",
553 .dependencies = featureSet(&[_]Feature{}),
554 };
555 result[@intFromEnum(Feature.get_wave_id_inst)] = .{
556 .llvm_name = "get-wave-id-inst",
557 .description = "Has s_get_waveid_in_workgroup instruction",
558 .dependencies = featureSet(&[_]Feature{}),
559 };
560 result[@intFromEnum(Feature.gfx10)] = .{
561 .llvm_name = "gfx10",
562 .description = "GFX10 GPU generation",
563 .dependencies = featureSet(&[_]Feature{
564 .@"16_bit_insts",
565 .a16,
566 .add_no_carry_insts,
567 .aperture_regs,
568 .atomic_fmin_fmax_flat_f32,
569 .atomic_fmin_fmax_flat_f64,
570 .atomic_fmin_fmax_global_f32,
571 .atomic_fmin_fmax_global_f64,
572 .ci_insts,
573 .default_component_zero,
574 .dpp,
575 .dpp8,
576 .extended_image_insts,
577 .fast_denormal_f32,
578 .fast_fmaf,
579 .flat_address_space,
580 .flat_global_insts,
581 .flat_inst_offsets,
582 .flat_scratch_insts,
583 .fma_mix_insts,
584 .fp64,
585 .g16,
586 .gds,
587 .gfx10_insts,
588 .gfx8_insts,
589 .gfx9_insts,
590 .gws,
591 .image_insts,
592 .int_clamp_insts,
593 .inv_2pi_inline_imm,
594 .localmemorysize65536,
595 .max_hard_clause_length_63,
596 .mimg_r128,
597 .movrel,
598 .no_data_dep_hazard,
599 .no_sdst_cmpx,
600 .pk_fmac_f16_inst,
601 .s_memrealtime,
602 .s_memtime_inst,
603 .sdwa,
604 .sdwa_omod,
605 .sdwa_scalar,
606 .sdwa_sdst,
607 .unaligned_buffer_access,
608 .unaligned_ds_access,
609 .vmem_write_vgpr_in_order,
610 .vop3_literal,
611 .vop3p,
612 .vscnt,
613 }),
614 };
615 result[@intFromEnum(Feature.gfx10_3_insts)] = .{
616 .llvm_name = "gfx10-3-insts",
617 .description = "Additional instructions for GFX10.3",
618 .dependencies = featureSet(&[_]Feature{}),
619 };
620 result[@intFromEnum(Feature.gfx10_a_encoding)] = .{
621 .llvm_name = "gfx10_a-encoding",
622 .description = "Has BVH ray tracing instructions",
623 .dependencies = featureSet(&[_]Feature{}),
624 };
625 result[@intFromEnum(Feature.gfx10_b_encoding)] = .{
626 .llvm_name = "gfx10_b-encoding",
627 .description = "Encoding format GFX10_B",
628 .dependencies = featureSet(&[_]Feature{}),
629 };
630 result[@intFromEnum(Feature.gfx10_insts)] = .{
631 .llvm_name = "gfx10-insts",
632 .description = "Additional instructions for GFX10+",
633 .dependencies = featureSet(&[_]Feature{}),
634 };
635 result[@intFromEnum(Feature.gfx11)] = .{
636 .llvm_name = "gfx11",
637 .description = "GFX11 GPU generation",
638 .dependencies = featureSet(&[_]Feature{
639 .@"16_bit_insts",
640 .a16,
641 .add_no_carry_insts,
642 .aperture_regs,
643 .atomic_fmin_fmax_flat_f32,
644 .atomic_fmin_fmax_global_f32,
645 .ci_insts,
646 .default_component_zero,
647 .dpp,
648 .dpp8,
649 .extended_image_insts,
650 .fast_denormal_f32,
651 .fast_fmaf,
652 .flat_address_space,
653 .flat_global_insts,
654 .flat_inst_offsets,
655 .flat_scratch_insts,
656 .fma_mix_insts,
657 .fp64,
658 .g16,
659 .gds,
660 .gfx10_3_insts,
661 .gfx10_a_encoding,
662 .gfx10_b_encoding,
663 .gfx10_insts,
664 .gfx11_insts,
665 .gfx8_insts,
666 .gfx9_insts,
667 .gws,
668 .int_clamp_insts,
669 .inv_2pi_inline_imm,
670 .localmemorysize65536,
671 .max_hard_clause_length_32,
672 .mimg_r128,
673 .movrel,
674 .no_data_dep_hazard,
675 .no_sdst_cmpx,
676 .pk_fmac_f16_inst,
677 .true16,
678 .unaligned_buffer_access,
679 .unaligned_ds_access,
680 .vmem_write_vgpr_in_order,
681 .vop3_literal,
682 .vop3p,
683 .vopd,
684 .vscnt,
685 }),
686 };
687 result[@intFromEnum(Feature.gfx11_insts)] = .{
688 .llvm_name = "gfx11-insts",
689 .description = "Additional instructions for GFX11+",
690 .dependencies = featureSet(&[_]Feature{}),
691 };
692 result[@intFromEnum(Feature.gfx12)] = .{
693 .llvm_name = "gfx12",
694 .description = "GFX12 GPU generation",
695 .dependencies = featureSet(&[_]Feature{
696 .@"16_bit_insts",
697 .a16,
698 .add_no_carry_insts,
699 .agent_scope_fine_grained_remote_memory_atomics,
700 .aperture_regs,
701 .atomic_fmin_fmax_flat_f32,
702 .atomic_fmin_fmax_global_f32,
703 .ci_insts,
704 .default_component_broadcast,
705 .dpp,
706 .dpp8,
707 .fast_denormal_f32,
708 .fast_fmaf,
709 .flat_address_space,
710 .flat_global_insts,
711 .flat_inst_offsets,
712 .flat_scratch_insts,
713 .fma_mix_insts,
714 .fp64,
715 .g16,
716 .gfx10_3_insts,
717 .gfx10_a_encoding,
718 .gfx10_b_encoding,
719 .gfx10_insts,
720 .gfx11_insts,
721 .gfx12_insts,
722 .gfx8_insts,
723 .gfx9_insts,
724 .int_clamp_insts,
725 .inv_2pi_inline_imm,
726 .localmemorysize65536,
727 .max_hard_clause_length_32,
728 .mimg_r128,
729 .movrel,
730 .no_data_dep_hazard,
731 .no_sdst_cmpx,
732 .pk_fmac_f16_inst,
733 .true16,
734 .unaligned_buffer_access,
735 .unaligned_ds_access,
736 .vop3_literal,
737 .vop3p,
738 .vopd,
739 .vscnt,
740 }),
741 };
742 result[@intFromEnum(Feature.gfx12_insts)] = .{
743 .llvm_name = "gfx12-insts",
744 .description = "Additional instructions for GFX12+",
745 .dependencies = featureSet(&[_]Feature{}),
746 };
747 result[@intFromEnum(Feature.gfx7_gfx8_gfx9_insts)] = .{
748 .llvm_name = "gfx7-gfx8-gfx9-insts",
749 .description = "Instructions shared in GFX7, GFX8, GFX9",
750 .dependencies = featureSet(&[_]Feature{}),
751 };
752 result[@intFromEnum(Feature.gfx8_insts)] = .{
753 .llvm_name = "gfx8-insts",
754 .description = "Additional instructions for GFX8+",
755 .dependencies = featureSet(&[_]Feature{}),
756 };
757 result[@intFromEnum(Feature.gfx9)] = .{
758 .llvm_name = "gfx9",
759 .description = "GFX9 GPU generation",
760 .dependencies = featureSet(&[_]Feature{
761 .@"16_bit_insts",
762 .a16,
763 .add_no_carry_insts,
764 .aperture_regs,
765 .ci_insts,
766 .default_component_zero,
767 .dpp,
768 .fast_denormal_f32,
769 .fast_fmaf,
770 .flat_address_space,
771 .flat_global_insts,
772 .flat_inst_offsets,
773 .flat_scratch_insts,
774 .fp64,
775 .gcn3_encoding,
776 .gfx7_gfx8_gfx9_insts,
777 .gfx8_insts,
778 .gfx9_insts,
779 .gws,
780 .int_clamp_insts,
781 .inv_2pi_inline_imm,
782 .localmemorysize65536,
783 .negative_scratch_offset_bug,
784 .r128_a16,
785 .s_memrealtime,
786 .s_memtime_inst,
787 .scalar_atomics,
788 .scalar_flat_scratch_insts,
789 .scalar_stores,
790 .sdwa,
791 .sdwa_omod,
792 .sdwa_scalar,
793 .sdwa_sdst,
794 .unaligned_buffer_access,
795 .unaligned_ds_access,
796 .vgpr_index_mode,
797 .vmem_write_vgpr_in_order,
798 .vop3p,
799 .wavefrontsize64,
800 .xnack_support,
801 }),
802 };
803 result[@intFromEnum(Feature.gfx90a_insts)] = .{
804 .llvm_name = "gfx90a-insts",
805 .description = "Additional instructions for GFX90A+",
806 .dependencies = featureSet(&[_]Feature{}),
807 };
808 result[@intFromEnum(Feature.gfx940_insts)] = .{
809 .llvm_name = "gfx940-insts",
810 .description = "Additional instructions for GFX940+",
811 .dependencies = featureSet(&[_]Feature{}),
812 };
813 result[@intFromEnum(Feature.gfx9_insts)] = .{
814 .llvm_name = "gfx9-insts",
815 .description = "Additional instructions for GFX9+",
816 .dependencies = featureSet(&[_]Feature{}),
817 };
818 result[@intFromEnum(Feature.gws)] = .{
819 .llvm_name = "gws",
820 .description = "Has Global Wave Sync",
821 .dependencies = featureSet(&[_]Feature{}),
822 };
823 result[@intFromEnum(Feature.half_rate_64_ops)] = .{
824 .llvm_name = "half-rate-64-ops",
825 .description = "Most fp64 instructions are half rate instead of quarter",
826 .dependencies = featureSet(&[_]Feature{}),
827 };
828 result[@intFromEnum(Feature.image_gather4_d16_bug)] = .{
829 .llvm_name = "image-gather4-d16-bug",
830 .description = "Image Gather4 D16 hardware bug",
831 .dependencies = featureSet(&[_]Feature{}),
832 };
833 result[@intFromEnum(Feature.image_insts)] = .{
834 .llvm_name = "image-insts",
835 .description = "Support image instructions",
836 .dependencies = featureSet(&[_]Feature{}),
837 };
838 result[@intFromEnum(Feature.image_store_d16_bug)] = .{
839 .llvm_name = "image-store-d16-bug",
840 .description = "Image Store D16 hardware bug",
841 .dependencies = featureSet(&[_]Feature{}),
842 };
843 result[@intFromEnum(Feature.inst_fwd_prefetch_bug)] = .{
844 .llvm_name = "inst-fwd-prefetch-bug",
845 .description = "S_INST_PREFETCH instruction causes shader to hang",
846 .dependencies = featureSet(&[_]Feature{}),
847 };
848 result[@intFromEnum(Feature.int_clamp_insts)] = .{
849 .llvm_name = "int-clamp-insts",
850 .description = "Support clamp for integer destination",
851 .dependencies = featureSet(&[_]Feature{}),
852 };
853 result[@intFromEnum(Feature.inv_2pi_inline_imm)] = .{
854 .llvm_name = "inv-2pi-inline-imm",
855 .description = "Has 1 / (2 * pi) as inline immediate",
856 .dependencies = featureSet(&[_]Feature{}),
857 };
858 result[@intFromEnum(Feature.kernarg_preload)] = .{
859 .llvm_name = "kernarg-preload",
860 .description = "Hardware supports preloading of kernel arguments in user SGPRs.",
861 .dependencies = featureSet(&[_]Feature{}),
862 };
863 result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{
864 .llvm_name = "lds-branch-vmem-war-hazard",
865 .description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
866 .dependencies = featureSet(&[_]Feature{}),
867 };
868 result[@intFromEnum(Feature.lds_misaligned_bug)] = .{
869 .llvm_name = "lds-misaligned-bug",
870 .description = "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode",
871 .dependencies = featureSet(&[_]Feature{}),
872 };
873 result[@intFromEnum(Feature.ldsbankcount16)] = .{
874 .llvm_name = "ldsbankcount16",
875 .description = "The number of LDS banks per compute unit.",
876 .dependencies = featureSet(&[_]Feature{}),
877 };
878 result[@intFromEnum(Feature.ldsbankcount32)] = .{
879 .llvm_name = "ldsbankcount32",
880 .description = "The number of LDS banks per compute unit.",
881 .dependencies = featureSet(&[_]Feature{}),
882 };
883 result[@intFromEnum(Feature.load_store_opt)] = .{
884 .llvm_name = "load-store-opt",
885 .description = "Enable SI load/store optimizer pass",
886 .dependencies = featureSet(&[_]Feature{}),
887 };
888 result[@intFromEnum(Feature.localmemorysize32768)] = .{
889 .llvm_name = "localmemorysize32768",
890 .description = "The size of local memory in bytes",
891 .dependencies = featureSet(&[_]Feature{}),
892 };
893 result[@intFromEnum(Feature.localmemorysize65536)] = .{
894 .llvm_name = "localmemorysize65536",
895 .description = "The size of local memory in bytes",
896 .dependencies = featureSet(&[_]Feature{}),
897 };
898 result[@intFromEnum(Feature.mad_intra_fwd_bug)] = .{
899 .llvm_name = "mad-intra-fwd-bug",
900 .description = "MAD_U64/I64 intra instruction forwarding bug",
901 .dependencies = featureSet(&[_]Feature{}),
902 };
903 result[@intFromEnum(Feature.mad_mac_f32_insts)] = .{
904 .llvm_name = "mad-mac-f32-insts",
905 .description = "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions",
906 .dependencies = featureSet(&[_]Feature{}),
907 };
908 result[@intFromEnum(Feature.mad_mix_insts)] = .{
909 .llvm_name = "mad-mix-insts",
910 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
911 .dependencies = featureSet(&[_]Feature{}),
912 };
913 result[@intFromEnum(Feature.mai_insts)] = .{
914 .llvm_name = "mai-insts",
915 .description = "Has mAI instructions",
916 .dependencies = featureSet(&[_]Feature{}),
917 };
918 result[@intFromEnum(Feature.max_hard_clause_length_32)] = .{
919 .llvm_name = "max-hard-clause-length-32",
920 .description = "Maximum number of instructions in an explicit S_CLAUSE is 32",
921 .dependencies = featureSet(&[_]Feature{}),
922 };
923 result[@intFromEnum(Feature.max_hard_clause_length_63)] = .{
924 .llvm_name = "max-hard-clause-length-63",
925 .description = "Maximum number of instructions in an explicit S_CLAUSE is 63",
926 .dependencies = featureSet(&[_]Feature{}),
927 };
928 result[@intFromEnum(Feature.max_private_element_size_16)] = .{
929 .llvm_name = "max-private-element-size-16",
930 .description = "Maximum private access size may be 16",
931 .dependencies = featureSet(&[_]Feature{}),
932 };
933 result[@intFromEnum(Feature.max_private_element_size_4)] = .{
934 .llvm_name = "max-private-element-size-4",
935 .description = "Maximum private access size may be 4",
936 .dependencies = featureSet(&[_]Feature{}),
937 };
938 result[@intFromEnum(Feature.max_private_element_size_8)] = .{
939 .llvm_name = "max-private-element-size-8",
940 .description = "Maximum private access size may be 8",
941 .dependencies = featureSet(&[_]Feature{}),
942 };
943 result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{
944 .llvm_name = "memory-atomic-fadd-f32-denormal-support",
945 .description = "global/flat/buffer atomic fadd for float supports denormal handling",
946 .dependencies = featureSet(&[_]Feature{}),
947 };
948 result[@intFromEnum(Feature.mfma_inline_literal_bug)] = .{
949 .llvm_name = "mfma-inline-literal-bug",
950 .description = "MFMA cannot use inline literal as SrcC",
951 .dependencies = featureSet(&[_]Feature{}),
952 };
953 result[@intFromEnum(Feature.mimg_r128)] = .{
954 .llvm_name = "mimg-r128",
955 .description = "Support 128-bit texture resources",
956 .dependencies = featureSet(&[_]Feature{}),
957 };
958 result[@intFromEnum(Feature.movrel)] = .{
959 .llvm_name = "movrel",
960 .description = "Has v_movrel*_b32 instructions",
961 .dependencies = featureSet(&[_]Feature{}),
962 };
963 result[@intFromEnum(Feature.msaa_load_dst_sel_bug)] = .{
964 .llvm_name = "msaa-load-dst-sel-bug",
965 .description = "MSAA loads not honoring dst_sel bug",
966 .dependencies = featureSet(&[_]Feature{}),
967 };
968 result[@intFromEnum(Feature.negative_scratch_offset_bug)] = .{
969 .llvm_name = "negative-scratch-offset-bug",
970 .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9",
971 .dependencies = featureSet(&[_]Feature{}),
972 };
973 result[@intFromEnum(Feature.negative_unaligned_scratch_offset_bug)] = .{
974 .llvm_name = "negative-unaligned-scratch-offset-bug",
975 .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10",
976 .dependencies = featureSet(&[_]Feature{}),
977 };
978 result[@intFromEnum(Feature.no_data_dep_hazard)] = .{
979 .llvm_name = "no-data-dep-hazard",
980 .description = "Does not need SW waitstates",
981 .dependencies = featureSet(&[_]Feature{}),
982 };
983 result[@intFromEnum(Feature.no_sdst_cmpx)] = .{
984 .llvm_name = "no-sdst-cmpx",
985 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
986 .dependencies = featureSet(&[_]Feature{}),
987 };
988 result[@intFromEnum(Feature.nsa_clause_bug)] = .{
989 .llvm_name = "nsa-clause-bug",
990 .description = "MIMG-NSA in a hard clause has unpredictable results on GFX10.1",
991 .dependencies = featureSet(&[_]Feature{}),
992 };
993 result[@intFromEnum(Feature.nsa_encoding)] = .{
994 .llvm_name = "nsa-encoding",
995 .description = "Support NSA encoding for image instructions",
996 .dependencies = featureSet(&[_]Feature{}),
997 };
998 result[@intFromEnum(Feature.nsa_to_vmem_bug)] = .{
999 .llvm_name = "nsa-to-vmem-bug",
1000 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
1001 .dependencies = featureSet(&[_]Feature{}),
1002 };
1003 result[@intFromEnum(Feature.offset_3f_bug)] = .{
1004 .llvm_name = "offset-3f-bug",
1005 .description = "Branch offset of 3f hardware bug",
1006 .dependencies = featureSet(&[_]Feature{}),
1007 };
1008 result[@intFromEnum(Feature.packed_fp32_ops)] = .{
1009 .llvm_name = "packed-fp32-ops",
1010 .description = "Support packed fp32 instructions",
1011 .dependencies = featureSet(&[_]Feature{}),
1012 };
1013 result[@intFromEnum(Feature.packed_tid)] = .{
1014 .llvm_name = "packed-tid",
1015 .description = "Workitem IDs are packed into v0 at kernel launch",
1016 .dependencies = featureSet(&[_]Feature{}),
1017 };
1018 result[@intFromEnum(Feature.partial_nsa_encoding)] = .{
1019 .llvm_name = "partial-nsa-encoding",
1020 .description = "Support partial NSA encoding for image instructions",
1021 .dependencies = featureSet(&[_]Feature{}),
1022 };
1023 result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
1024 .llvm_name = "pk-fmac-f16-inst",
1025 .description = "Has v_pk_fmac_f16 instruction",
1026 .dependencies = featureSet(&[_]Feature{}),
1027 };
1028 result[@intFromEnum(Feature.precise_memory)] = .{
1029 .llvm_name = "precise-memory",
1030 .description = "Enable precise memory mode",
1031 .dependencies = featureSet(&[_]Feature{}),
1032 };
1033 result[@intFromEnum(Feature.priv_enabled_trap2_nop_bug)] = .{
1034 .llvm_name = "priv-enabled-trap2-nop-bug",
1035 .description = "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug",
1036 .dependencies = featureSet(&[_]Feature{}),
1037 };
1038 result[@intFromEnum(Feature.promote_alloca)] = .{
1039 .llvm_name = "promote-alloca",
1040 .description = "Enable promote alloca pass",
1041 .dependencies = featureSet(&[_]Feature{}),
1042 };
1043 result[@intFromEnum(Feature.prt_strict_null)] = .{
1044 .llvm_name = "enable-prt-strict-null",
1045 .description = "Enable zeroing of result registers for sparse texture fetches",
1046 .dependencies = featureSet(&[_]Feature{}),
1047 };
1048 result[@intFromEnum(Feature.pseudo_scalar_trans)] = .{
1049 .llvm_name = "pseudo-scalar-trans",
1050 .description = "Has Pseudo Scalar Transcendental instructions",
1051 .dependencies = featureSet(&[_]Feature{}),
1052 };
1053 result[@intFromEnum(Feature.r128_a16)] = .{
1054 .llvm_name = "r128-a16",
1055 .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
1056 .dependencies = featureSet(&[_]Feature{}),
1057 };
1058 result[@intFromEnum(Feature.real_true16)] = .{
1059 .llvm_name = "real-true16",
1060 .description = "Use true 16-bit registers",
1061 .dependencies = featureSet(&[_]Feature{}),
1062 };
1063 result[@intFromEnum(Feature.required_export_priority)] = .{
1064 .llvm_name = "required-export-priority",
1065 .description = "Export priority must be explicitly manipulated on GFX11.5",
1066 .dependencies = featureSet(&[_]Feature{}),
1067 };
1068 result[@intFromEnum(Feature.requires_cov6)] = .{
1069 .llvm_name = "requires-cov6",
1070 .description = "Target Requires Code Object V6",
1071 .dependencies = featureSet(&[_]Feature{}),
1072 };
1073 result[@intFromEnum(Feature.restricted_soffset)] = .{
1074 .llvm_name = "restricted-soffset",
1075 .description = "Has restricted SOffset (immediate not supported).",
1076 .dependencies = featureSet(&[_]Feature{}),
1077 };
1078 result[@intFromEnum(Feature.s_memrealtime)] = .{
1079 .llvm_name = "s-memrealtime",
1080 .description = "Has s_memrealtime instruction",
1081 .dependencies = featureSet(&[_]Feature{}),
1082 };
1083 result[@intFromEnum(Feature.s_memtime_inst)] = .{
1084 .llvm_name = "s-memtime-inst",
1085 .description = "Has s_memtime instruction",
1086 .dependencies = featureSet(&[_]Feature{}),
1087 };
1088 result[@intFromEnum(Feature.salu_float)] = .{
1089 .llvm_name = "salu-float",
1090 .description = "Has SALU floating point instructions",
1091 .dependencies = featureSet(&[_]Feature{}),
1092 };
1093 result[@intFromEnum(Feature.scalar_atomics)] = .{
1094 .llvm_name = "scalar-atomics",
1095 .description = "Has atomic scalar memory instructions",
1096 .dependencies = featureSet(&[_]Feature{}),
1097 };
1098 result[@intFromEnum(Feature.scalar_dwordx3_loads)] = .{
1099 .llvm_name = "scalar-dwordx3-loads",
1100 .description = "Has 96-bit scalar load instructions",
1101 .dependencies = featureSet(&[_]Feature{}),
1102 };
1103 result[@intFromEnum(Feature.scalar_flat_scratch_insts)] = .{
1104 .llvm_name = "scalar-flat-scratch-insts",
1105 .description = "Have s_scratch_* flat memory instructions",
1106 .dependencies = featureSet(&[_]Feature{}),
1107 };
1108 result[@intFromEnum(Feature.scalar_stores)] = .{
1109 .llvm_name = "scalar-stores",
1110 .description = "Has store scalar memory instructions",
1111 .dependencies = featureSet(&[_]Feature{}),
1112 };
1113 result[@intFromEnum(Feature.sdwa)] = .{
1114 .llvm_name = "sdwa",
1115 .description = "Support SDWA (Sub-DWORD Addressing) extension",
1116 .dependencies = featureSet(&[_]Feature{}),
1117 };
1118 result[@intFromEnum(Feature.sdwa_mav)] = .{
1119 .llvm_name = "sdwa-mav",
1120 .description = "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension",
1121 .dependencies = featureSet(&[_]Feature{}),
1122 };
1123 result[@intFromEnum(Feature.sdwa_omod)] = .{
1124 .llvm_name = "sdwa-omod",
1125 .description = "Support OMod with SDWA (Sub-DWORD Addressing) extension",
1126 .dependencies = featureSet(&[_]Feature{}),
1127 };
1128 result[@intFromEnum(Feature.sdwa_out_mods_vopc)] = .{
1129 .llvm_name = "sdwa-out-mods-vopc",
1130 .description = "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension",
1131 .dependencies = featureSet(&[_]Feature{}),
1132 };
1133 result[@intFromEnum(Feature.sdwa_scalar)] = .{
1134 .llvm_name = "sdwa-scalar",
1135 .description = "Support scalar register with SDWA (Sub-DWORD Addressing) extension",
1136 .dependencies = featureSet(&[_]Feature{}),
1137 };
1138 result[@intFromEnum(Feature.sdwa_sdst)] = .{
1139 .llvm_name = "sdwa-sdst",
1140 .description = "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension",
1141 .dependencies = featureSet(&[_]Feature{}),
1142 };
1143 result[@intFromEnum(Feature.sea_islands)] = .{
1144 .llvm_name = "sea-islands",
1145 .description = "SEA_ISLANDS GPU generation",
1146 .dependencies = featureSet(&[_]Feature{
1147 .atomic_fmin_fmax_flat_f32,
1148 .atomic_fmin_fmax_flat_f64,
1149 .atomic_fmin_fmax_global_f32,
1150 .atomic_fmin_fmax_global_f64,
1151 .ci_insts,
1152 .default_component_zero,
1153 .ds_src2_insts,
1154 .extended_image_insts,
1155 .flat_address_space,
1156 .fp64,
1157 .gds,
1158 .gfx7_gfx8_gfx9_insts,
1159 .gws,
1160 .image_insts,
1161 .localmemorysize65536,
1162 .mad_mac_f32_insts,
1163 .mimg_r128,
1164 .movrel,
1165 .s_memtime_inst,
1166 .trig_reduced_range,
1167 .unaligned_buffer_access,
1168 .vmem_write_vgpr_in_order,
1169 .wavefrontsize64,
1170 }),
1171 };
1172 result[@intFromEnum(Feature.sgpr_init_bug)] = .{
1173 .llvm_name = "sgpr-init-bug",
1174 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
1175 .dependencies = featureSet(&[_]Feature{}),
1176 };
1177 result[@intFromEnum(Feature.shader_cycles_hi_lo_registers)] = .{
1178 .llvm_name = "shader-cycles-hi-lo-registers",
1179 .description = "Has SHADER_CYCLES_HI/LO hardware registers",
1180 .dependencies = featureSet(&[_]Feature{}),
1181 };
1182 result[@intFromEnum(Feature.shader_cycles_register)] = .{
1183 .llvm_name = "shader-cycles-register",
1184 .description = "Has SHADER_CYCLES hardware register",
1185 .dependencies = featureSet(&[_]Feature{}),
1186 };
1187 result[@intFromEnum(Feature.si_scheduler)] = .{
1188 .llvm_name = "si-scheduler",
1189 .description = "Enable SI Machine Scheduler",
1190 .dependencies = featureSet(&[_]Feature{}),
1191 };
1192 result[@intFromEnum(Feature.smem_to_vector_write_hazard)] = .{
1193 .llvm_name = "smem-to-vector-write-hazard",
1194 .description = "s_load_dword followed by v_cmp page faults",
1195 .dependencies = featureSet(&[_]Feature{}),
1196 };
1197 result[@intFromEnum(Feature.southern_islands)] = .{
1198 .llvm_name = "southern-islands",
1199 .description = "SOUTHERN_ISLANDS GPU generation",
1200 .dependencies = featureSet(&[_]Feature{
1201 .atomic_fmin_fmax_global_f32,
1202 .atomic_fmin_fmax_global_f64,
1203 .default_component_zero,
1204 .ds_src2_insts,
1205 .extended_image_insts,
1206 .fp64,
1207 .gds,
1208 .gws,
1209 .image_insts,
1210 .ldsbankcount32,
1211 .localmemorysize32768,
1212 .mad_mac_f32_insts,
1213 .mimg_r128,
1214 .movrel,
1215 .s_memtime_inst,
1216 .trig_reduced_range,
1217 .vmem_write_vgpr_in_order,
1218 .wavefrontsize64,
1219 }),
1220 };
1221 result[@intFromEnum(Feature.sramecc)] = .{
1222 .llvm_name = "sramecc",
1223 .description = "Enable SRAMECC",
1224 .dependencies = featureSet(&[_]Feature{}),
1225 };
1226 result[@intFromEnum(Feature.sramecc_support)] = .{
1227 .llvm_name = "sramecc-support",
1228 .description = "Hardware supports SRAMECC",
1229 .dependencies = featureSet(&[_]Feature{}),
1230 };
1231 result[@intFromEnum(Feature.tgsplit)] = .{
1232 .llvm_name = "tgsplit",
1233 .description = "Enable threadgroup split execution",
1234 .dependencies = featureSet(&[_]Feature{}),
1235 };
1236 result[@intFromEnum(Feature.trap_handler)] = .{
1237 .llvm_name = "trap-handler",
1238 .description = "Trap handler support",
1239 .dependencies = featureSet(&[_]Feature{}),
1240 };
1241 result[@intFromEnum(Feature.trig_reduced_range)] = .{
1242 .llvm_name = "trig-reduced-range",
1243 .description = "Requires use of fract on arguments to trig instructions",
1244 .dependencies = featureSet(&[_]Feature{}),
1245 };
1246 result[@intFromEnum(Feature.true16)] = .{
1247 .llvm_name = "true16",
1248 .description = "True 16-bit operand instructions",
1249 .dependencies = featureSet(&[_]Feature{}),
1250 };
1251 result[@intFromEnum(Feature.unaligned_access_mode)] = .{
1252 .llvm_name = "unaligned-access-mode",
1253 .description = "Enable unaligned global, local and region loads and stores if the hardware supports it",
1254 .dependencies = featureSet(&[_]Feature{}),
1255 };
1256 result[@intFromEnum(Feature.unaligned_buffer_access)] = .{
1257 .llvm_name = "unaligned-buffer-access",
1258 .description = "Hardware supports unaligned global loads and stores",
1259 .dependencies = featureSet(&[_]Feature{}),
1260 };
1261 result[@intFromEnum(Feature.unaligned_ds_access)] = .{
1262 .llvm_name = "unaligned-ds-access",
1263 .description = "Hardware supports unaligned local and region loads and stores",
1264 .dependencies = featureSet(&[_]Feature{}),
1265 };
1266 result[@intFromEnum(Feature.unaligned_scratch_access)] = .{
1267 .llvm_name = "unaligned-scratch-access",
1268 .description = "Support unaligned scratch loads and stores",
1269 .dependencies = featureSet(&[_]Feature{}),
1270 };
1271 result[@intFromEnum(Feature.unpacked_d16_vmem)] = .{
1272 .llvm_name = "unpacked-d16-vmem",
1273 .description = "Has unpacked d16 vmem instructions",
1274 .dependencies = featureSet(&[_]Feature{}),
1275 };
1276 result[@intFromEnum(Feature.unsafe_ds_offset_folding)] = .{
1277 .llvm_name = "unsafe-ds-offset-folding",
1278 .description = "Force using DS instruction immediate offsets on SI",
1279 .dependencies = featureSet(&[_]Feature{}),
1280 };
1281 result[@intFromEnum(Feature.user_sgpr_init16_bug)] = .{
1282 .llvm_name = "user-sgpr-init16-bug",
1283 .description = "Bug requiring at least 16 user+system SGPRs to be enabled",
1284 .dependencies = featureSet(&[_]Feature{}),
1285 };
1286 result[@intFromEnum(Feature.valu_trans_use_hazard)] = .{
1287 .llvm_name = "valu-trans-use-hazard",
1288 .description = "Hazard when TRANS instructions are closely followed by a use of the result",
1289 .dependencies = featureSet(&[_]Feature{}),
1290 };
1291 result[@intFromEnum(Feature.vcmpx_exec_war_hazard)] = .{
1292 .llvm_name = "vcmpx-exec-war-hazard",
1293 .description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
1294 .dependencies = featureSet(&[_]Feature{}),
1295 };
1296 result[@intFromEnum(Feature.vcmpx_permlane_hazard)] = .{
1297 .llvm_name = "vcmpx-permlane-hazard",
1298 .description = "TODO: describe me",
1299 .dependencies = featureSet(&[_]Feature{}),
1300 };
1301 result[@intFromEnum(Feature.vgpr_index_mode)] = .{
1302 .llvm_name = "vgpr-index-mode",
1303 .description = "Has VGPR mode register indexing",
1304 .dependencies = featureSet(&[_]Feature{}),
1305 };
1306 result[@intFromEnum(Feature.vgpr_singleuse_hint)] = .{
1307 .llvm_name = "vgpr-singleuse-hint",
1308 .description = "Has single-use VGPR hint instructions",
1309 .dependencies = featureSet(&[_]Feature{}),
1310 };
1311 result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{
1312 .llvm_name = "vmem-to-scalar-write-hazard",
1313 .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
1314 .dependencies = featureSet(&[_]Feature{}),
1315 };
1316 result[@intFromEnum(Feature.vmem_write_vgpr_in_order)] = .{
1317 .llvm_name = "vmem-write-vgpr-in-order",
1318 .description = "VMEM instructions of the same type write VGPR results in order",
1319 .dependencies = featureSet(&[_]Feature{}),
1320 };
1321 result[@intFromEnum(Feature.volcanic_islands)] = .{
1322 .llvm_name = "volcanic-islands",
1323 .description = "VOLCANIC_ISLANDS GPU generation",
1324 .dependencies = featureSet(&[_]Feature{
1325 .@"16_bit_insts",
1326 .ci_insts,
1327 .default_component_zero,
1328 .dpp,
1329 .ds_src2_insts,
1330 .extended_image_insts,
1331 .fast_denormal_f32,
1332 .flat_address_space,
1333 .fp64,
1334 .gcn3_encoding,
1335 .gds,
1336 .gfx7_gfx8_gfx9_insts,
1337 .gfx8_insts,
1338 .gws,
1339 .image_insts,
1340 .int_clamp_insts,
1341 .inv_2pi_inline_imm,
1342 .localmemorysize65536,
1343 .mad_mac_f32_insts,
1344 .mimg_r128,
1345 .movrel,
1346 .s_memrealtime,
1347 .s_memtime_inst,
1348 .scalar_stores,
1349 .sdwa,
1350 .sdwa_mav,
1351 .sdwa_out_mods_vopc,
1352 .trig_reduced_range,
1353 .unaligned_buffer_access,
1354 .vgpr_index_mode,
1355 .vmem_write_vgpr_in_order,
1356 .wavefrontsize64,
1357 }),
1358 };
1359 result[@intFromEnum(Feature.vop3_literal)] = .{
1360 .llvm_name = "vop3-literal",
1361 .description = "Can use one literal in VOP3",
1362 .dependencies = featureSet(&[_]Feature{}),
1363 };
1364 result[@intFromEnum(Feature.vop3p)] = .{
1365 .llvm_name = "vop3p",
1366 .description = "Has VOP3P packed instructions",
1367 .dependencies = featureSet(&[_]Feature{}),
1368 };
1369 result[@intFromEnum(Feature.vopd)] = .{
1370 .llvm_name = "vopd",
1371 .description = "Has VOPD dual issue wave32 instructions",
1372 .dependencies = featureSet(&[_]Feature{}),
1373 };
1374 result[@intFromEnum(Feature.vscnt)] = .{
1375 .llvm_name = "vscnt",
1376 .description = "Has separate store vscnt counter",
1377 .dependencies = featureSet(&[_]Feature{}),
1378 };
1379 result[@intFromEnum(Feature.wavefrontsize16)] = .{
1380 .llvm_name = "wavefrontsize16",
1381 .description = "The number of threads per wavefront",
1382 .dependencies = featureSet(&[_]Feature{}),
1383 };
1384 result[@intFromEnum(Feature.wavefrontsize32)] = .{
1385 .llvm_name = "wavefrontsize32",
1386 .description = "The number of threads per wavefront",
1387 .dependencies = featureSet(&[_]Feature{}),
1388 };
1389 result[@intFromEnum(Feature.wavefrontsize64)] = .{
1390 .llvm_name = "wavefrontsize64",
1391 .description = "The number of threads per wavefront",
1392 .dependencies = featureSet(&[_]Feature{}),
1393 };
1394 result[@intFromEnum(Feature.xnack)] = .{
1395 .llvm_name = "xnack",
1396 .description = "Enable XNACK support",
1397 .dependencies = featureSet(&[_]Feature{}),
1398 };
1399 result[@intFromEnum(Feature.xnack_support)] = .{
1400 .llvm_name = "xnack-support",
1401 .description = "Hardware supports XNACK",
1402 .dependencies = featureSet(&[_]Feature{}),
1403 };
1404 const ti = @typeInfo(Feature);
1405 for (&result, 0..) |*elem, i| {
1406 elem.index = i;
1407 elem.name = ti.@"enum".fields[i].name;
1408 }
1409 break :blk result;
1410};
1411
1412pub const cpu = struct {
1413 pub const bonaire = CpuModel{
1414 .name = "bonaire",
1415 .llvm_name = "bonaire",
1416 .features = featureSet(&[_]Feature{
1417 .ldsbankcount32,
1418 .sea_islands,
1419 }),
1420 };
1421 pub const carrizo = CpuModel{
1422 .name = "carrizo",
1423 .llvm_name = "carrizo",
1424 .features = featureSet(&[_]Feature{
1425 .fast_fmaf,
1426 .half_rate_64_ops,
1427 .ldsbankcount32,
1428 .unpacked_d16_vmem,
1429 .volcanic_islands,
1430 .xnack_support,
1431 }),
1432 };
1433 pub const fiji = CpuModel{
1434 .name = "fiji",
1435 .llvm_name = "fiji",
1436 .features = featureSet(&[_]Feature{
1437 .ldsbankcount32,
1438 .unpacked_d16_vmem,
1439 .volcanic_islands,
1440 }),
1441 };
1442 pub const generic = CpuModel{
1443 .name = "generic",
1444 .llvm_name = "generic",
1445 .features = featureSet(&[_]Feature{
1446 .gds,
1447 .gws,
1448 .wavefrontsize64,
1449 }),
1450 };
1451 pub const generic_hsa = CpuModel{
1452 .name = "generic_hsa",
1453 .llvm_name = "generic-hsa",
1454 .features = featureSet(&[_]Feature{
1455 .flat_address_space,
1456 .gds,
1457 .gws,
1458 .wavefrontsize64,
1459 }),
1460 };
1461 pub const gfx1010 = CpuModel{
1462 .name = "gfx1010",
1463 .llvm_name = "gfx1010",
1464 .features = featureSet(&[_]Feature{
1465 .back_off_barrier,
1466 .dl_insts,
1467 .ds_src2_insts,
1468 .flat_segment_offset_bug,
1469 .get_wave_id_inst,
1470 .gfx10,
1471 .inst_fwd_prefetch_bug,
1472 .lds_branch_vmem_war_hazard,
1473 .lds_misaligned_bug,
1474 .ldsbankcount32,
1475 .mad_mac_f32_insts,
1476 .negative_unaligned_scratch_offset_bug,
1477 .nsa_clause_bug,
1478 .nsa_encoding,
1479 .nsa_to_vmem_bug,
1480 .offset_3f_bug,
1481 .scalar_atomics,
1482 .scalar_flat_scratch_insts,
1483 .scalar_stores,
1484 .smem_to_vector_write_hazard,
1485 .vcmpx_exec_war_hazard,
1486 .vcmpx_permlane_hazard,
1487 .vmem_to_scalar_write_hazard,
1488 .xnack_support,
1489 }),
1490 };
1491 pub const gfx1011 = CpuModel{
1492 .name = "gfx1011",
1493 .llvm_name = "gfx1011",
1494 .features = featureSet(&[_]Feature{
1495 .back_off_barrier,
1496 .dl_insts,
1497 .dot10_insts,
1498 .dot1_insts,
1499 .dot2_insts,
1500 .dot5_insts,
1501 .dot6_insts,
1502 .dot7_insts,
1503 .ds_src2_insts,
1504 .flat_segment_offset_bug,
1505 .get_wave_id_inst,
1506 .gfx10,
1507 .inst_fwd_prefetch_bug,
1508 .lds_branch_vmem_war_hazard,
1509 .lds_misaligned_bug,
1510 .ldsbankcount32,
1511 .mad_mac_f32_insts,
1512 .negative_unaligned_scratch_offset_bug,
1513 .nsa_clause_bug,
1514 .nsa_encoding,
1515 .nsa_to_vmem_bug,
1516 .offset_3f_bug,
1517 .scalar_atomics,
1518 .scalar_flat_scratch_insts,
1519 .scalar_stores,
1520 .smem_to_vector_write_hazard,
1521 .vcmpx_exec_war_hazard,
1522 .vcmpx_permlane_hazard,
1523 .vmem_to_scalar_write_hazard,
1524 .xnack_support,
1525 }),
1526 };
1527 pub const gfx1012 = CpuModel{
1528 .name = "gfx1012",
1529 .llvm_name = "gfx1012",
1530 .features = featureSet(&[_]Feature{
1531 .back_off_barrier,
1532 .dl_insts,
1533 .dot10_insts,
1534 .dot1_insts,
1535 .dot2_insts,
1536 .dot5_insts,
1537 .dot6_insts,
1538 .dot7_insts,
1539 .ds_src2_insts,
1540 .flat_segment_offset_bug,
1541 .get_wave_id_inst,
1542 .gfx10,
1543 .inst_fwd_prefetch_bug,
1544 .lds_branch_vmem_war_hazard,
1545 .lds_misaligned_bug,
1546 .ldsbankcount32,
1547 .mad_mac_f32_insts,
1548 .negative_unaligned_scratch_offset_bug,
1549 .nsa_clause_bug,
1550 .nsa_encoding,
1551 .nsa_to_vmem_bug,
1552 .offset_3f_bug,
1553 .scalar_atomics,
1554 .scalar_flat_scratch_insts,
1555 .scalar_stores,
1556 .smem_to_vector_write_hazard,
1557 .vcmpx_exec_war_hazard,
1558 .vcmpx_permlane_hazard,
1559 .vmem_to_scalar_write_hazard,
1560 .xnack_support,
1561 }),
1562 };
1563 pub const gfx1013 = CpuModel{
1564 .name = "gfx1013",
1565 .llvm_name = "gfx1013",
1566 .features = featureSet(&[_]Feature{
1567 .back_off_barrier,
1568 .dl_insts,
1569 .ds_src2_insts,
1570 .flat_segment_offset_bug,
1571 .get_wave_id_inst,
1572 .gfx10,
1573 .gfx10_a_encoding,
1574 .inst_fwd_prefetch_bug,
1575 .lds_branch_vmem_war_hazard,
1576 .lds_misaligned_bug,
1577 .ldsbankcount32,
1578 .mad_mac_f32_insts,
1579 .negative_unaligned_scratch_offset_bug,
1580 .nsa_clause_bug,
1581 .nsa_encoding,
1582 .nsa_to_vmem_bug,
1583 .offset_3f_bug,
1584 .scalar_atomics,
1585 .scalar_flat_scratch_insts,
1586 .scalar_stores,
1587 .smem_to_vector_write_hazard,
1588 .vcmpx_exec_war_hazard,
1589 .vcmpx_permlane_hazard,
1590 .vmem_to_scalar_write_hazard,
1591 .xnack_support,
1592 }),
1593 };
1594 pub const gfx1030 = CpuModel{
1595 .name = "gfx1030",
1596 .llvm_name = "gfx1030",
1597 .features = featureSet(&[_]Feature{
1598 .back_off_barrier,
1599 .dl_insts,
1600 .dot10_insts,
1601 .dot1_insts,
1602 .dot2_insts,
1603 .dot5_insts,
1604 .dot6_insts,
1605 .dot7_insts,
1606 .gfx10,
1607 .gfx10_3_insts,
1608 .gfx10_a_encoding,
1609 .gfx10_b_encoding,
1610 .ldsbankcount32,
1611 .nsa_encoding,
1612 .shader_cycles_register,
1613 }),
1614 };
1615 pub const gfx1031 = CpuModel{
1616 .name = "gfx1031",
1617 .llvm_name = "gfx1031",
1618 .features = featureSet(&[_]Feature{
1619 .back_off_barrier,
1620 .dl_insts,
1621 .dot10_insts,
1622 .dot1_insts,
1623 .dot2_insts,
1624 .dot5_insts,
1625 .dot6_insts,
1626 .dot7_insts,
1627 .gfx10,
1628 .gfx10_3_insts,
1629 .gfx10_a_encoding,
1630 .gfx10_b_encoding,
1631 .ldsbankcount32,
1632 .nsa_encoding,
1633 .shader_cycles_register,
1634 }),
1635 };
1636 pub const gfx1032 = CpuModel{
1637 .name = "gfx1032",
1638 .llvm_name = "gfx1032",
1639 .features = featureSet(&[_]Feature{
1640 .back_off_barrier,
1641 .dl_insts,
1642 .dot10_insts,
1643 .dot1_insts,
1644 .dot2_insts,
1645 .dot5_insts,
1646 .dot6_insts,
1647 .dot7_insts,
1648 .gfx10,
1649 .gfx10_3_insts,
1650 .gfx10_a_encoding,
1651 .gfx10_b_encoding,
1652 .ldsbankcount32,
1653 .nsa_encoding,
1654 .shader_cycles_register,
1655 }),
1656 };
1657 pub const gfx1033 = CpuModel{
1658 .name = "gfx1033",
1659 .llvm_name = "gfx1033",
1660 .features = featureSet(&[_]Feature{
1661 .back_off_barrier,
1662 .dl_insts,
1663 .dot10_insts,
1664 .dot1_insts,
1665 .dot2_insts,
1666 .dot5_insts,
1667 .dot6_insts,
1668 .dot7_insts,
1669 .gfx10,
1670 .gfx10_3_insts,
1671 .gfx10_a_encoding,
1672 .gfx10_b_encoding,
1673 .ldsbankcount32,
1674 .nsa_encoding,
1675 .shader_cycles_register,
1676 }),
1677 };
1678 pub const gfx1034 = CpuModel{
1679 .name = "gfx1034",
1680 .llvm_name = "gfx1034",
1681 .features = featureSet(&[_]Feature{
1682 .back_off_barrier,
1683 .dl_insts,
1684 .dot10_insts,
1685 .dot1_insts,
1686 .dot2_insts,
1687 .dot5_insts,
1688 .dot6_insts,
1689 .dot7_insts,
1690 .gfx10,
1691 .gfx10_3_insts,
1692 .gfx10_a_encoding,
1693 .gfx10_b_encoding,
1694 .ldsbankcount32,
1695 .nsa_encoding,
1696 .shader_cycles_register,
1697 }),
1698 };
1699 pub const gfx1035 = CpuModel{
1700 .name = "gfx1035",
1701 .llvm_name = "gfx1035",
1702 .features = featureSet(&[_]Feature{
1703 .back_off_barrier,
1704 .dl_insts,
1705 .dot10_insts,
1706 .dot1_insts,
1707 .dot2_insts,
1708 .dot5_insts,
1709 .dot6_insts,
1710 .dot7_insts,
1711 .gfx10,
1712 .gfx10_3_insts,
1713 .gfx10_a_encoding,
1714 .gfx10_b_encoding,
1715 .ldsbankcount32,
1716 .nsa_encoding,
1717 .shader_cycles_register,
1718 }),
1719 };
1720 pub const gfx1036 = CpuModel{
1721 .name = "gfx1036",
1722 .llvm_name = "gfx1036",
1723 .features = featureSet(&[_]Feature{
1724 .back_off_barrier,
1725 .dl_insts,
1726 .dot10_insts,
1727 .dot1_insts,
1728 .dot2_insts,
1729 .dot5_insts,
1730 .dot6_insts,
1731 .dot7_insts,
1732 .gfx10,
1733 .gfx10_3_insts,
1734 .gfx10_a_encoding,
1735 .gfx10_b_encoding,
1736 .ldsbankcount32,
1737 .nsa_encoding,
1738 .shader_cycles_register,
1739 }),
1740 };
1741 pub const gfx10_1_generic = CpuModel{
1742 .name = "gfx10_1_generic",
1743 .llvm_name = "gfx10-1-generic",
1744 .features = featureSet(&[_]Feature{
1745 .back_off_barrier,
1746 .dl_insts,
1747 .ds_src2_insts,
1748 .flat_segment_offset_bug,
1749 .get_wave_id_inst,
1750 .gfx10,
1751 .inst_fwd_prefetch_bug,
1752 .lds_branch_vmem_war_hazard,
1753 .lds_misaligned_bug,
1754 .ldsbankcount32,
1755 .mad_mac_f32_insts,
1756 .negative_unaligned_scratch_offset_bug,
1757 .nsa_clause_bug,
1758 .nsa_encoding,
1759 .nsa_to_vmem_bug,
1760 .offset_3f_bug,
1761 .requires_cov6,
1762 .scalar_atomics,
1763 .scalar_flat_scratch_insts,
1764 .scalar_stores,
1765 .smem_to_vector_write_hazard,
1766 .vcmpx_exec_war_hazard,
1767 .vcmpx_permlane_hazard,
1768 .vmem_to_scalar_write_hazard,
1769 .xnack_support,
1770 }),
1771 };
1772 pub const gfx10_3_generic = CpuModel{
1773 .name = "gfx10_3_generic",
1774 .llvm_name = "gfx10-3-generic",
1775 .features = featureSet(&[_]Feature{
1776 .back_off_barrier,
1777 .dl_insts,
1778 .dot10_insts,
1779 .dot1_insts,
1780 .dot2_insts,
1781 .dot5_insts,
1782 .dot6_insts,
1783 .dot7_insts,
1784 .gfx10,
1785 .gfx10_3_insts,
1786 .gfx10_a_encoding,
1787 .gfx10_b_encoding,
1788 .ldsbankcount32,
1789 .nsa_encoding,
1790 .requires_cov6,
1791 .shader_cycles_register,
1792 }),
1793 };
1794 pub const gfx1100 = CpuModel{
1795 .name = "gfx1100",
1796 .llvm_name = "gfx1100",
1797 .features = featureSet(&[_]Feature{
1798 .allocate1_5xvgprs,
1799 .architected_flat_scratch,
1800 .atomic_fadd_no_rtn_insts,
1801 .atomic_fadd_rtn_insts,
1802 .dl_insts,
1803 .dot10_insts,
1804 .dot5_insts,
1805 .dot7_insts,
1806 .dot8_insts,
1807 .dot9_insts,
1808 .flat_atomic_fadd_f32_inst,
1809 .gfx11,
1810 .image_insts,
1811 .ldsbankcount32,
1812 .mad_intra_fwd_bug,
1813 .memory_atomic_fadd_f32_denormal_support,
1814 .msaa_load_dst_sel_bug,
1815 .nsa_encoding,
1816 .packed_tid,
1817 .partial_nsa_encoding,
1818 .priv_enabled_trap2_nop_bug,
1819 .shader_cycles_register,
1820 .user_sgpr_init16_bug,
1821 .valu_trans_use_hazard,
1822 .vcmpx_permlane_hazard,
1823 }),
1824 };
1825 pub const gfx1101 = CpuModel{
1826 .name = "gfx1101",
1827 .llvm_name = "gfx1101",
1828 .features = featureSet(&[_]Feature{
1829 .allocate1_5xvgprs,
1830 .architected_flat_scratch,
1831 .atomic_fadd_no_rtn_insts,
1832 .atomic_fadd_rtn_insts,
1833 .dl_insts,
1834 .dot10_insts,
1835 .dot5_insts,
1836 .dot7_insts,
1837 .dot8_insts,
1838 .dot9_insts,
1839 .flat_atomic_fadd_f32_inst,
1840 .gfx11,
1841 .image_insts,
1842 .ldsbankcount32,
1843 .mad_intra_fwd_bug,
1844 .memory_atomic_fadd_f32_denormal_support,
1845 .msaa_load_dst_sel_bug,
1846 .nsa_encoding,
1847 .packed_tid,
1848 .partial_nsa_encoding,
1849 .priv_enabled_trap2_nop_bug,
1850 .shader_cycles_register,
1851 .valu_trans_use_hazard,
1852 .vcmpx_permlane_hazard,
1853 }),
1854 };
1855 pub const gfx1102 = CpuModel{
1856 .name = "gfx1102",
1857 .llvm_name = "gfx1102",
1858 .features = featureSet(&[_]Feature{
1859 .architected_flat_scratch,
1860 .atomic_fadd_no_rtn_insts,
1861 .atomic_fadd_rtn_insts,
1862 .dl_insts,
1863 .dot10_insts,
1864 .dot5_insts,
1865 .dot7_insts,
1866 .dot8_insts,
1867 .dot9_insts,
1868 .flat_atomic_fadd_f32_inst,
1869 .gfx11,
1870 .image_insts,
1871 .ldsbankcount32,
1872 .mad_intra_fwd_bug,
1873 .memory_atomic_fadd_f32_denormal_support,
1874 .msaa_load_dst_sel_bug,
1875 .nsa_encoding,
1876 .packed_tid,
1877 .partial_nsa_encoding,
1878 .priv_enabled_trap2_nop_bug,
1879 .shader_cycles_register,
1880 .user_sgpr_init16_bug,
1881 .valu_trans_use_hazard,
1882 .vcmpx_permlane_hazard,
1883 }),
1884 };
1885 pub const gfx1103 = CpuModel{
1886 .name = "gfx1103",
1887 .llvm_name = "gfx1103",
1888 .features = featureSet(&[_]Feature{
1889 .architected_flat_scratch,
1890 .atomic_fadd_no_rtn_insts,
1891 .atomic_fadd_rtn_insts,
1892 .dl_insts,
1893 .dot10_insts,
1894 .dot5_insts,
1895 .dot7_insts,
1896 .dot8_insts,
1897 .dot9_insts,
1898 .flat_atomic_fadd_f32_inst,
1899 .gfx11,
1900 .image_insts,
1901 .ldsbankcount32,
1902 .mad_intra_fwd_bug,
1903 .memory_atomic_fadd_f32_denormal_support,
1904 .msaa_load_dst_sel_bug,
1905 .nsa_encoding,
1906 .packed_tid,
1907 .partial_nsa_encoding,
1908 .priv_enabled_trap2_nop_bug,
1909 .shader_cycles_register,
1910 .valu_trans_use_hazard,
1911 .vcmpx_permlane_hazard,
1912 }),
1913 };
1914 pub const gfx1150 = CpuModel{
1915 .name = "gfx1150",
1916 .llvm_name = "gfx1150",
1917 .features = featureSet(&[_]Feature{
1918 .architected_flat_scratch,
1919 .atomic_fadd_no_rtn_insts,
1920 .atomic_fadd_rtn_insts,
1921 .dl_insts,
1922 .dot10_insts,
1923 .dot5_insts,
1924 .dot7_insts,
1925 .dot8_insts,
1926 .dot9_insts,
1927 .dpp_src1_sgpr,
1928 .flat_atomic_fadd_f32_inst,
1929 .gfx11,
1930 .image_insts,
1931 .ldsbankcount32,
1932 .memory_atomic_fadd_f32_denormal_support,
1933 .nsa_encoding,
1934 .packed_tid,
1935 .partial_nsa_encoding,
1936 .required_export_priority,
1937 .salu_float,
1938 .shader_cycles_register,
1939 .vcmpx_permlane_hazard,
1940 .vgpr_singleuse_hint,
1941 }),
1942 };
1943 pub const gfx1151 = CpuModel{
1944 .name = "gfx1151",
1945 .llvm_name = "gfx1151",
1946 .features = featureSet(&[_]Feature{
1947 .allocate1_5xvgprs,
1948 .architected_flat_scratch,
1949 .atomic_fadd_no_rtn_insts,
1950 .atomic_fadd_rtn_insts,
1951 .dl_insts,
1952 .dot10_insts,
1953 .dot5_insts,
1954 .dot7_insts,
1955 .dot8_insts,
1956 .dot9_insts,
1957 .dpp_src1_sgpr,
1958 .flat_atomic_fadd_f32_inst,
1959 .gfx11,
1960 .image_insts,
1961 .ldsbankcount32,
1962 .memory_atomic_fadd_f32_denormal_support,
1963 .nsa_encoding,
1964 .packed_tid,
1965 .partial_nsa_encoding,
1966 .required_export_priority,
1967 .salu_float,
1968 .shader_cycles_register,
1969 .vcmpx_permlane_hazard,
1970 .vgpr_singleuse_hint,
1971 }),
1972 };
1973 pub const gfx1152 = CpuModel{
1974 .name = "gfx1152",
1975 .llvm_name = "gfx1152",
1976 .features = featureSet(&[_]Feature{
1977 .architected_flat_scratch,
1978 .atomic_fadd_no_rtn_insts,
1979 .atomic_fadd_rtn_insts,
1980 .dl_insts,
1981 .dot10_insts,
1982 .dot5_insts,
1983 .dot7_insts,
1984 .dot8_insts,
1985 .dot9_insts,
1986 .dpp_src1_sgpr,
1987 .flat_atomic_fadd_f32_inst,
1988 .gfx11,
1989 .image_insts,
1990 .ldsbankcount32,
1991 .memory_atomic_fadd_f32_denormal_support,
1992 .nsa_encoding,
1993 .packed_tid,
1994 .partial_nsa_encoding,
1995 .required_export_priority,
1996 .salu_float,
1997 .shader_cycles_register,
1998 .vcmpx_permlane_hazard,
1999 .vgpr_singleuse_hint,
2000 }),
2001 };
2002 pub const gfx11_generic = CpuModel{
2003 .name = "gfx11_generic",
2004 .llvm_name = "gfx11-generic",
2005 .features = featureSet(&[_]Feature{
2006 .architected_flat_scratch,
2007 .atomic_fadd_no_rtn_insts,
2008 .atomic_fadd_rtn_insts,
2009 .dl_insts,
2010 .dot10_insts,
2011 .dot5_insts,
2012 .dot7_insts,
2013 .dot8_insts,
2014 .dot9_insts,
2015 .flat_atomic_fadd_f32_inst,
2016 .gfx11,
2017 .image_insts,
2018 .ldsbankcount32,
2019 .mad_intra_fwd_bug,
2020 .memory_atomic_fadd_f32_denormal_support,
2021 .msaa_load_dst_sel_bug,
2022 .nsa_encoding,
2023 .packed_tid,
2024 .partial_nsa_encoding,
2025 .priv_enabled_trap2_nop_bug,
2026 .required_export_priority,
2027 .requires_cov6,
2028 .shader_cycles_register,
2029 .user_sgpr_init16_bug,
2030 .valu_trans_use_hazard,
2031 .vcmpx_permlane_hazard,
2032 }),
2033 };
2034 pub const gfx1200 = CpuModel{
2035 .name = "gfx1200",
2036 .llvm_name = "gfx1200",
2037 .features = featureSet(&[_]Feature{
2038 .allocate1_5xvgprs,
2039 .architected_flat_scratch,
2040 .architected_sgprs,
2041 .atomic_buffer_global_pk_add_f16_insts,
2042 .atomic_buffer_pk_add_bf16_inst,
2043 .atomic_ds_pk_add_16_insts,
2044 .atomic_fadd_no_rtn_insts,
2045 .atomic_fadd_rtn_insts,
2046 .atomic_flat_pk_add_16_insts,
2047 .atomic_global_pk_add_bf16_inst,
2048 .dl_insts,
2049 .dot10_insts,
2050 .dot11_insts,
2051 .dot7_insts,
2052 .dot8_insts,
2053 .dot9_insts,
2054 .dpp_src1_sgpr,
2055 .extended_image_insts,
2056 .flat_atomic_fadd_f32_inst,
2057 .fp8_conversion_insts,
2058 .gfx12,
2059 .image_insts,
2060 .ldsbankcount32,
2061 .memory_atomic_fadd_f32_denormal_support,
2062 .nsa_encoding,
2063 .packed_tid,
2064 .partial_nsa_encoding,
2065 .pseudo_scalar_trans,
2066 .restricted_soffset,
2067 .salu_float,
2068 .scalar_dwordx3_loads,
2069 .shader_cycles_hi_lo_registers,
2070 .vcmpx_permlane_hazard,
2071 .vgpr_singleuse_hint,
2072 }),
2073 };
2074 pub const gfx1201 = CpuModel{
2075 .name = "gfx1201",
2076 .llvm_name = "gfx1201",
2077 .features = featureSet(&[_]Feature{
2078 .allocate1_5xvgprs,
2079 .architected_flat_scratch,
2080 .architected_sgprs,
2081 .atomic_buffer_global_pk_add_f16_insts,
2082 .atomic_buffer_pk_add_bf16_inst,
2083 .atomic_ds_pk_add_16_insts,
2084 .atomic_fadd_no_rtn_insts,
2085 .atomic_fadd_rtn_insts,
2086 .atomic_flat_pk_add_16_insts,
2087 .atomic_global_pk_add_bf16_inst,
2088 .dl_insts,
2089 .dot10_insts,
2090 .dot11_insts,
2091 .dot7_insts,
2092 .dot8_insts,
2093 .dot9_insts,
2094 .dpp_src1_sgpr,
2095 .extended_image_insts,
2096 .flat_atomic_fadd_f32_inst,
2097 .fp8_conversion_insts,
2098 .gfx12,
2099 .image_insts,
2100 .ldsbankcount32,
2101 .memory_atomic_fadd_f32_denormal_support,
2102 .nsa_encoding,
2103 .packed_tid,
2104 .partial_nsa_encoding,
2105 .pseudo_scalar_trans,
2106 .restricted_soffset,
2107 .salu_float,
2108 .scalar_dwordx3_loads,
2109 .shader_cycles_hi_lo_registers,
2110 .vcmpx_permlane_hazard,
2111 .vgpr_singleuse_hint,
2112 }),
2113 };
2114 pub const gfx12_generic = CpuModel{
2115 .name = "gfx12_generic",
2116 .llvm_name = "gfx12-generic",
2117 .features = featureSet(&[_]Feature{
2118 .allocate1_5xvgprs,
2119 .architected_flat_scratch,
2120 .architected_sgprs,
2121 .atomic_buffer_global_pk_add_f16_insts,
2122 .atomic_buffer_pk_add_bf16_inst,
2123 .atomic_ds_pk_add_16_insts,
2124 .atomic_fadd_no_rtn_insts,
2125 .atomic_fadd_rtn_insts,
2126 .atomic_flat_pk_add_16_insts,
2127 .atomic_global_pk_add_bf16_inst,
2128 .dl_insts,
2129 .dot10_insts,
2130 .dot11_insts,
2131 .dot7_insts,
2132 .dot8_insts,
2133 .dot9_insts,
2134 .dpp_src1_sgpr,
2135 .extended_image_insts,
2136 .flat_atomic_fadd_f32_inst,
2137 .fp8_conversion_insts,
2138 .gfx12,
2139 .image_insts,
2140 .ldsbankcount32,
2141 .memory_atomic_fadd_f32_denormal_support,
2142 .nsa_encoding,
2143 .packed_tid,
2144 .partial_nsa_encoding,
2145 .pseudo_scalar_trans,
2146 .requires_cov6,
2147 .restricted_soffset,
2148 .salu_float,
2149 .scalar_dwordx3_loads,
2150 .shader_cycles_hi_lo_registers,
2151 .vcmpx_permlane_hazard,
2152 .vgpr_singleuse_hint,
2153 }),
2154 };
2155 pub const gfx600 = CpuModel{
2156 .name = "gfx600",
2157 .llvm_name = "gfx600",
2158 .features = featureSet(&[_]Feature{
2159 .fast_fmaf,
2160 .half_rate_64_ops,
2161 .southern_islands,
2162 }),
2163 };
2164 pub const gfx601 = CpuModel{
2165 .name = "gfx601",
2166 .llvm_name = "gfx601",
2167 .features = featureSet(&[_]Feature{
2168 .southern_islands,
2169 }),
2170 };
2171 pub const gfx602 = CpuModel{
2172 .name = "gfx602",
2173 .llvm_name = "gfx602",
2174 .features = featureSet(&[_]Feature{
2175 .southern_islands,
2176 }),
2177 };
2178 pub const gfx700 = CpuModel{
2179 .name = "gfx700",
2180 .llvm_name = "gfx700",
2181 .features = featureSet(&[_]Feature{
2182 .ldsbankcount32,
2183 .sea_islands,
2184 }),
2185 };
2186 pub const gfx701 = CpuModel{
2187 .name = "gfx701",
2188 .llvm_name = "gfx701",
2189 .features = featureSet(&[_]Feature{
2190 .fast_fmaf,
2191 .half_rate_64_ops,
2192 .ldsbankcount32,
2193 .sea_islands,
2194 }),
2195 };
2196 pub const gfx702 = CpuModel{
2197 .name = "gfx702",
2198 .llvm_name = "gfx702",
2199 .features = featureSet(&[_]Feature{
2200 .fast_fmaf,
2201 .ldsbankcount16,
2202 .sea_islands,
2203 }),
2204 };
2205 pub const gfx703 = CpuModel{
2206 .name = "gfx703",
2207 .llvm_name = "gfx703",
2208 .features = featureSet(&[_]Feature{
2209 .ldsbankcount16,
2210 .sea_islands,
2211 }),
2212 };
2213 pub const gfx704 = CpuModel{
2214 .name = "gfx704",
2215 .llvm_name = "gfx704",
2216 .features = featureSet(&[_]Feature{
2217 .ldsbankcount32,
2218 .sea_islands,
2219 }),
2220 };
2221 pub const gfx705 = CpuModel{
2222 .name = "gfx705",
2223 .llvm_name = "gfx705",
2224 .features = featureSet(&[_]Feature{
2225 .ldsbankcount16,
2226 .sea_islands,
2227 }),
2228 };
2229 pub const gfx801 = CpuModel{
2230 .name = "gfx801",
2231 .llvm_name = "gfx801",
2232 .features = featureSet(&[_]Feature{
2233 .fast_fmaf,
2234 .half_rate_64_ops,
2235 .ldsbankcount32,
2236 .unpacked_d16_vmem,
2237 .volcanic_islands,
2238 .xnack_support,
2239 }),
2240 };
2241 pub const gfx802 = CpuModel{
2242 .name = "gfx802",
2243 .llvm_name = "gfx802",
2244 .features = featureSet(&[_]Feature{
2245 .ldsbankcount32,
2246 .sgpr_init_bug,
2247 .unpacked_d16_vmem,
2248 .volcanic_islands,
2249 }),
2250 };
2251 pub const gfx803 = CpuModel{
2252 .name = "gfx803",
2253 .llvm_name = "gfx803",
2254 .features = featureSet(&[_]Feature{
2255 .ldsbankcount32,
2256 .unpacked_d16_vmem,
2257 .volcanic_islands,
2258 }),
2259 };
2260 pub const gfx805 = CpuModel{
2261 .name = "gfx805",
2262 .llvm_name = "gfx805",
2263 .features = featureSet(&[_]Feature{
2264 .ldsbankcount32,
2265 .sgpr_init_bug,
2266 .unpacked_d16_vmem,
2267 .volcanic_islands,
2268 }),
2269 };
2270 pub const gfx810 = CpuModel{
2271 .name = "gfx810",
2272 .llvm_name = "gfx810",
2273 .features = featureSet(&[_]Feature{
2274 .image_gather4_d16_bug,
2275 .image_store_d16_bug,
2276 .ldsbankcount16,
2277 .volcanic_islands,
2278 .xnack_support,
2279 }),
2280 };
2281 pub const gfx900 = CpuModel{
2282 .name = "gfx900",
2283 .llvm_name = "gfx900",
2284 .features = featureSet(&[_]Feature{
2285 .ds_src2_insts,
2286 .extended_image_insts,
2287 .gds,
2288 .gfx9,
2289 .image_gather4_d16_bug,
2290 .image_insts,
2291 .ldsbankcount32,
2292 .mad_mac_f32_insts,
2293 .mad_mix_insts,
2294 }),
2295 };
2296 pub const gfx902 = CpuModel{
2297 .name = "gfx902",
2298 .llvm_name = "gfx902",
2299 .features = featureSet(&[_]Feature{
2300 .ds_src2_insts,
2301 .extended_image_insts,
2302 .gds,
2303 .gfx9,
2304 .image_gather4_d16_bug,
2305 .image_insts,
2306 .ldsbankcount32,
2307 .mad_mac_f32_insts,
2308 .mad_mix_insts,
2309 }),
2310 };
2311 pub const gfx904 = CpuModel{
2312 .name = "gfx904",
2313 .llvm_name = "gfx904",
2314 .features = featureSet(&[_]Feature{
2315 .ds_src2_insts,
2316 .extended_image_insts,
2317 .fma_mix_insts,
2318 .gds,
2319 .gfx9,
2320 .image_gather4_d16_bug,
2321 .image_insts,
2322 .ldsbankcount32,
2323 .mad_mac_f32_insts,
2324 }),
2325 };
2326 pub const gfx906 = CpuModel{
2327 .name = "gfx906",
2328 .llvm_name = "gfx906",
2329 .features = featureSet(&[_]Feature{
2330 .dl_insts,
2331 .dot10_insts,
2332 .dot1_insts,
2333 .dot2_insts,
2334 .dot7_insts,
2335 .ds_src2_insts,
2336 .extended_image_insts,
2337 .fma_mix_insts,
2338 .gds,
2339 .gfx9,
2340 .half_rate_64_ops,
2341 .image_gather4_d16_bug,
2342 .image_insts,
2343 .ldsbankcount32,
2344 .mad_mac_f32_insts,
2345 .sramecc_support,
2346 }),
2347 };
2348 pub const gfx908 = CpuModel{
2349 .name = "gfx908",
2350 .llvm_name = "gfx908",
2351 .features = featureSet(&[_]Feature{
2352 .atomic_buffer_global_pk_add_f16_no_rtn_insts,
2353 .atomic_fadd_no_rtn_insts,
2354 .dl_insts,
2355 .dot10_insts,
2356 .dot1_insts,
2357 .dot2_insts,
2358 .dot3_insts,
2359 .dot4_insts,
2360 .dot5_insts,
2361 .dot6_insts,
2362 .dot7_insts,
2363 .ds_src2_insts,
2364 .extended_image_insts,
2365 .fma_mix_insts,
2366 .gds,
2367 .gfx9,
2368 .half_rate_64_ops,
2369 .image_gather4_d16_bug,
2370 .image_insts,
2371 .ldsbankcount32,
2372 .mad_mac_f32_insts,
2373 .mai_insts,
2374 .mfma_inline_literal_bug,
2375 .pk_fmac_f16_inst,
2376 .sramecc_support,
2377 }),
2378 };
2379 pub const gfx909 = CpuModel{
2380 .name = "gfx909",
2381 .llvm_name = "gfx909",
2382 .features = featureSet(&[_]Feature{
2383 .ds_src2_insts,
2384 .extended_image_insts,
2385 .gds,
2386 .gfx9,
2387 .image_gather4_d16_bug,
2388 .image_insts,
2389 .ldsbankcount32,
2390 .mad_mac_f32_insts,
2391 .mad_mix_insts,
2392 }),
2393 };
2394 pub const gfx90a = CpuModel{
2395 .name = "gfx90a",
2396 .llvm_name = "gfx90a",
2397 .features = featureSet(&[_]Feature{
2398 .atomic_buffer_global_pk_add_f16_insts,
2399 .atomic_fadd_no_rtn_insts,
2400 .atomic_fadd_rtn_insts,
2401 .atomic_fmin_fmax_flat_f64,
2402 .atomic_fmin_fmax_global_f64,
2403 .back_off_barrier,
2404 .dl_insts,
2405 .dot10_insts,
2406 .dot1_insts,
2407 .dot2_insts,
2408 .dot3_insts,
2409 .dot4_insts,
2410 .dot5_insts,
2411 .dot6_insts,
2412 .dot7_insts,
2413 .dpp_64bit,
2414 .flat_buffer_global_fadd_f64_inst,
2415 .fma_mix_insts,
2416 .fmacf64_inst,
2417 .full_rate_64_ops,
2418 .gfx9,
2419 .gfx90a_insts,
2420 .image_insts,
2421 .kernarg_preload,
2422 .ldsbankcount32,
2423 .mad_mac_f32_insts,
2424 .mai_insts,
2425 .packed_fp32_ops,
2426 .packed_tid,
2427 .pk_fmac_f16_inst,
2428 .sramecc_support,
2429 }),
2430 };
2431 pub const gfx90c = CpuModel{
2432 .name = "gfx90c",
2433 .llvm_name = "gfx90c",
2434 .features = featureSet(&[_]Feature{
2435 .ds_src2_insts,
2436 .extended_image_insts,
2437 .gds,
2438 .gfx9,
2439 .image_gather4_d16_bug,
2440 .image_insts,
2441 .ldsbankcount32,
2442 .mad_mac_f32_insts,
2443 .mad_mix_insts,
2444 }),
2445 };
2446 pub const gfx940 = CpuModel{
2447 .name = "gfx940",
2448 .llvm_name = "gfx940",
2449 .features = featureSet(&[_]Feature{
2450 .agent_scope_fine_grained_remote_memory_atomics,
2451 .architected_flat_scratch,
2452 .atomic_buffer_global_pk_add_f16_insts,
2453 .atomic_ds_pk_add_16_insts,
2454 .atomic_fadd_no_rtn_insts,
2455 .atomic_fadd_rtn_insts,
2456 .atomic_flat_pk_add_16_insts,
2457 .atomic_fmin_fmax_flat_f64,
2458 .atomic_fmin_fmax_global_f64,
2459 .atomic_global_pk_add_bf16_inst,
2460 .back_off_barrier,
2461 .dl_insts,
2462 .dot10_insts,
2463 .dot1_insts,
2464 .dot2_insts,
2465 .dot3_insts,
2466 .dot4_insts,
2467 .dot5_insts,
2468 .dot6_insts,
2469 .dot7_insts,
2470 .dpp_64bit,
2471 .flat_atomic_fadd_f32_inst,
2472 .flat_buffer_global_fadd_f64_inst,
2473 .fma_mix_insts,
2474 .fmacf64_inst,
2475 .force_store_sc0_sc1,
2476 .fp8_conversion_insts,
2477 .fp8_insts,
2478 .full_rate_64_ops,
2479 .gfx9,
2480 .gfx90a_insts,
2481 .gfx940_insts,
2482 .kernarg_preload,
2483 .ldsbankcount32,
2484 .mai_insts,
2485 .memory_atomic_fadd_f32_denormal_support,
2486 .packed_fp32_ops,
2487 .packed_tid,
2488 .pk_fmac_f16_inst,
2489 .sramecc_support,
2490 }),
2491 };
2492 pub const gfx941 = CpuModel{
2493 .name = "gfx941",
2494 .llvm_name = "gfx941",
2495 .features = featureSet(&[_]Feature{
2496 .agent_scope_fine_grained_remote_memory_atomics,
2497 .architected_flat_scratch,
2498 .atomic_buffer_global_pk_add_f16_insts,
2499 .atomic_ds_pk_add_16_insts,
2500 .atomic_fadd_no_rtn_insts,
2501 .atomic_fadd_rtn_insts,
2502 .atomic_flat_pk_add_16_insts,
2503 .atomic_fmin_fmax_flat_f64,
2504 .atomic_fmin_fmax_global_f64,
2505 .atomic_global_pk_add_bf16_inst,
2506 .back_off_barrier,
2507 .dl_insts,
2508 .dot10_insts,
2509 .dot1_insts,
2510 .dot2_insts,
2511 .dot3_insts,
2512 .dot4_insts,
2513 .dot5_insts,
2514 .dot6_insts,
2515 .dot7_insts,
2516 .dpp_64bit,
2517 .flat_atomic_fadd_f32_inst,
2518 .flat_buffer_global_fadd_f64_inst,
2519 .fma_mix_insts,
2520 .fmacf64_inst,
2521 .force_store_sc0_sc1,
2522 .fp8_conversion_insts,
2523 .fp8_insts,
2524 .full_rate_64_ops,
2525 .gfx9,
2526 .gfx90a_insts,
2527 .gfx940_insts,
2528 .kernarg_preload,
2529 .ldsbankcount32,
2530 .mai_insts,
2531 .memory_atomic_fadd_f32_denormal_support,
2532 .packed_fp32_ops,
2533 .packed_tid,
2534 .pk_fmac_f16_inst,
2535 .sramecc_support,
2536 }),
2537 };
2538 pub const gfx942 = CpuModel{
2539 .name = "gfx942",
2540 .llvm_name = "gfx942",
2541 .features = featureSet(&[_]Feature{
2542 .agent_scope_fine_grained_remote_memory_atomics,
2543 .architected_flat_scratch,
2544 .atomic_buffer_global_pk_add_f16_insts,
2545 .atomic_ds_pk_add_16_insts,
2546 .atomic_fadd_no_rtn_insts,
2547 .atomic_fadd_rtn_insts,
2548 .atomic_flat_pk_add_16_insts,
2549 .atomic_fmin_fmax_flat_f64,
2550 .atomic_fmin_fmax_global_f64,
2551 .atomic_global_pk_add_bf16_inst,
2552 .back_off_barrier,
2553 .dl_insts,
2554 .dot10_insts,
2555 .dot1_insts,
2556 .dot2_insts,
2557 .dot3_insts,
2558 .dot4_insts,
2559 .dot5_insts,
2560 .dot6_insts,
2561 .dot7_insts,
2562 .dpp_64bit,
2563 .flat_atomic_fadd_f32_inst,
2564 .flat_buffer_global_fadd_f64_inst,
2565 .fma_mix_insts,
2566 .fmacf64_inst,
2567 .fp8_conversion_insts,
2568 .fp8_insts,
2569 .full_rate_64_ops,
2570 .gfx9,
2571 .gfx90a_insts,
2572 .gfx940_insts,
2573 .kernarg_preload,
2574 .ldsbankcount32,
2575 .mai_insts,
2576 .memory_atomic_fadd_f32_denormal_support,
2577 .packed_fp32_ops,
2578 .packed_tid,
2579 .pk_fmac_f16_inst,
2580 .sramecc_support,
2581 }),
2582 };
2583 pub const gfx9_generic = CpuModel{
2584 .name = "gfx9_generic",
2585 .llvm_name = "gfx9-generic",
2586 .features = featureSet(&[_]Feature{
2587 .ds_src2_insts,
2588 .extended_image_insts,
2589 .gds,
2590 .gfx9,
2591 .image_gather4_d16_bug,
2592 .image_insts,
2593 .ldsbankcount32,
2594 .mad_mac_f32_insts,
2595 .requires_cov6,
2596 }),
2597 };
2598 pub const hainan = CpuModel{
2599 .name = "hainan",
2600 .llvm_name = "hainan",
2601 .features = featureSet(&[_]Feature{
2602 .southern_islands,
2603 }),
2604 };
2605 pub const hawaii = CpuModel{
2606 .name = "hawaii",
2607 .llvm_name = "hawaii",
2608 .features = featureSet(&[_]Feature{
2609 .fast_fmaf,
2610 .half_rate_64_ops,
2611 .ldsbankcount32,
2612 .sea_islands,
2613 }),
2614 };
2615 pub const iceland = CpuModel{
2616 .name = "iceland",
2617 .llvm_name = "iceland",
2618 .features = featureSet(&[_]Feature{
2619 .ldsbankcount32,
2620 .sgpr_init_bug,
2621 .unpacked_d16_vmem,
2622 .volcanic_islands,
2623 }),
2624 };
2625 pub const kabini = CpuModel{
2626 .name = "kabini",
2627 .llvm_name = "kabini",
2628 .features = featureSet(&[_]Feature{
2629 .ldsbankcount16,
2630 .sea_islands,
2631 }),
2632 };
2633 pub const kaveri = CpuModel{
2634 .name = "kaveri",
2635 .llvm_name = "kaveri",
2636 .features = featureSet(&[_]Feature{
2637 .ldsbankcount32,
2638 .sea_islands,
2639 }),
2640 };
2641 pub const mullins = CpuModel{
2642 .name = "mullins",
2643 .llvm_name = "mullins",
2644 .features = featureSet(&[_]Feature{
2645 .ldsbankcount16,
2646 .sea_islands,
2647 }),
2648 };
2649 pub const oland = CpuModel{
2650 .name = "oland",
2651 .llvm_name = "oland",
2652 .features = featureSet(&[_]Feature{
2653 .southern_islands,
2654 }),
2655 };
2656 pub const pitcairn = CpuModel{
2657 .name = "pitcairn",
2658 .llvm_name = "pitcairn",
2659 .features = featureSet(&[_]Feature{
2660 .southern_islands,
2661 }),
2662 };
2663 pub const polaris10 = CpuModel{
2664 .name = "polaris10",
2665 .llvm_name = "polaris10",
2666 .features = featureSet(&[_]Feature{
2667 .ldsbankcount32,
2668 .unpacked_d16_vmem,
2669 .volcanic_islands,
2670 }),
2671 };
2672 pub const polaris11 = CpuModel{
2673 .name = "polaris11",
2674 .llvm_name = "polaris11",
2675 .features = featureSet(&[_]Feature{
2676 .ldsbankcount32,
2677 .unpacked_d16_vmem,
2678 .volcanic_islands,
2679 }),
2680 };
2681 pub const stoney = CpuModel{
2682 .name = "stoney",
2683 .llvm_name = "stoney",
2684 .features = featureSet(&[_]Feature{
2685 .image_gather4_d16_bug,
2686 .image_store_d16_bug,
2687 .ldsbankcount16,
2688 .volcanic_islands,
2689 .xnack_support,
2690 }),
2691 };
2692 pub const tahiti = CpuModel{
2693 .name = "tahiti",
2694 .llvm_name = "tahiti",
2695 .features = featureSet(&[_]Feature{
2696 .fast_fmaf,
2697 .half_rate_64_ops,
2698 .southern_islands,
2699 }),
2700 };
2701 pub const tonga = CpuModel{
2702 .name = "tonga",
2703 .llvm_name = "tonga",
2704 .features = featureSet(&[_]Feature{
2705 .ldsbankcount32,
2706 .sgpr_init_bug,
2707 .unpacked_d16_vmem,
2708 .volcanic_islands,
2709 }),
2710 };
2711 pub const tongapro = CpuModel{
2712 .name = "tongapro",
2713 .llvm_name = "tongapro",
2714 .features = featureSet(&[_]Feature{
2715 .ldsbankcount32,
2716 .sgpr_init_bug,
2717 .unpacked_d16_vmem,
2718 .volcanic_islands,
2719 }),
2720 };
2721 pub const verde = CpuModel{
2722 .name = "verde",
2723 .llvm_name = "verde",
2724 .features = featureSet(&[_]Feature{
2725 .southern_islands,
2726 }),
2727 };
2728};
lib/std/Target/amdgpu.zig deleted-2728
...@@ -1,2728 +0,0 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"16_bit_insts",
9 a16,
10 add_no_carry_insts,
11 agent_scope_fine_grained_remote_memory_atomics,
12 allocate1_5xvgprs,
13 aperture_regs,
14 architected_flat_scratch,
15 architected_sgprs,
16 atomic_buffer_global_pk_add_f16_insts,
17 atomic_buffer_global_pk_add_f16_no_rtn_insts,
18 atomic_buffer_pk_add_bf16_inst,
19 atomic_csub_no_rtn_insts,
20 atomic_ds_pk_add_16_insts,
21 atomic_fadd_no_rtn_insts,
22 atomic_fadd_rtn_insts,
23 atomic_flat_pk_add_16_insts,
24 atomic_fmin_fmax_flat_f32,
25 atomic_fmin_fmax_flat_f64,
26 atomic_fmin_fmax_global_f32,
27 atomic_fmin_fmax_global_f64,
28 atomic_global_pk_add_bf16_inst,
29 auto_waitcnt_before_barrier,
30 back_off_barrier,
31 ci_insts,
32 cumode,
33 default_component_broadcast,
34 default_component_zero,
35 dl_insts,
36 dot10_insts,
37 dot11_insts,
38 dot1_insts,
39 dot2_insts,
40 dot3_insts,
41 dot4_insts,
42 dot5_insts,
43 dot6_insts,
44 dot7_insts,
45 dot8_insts,
46 dot9_insts,
47 dpp,
48 dpp8,
49 dpp_64bit,
50 dpp_src1_sgpr,
51 ds128,
52 ds_src2_insts,
53 extended_image_insts,
54 fast_denormal_f32,
55 fast_fmaf,
56 flat_address_space,
57 flat_atomic_fadd_f32_inst,
58 flat_buffer_global_fadd_f64_inst,
59 flat_for_global,
60 flat_global_insts,
61 flat_inst_offsets,
62 flat_scratch,
63 flat_scratch_insts,
64 flat_segment_offset_bug,
65 fma_mix_insts,
66 fmacf64_inst,
67 fmaf,
68 force_store_sc0_sc1,
69 fp64,
70 fp8_conversion_insts,
71 fp8_insts,
72 full_rate_64_ops,
73 g16,
74 gcn3_encoding,
75 gds,
76 get_wave_id_inst,
77 gfx10,
78 gfx10_3_insts,
79 gfx10_a_encoding,
80 gfx10_b_encoding,
81 gfx10_insts,
82 gfx11,
83 gfx11_insts,
84 gfx12,
85 gfx12_insts,
86 gfx7_gfx8_gfx9_insts,
87 gfx8_insts,
88 gfx9,
89 gfx90a_insts,
90 gfx940_insts,
91 gfx9_insts,
92 gws,
93 half_rate_64_ops,
94 image_gather4_d16_bug,
95 image_insts,
96 image_store_d16_bug,
97 inst_fwd_prefetch_bug,
98 int_clamp_insts,
99 inv_2pi_inline_imm,
100 kernarg_preload,
101 lds_branch_vmem_war_hazard,
102 lds_misaligned_bug,
103 ldsbankcount16,
104 ldsbankcount32,
105 load_store_opt,
106 localmemorysize32768,
107 localmemorysize65536,
108 mad_intra_fwd_bug,
109 mad_mac_f32_insts,
110 mad_mix_insts,
111 mai_insts,
112 max_hard_clause_length_32,
113 max_hard_clause_length_63,
114 max_private_element_size_16,
115 max_private_element_size_4,
116 max_private_element_size_8,
117 memory_atomic_fadd_f32_denormal_support,
118 mfma_inline_literal_bug,
119 mimg_r128,
120 movrel,
121 msaa_load_dst_sel_bug,
122 negative_scratch_offset_bug,
123 negative_unaligned_scratch_offset_bug,
124 no_data_dep_hazard,
125 no_sdst_cmpx,
126 nsa_clause_bug,
127 nsa_encoding,
128 nsa_to_vmem_bug,
129 offset_3f_bug,
130 packed_fp32_ops,
131 packed_tid,
132 partial_nsa_encoding,
133 pk_fmac_f16_inst,
134 precise_memory,
135 priv_enabled_trap2_nop_bug,
136 promote_alloca,
137 prt_strict_null,
138 pseudo_scalar_trans,
139 r128_a16,
140 real_true16,
141 required_export_priority,
142 requires_cov6,
143 restricted_soffset,
144 s_memrealtime,
145 s_memtime_inst,
146 salu_float,
147 scalar_atomics,
148 scalar_dwordx3_loads,
149 scalar_flat_scratch_insts,
150 scalar_stores,
151 sdwa,
152 sdwa_mav,
153 sdwa_omod,
154 sdwa_out_mods_vopc,
155 sdwa_scalar,
156 sdwa_sdst,
157 sea_islands,
158 sgpr_init_bug,
159 shader_cycles_hi_lo_registers,
160 shader_cycles_register,
161 si_scheduler,
162 smem_to_vector_write_hazard,
163 southern_islands,
164 sramecc,
165 sramecc_support,
166 tgsplit,
167 trap_handler,
168 trig_reduced_range,
169 true16,
170 unaligned_access_mode,
171 unaligned_buffer_access,
172 unaligned_ds_access,
173 unaligned_scratch_access,
174 unpacked_d16_vmem,
175 unsafe_ds_offset_folding,
176 user_sgpr_init16_bug,
177 valu_trans_use_hazard,
178 vcmpx_exec_war_hazard,
179 vcmpx_permlane_hazard,
180 vgpr_index_mode,
181 vgpr_singleuse_hint,
182 vmem_to_scalar_write_hazard,
183 vmem_write_vgpr_in_order,
184 volcanic_islands,
185 vop3_literal,
186 vop3p,
187 vopd,
188 vscnt,
189 wavefrontsize16,
190 wavefrontsize32,
191 wavefrontsize64,
192 xnack,
193 xnack_support,
194};
195
196pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
197pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
198pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
199pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
200
201pub const all_features = blk: {
202 const len = @typeInfo(Feature).@"enum".fields.len;
203 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
204 var result: [len]CpuFeature = undefined;
205 result[@intFromEnum(Feature.@"16_bit_insts")] = .{
206 .llvm_name = "16-bit-insts",
207 .description = "Has i16/f16 instructions",
208 .dependencies = featureSet(&[_]Feature{}),
209 };
210 result[@intFromEnum(Feature.a16)] = .{
211 .llvm_name = "a16",
212 .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
213 .dependencies = featureSet(&[_]Feature{}),
214 };
215 result[@intFromEnum(Feature.add_no_carry_insts)] = .{
216 .llvm_name = "add-no-carry-insts",
217 .description = "Have VALU add/sub instructions without carry out",
218 .dependencies = featureSet(&[_]Feature{}),
219 };
220 result[@intFromEnum(Feature.agent_scope_fine_grained_remote_memory_atomics)] = .{
221 .llvm_name = "agent-scope-fine-grained-remote-memory-atomics",
222 .description = "Agent (device) scoped atomic operations, excluding those directly supported by PCIe (i.e. integer atomic add, exchange, and compare-and-swap), are functional for allocations in host or peer device memory.",
223 .dependencies = featureSet(&[_]Feature{}),
224 };
225 result[@intFromEnum(Feature.allocate1_5xvgprs)] = .{
226 .llvm_name = "allocate1_5xvgprs",
227 .description = "Has 50% more physical VGPRs and 50% larger allocation granule",
228 .dependencies = featureSet(&[_]Feature{}),
229 };
230 result[@intFromEnum(Feature.aperture_regs)] = .{
231 .llvm_name = "aperture-regs",
232 .description = "Has Memory Aperture Base and Size Registers",
233 .dependencies = featureSet(&[_]Feature{}),
234 };
235 result[@intFromEnum(Feature.architected_flat_scratch)] = .{
236 .llvm_name = "architected-flat-scratch",
237 .description = "Flat Scratch register is a readonly SPI initialized architected register",
238 .dependencies = featureSet(&[_]Feature{}),
239 };
240 result[@intFromEnum(Feature.architected_sgprs)] = .{
241 .llvm_name = "architected-sgprs",
242 .description = "Enable the architected SGPRs",
243 .dependencies = featureSet(&[_]Feature{}),
244 };
245 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
246 .llvm_name = "atomic-buffer-global-pk-add-f16-insts",
247 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
248 .dependencies = featureSet(&[_]Feature{
249 .flat_global_insts,
250 }),
251 };
252 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_no_rtn_insts)] = .{
253 .llvm_name = "atomic-buffer-global-pk-add-f16-no-rtn-insts",
254 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
255 .dependencies = featureSet(&[_]Feature{
256 .flat_global_insts,
257 }),
258 };
259 result[@intFromEnum(Feature.atomic_buffer_pk_add_bf16_inst)] = .{
260 .llvm_name = "atomic-buffer-pk-add-bf16-inst",
261 .description = "Has buffer_atomic_pk_add_bf16 instruction",
262 .dependencies = featureSet(&[_]Feature{}),
263 };
264 result[@intFromEnum(Feature.atomic_csub_no_rtn_insts)] = .{
265 .llvm_name = "atomic-csub-no-rtn-insts",
266 .description = "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value",
267 .dependencies = featureSet(&[_]Feature{}),
268 };
269 result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{
270 .llvm_name = "atomic-ds-pk-add-16-insts",
271 .description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions",
272 .dependencies = featureSet(&[_]Feature{}),
273 };
274 result[@intFromEnum(Feature.atomic_fadd_no_rtn_insts)] = .{
275 .llvm_name = "atomic-fadd-no-rtn-insts",
276 .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value",
277 .dependencies = featureSet(&[_]Feature{
278 .flat_global_insts,
279 }),
280 };
281 result[@intFromEnum(Feature.atomic_fadd_rtn_insts)] = .{
282 .llvm_name = "atomic-fadd-rtn-insts",
283 .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that return original value",
284 .dependencies = featureSet(&[_]Feature{
285 .flat_global_insts,
286 }),
287 };
288 result[@intFromEnum(Feature.atomic_flat_pk_add_16_insts)] = .{
289 .llvm_name = "atomic-flat-pk-add-16-insts",
290 .description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions",
291 .dependencies = featureSet(&[_]Feature{}),
292 };
293 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{
294 .llvm_name = "atomic-fmin-fmax-flat-f32",
295 .description = "Has flat memory instructions for atomicrmw fmin/fmax for float",
296 .dependencies = featureSet(&[_]Feature{}),
297 };
298 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{
299 .llvm_name = "atomic-fmin-fmax-flat-f64",
300 .description = "Has flat memory instructions for atomicrmw fmin/fmax for double",
301 .dependencies = featureSet(&[_]Feature{}),
302 };
303 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{
304 .llvm_name = "atomic-fmin-fmax-global-f32",
305 .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float",
306 .dependencies = featureSet(&[_]Feature{}),
307 };
308 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f64)] = .{
309 .llvm_name = "atomic-fmin-fmax-global-f64",
310 .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float",
311 .dependencies = featureSet(&[_]Feature{}),
312 };
313 result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{
314 .llvm_name = "atomic-global-pk-add-bf16-inst",
315 .description = "Has global_atomic_pk_add_bf16 instruction",
316 .dependencies = featureSet(&[_]Feature{
317 .flat_global_insts,
318 }),
319 };
320 result[@intFromEnum(Feature.auto_waitcnt_before_barrier)] = .{
321 .llvm_name = "auto-waitcnt-before-barrier",
322 .description = "Hardware automatically inserts waitcnt before barrier",
323 .dependencies = featureSet(&[_]Feature{}),
324 };
325 result[@intFromEnum(Feature.back_off_barrier)] = .{
326 .llvm_name = "back-off-barrier",
327 .description = "Hardware supports backing off s_barrier if an exception occurs",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
330 result[@intFromEnum(Feature.ci_insts)] = .{
331 .llvm_name = "ci-insts",
332 .description = "Additional instructions for CI+",
333 .dependencies = featureSet(&[_]Feature{}),
334 };
335 result[@intFromEnum(Feature.cumode)] = .{
336 .llvm_name = "cumode",
337 .description = "Enable CU wavefront execution mode",
338 .dependencies = featureSet(&[_]Feature{}),
339 };
340 result[@intFromEnum(Feature.default_component_broadcast)] = .{
341 .llvm_name = "default-component-broadcast",
342 .description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",
343 .dependencies = featureSet(&[_]Feature{}),
344 };
345 result[@intFromEnum(Feature.default_component_zero)] = .{
346 .llvm_name = "default-component-zero",
347 .description = "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)",
348 .dependencies = featureSet(&[_]Feature{}),
349 };
350 result[@intFromEnum(Feature.dl_insts)] = .{
351 .llvm_name = "dl-insts",
352 .description = "Has v_fmac_f32 and v_xnor_b32 instructions",
353 .dependencies = featureSet(&[_]Feature{}),
354 };
355 result[@intFromEnum(Feature.dot10_insts)] = .{
356 .llvm_name = "dot10-insts",
357 .description = "Has v_dot2_f32_f16 instruction",
358 .dependencies = featureSet(&[_]Feature{}),
359 };
360 result[@intFromEnum(Feature.dot11_insts)] = .{
361 .llvm_name = "dot11-insts",
362 .description = "Has v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8, v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8 instructions",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@intFromEnum(Feature.dot1_insts)] = .{
366 .llvm_name = "dot1-insts",
367 .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
368 .dependencies = featureSet(&[_]Feature{}),
369 };
370 result[@intFromEnum(Feature.dot2_insts)] = .{
371 .llvm_name = "dot2-insts",
372 .description = "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions",
373 .dependencies = featureSet(&[_]Feature{}),
374 };
375 result[@intFromEnum(Feature.dot3_insts)] = .{
376 .llvm_name = "dot3-insts",
377 .description = "Has v_dot8c_i32_i4 instruction",
378 .dependencies = featureSet(&[_]Feature{}),
379 };
380 result[@intFromEnum(Feature.dot4_insts)] = .{
381 .llvm_name = "dot4-insts",
382 .description = "Has v_dot2c_i32_i16 instruction",
383 .dependencies = featureSet(&[_]Feature{}),
384 };
385 result[@intFromEnum(Feature.dot5_insts)] = .{
386 .llvm_name = "dot5-insts",
387 .description = "Has v_dot2c_f32_f16 instruction",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@intFromEnum(Feature.dot6_insts)] = .{
391 .llvm_name = "dot6-insts",
392 .description = "Has v_dot4c_i32_i8 instruction",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
395 result[@intFromEnum(Feature.dot7_insts)] = .{
396 .llvm_name = "dot7-insts",
397 .description = "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
400 result[@intFromEnum(Feature.dot8_insts)] = .{
401 .llvm_name = "dot8-insts",
402 .description = "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions",
403 .dependencies = featureSet(&[_]Feature{}),
404 };
405 result[@intFromEnum(Feature.dot9_insts)] = .{
406 .llvm_name = "dot9-insts",
407 .description = "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@intFromEnum(Feature.dpp)] = .{
411 .llvm_name = "dpp",
412 .description = "Support DPP (Data Parallel Primitives) extension",
413 .dependencies = featureSet(&[_]Feature{}),
414 };
415 result[@intFromEnum(Feature.dpp8)] = .{
416 .llvm_name = "dpp8",
417 .description = "Support DPP8 (Data Parallel Primitives) extension",
418 .dependencies = featureSet(&[_]Feature{}),
419 };
420 result[@intFromEnum(Feature.dpp_64bit)] = .{
421 .llvm_name = "dpp-64bit",
422 .description = "Support DPP (Data Parallel Primitives) extension in DP ALU",
423 .dependencies = featureSet(&[_]Feature{}),
424 };
425 result[@intFromEnum(Feature.dpp_src1_sgpr)] = .{
426 .llvm_name = "dpp-src1-sgpr",
427 .description = "Support SGPR for Src1 of DPP instructions",
428 .dependencies = featureSet(&[_]Feature{}),
429 };
430 result[@intFromEnum(Feature.ds128)] = .{
431 .llvm_name = "enable-ds128",
432 .description = "Use ds_{read|write}_b128",
433 .dependencies = featureSet(&[_]Feature{}),
434 };
435 result[@intFromEnum(Feature.ds_src2_insts)] = .{
436 .llvm_name = "ds-src2-insts",
437 .description = "Has ds_*_src2 instructions",
438 .dependencies = featureSet(&[_]Feature{}),
439 };
440 result[@intFromEnum(Feature.extended_image_insts)] = .{
441 .llvm_name = "extended-image-insts",
442 .description = "Support mips != 0, lod != 0, gather4, and get_lod",
443 .dependencies = featureSet(&[_]Feature{}),
444 };
445 result[@intFromEnum(Feature.fast_denormal_f32)] = .{
446 .llvm_name = "fast-denormal-f32",
447 .description = "Enabling denormals does not cause f32 instructions to run at f64 rates",
448 .dependencies = featureSet(&[_]Feature{}),
449 };
450 result[@intFromEnum(Feature.fast_fmaf)] = .{
451 .llvm_name = "fast-fmaf",
452 .description = "Assuming f32 fma is at least as fast as mul + add",
453 .dependencies = featureSet(&[_]Feature{}),
454 };
455 result[@intFromEnum(Feature.flat_address_space)] = .{
456 .llvm_name = "flat-address-space",
457 .description = "Support flat address space",
458 .dependencies = featureSet(&[_]Feature{}),
459 };
460 result[@intFromEnum(Feature.flat_atomic_fadd_f32_inst)] = .{
461 .llvm_name = "flat-atomic-fadd-f32-inst",
462 .description = "Has flat_atomic_add_f32 instruction",
463 .dependencies = featureSet(&[_]Feature{}),
464 };
465 result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{
466 .llvm_name = "flat-buffer-global-fadd-f64-inst",
467 .description = "Has flat, buffer, and global instructions for f64 atomic fadd",
468 .dependencies = featureSet(&[_]Feature{}),
469 };
470 result[@intFromEnum(Feature.flat_for_global)] = .{
471 .llvm_name = "flat-for-global",
472 .description = "Force to generate flat instruction for global",
473 .dependencies = featureSet(&[_]Feature{}),
474 };
475 result[@intFromEnum(Feature.flat_global_insts)] = .{
476 .llvm_name = "flat-global-insts",
477 .description = "Have global_* flat memory instructions",
478 .dependencies = featureSet(&[_]Feature{}),
479 };
480 result[@intFromEnum(Feature.flat_inst_offsets)] = .{
481 .llvm_name = "flat-inst-offsets",
482 .description = "Flat instructions have immediate offset addressing mode",
483 .dependencies = featureSet(&[_]Feature{}),
484 };
485 result[@intFromEnum(Feature.flat_scratch)] = .{
486 .llvm_name = "enable-flat-scratch",
487 .description = "Use scratch_* flat memory instructions to access scratch",
488 .dependencies = featureSet(&[_]Feature{}),
489 };
490 result[@intFromEnum(Feature.flat_scratch_insts)] = .{
491 .llvm_name = "flat-scratch-insts",
492 .description = "Have scratch_* flat memory instructions",
493 .dependencies = featureSet(&[_]Feature{}),
494 };
495 result[@intFromEnum(Feature.flat_segment_offset_bug)] = .{
496 .llvm_name = "flat-segment-offset-bug",
497 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
498 .dependencies = featureSet(&[_]Feature{}),
499 };
500 result[@intFromEnum(Feature.fma_mix_insts)] = .{
501 .llvm_name = "fma-mix-insts",
502 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
503 .dependencies = featureSet(&[_]Feature{}),
504 };
505 result[@intFromEnum(Feature.fmacf64_inst)] = .{
506 .llvm_name = "fmacf64-inst",
507 .description = "Has v_fmac_f64 instruction",
508 .dependencies = featureSet(&[_]Feature{}),
509 };
510 result[@intFromEnum(Feature.fmaf)] = .{
511 .llvm_name = "fmaf",
512 .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
513 .dependencies = featureSet(&[_]Feature{}),
514 };
515 result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
516 .llvm_name = "force-store-sc0-sc1",
517 .description = "Has SC0 and SC1 on stores",
518 .dependencies = featureSet(&[_]Feature{}),
519 };
520 result[@intFromEnum(Feature.fp64)] = .{
521 .llvm_name = "fp64",
522 .description = "Enable double precision operations",
523 .dependencies = featureSet(&[_]Feature{}),
524 };
525 result[@intFromEnum(Feature.fp8_conversion_insts)] = .{
526 .llvm_name = "fp8-conversion-insts",
527 .description = "Has fp8 and bf8 conversion instructions",
528 .dependencies = featureSet(&[_]Feature{}),
529 };
530 result[@intFromEnum(Feature.fp8_insts)] = .{
531 .llvm_name = "fp8-insts",
532 .description = "Has fp8 and bf8 instructions",
533 .dependencies = featureSet(&[_]Feature{}),
534 };
535 result[@intFromEnum(Feature.full_rate_64_ops)] = .{
536 .llvm_name = "full-rate-64-ops",
537 .description = "Most fp64 instructions are full rate",
538 .dependencies = featureSet(&[_]Feature{}),
539 };
540 result[@intFromEnum(Feature.g16)] = .{
541 .llvm_name = "g16",
542 .description = "Support G16 for 16-bit gradient image operands",
543 .dependencies = featureSet(&[_]Feature{}),
544 };
545 result[@intFromEnum(Feature.gcn3_encoding)] = .{
546 .llvm_name = "gcn3-encoding",
547 .description = "Encoding format for VI",
548 .dependencies = featureSet(&[_]Feature{}),
549 };
550 result[@intFromEnum(Feature.gds)] = .{
551 .llvm_name = "gds",
552 .description = "Has Global Data Share",
553 .dependencies = featureSet(&[_]Feature{}),
554 };
555 result[@intFromEnum(Feature.get_wave_id_inst)] = .{
556 .llvm_name = "get-wave-id-inst",
557 .description = "Has s_get_waveid_in_workgroup instruction",
558 .dependencies = featureSet(&[_]Feature{}),
559 };
560 result[@intFromEnum(Feature.gfx10)] = .{
561 .llvm_name = "gfx10",
562 .description = "GFX10 GPU generation",
563 .dependencies = featureSet(&[_]Feature{
564 .@"16_bit_insts",
565 .a16,
566 .add_no_carry_insts,
567 .aperture_regs,
568 .atomic_fmin_fmax_flat_f32,
569 .atomic_fmin_fmax_flat_f64,
570 .atomic_fmin_fmax_global_f32,
571 .atomic_fmin_fmax_global_f64,
572 .ci_insts,
573 .default_component_zero,
574 .dpp,
575 .dpp8,
576 .extended_image_insts,
577 .fast_denormal_f32,
578 .fast_fmaf,
579 .flat_address_space,
580 .flat_global_insts,
581 .flat_inst_offsets,
582 .flat_scratch_insts,
583 .fma_mix_insts,
584 .fp64,
585 .g16,
586 .gds,
587 .gfx10_insts,
588 .gfx8_insts,
589 .gfx9_insts,
590 .gws,
591 .image_insts,
592 .int_clamp_insts,
593 .inv_2pi_inline_imm,
594 .localmemorysize65536,
595 .max_hard_clause_length_63,
596 .mimg_r128,
597 .movrel,
598 .no_data_dep_hazard,
599 .no_sdst_cmpx,
600 .pk_fmac_f16_inst,
601 .s_memrealtime,
602 .s_memtime_inst,
603 .sdwa,
604 .sdwa_omod,
605 .sdwa_scalar,
606 .sdwa_sdst,
607 .unaligned_buffer_access,
608 .unaligned_ds_access,
609 .vmem_write_vgpr_in_order,
610 .vop3_literal,
611 .vop3p,
612 .vscnt,
613 }),
614 };
615 result[@intFromEnum(Feature.gfx10_3_insts)] = .{
616 .llvm_name = "gfx10-3-insts",
617 .description = "Additional instructions for GFX10.3",
618 .dependencies = featureSet(&[_]Feature{}),
619 };
620 result[@intFromEnum(Feature.gfx10_a_encoding)] = .{
621 .llvm_name = "gfx10_a-encoding",
622 .description = "Has BVH ray tracing instructions",
623 .dependencies = featureSet(&[_]Feature{}),
624 };
625 result[@intFromEnum(Feature.gfx10_b_encoding)] = .{
626 .llvm_name = "gfx10_b-encoding",
627 .description = "Encoding format GFX10_B",
628 .dependencies = featureSet(&[_]Feature{}),
629 };
630 result[@intFromEnum(Feature.gfx10_insts)] = .{
631 .llvm_name = "gfx10-insts",
632 .description = "Additional instructions for GFX10+",
633 .dependencies = featureSet(&[_]Feature{}),
634 };
635 result[@intFromEnum(Feature.gfx11)] = .{
636 .llvm_name = "gfx11",
637 .description = "GFX11 GPU generation",
638 .dependencies = featureSet(&[_]Feature{
639 .@"16_bit_insts",
640 .a16,
641 .add_no_carry_insts,
642 .aperture_regs,
643 .atomic_fmin_fmax_flat_f32,
644 .atomic_fmin_fmax_global_f32,
645 .ci_insts,
646 .default_component_zero,
647 .dpp,
648 .dpp8,
649 .extended_image_insts,
650 .fast_denormal_f32,
651 .fast_fmaf,
652 .flat_address_space,
653 .flat_global_insts,
654 .flat_inst_offsets,
655 .flat_scratch_insts,
656 .fma_mix_insts,
657 .fp64,
658 .g16,
659 .gds,
660 .gfx10_3_insts,
661 .gfx10_a_encoding,
662 .gfx10_b_encoding,
663 .gfx10_insts,
664 .gfx11_insts,
665 .gfx8_insts,
666 .gfx9_insts,
667 .gws,
668 .int_clamp_insts,
669 .inv_2pi_inline_imm,
670 .localmemorysize65536,
671 .max_hard_clause_length_32,
672 .mimg_r128,
673 .movrel,
674 .no_data_dep_hazard,
675 .no_sdst_cmpx,
676 .pk_fmac_f16_inst,
677 .true16,
678 .unaligned_buffer_access,
679 .unaligned_ds_access,
680 .vmem_write_vgpr_in_order,
681 .vop3_literal,
682 .vop3p,
683 .vopd,
684 .vscnt,
685 }),
686 };
687 result[@intFromEnum(Feature.gfx11_insts)] = .{
688 .llvm_name = "gfx11-insts",
689 .description = "Additional instructions for GFX11+",
690 .dependencies = featureSet(&[_]Feature{}),
691 };
692 result[@intFromEnum(Feature.gfx12)] = .{
693 .llvm_name = "gfx12",
694 .description = "GFX12 GPU generation",
695 .dependencies = featureSet(&[_]Feature{
696 .@"16_bit_insts",
697 .a16,
698 .add_no_carry_insts,
699 .agent_scope_fine_grained_remote_memory_atomics,
700 .aperture_regs,
701 .atomic_fmin_fmax_flat_f32,
702 .atomic_fmin_fmax_global_f32,
703 .ci_insts,
704 .default_component_broadcast,
705 .dpp,
706 .dpp8,
707 .fast_denormal_f32,
708 .fast_fmaf,
709 .flat_address_space,
710 .flat_global_insts,
711 .flat_inst_offsets,
712 .flat_scratch_insts,
713 .fma_mix_insts,
714 .fp64,
715 .g16,
716 .gfx10_3_insts,
717 .gfx10_a_encoding,
718 .gfx10_b_encoding,
719 .gfx10_insts,
720 .gfx11_insts,
721 .gfx12_insts,
722 .gfx8_insts,
723 .gfx9_insts,
724 .int_clamp_insts,
725 .inv_2pi_inline_imm,
726 .localmemorysize65536,
727 .max_hard_clause_length_32,
728 .mimg_r128,
729 .movrel,
730 .no_data_dep_hazard,
731 .no_sdst_cmpx,
732 .pk_fmac_f16_inst,
733 .true16,
734 .unaligned_buffer_access,
735 .unaligned_ds_access,
736 .vop3_literal,
737 .vop3p,
738 .vopd,
739 .vscnt,
740 }),
741 };
742 result[@intFromEnum(Feature.gfx12_insts)] = .{
743 .llvm_name = "gfx12-insts",
744 .description = "Additional instructions for GFX12+",
745 .dependencies = featureSet(&[_]Feature{}),
746 };
747 result[@intFromEnum(Feature.gfx7_gfx8_gfx9_insts)] = .{
748 .llvm_name = "gfx7-gfx8-gfx9-insts",
749 .description = "Instructions shared in GFX7, GFX8, GFX9",
750 .dependencies = featureSet(&[_]Feature{}),
751 };
752 result[@intFromEnum(Feature.gfx8_insts)] = .{
753 .llvm_name = "gfx8-insts",
754 .description = "Additional instructions for GFX8+",
755 .dependencies = featureSet(&[_]Feature{}),
756 };
757 result[@intFromEnum(Feature.gfx9)] = .{
758 .llvm_name = "gfx9",
759 .description = "GFX9 GPU generation",
760 .dependencies = featureSet(&[_]Feature{
761 .@"16_bit_insts",
762 .a16,
763 .add_no_carry_insts,
764 .aperture_regs,
765 .ci_insts,
766 .default_component_zero,
767 .dpp,
768 .fast_denormal_f32,
769 .fast_fmaf,
770 .flat_address_space,
771 .flat_global_insts,
772 .flat_inst_offsets,
773 .flat_scratch_insts,
774 .fp64,
775 .gcn3_encoding,
776 .gfx7_gfx8_gfx9_insts,
777 .gfx8_insts,
778 .gfx9_insts,
779 .gws,
780 .int_clamp_insts,
781 .inv_2pi_inline_imm,
782 .localmemorysize65536,
783 .negative_scratch_offset_bug,
784 .r128_a16,
785 .s_memrealtime,
786 .s_memtime_inst,
787 .scalar_atomics,
788 .scalar_flat_scratch_insts,
789 .scalar_stores,
790 .sdwa,
791 .sdwa_omod,
792 .sdwa_scalar,
793 .sdwa_sdst,
794 .unaligned_buffer_access,
795 .unaligned_ds_access,
796 .vgpr_index_mode,
797 .vmem_write_vgpr_in_order,
798 .vop3p,
799 .wavefrontsize64,
800 .xnack_support,
801 }),
802 };
803 result[@intFromEnum(Feature.gfx90a_insts)] = .{
804 .llvm_name = "gfx90a-insts",
805 .description = "Additional instructions for GFX90A+",
806 .dependencies = featureSet(&[_]Feature{}),
807 };
808 result[@intFromEnum(Feature.gfx940_insts)] = .{
809 .llvm_name = "gfx940-insts",
810 .description = "Additional instructions for GFX940+",
811 .dependencies = featureSet(&[_]Feature{}),
812 };
813 result[@intFromEnum(Feature.gfx9_insts)] = .{
814 .llvm_name = "gfx9-insts",
815 .description = "Additional instructions for GFX9+",
816 .dependencies = featureSet(&[_]Feature{}),
817 };
818 result[@intFromEnum(Feature.gws)] = .{
819 .llvm_name = "gws",
820 .description = "Has Global Wave Sync",
821 .dependencies = featureSet(&[_]Feature{}),
822 };
823 result[@intFromEnum(Feature.half_rate_64_ops)] = .{
824 .llvm_name = "half-rate-64-ops",
825 .description = "Most fp64 instructions are half rate instead of quarter",
826 .dependencies = featureSet(&[_]Feature{}),
827 };
828 result[@intFromEnum(Feature.image_gather4_d16_bug)] = .{
829 .llvm_name = "image-gather4-d16-bug",
830 .description = "Image Gather4 D16 hardware bug",
831 .dependencies = featureSet(&[_]Feature{}),
832 };
833 result[@intFromEnum(Feature.image_insts)] = .{
834 .llvm_name = "image-insts",
835 .description = "Support image instructions",
836 .dependencies = featureSet(&[_]Feature{}),
837 };
838 result[@intFromEnum(Feature.image_store_d16_bug)] = .{
839 .llvm_name = "image-store-d16-bug",
840 .description = "Image Store D16 hardware bug",
841 .dependencies = featureSet(&[_]Feature{}),
842 };
843 result[@intFromEnum(Feature.inst_fwd_prefetch_bug)] = .{
844 .llvm_name = "inst-fwd-prefetch-bug",
845 .description = "S_INST_PREFETCH instruction causes shader to hang",
846 .dependencies = featureSet(&[_]Feature{}),
847 };
848 result[@intFromEnum(Feature.int_clamp_insts)] = .{
849 .llvm_name = "int-clamp-insts",
850 .description = "Support clamp for integer destination",
851 .dependencies = featureSet(&[_]Feature{}),
852 };
853 result[@intFromEnum(Feature.inv_2pi_inline_imm)] = .{
854 .llvm_name = "inv-2pi-inline-imm",
855 .description = "Has 1 / (2 * pi) as inline immediate",
856 .dependencies = featureSet(&[_]Feature{}),
857 };
858 result[@intFromEnum(Feature.kernarg_preload)] = .{
859 .llvm_name = "kernarg-preload",
860 .description = "Hardware supports preloading of kernel arguments in user SGPRs.",
861 .dependencies = featureSet(&[_]Feature{}),
862 };
863 result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{
864 .llvm_name = "lds-branch-vmem-war-hazard",
865 .description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
866 .dependencies = featureSet(&[_]Feature{}),
867 };
868 result[@intFromEnum(Feature.lds_misaligned_bug)] = .{
869 .llvm_name = "lds-misaligned-bug",
870 .description = "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode",
871 .dependencies = featureSet(&[_]Feature{}),
872 };
873 result[@intFromEnum(Feature.ldsbankcount16)] = .{
874 .llvm_name = "ldsbankcount16",
875 .description = "The number of LDS banks per compute unit.",
876 .dependencies = featureSet(&[_]Feature{}),
877 };
878 result[@intFromEnum(Feature.ldsbankcount32)] = .{
879 .llvm_name = "ldsbankcount32",
880 .description = "The number of LDS banks per compute unit.",
881 .dependencies = featureSet(&[_]Feature{}),
882 };
883 result[@intFromEnum(Feature.load_store_opt)] = .{
884 .llvm_name = "load-store-opt",
885 .description = "Enable SI load/store optimizer pass",
886 .dependencies = featureSet(&[_]Feature{}),
887 };
888 result[@intFromEnum(Feature.localmemorysize32768)] = .{
889 .llvm_name = "localmemorysize32768",
890 .description = "The size of local memory in bytes",
891 .dependencies = featureSet(&[_]Feature{}),
892 };
893 result[@intFromEnum(Feature.localmemorysize65536)] = .{
894 .llvm_name = "localmemorysize65536",
895 .description = "The size of local memory in bytes",
896 .dependencies = featureSet(&[_]Feature{}),
897 };
898 result[@intFromEnum(Feature.mad_intra_fwd_bug)] = .{
899 .llvm_name = "mad-intra-fwd-bug",
900 .description = "MAD_U64/I64 intra instruction forwarding bug",
901 .dependencies = featureSet(&[_]Feature{}),
902 };
903 result[@intFromEnum(Feature.mad_mac_f32_insts)] = .{
904 .llvm_name = "mad-mac-f32-insts",
905 .description = "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions",
906 .dependencies = featureSet(&[_]Feature{}),
907 };
908 result[@intFromEnum(Feature.mad_mix_insts)] = .{
909 .llvm_name = "mad-mix-insts",
910 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
911 .dependencies = featureSet(&[_]Feature{}),
912 };
913 result[@intFromEnum(Feature.mai_insts)] = .{
914 .llvm_name = "mai-insts",
915 .description = "Has mAI instructions",
916 .dependencies = featureSet(&[_]Feature{}),
917 };
918 result[@intFromEnum(Feature.max_hard_clause_length_32)] = .{
919 .llvm_name = "max-hard-clause-length-32",
920 .description = "Maximum number of instructions in an explicit S_CLAUSE is 32",
921 .dependencies = featureSet(&[_]Feature{}),
922 };
923 result[@intFromEnum(Feature.max_hard_clause_length_63)] = .{
924 .llvm_name = "max-hard-clause-length-63",
925 .description = "Maximum number of instructions in an explicit S_CLAUSE is 63",
926 .dependencies = featureSet(&[_]Feature{}),
927 };
928 result[@intFromEnum(Feature.max_private_element_size_16)] = .{
929 .llvm_name = "max-private-element-size-16",
930 .description = "Maximum private access size may be 16",
931 .dependencies = featureSet(&[_]Feature{}),
932 };
933 result[@intFromEnum(Feature.max_private_element_size_4)] = .{
934 .llvm_name = "max-private-element-size-4",
935 .description = "Maximum private access size may be 4",
936 .dependencies = featureSet(&[_]Feature{}),
937 };
938 result[@intFromEnum(Feature.max_private_element_size_8)] = .{
939 .llvm_name = "max-private-element-size-8",
940 .description = "Maximum private access size may be 8",
941 .dependencies = featureSet(&[_]Feature{}),
942 };
943 result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{
944 .llvm_name = "memory-atomic-fadd-f32-denormal-support",
945 .description = "global/flat/buffer atomic fadd for float supports denormal handling",
946 .dependencies = featureSet(&[_]Feature{}),
947 };
948 result[@intFromEnum(Feature.mfma_inline_literal_bug)] = .{
949 .llvm_name = "mfma-inline-literal-bug",
950 .description = "MFMA cannot use inline literal as SrcC",
951 .dependencies = featureSet(&[_]Feature{}),
952 };
953 result[@intFromEnum(Feature.mimg_r128)] = .{
954 .llvm_name = "mimg-r128",
955 .description = "Support 128-bit texture resources",
956 .dependencies = featureSet(&[_]Feature{}),
957 };
958 result[@intFromEnum(Feature.movrel)] = .{
959 .llvm_name = "movrel",
960 .description = "Has v_movrel*_b32 instructions",
961 .dependencies = featureSet(&[_]Feature{}),
962 };
963 result[@intFromEnum(Feature.msaa_load_dst_sel_bug)] = .{
964 .llvm_name = "msaa-load-dst-sel-bug",
965 .description = "MSAA loads not honoring dst_sel bug",
966 .dependencies = featureSet(&[_]Feature{}),
967 };
968 result[@intFromEnum(Feature.negative_scratch_offset_bug)] = .{
969 .llvm_name = "negative-scratch-offset-bug",
970 .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9",
971 .dependencies = featureSet(&[_]Feature{}),
972 };
973 result[@intFromEnum(Feature.negative_unaligned_scratch_offset_bug)] = .{
974 .llvm_name = "negative-unaligned-scratch-offset-bug",
975 .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10",
976 .dependencies = featureSet(&[_]Feature{}),
977 };
978 result[@intFromEnum(Feature.no_data_dep_hazard)] = .{
979 .llvm_name = "no-data-dep-hazard",
980 .description = "Does not need SW waitstates",
981 .dependencies = featureSet(&[_]Feature{}),
982 };
983 result[@intFromEnum(Feature.no_sdst_cmpx)] = .{
984 .llvm_name = "no-sdst-cmpx",
985 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
986 .dependencies = featureSet(&[_]Feature{}),
987 };
988 result[@intFromEnum(Feature.nsa_clause_bug)] = .{
989 .llvm_name = "nsa-clause-bug",
990 .description = "MIMG-NSA in a hard clause has unpredictable results on GFX10.1",
991 .dependencies = featureSet(&[_]Feature{}),
992 };
993 result[@intFromEnum(Feature.nsa_encoding)] = .{
994 .llvm_name = "nsa-encoding",
995 .description = "Support NSA encoding for image instructions",
996 .dependencies = featureSet(&[_]Feature{}),
997 };
998 result[@intFromEnum(Feature.nsa_to_vmem_bug)] = .{
999 .llvm_name = "nsa-to-vmem-bug",
1000 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
1001 .dependencies = featureSet(&[_]Feature{}),
1002 };
1003 result[@intFromEnum(Feature.offset_3f_bug)] = .{
1004 .llvm_name = "offset-3f-bug",
1005 .description = "Branch offset of 3f hardware bug",
1006 .dependencies = featureSet(&[_]Feature{}),
1007 };
1008 result[@intFromEnum(Feature.packed_fp32_ops)] = .{
1009 .llvm_name = "packed-fp32-ops",
1010 .description = "Support packed fp32 instructions",
1011 .dependencies = featureSet(&[_]Feature{}),
1012 };
1013 result[@intFromEnum(Feature.packed_tid)] = .{
1014 .llvm_name = "packed-tid",
1015 .description = "Workitem IDs are packed into v0 at kernel launch",
1016 .dependencies = featureSet(&[_]Feature{}),
1017 };
1018 result[@intFromEnum(Feature.partial_nsa_encoding)] = .{
1019 .llvm_name = "partial-nsa-encoding",
1020 .description = "Support partial NSA encoding for image instructions",
1021 .dependencies = featureSet(&[_]Feature{}),
1022 };
1023 result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
1024 .llvm_name = "pk-fmac-f16-inst",
1025 .description = "Has v_pk_fmac_f16 instruction",
1026 .dependencies = featureSet(&[_]Feature{}),
1027 };
1028 result[@intFromEnum(Feature.precise_memory)] = .{
1029 .llvm_name = "precise-memory",
1030 .description = "Enable precise memory mode",
1031 .dependencies = featureSet(&[_]Feature{}),
1032 };
1033 result[@intFromEnum(Feature.priv_enabled_trap2_nop_bug)] = .{
1034 .llvm_name = "priv-enabled-trap2-nop-bug",
1035 .description = "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug",
1036 .dependencies = featureSet(&[_]Feature{}),
1037 };
1038 result[@intFromEnum(Feature.promote_alloca)] = .{
1039 .llvm_name = "promote-alloca",
1040 .description = "Enable promote alloca pass",
1041 .dependencies = featureSet(&[_]Feature{}),
1042 };
1043 result[@intFromEnum(Feature.prt_strict_null)] = .{
1044 .llvm_name = "enable-prt-strict-null",
1045 .description = "Enable zeroing of result registers for sparse texture fetches",
1046 .dependencies = featureSet(&[_]Feature{}),
1047 };
1048 result[@intFromEnum(Feature.pseudo_scalar_trans)] = .{
1049 .llvm_name = "pseudo-scalar-trans",
1050 .description = "Has Pseudo Scalar Transcendental instructions",
1051 .dependencies = featureSet(&[_]Feature{}),
1052 };
1053 result[@intFromEnum(Feature.r128_a16)] = .{
1054 .llvm_name = "r128-a16",
1055 .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
1056 .dependencies = featureSet(&[_]Feature{}),
1057 };
1058 result[@intFromEnum(Feature.real_true16)] = .{
1059 .llvm_name = "real-true16",
1060 .description = "Use true 16-bit registers",
1061 .dependencies = featureSet(&[_]Feature{}),
1062 };
1063 result[@intFromEnum(Feature.required_export_priority)] = .{
1064 .llvm_name = "required-export-priority",
1065 .description = "Export priority must be explicitly manipulated on GFX11.5",
1066 .dependencies = featureSet(&[_]Feature{}),
1067 };
1068 result[@intFromEnum(Feature.requires_cov6)] = .{
1069 .llvm_name = "requires-cov6",
1070 .description = "Target Requires Code Object V6",
1071 .dependencies = featureSet(&[_]Feature{}),
1072 };
1073 result[@intFromEnum(Feature.restricted_soffset)] = .{
1074 .llvm_name = "restricted-soffset",
1075 .description = "Has restricted SOffset (immediate not supported).",
1076 .dependencies = featureSet(&[_]Feature{}),
1077 };
1078 result[@intFromEnum(Feature.s_memrealtime)] = .{
1079 .llvm_name = "s-memrealtime",
1080 .description = "Has s_memrealtime instruction",
1081 .dependencies = featureSet(&[_]Feature{}),
1082 };
1083 result[@intFromEnum(Feature.s_memtime_inst)] = .{
1084 .llvm_name = "s-memtime-inst",
1085 .description = "Has s_memtime instruction",
1086 .dependencies = featureSet(&[_]Feature{}),
1087 };
1088 result[@intFromEnum(Feature.salu_float)] = .{
1089 .llvm_name = "salu-float",
1090 .description = "Has SALU floating point instructions",
1091 .dependencies = featureSet(&[_]Feature{}),
1092 };
1093 result[@intFromEnum(Feature.scalar_atomics)] = .{
1094 .llvm_name = "scalar-atomics",
1095 .description = "Has atomic scalar memory instructions",
1096 .dependencies = featureSet(&[_]Feature{}),
1097 };
1098 result[@intFromEnum(Feature.scalar_dwordx3_loads)] = .{
1099 .llvm_name = "scalar-dwordx3-loads",
1100 .description = "Has 96-bit scalar load instructions",
1101 .dependencies = featureSet(&[_]Feature{}),
1102 };
1103 result[@intFromEnum(Feature.scalar_flat_scratch_insts)] = .{
1104 .llvm_name = "scalar-flat-scratch-insts",
1105 .description = "Have s_scratch_* flat memory instructions",
1106 .dependencies = featureSet(&[_]Feature{}),
1107 };
1108 result[@intFromEnum(Feature.scalar_stores)] = .{
1109 .llvm_name = "scalar-stores",
1110 .description = "Has store scalar memory instructions",
1111 .dependencies = featureSet(&[_]Feature{}),
1112 };
1113 result[@intFromEnum(Feature.sdwa)] = .{
1114 .llvm_name = "sdwa",
1115 .description = "Support SDWA (Sub-DWORD Addressing) extension",
1116 .dependencies = featureSet(&[_]Feature{}),
1117 };
1118 result[@intFromEnum(Feature.sdwa_mav)] = .{
1119 .llvm_name = "sdwa-mav",
1120 .description = "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension",
1121 .dependencies = featureSet(&[_]Feature{}),
1122 };
1123 result[@intFromEnum(Feature.sdwa_omod)] = .{
1124 .llvm_name = "sdwa-omod",
1125 .description = "Support OMod with SDWA (Sub-DWORD Addressing) extension",
1126 .dependencies = featureSet(&[_]Feature{}),
1127 };
1128 result[@intFromEnum(Feature.sdwa_out_mods_vopc)] = .{
1129 .llvm_name = "sdwa-out-mods-vopc",
1130 .description = "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension",
1131 .dependencies = featureSet(&[_]Feature{}),
1132 };
1133 result[@intFromEnum(Feature.sdwa_scalar)] = .{
1134 .llvm_name = "sdwa-scalar",
1135 .description = "Support scalar register with SDWA (Sub-DWORD Addressing) extension",
1136 .dependencies = featureSet(&[_]Feature{}),
1137 };
1138 result[@intFromEnum(Feature.sdwa_sdst)] = .{
1139 .llvm_name = "sdwa-sdst",
1140 .description = "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension",
1141 .dependencies = featureSet(&[_]Feature{}),
1142 };
1143 result[@intFromEnum(Feature.sea_islands)] = .{
1144 .llvm_name = "sea-islands",
1145 .description = "SEA_ISLANDS GPU generation",
1146 .dependencies = featureSet(&[_]Feature{
1147 .atomic_fmin_fmax_flat_f32,
1148 .atomic_fmin_fmax_flat_f64,
1149 .atomic_fmin_fmax_global_f32,
1150 .atomic_fmin_fmax_global_f64,
1151 .ci_insts,
1152 .default_component_zero,
1153 .ds_src2_insts,
1154 .extended_image_insts,
1155 .flat_address_space,
1156 .fp64,
1157 .gds,
1158 .gfx7_gfx8_gfx9_insts,
1159 .gws,
1160 .image_insts,
1161 .localmemorysize65536,
1162 .mad_mac_f32_insts,
1163 .mimg_r128,
1164 .movrel,
1165 .s_memtime_inst,
1166 .trig_reduced_range,
1167 .unaligned_buffer_access,
1168 .vmem_write_vgpr_in_order,
1169 .wavefrontsize64,
1170 }),
1171 };
1172 result[@intFromEnum(Feature.sgpr_init_bug)] = .{
1173 .llvm_name = "sgpr-init-bug",
1174 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
1175 .dependencies = featureSet(&[_]Feature{}),
1176 };
1177 result[@intFromEnum(Feature.shader_cycles_hi_lo_registers)] = .{
1178 .llvm_name = "shader-cycles-hi-lo-registers",
1179 .description = "Has SHADER_CYCLES_HI/LO hardware registers",
1180 .dependencies = featureSet(&[_]Feature{}),
1181 };
1182 result[@intFromEnum(Feature.shader_cycles_register)] = .{
1183 .llvm_name = "shader-cycles-register",
1184 .description = "Has SHADER_CYCLES hardware register",
1185 .dependencies = featureSet(&[_]Feature{}),
1186 };
1187 result[@intFromEnum(Feature.si_scheduler)] = .{
1188 .llvm_name = "si-scheduler",
1189 .description = "Enable SI Machine Scheduler",
1190 .dependencies = featureSet(&[_]Feature{}),
1191 };
1192 result[@intFromEnum(Feature.smem_to_vector_write_hazard)] = .{
1193 .llvm_name = "smem-to-vector-write-hazard",
1194 .description = "s_load_dword followed by v_cmp page faults",
1195 .dependencies = featureSet(&[_]Feature{}),
1196 };
1197 result[@intFromEnum(Feature.southern_islands)] = .{
1198 .llvm_name = "southern-islands",
1199 .description = "SOUTHERN_ISLANDS GPU generation",
1200 .dependencies = featureSet(&[_]Feature{
1201 .atomic_fmin_fmax_global_f32,
1202 .atomic_fmin_fmax_global_f64,
1203 .default_component_zero,
1204 .ds_src2_insts,
1205 .extended_image_insts,
1206 .fp64,
1207 .gds,
1208 .gws,
1209 .image_insts,
1210 .ldsbankcount32,
1211 .localmemorysize32768,
1212 .mad_mac_f32_insts,
1213 .mimg_r128,
1214 .movrel,
1215 .s_memtime_inst,
1216 .trig_reduced_range,
1217 .vmem_write_vgpr_in_order,
1218 .wavefrontsize64,
1219 }),
1220 };
1221 result[@intFromEnum(Feature.sramecc)] = .{
1222 .llvm_name = "sramecc",
1223 .description = "Enable SRAMECC",
1224 .dependencies = featureSet(&[_]Feature{}),
1225 };
1226 result[@intFromEnum(Feature.sramecc_support)] = .{
1227 .llvm_name = "sramecc-support",
1228 .description = "Hardware supports SRAMECC",
1229 .dependencies = featureSet(&[_]Feature{}),
1230 };
1231 result[@intFromEnum(Feature.tgsplit)] = .{
1232 .llvm_name = "tgsplit",
1233 .description = "Enable threadgroup split execution",
1234 .dependencies = featureSet(&[_]Feature{}),
1235 };
1236 result[@intFromEnum(Feature.trap_handler)] = .{
1237 .llvm_name = "trap-handler",
1238 .description = "Trap handler support",
1239 .dependencies = featureSet(&[_]Feature{}),
1240 };
1241 result[@intFromEnum(Feature.trig_reduced_range)] = .{
1242 .llvm_name = "trig-reduced-range",
1243 .description = "Requires use of fract on arguments to trig instructions",
1244 .dependencies = featureSet(&[_]Feature{}),
1245 };
1246 result[@intFromEnum(Feature.true16)] = .{
1247 .llvm_name = "true16",
1248 .description = "True 16-bit operand instructions",
1249 .dependencies = featureSet(&[_]Feature{}),
1250 };
1251 result[@intFromEnum(Feature.unaligned_access_mode)] = .{
1252 .llvm_name = "unaligned-access-mode",
1253 .description = "Enable unaligned global, local and region loads and stores if the hardware supports it",
1254 .dependencies = featureSet(&[_]Feature{}),
1255 };
1256 result[@intFromEnum(Feature.unaligned_buffer_access)] = .{
1257 .llvm_name = "unaligned-buffer-access",
1258 .description = "Hardware supports unaligned global loads and stores",
1259 .dependencies = featureSet(&[_]Feature{}),
1260 };
1261 result[@intFromEnum(Feature.unaligned_ds_access)] = .{
1262 .llvm_name = "unaligned-ds-access",
1263 .description = "Hardware supports unaligned local and region loads and stores",
1264 .dependencies = featureSet(&[_]Feature{}),
1265 };
1266 result[@intFromEnum(Feature.unaligned_scratch_access)] = .{
1267 .llvm_name = "unaligned-scratch-access",
1268 .description = "Support unaligned scratch loads and stores",
1269 .dependencies = featureSet(&[_]Feature{}),
1270 };
1271 result[@intFromEnum(Feature.unpacked_d16_vmem)] = .{
1272 .llvm_name = "unpacked-d16-vmem",
1273 .description = "Has unpacked d16 vmem instructions",
1274 .dependencies = featureSet(&[_]Feature{}),
1275 };
1276 result[@intFromEnum(Feature.unsafe_ds_offset_folding)] = .{
1277 .llvm_name = "unsafe-ds-offset-folding",
1278 .description = "Force using DS instruction immediate offsets on SI",
1279 .dependencies = featureSet(&[_]Feature{}),
1280 };
1281 result[@intFromEnum(Feature.user_sgpr_init16_bug)] = .{
1282 .llvm_name = "user-sgpr-init16-bug",
1283 .description = "Bug requiring at least 16 user+system SGPRs to be enabled",
1284 .dependencies = featureSet(&[_]Feature{}),
1285 };
1286 result[@intFromEnum(Feature.valu_trans_use_hazard)] = .{
1287 .llvm_name = "valu-trans-use-hazard",
1288 .description = "Hazard when TRANS instructions are closely followed by a use of the result",
1289 .dependencies = featureSet(&[_]Feature{}),
1290 };
1291 result[@intFromEnum(Feature.vcmpx_exec_war_hazard)] = .{
1292 .llvm_name = "vcmpx-exec-war-hazard",
1293 .description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
1294 .dependencies = featureSet(&[_]Feature{}),
1295 };
1296 result[@intFromEnum(Feature.vcmpx_permlane_hazard)] = .{
1297 .llvm_name = "vcmpx-permlane-hazard",
1298 .description = "TODO: describe me",
1299 .dependencies = featureSet(&[_]Feature{}),
1300 };
1301 result[@intFromEnum(Feature.vgpr_index_mode)] = .{
1302 .llvm_name = "vgpr-index-mode",
1303 .description = "Has VGPR mode register indexing",
1304 .dependencies = featureSet(&[_]Feature{}),
1305 };
1306 result[@intFromEnum(Feature.vgpr_singleuse_hint)] = .{
1307 .llvm_name = "vgpr-singleuse-hint",
1308 .description = "Has single-use VGPR hint instructions",
1309 .dependencies = featureSet(&[_]Feature{}),
1310 };
1311 result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{
1312 .llvm_name = "vmem-to-scalar-write-hazard",
1313 .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
1314 .dependencies = featureSet(&[_]Feature{}),
1315 };
1316 result[@intFromEnum(Feature.vmem_write_vgpr_in_order)] = .{
1317 .llvm_name = "vmem-write-vgpr-in-order",
1318 .description = "VMEM instructions of the same type write VGPR results in order",
1319 .dependencies = featureSet(&[_]Feature{}),
1320 };
1321 result[@intFromEnum(Feature.volcanic_islands)] = .{
1322 .llvm_name = "volcanic-islands",
1323 .description = "VOLCANIC_ISLANDS GPU generation",
1324 .dependencies = featureSet(&[_]Feature{
1325 .@"16_bit_insts",
1326 .ci_insts,
1327 .default_component_zero,
1328 .dpp,
1329 .ds_src2_insts,
1330 .extended_image_insts,
1331 .fast_denormal_f32,
1332 .flat_address_space,
1333 .fp64,
1334 .gcn3_encoding,
1335 .gds,
1336 .gfx7_gfx8_gfx9_insts,
1337 .gfx8_insts,
1338 .gws,
1339 .image_insts,
1340 .int_clamp_insts,
1341 .inv_2pi_inline_imm,
1342 .localmemorysize65536,
1343 .mad_mac_f32_insts,
1344 .mimg_r128,
1345 .movrel,
1346 .s_memrealtime,
1347 .s_memtime_inst,
1348 .scalar_stores,
1349 .sdwa,
1350 .sdwa_mav,
1351 .sdwa_out_mods_vopc,
1352 .trig_reduced_range,
1353 .unaligned_buffer_access,
1354 .vgpr_index_mode,
1355 .vmem_write_vgpr_in_order,
1356 .wavefrontsize64,
1357 }),
1358 };
1359 result[@intFromEnum(Feature.vop3_literal)] = .{
1360 .llvm_name = "vop3-literal",
1361 .description = "Can use one literal in VOP3",
1362 .dependencies = featureSet(&[_]Feature{}),
1363 };
1364 result[@intFromEnum(Feature.vop3p)] = .{
1365 .llvm_name = "vop3p",
1366 .description = "Has VOP3P packed instructions",
1367 .dependencies = featureSet(&[_]Feature{}),
1368 };
1369 result[@intFromEnum(Feature.vopd)] = .{
1370 .llvm_name = "vopd",
1371 .description = "Has VOPD dual issue wave32 instructions",
1372 .dependencies = featureSet(&[_]Feature{}),
1373 };
1374 result[@intFromEnum(Feature.vscnt)] = .{
1375 .llvm_name = "vscnt",
1376 .description = "Has separate store vscnt counter",
1377 .dependencies = featureSet(&[_]Feature{}),
1378 };
1379 result[@intFromEnum(Feature.wavefrontsize16)] = .{
1380 .llvm_name = "wavefrontsize16",
1381 .description = "The number of threads per wavefront",
1382 .dependencies = featureSet(&[_]Feature{}),
1383 };
1384 result[@intFromEnum(Feature.wavefrontsize32)] = .{
1385 .llvm_name = "wavefrontsize32",
1386 .description = "The number of threads per wavefront",
1387 .dependencies = featureSet(&[_]Feature{}),
1388 };
1389 result[@intFromEnum(Feature.wavefrontsize64)] = .{
1390 .llvm_name = "wavefrontsize64",
1391 .description = "The number of threads per wavefront",
1392 .dependencies = featureSet(&[_]Feature{}),
1393 };
1394 result[@intFromEnum(Feature.xnack)] = .{
1395 .llvm_name = "xnack",
1396 .description = "Enable XNACK support",
1397 .dependencies = featureSet(&[_]Feature{}),
1398 };
1399 result[@intFromEnum(Feature.xnack_support)] = .{
1400 .llvm_name = "xnack-support",
1401 .description = "Hardware supports XNACK",
1402 .dependencies = featureSet(&[_]Feature{}),
1403 };
1404 const ti = @typeInfo(Feature);
1405 for (&result, 0..) |*elem, i| {
1406 elem.index = i;
1407 elem.name = ti.@"enum".fields[i].name;
1408 }
1409 break :blk result;
1410};
1411
1412pub const cpu = struct {
1413 pub const bonaire = CpuModel{
1414 .name = "bonaire",
1415 .llvm_name = "bonaire",
1416 .features = featureSet(&[_]Feature{
1417 .ldsbankcount32,
1418 .sea_islands,
1419 }),
1420 };
1421 pub const carrizo = CpuModel{
1422 .name = "carrizo",
1423 .llvm_name = "carrizo",
1424 .features = featureSet(&[_]Feature{
1425 .fast_fmaf,
1426 .half_rate_64_ops,
1427 .ldsbankcount32,
1428 .unpacked_d16_vmem,
1429 .volcanic_islands,
1430 .xnack_support,
1431 }),
1432 };
1433 pub const fiji = CpuModel{
1434 .name = "fiji",
1435 .llvm_name = "fiji",
1436 .features = featureSet(&[_]Feature{
1437 .ldsbankcount32,
1438 .unpacked_d16_vmem,
1439 .volcanic_islands,
1440 }),
1441 };
1442 pub const generic = CpuModel{
1443 .name = "generic",
1444 .llvm_name = "generic",
1445 .features = featureSet(&[_]Feature{
1446 .gds,
1447 .gws,
1448 .wavefrontsize64,
1449 }),
1450 };
1451 pub const generic_hsa = CpuModel{
1452 .name = "generic_hsa",
1453 .llvm_name = "generic-hsa",
1454 .features = featureSet(&[_]Feature{
1455 .flat_address_space,
1456 .gds,
1457 .gws,
1458 .wavefrontsize64,
1459 }),
1460 };
1461 pub const gfx1010 = CpuModel{
1462 .name = "gfx1010",
1463 .llvm_name = "gfx1010",
1464 .features = featureSet(&[_]Feature{
1465 .back_off_barrier,
1466 .dl_insts,
1467 .ds_src2_insts,
1468 .flat_segment_offset_bug,
1469 .get_wave_id_inst,
1470 .gfx10,
1471 .inst_fwd_prefetch_bug,
1472 .lds_branch_vmem_war_hazard,
1473 .lds_misaligned_bug,
1474 .ldsbankcount32,
1475 .mad_mac_f32_insts,
1476 .negative_unaligned_scratch_offset_bug,
1477 .nsa_clause_bug,
1478 .nsa_encoding,
1479 .nsa_to_vmem_bug,
1480 .offset_3f_bug,
1481 .scalar_atomics,
1482 .scalar_flat_scratch_insts,
1483 .scalar_stores,
1484 .smem_to_vector_write_hazard,
1485 .vcmpx_exec_war_hazard,
1486 .vcmpx_permlane_hazard,
1487 .vmem_to_scalar_write_hazard,
1488 .xnack_support,
1489 }),
1490 };
1491 pub const gfx1011 = CpuModel{
1492 .name = "gfx1011",
1493 .llvm_name = "gfx1011",
1494 .features = featureSet(&[_]Feature{
1495 .back_off_barrier,
1496 .dl_insts,
1497 .dot10_insts,
1498 .dot1_insts,
1499 .dot2_insts,
1500 .dot5_insts,
1501 .dot6_insts,
1502 .dot7_insts,
1503 .ds_src2_insts,
1504 .flat_segment_offset_bug,
1505 .get_wave_id_inst,
1506 .gfx10,
1507 .inst_fwd_prefetch_bug,
1508 .lds_branch_vmem_war_hazard,
1509 .lds_misaligned_bug,
1510 .ldsbankcount32,
1511 .mad_mac_f32_insts,
1512 .negative_unaligned_scratch_offset_bug,
1513 .nsa_clause_bug,
1514 .nsa_encoding,
1515 .nsa_to_vmem_bug,
1516 .offset_3f_bug,
1517 .scalar_atomics,
1518 .scalar_flat_scratch_insts,
1519 .scalar_stores,
1520 .smem_to_vector_write_hazard,
1521 .vcmpx_exec_war_hazard,
1522 .vcmpx_permlane_hazard,
1523 .vmem_to_scalar_write_hazard,
1524 .xnack_support,
1525 }),
1526 };
1527 pub const gfx1012 = CpuModel{
1528 .name = "gfx1012",
1529 .llvm_name = "gfx1012",
1530 .features = featureSet(&[_]Feature{
1531 .back_off_barrier,
1532 .dl_insts,
1533 .dot10_insts,
1534 .dot1_insts,
1535 .dot2_insts,
1536 .dot5_insts,
1537 .dot6_insts,
1538 .dot7_insts,
1539 .ds_src2_insts,
1540 .flat_segment_offset_bug,
1541 .get_wave_id_inst,
1542 .gfx10,
1543 .inst_fwd_prefetch_bug,
1544 .lds_branch_vmem_war_hazard,
1545 .lds_misaligned_bug,
1546 .ldsbankcount32,
1547 .mad_mac_f32_insts,
1548 .negative_unaligned_scratch_offset_bug,
1549 .nsa_clause_bug,
1550 .nsa_encoding,
1551 .nsa_to_vmem_bug,
1552 .offset_3f_bug,
1553 .scalar_atomics,
1554 .scalar_flat_scratch_insts,
1555 .scalar_stores,
1556 .smem_to_vector_write_hazard,
1557 .vcmpx_exec_war_hazard,
1558 .vcmpx_permlane_hazard,
1559 .vmem_to_scalar_write_hazard,
1560 .xnack_support,
1561 }),
1562 };
1563 pub const gfx1013 = CpuModel{
1564 .name = "gfx1013",
1565 .llvm_name = "gfx1013",
1566 .features = featureSet(&[_]Feature{
1567 .back_off_barrier,
1568 .dl_insts,
1569 .ds_src2_insts,
1570 .flat_segment_offset_bug,
1571 .get_wave_id_inst,
1572 .gfx10,
1573 .gfx10_a_encoding,
1574 .inst_fwd_prefetch_bug,
1575 .lds_branch_vmem_war_hazard,
1576 .lds_misaligned_bug,
1577 .ldsbankcount32,
1578 .mad_mac_f32_insts,
1579 .negative_unaligned_scratch_offset_bug,
1580 .nsa_clause_bug,
1581 .nsa_encoding,
1582 .nsa_to_vmem_bug,
1583 .offset_3f_bug,
1584 .scalar_atomics,
1585 .scalar_flat_scratch_insts,
1586 .scalar_stores,
1587 .smem_to_vector_write_hazard,
1588 .vcmpx_exec_war_hazard,
1589 .vcmpx_permlane_hazard,
1590 .vmem_to_scalar_write_hazard,
1591 .xnack_support,
1592 }),
1593 };
1594 pub const gfx1030 = CpuModel{
1595 .name = "gfx1030",
1596 .llvm_name = "gfx1030",
1597 .features = featureSet(&[_]Feature{
1598 .back_off_barrier,
1599 .dl_insts,
1600 .dot10_insts,
1601 .dot1_insts,
1602 .dot2_insts,
1603 .dot5_insts,
1604 .dot6_insts,
1605 .dot7_insts,
1606 .gfx10,
1607 .gfx10_3_insts,
1608 .gfx10_a_encoding,
1609 .gfx10_b_encoding,
1610 .ldsbankcount32,
1611 .nsa_encoding,
1612 .shader_cycles_register,
1613 }),
1614 };
1615 pub const gfx1031 = CpuModel{
1616 .name = "gfx1031",
1617 .llvm_name = "gfx1031",
1618 .features = featureSet(&[_]Feature{
1619 .back_off_barrier,
1620 .dl_insts,
1621 .dot10_insts,
1622 .dot1_insts,
1623 .dot2_insts,
1624 .dot5_insts,
1625 .dot6_insts,
1626 .dot7_insts,
1627 .gfx10,
1628 .gfx10_3_insts,
1629 .gfx10_a_encoding,
1630 .gfx10_b_encoding,
1631 .ldsbankcount32,
1632 .nsa_encoding,
1633 .shader_cycles_register,
1634 }),
1635 };
1636 pub const gfx1032 = CpuModel{
1637 .name = "gfx1032",
1638 .llvm_name = "gfx1032",
1639 .features = featureSet(&[_]Feature{
1640 .back_off_barrier,
1641 .dl_insts,
1642 .dot10_insts,
1643 .dot1_insts,
1644 .dot2_insts,
1645 .dot5_insts,
1646 .dot6_insts,
1647 .dot7_insts,
1648 .gfx10,
1649 .gfx10_3_insts,
1650 .gfx10_a_encoding,
1651 .gfx10_b_encoding,
1652 .ldsbankcount32,
1653 .nsa_encoding,
1654 .shader_cycles_register,
1655 }),
1656 };
1657 pub const gfx1033 = CpuModel{
1658 .name = "gfx1033",
1659 .llvm_name = "gfx1033",
1660 .features = featureSet(&[_]Feature{
1661 .back_off_barrier,
1662 .dl_insts,
1663 .dot10_insts,
1664 .dot1_insts,
1665 .dot2_insts,
1666 .dot5_insts,
1667 .dot6_insts,
1668 .dot7_insts,
1669 .gfx10,
1670 .gfx10_3_insts,
1671 .gfx10_a_encoding,
1672 .gfx10_b_encoding,
1673 .ldsbankcount32,
1674 .nsa_encoding,
1675 .shader_cycles_register,
1676 }),
1677 };
1678 pub const gfx1034 = CpuModel{
1679 .name = "gfx1034",
1680 .llvm_name = "gfx1034",
1681 .features = featureSet(&[_]Feature{
1682 .back_off_barrier,
1683 .dl_insts,
1684 .dot10_insts,
1685 .dot1_insts,
1686 .dot2_insts,
1687 .dot5_insts,
1688 .dot6_insts,
1689 .dot7_insts,
1690 .gfx10,
1691 .gfx10_3_insts,
1692 .gfx10_a_encoding,
1693 .gfx10_b_encoding,
1694 .ldsbankcount32,
1695 .nsa_encoding,
1696 .shader_cycles_register,
1697 }),
1698 };
1699 pub const gfx1035 = CpuModel{
1700 .name = "gfx1035",
1701 .llvm_name = "gfx1035",
1702 .features = featureSet(&[_]Feature{
1703 .back_off_barrier,
1704 .dl_insts,
1705 .dot10_insts,
1706 .dot1_insts,
1707 .dot2_insts,
1708 .dot5_insts,
1709 .dot6_insts,
1710 .dot7_insts,
1711 .gfx10,
1712 .gfx10_3_insts,
1713 .gfx10_a_encoding,
1714 .gfx10_b_encoding,
1715 .ldsbankcount32,
1716 .nsa_encoding,
1717 .shader_cycles_register,
1718 }),
1719 };
1720 pub const gfx1036 = CpuModel{
1721 .name = "gfx1036",
1722 .llvm_name = "gfx1036",
1723 .features = featureSet(&[_]Feature{
1724 .back_off_barrier,
1725 .dl_insts,
1726 .dot10_insts,
1727 .dot1_insts,
1728 .dot2_insts,
1729 .dot5_insts,
1730 .dot6_insts,
1731 .dot7_insts,
1732 .gfx10,
1733 .gfx10_3_insts,
1734 .gfx10_a_encoding,
1735 .gfx10_b_encoding,
1736 .ldsbankcount32,
1737 .nsa_encoding,
1738 .shader_cycles_register,
1739 }),
1740 };
1741 pub const gfx10_1_generic = CpuModel{
1742 .name = "gfx10_1_generic",
1743 .llvm_name = "gfx10-1-generic",
1744 .features = featureSet(&[_]Feature{
1745 .back_off_barrier,
1746 .dl_insts,
1747 .ds_src2_insts,
1748 .flat_segment_offset_bug,
1749 .get_wave_id_inst,
1750 .gfx10,
1751 .inst_fwd_prefetch_bug,
1752 .lds_branch_vmem_war_hazard,
1753 .lds_misaligned_bug,
1754 .ldsbankcount32,
1755 .mad_mac_f32_insts,
1756 .negative_unaligned_scratch_offset_bug,
1757 .nsa_clause_bug,
1758 .nsa_encoding,
1759 .nsa_to_vmem_bug,
1760 .offset_3f_bug,
1761 .requires_cov6,
1762 .scalar_atomics,
1763 .scalar_flat_scratch_insts,
1764 .scalar_stores,
1765 .smem_to_vector_write_hazard,
1766 .vcmpx_exec_war_hazard,
1767 .vcmpx_permlane_hazard,
1768 .vmem_to_scalar_write_hazard,
1769 .xnack_support,
1770 }),
1771 };
1772 pub const gfx10_3_generic = CpuModel{
1773 .name = "gfx10_3_generic",
1774 .llvm_name = "gfx10-3-generic",
1775 .features = featureSet(&[_]Feature{
1776 .back_off_barrier,
1777 .dl_insts,
1778 .dot10_insts,
1779 .dot1_insts,
1780 .dot2_insts,
1781 .dot5_insts,
1782 .dot6_insts,
1783 .dot7_insts,
1784 .gfx10,
1785 .gfx10_3_insts,
1786 .gfx10_a_encoding,
1787 .gfx10_b_encoding,
1788 .ldsbankcount32,
1789 .nsa_encoding,
1790 .requires_cov6,
1791 .shader_cycles_register,
1792 }),
1793 };
1794 pub const gfx1100 = CpuModel{
1795 .name = "gfx1100",
1796 .llvm_name = "gfx1100",
1797 .features = featureSet(&[_]Feature{
1798 .allocate1_5xvgprs,
1799 .architected_flat_scratch,
1800 .atomic_fadd_no_rtn_insts,
1801 .atomic_fadd_rtn_insts,
1802 .dl_insts,
1803 .dot10_insts,
1804 .dot5_insts,
1805 .dot7_insts,
1806 .dot8_insts,
1807 .dot9_insts,
1808 .flat_atomic_fadd_f32_inst,
1809 .gfx11,
1810 .image_insts,
1811 .ldsbankcount32,
1812 .mad_intra_fwd_bug,
1813 .memory_atomic_fadd_f32_denormal_support,
1814 .msaa_load_dst_sel_bug,
1815 .nsa_encoding,
1816 .packed_tid,
1817 .partial_nsa_encoding,
1818 .priv_enabled_trap2_nop_bug,
1819 .shader_cycles_register,
1820 .user_sgpr_init16_bug,
1821 .valu_trans_use_hazard,
1822 .vcmpx_permlane_hazard,
1823 }),
1824 };
1825 pub const gfx1101 = CpuModel{
1826 .name = "gfx1101",
1827 .llvm_name = "gfx1101",
1828 .features = featureSet(&[_]Feature{
1829 .allocate1_5xvgprs,
1830 .architected_flat_scratch,
1831 .atomic_fadd_no_rtn_insts,
1832 .atomic_fadd_rtn_insts,
1833 .dl_insts,
1834 .dot10_insts,
1835 .dot5_insts,
1836 .dot7_insts,
1837 .dot8_insts,
1838 .dot9_insts,
1839 .flat_atomic_fadd_f32_inst,
1840 .gfx11,
1841 .image_insts,
1842 .ldsbankcount32,
1843 .mad_intra_fwd_bug,
1844 .memory_atomic_fadd_f32_denormal_support,
1845 .msaa_load_dst_sel_bug,
1846 .nsa_encoding,
1847 .packed_tid,
1848 .partial_nsa_encoding,
1849 .priv_enabled_trap2_nop_bug,
1850 .shader_cycles_register,
1851 .valu_trans_use_hazard,
1852 .vcmpx_permlane_hazard,
1853 }),
1854 };
1855 pub const gfx1102 = CpuModel{
1856 .name = "gfx1102",
1857 .llvm_name = "gfx1102",
1858 .features = featureSet(&[_]Feature{
1859 .architected_flat_scratch,
1860 .atomic_fadd_no_rtn_insts,
1861 .atomic_fadd_rtn_insts,
1862 .dl_insts,
1863 .dot10_insts,
1864 .dot5_insts,
1865 .dot7_insts,
1866 .dot8_insts,
1867 .dot9_insts,
1868 .flat_atomic_fadd_f32_inst,
1869 .gfx11,
1870 .image_insts,
1871 .ldsbankcount32,
1872 .mad_intra_fwd_bug,
1873 .memory_atomic_fadd_f32_denormal_support,
1874 .msaa_load_dst_sel_bug,
1875 .nsa_encoding,
1876 .packed_tid,
1877 .partial_nsa_encoding,
1878 .priv_enabled_trap2_nop_bug,
1879 .shader_cycles_register,
1880 .user_sgpr_init16_bug,
1881 .valu_trans_use_hazard,
1882 .vcmpx_permlane_hazard,
1883 }),
1884 };
1885 pub const gfx1103 = CpuModel{
1886 .name = "gfx1103",
1887 .llvm_name = "gfx1103",
1888 .features = featureSet(&[_]Feature{
1889 .architected_flat_scratch,
1890 .atomic_fadd_no_rtn_insts,
1891 .atomic_fadd_rtn_insts,
1892 .dl_insts,
1893 .dot10_insts,
1894 .dot5_insts,
1895 .dot7_insts,
1896 .dot8_insts,
1897 .dot9_insts,
1898 .flat_atomic_fadd_f32_inst,
1899 .gfx11,
1900 .image_insts,
1901 .ldsbankcount32,
1902 .mad_intra_fwd_bug,
1903 .memory_atomic_fadd_f32_denormal_support,
1904 .msaa_load_dst_sel_bug,
1905 .nsa_encoding,
1906 .packed_tid,
1907 .partial_nsa_encoding,
1908 .priv_enabled_trap2_nop_bug,
1909 .shader_cycles_register,
1910 .valu_trans_use_hazard,
1911 .vcmpx_permlane_hazard,
1912 }),
1913 };
1914 pub const gfx1150 = CpuModel{
1915 .name = "gfx1150",
1916 .llvm_name = "gfx1150",
1917 .features = featureSet(&[_]Feature{
1918 .architected_flat_scratch,
1919 .atomic_fadd_no_rtn_insts,
1920 .atomic_fadd_rtn_insts,
1921 .dl_insts,
1922 .dot10_insts,
1923 .dot5_insts,
1924 .dot7_insts,
1925 .dot8_insts,
1926 .dot9_insts,
1927 .dpp_src1_sgpr,
1928 .flat_atomic_fadd_f32_inst,
1929 .gfx11,
1930 .image_insts,
1931 .ldsbankcount32,
1932 .memory_atomic_fadd_f32_denormal_support,
1933 .nsa_encoding,
1934 .packed_tid,
1935 .partial_nsa_encoding,
1936 .required_export_priority,
1937 .salu_float,
1938 .shader_cycles_register,
1939 .vcmpx_permlane_hazard,
1940 .vgpr_singleuse_hint,
1941 }),
1942 };
1943 pub const gfx1151 = CpuModel{
1944 .name = "gfx1151",
1945 .llvm_name = "gfx1151",
1946 .features = featureSet(&[_]Feature{
1947 .allocate1_5xvgprs,
1948 .architected_flat_scratch,
1949 .atomic_fadd_no_rtn_insts,
1950 .atomic_fadd_rtn_insts,
1951 .dl_insts,
1952 .dot10_insts,
1953 .dot5_insts,
1954 .dot7_insts,
1955 .dot8_insts,
1956 .dot9_insts,
1957 .dpp_src1_sgpr,
1958 .flat_atomic_fadd_f32_inst,
1959 .gfx11,
1960 .image_insts,
1961 .ldsbankcount32,
1962 .memory_atomic_fadd_f32_denormal_support,
1963 .nsa_encoding,
1964 .packed_tid,
1965 .partial_nsa_encoding,
1966 .required_export_priority,
1967 .salu_float,
1968 .shader_cycles_register,
1969 .vcmpx_permlane_hazard,
1970 .vgpr_singleuse_hint,
1971 }),
1972 };
1973 pub const gfx1152 = CpuModel{
1974 .name = "gfx1152",
1975 .llvm_name = "gfx1152",
1976 .features = featureSet(&[_]Feature{
1977 .architected_flat_scratch,
1978 .atomic_fadd_no_rtn_insts,
1979 .atomic_fadd_rtn_insts,
1980 .dl_insts,
1981 .dot10_insts,
1982 .dot5_insts,
1983 .dot7_insts,
1984 .dot8_insts,
1985 .dot9_insts,
1986 .dpp_src1_sgpr,
1987 .flat_atomic_fadd_f32_inst,
1988 .gfx11,
1989 .image_insts,
1990 .ldsbankcount32,
1991 .memory_atomic_fadd_f32_denormal_support,
1992 .nsa_encoding,
1993 .packed_tid,
1994 .partial_nsa_encoding,
1995 .required_export_priority,
1996 .salu_float,
1997 .shader_cycles_register,
1998 .vcmpx_permlane_hazard,
1999 .vgpr_singleuse_hint,
2000 }),
2001 };
2002 pub const gfx11_generic = CpuModel{
2003 .name = "gfx11_generic",
2004 .llvm_name = "gfx11-generic",
2005 .features = featureSet(&[_]Feature{
2006 .architected_flat_scratch,
2007 .atomic_fadd_no_rtn_insts,
2008 .atomic_fadd_rtn_insts,
2009 .dl_insts,
2010 .dot10_insts,
2011 .dot5_insts,
2012 .dot7_insts,
2013 .dot8_insts,
2014 .dot9_insts,
2015 .flat_atomic_fadd_f32_inst,
2016 .gfx11,
2017 .image_insts,
2018 .ldsbankcount32,
2019 .mad_intra_fwd_bug,
2020 .memory_atomic_fadd_f32_denormal_support,
2021 .msaa_load_dst_sel_bug,
2022 .nsa_encoding,
2023 .packed_tid,
2024 .partial_nsa_encoding,
2025 .priv_enabled_trap2_nop_bug,
2026 .required_export_priority,
2027 .requires_cov6,
2028 .shader_cycles_register,
2029 .user_sgpr_init16_bug,
2030 .valu_trans_use_hazard,
2031 .vcmpx_permlane_hazard,
2032 }),
2033 };
2034 pub const gfx1200 = CpuModel{
2035 .name = "gfx1200",
2036 .llvm_name = "gfx1200",
2037 .features = featureSet(&[_]Feature{
2038 .allocate1_5xvgprs,
2039 .architected_flat_scratch,
2040 .architected_sgprs,
2041 .atomic_buffer_global_pk_add_f16_insts,
2042 .atomic_buffer_pk_add_bf16_inst,
2043 .atomic_ds_pk_add_16_insts,
2044 .atomic_fadd_no_rtn_insts,
2045 .atomic_fadd_rtn_insts,
2046 .atomic_flat_pk_add_16_insts,
2047 .atomic_global_pk_add_bf16_inst,
2048 .dl_insts,
2049 .dot10_insts,
2050 .dot11_insts,
2051 .dot7_insts,
2052 .dot8_insts,
2053 .dot9_insts,
2054 .dpp_src1_sgpr,
2055 .extended_image_insts,
2056 .flat_atomic_fadd_f32_inst,
2057 .fp8_conversion_insts,
2058 .gfx12,
2059 .image_insts,
2060 .ldsbankcount32,
2061 .memory_atomic_fadd_f32_denormal_support,
2062 .nsa_encoding,
2063 .packed_tid,
2064 .partial_nsa_encoding,
2065 .pseudo_scalar_trans,
2066 .restricted_soffset,
2067 .salu_float,
2068 .scalar_dwordx3_loads,
2069 .shader_cycles_hi_lo_registers,
2070 .vcmpx_permlane_hazard,
2071 .vgpr_singleuse_hint,
2072 }),
2073 };
2074 pub const gfx1201 = CpuModel{
2075 .name = "gfx1201",
2076 .llvm_name = "gfx1201",
2077 .features = featureSet(&[_]Feature{
2078 .allocate1_5xvgprs,
2079 .architected_flat_scratch,
2080 .architected_sgprs,
2081 .atomic_buffer_global_pk_add_f16_insts,
2082 .atomic_buffer_pk_add_bf16_inst,
2083 .atomic_ds_pk_add_16_insts,
2084 .atomic_fadd_no_rtn_insts,
2085 .atomic_fadd_rtn_insts,
2086 .atomic_flat_pk_add_16_insts,
2087 .atomic_global_pk_add_bf16_inst,
2088 .dl_insts,
2089 .dot10_insts,
2090 .dot11_insts,
2091 .dot7_insts,
2092 .dot8_insts,
2093 .dot9_insts,
2094 .dpp_src1_sgpr,
2095 .extended_image_insts,
2096 .flat_atomic_fadd_f32_inst,
2097 .fp8_conversion_insts,
2098 .gfx12,
2099 .image_insts,
2100 .ldsbankcount32,
2101 .memory_atomic_fadd_f32_denormal_support,
2102 .nsa_encoding,
2103 .packed_tid,
2104 .partial_nsa_encoding,
2105 .pseudo_scalar_trans,
2106 .restricted_soffset,
2107 .salu_float,
2108 .scalar_dwordx3_loads,
2109 .shader_cycles_hi_lo_registers,
2110 .vcmpx_permlane_hazard,
2111 .vgpr_singleuse_hint,
2112 }),
2113 };
2114 pub const gfx12_generic = CpuModel{
2115 .name = "gfx12_generic",
2116 .llvm_name = "gfx12-generic",
2117 .features = featureSet(&[_]Feature{
2118 .allocate1_5xvgprs,
2119 .architected_flat_scratch,
2120 .architected_sgprs,
2121 .atomic_buffer_global_pk_add_f16_insts,
2122 .atomic_buffer_pk_add_bf16_inst,
2123 .atomic_ds_pk_add_16_insts,
2124 .atomic_fadd_no_rtn_insts,
2125 .atomic_fadd_rtn_insts,
2126 .atomic_flat_pk_add_16_insts,
2127 .atomic_global_pk_add_bf16_inst,
2128 .dl_insts,
2129 .dot10_insts,
2130 .dot11_insts,
2131 .dot7_insts,
2132 .dot8_insts,
2133 .dot9_insts,
2134 .dpp_src1_sgpr,
2135 .extended_image_insts,
2136 .flat_atomic_fadd_f32_inst,
2137 .fp8_conversion_insts,
2138 .gfx12,
2139 .image_insts,
2140 .ldsbankcount32,
2141 .memory_atomic_fadd_f32_denormal_support,
2142 .nsa_encoding,
2143 .packed_tid,
2144 .partial_nsa_encoding,
2145 .pseudo_scalar_trans,
2146 .requires_cov6,
2147 .restricted_soffset,
2148 .salu_float,
2149 .scalar_dwordx3_loads,
2150 .shader_cycles_hi_lo_registers,
2151 .vcmpx_permlane_hazard,
2152 .vgpr_singleuse_hint,
2153 }),
2154 };
2155 pub const gfx600 = CpuModel{
2156 .name = "gfx600",
2157 .llvm_name = "gfx600",
2158 .features = featureSet(&[_]Feature{
2159 .fast_fmaf,
2160 .half_rate_64_ops,
2161 .southern_islands,
2162 }),
2163 };
2164 pub const gfx601 = CpuModel{
2165 .name = "gfx601",
2166 .llvm_name = "gfx601",
2167 .features = featureSet(&[_]Feature{
2168 .southern_islands,
2169 }),
2170 };
2171 pub const gfx602 = CpuModel{
2172 .name = "gfx602",
2173 .llvm_name = "gfx602",
2174 .features = featureSet(&[_]Feature{
2175 .southern_islands,
2176 }),
2177 };
2178 pub const gfx700 = CpuModel{
2179 .name = "gfx700",
2180 .llvm_name = "gfx700",
2181 .features = featureSet(&[_]Feature{
2182 .ldsbankcount32,
2183 .sea_islands,
2184 }),
2185 };
2186 pub const gfx701 = CpuModel{
2187 .name = "gfx701",
2188 .llvm_name = "gfx701",
2189 .features = featureSet(&[_]Feature{
2190 .fast_fmaf,
2191 .half_rate_64_ops,
2192 .ldsbankcount32,
2193 .sea_islands,
2194 }),
2195 };
2196 pub const gfx702 = CpuModel{
2197 .name = "gfx702",
2198 .llvm_name = "gfx702",
2199 .features = featureSet(&[_]Feature{
2200 .fast_fmaf,
2201 .ldsbankcount16,
2202 .sea_islands,
2203 }),
2204 };
2205 pub const gfx703 = CpuModel{
2206 .name = "gfx703",
2207 .llvm_name = "gfx703",
2208 .features = featureSet(&[_]Feature{
2209 .ldsbankcount16,
2210 .sea_islands,
2211 }),
2212 };
2213 pub const gfx704 = CpuModel{
2214 .name = "gfx704",
2215 .llvm_name = "gfx704",
2216 .features = featureSet(&[_]Feature{
2217 .ldsbankcount32,
2218 .sea_islands,
2219 }),
2220 };
2221 pub const gfx705 = CpuModel{
2222 .name = "gfx705",
2223 .llvm_name = "gfx705",
2224 .features = featureSet(&[_]Feature{
2225 .ldsbankcount16,
2226 .sea_islands,
2227 }),
2228 };
2229 pub const gfx801 = CpuModel{
2230 .name = "gfx801",
2231 .llvm_name = "gfx801",
2232 .features = featureSet(&[_]Feature{
2233 .fast_fmaf,
2234 .half_rate_64_ops,
2235 .ldsbankcount32,
2236 .unpacked_d16_vmem,
2237 .volcanic_islands,
2238 .xnack_support,
2239 }),
2240 };
2241 pub const gfx802 = CpuModel{
2242 .name = "gfx802",
2243 .llvm_name = "gfx802",
2244 .features = featureSet(&[_]Feature{
2245 .ldsbankcount32,
2246 .sgpr_init_bug,
2247 .unpacked_d16_vmem,
2248 .volcanic_islands,
2249 }),
2250 };
2251 pub const gfx803 = CpuModel{
2252 .name = "gfx803",
2253 .llvm_name = "gfx803",
2254 .features = featureSet(&[_]Feature{
2255 .ldsbankcount32,
2256 .unpacked_d16_vmem,
2257 .volcanic_islands,
2258 }),
2259 };
2260 pub const gfx805 = CpuModel{
2261 .name = "gfx805",
2262 .llvm_name = "gfx805",
2263 .features = featureSet(&[_]Feature{
2264 .ldsbankcount32,
2265 .sgpr_init_bug,
2266 .unpacked_d16_vmem,
2267 .volcanic_islands,
2268 }),
2269 };
2270 pub const gfx810 = CpuModel{
2271 .name = "gfx810",
2272 .llvm_name = "gfx810",
2273 .features = featureSet(&[_]Feature{
2274 .image_gather4_d16_bug,
2275 .image_store_d16_bug,
2276 .ldsbankcount16,
2277 .volcanic_islands,
2278 .xnack_support,
2279 }),
2280 };
2281 pub const gfx900 = CpuModel{
2282 .name = "gfx900",
2283 .llvm_name = "gfx900",
2284 .features = featureSet(&[_]Feature{
2285 .ds_src2_insts,
2286 .extended_image_insts,
2287 .gds,
2288 .gfx9,
2289 .image_gather4_d16_bug,
2290 .image_insts,
2291 .ldsbankcount32,
2292 .mad_mac_f32_insts,
2293 .mad_mix_insts,
2294 }),
2295 };
2296 pub const gfx902 = CpuModel{
2297 .name = "gfx902",
2298 .llvm_name = "gfx902",
2299 .features = featureSet(&[_]Feature{
2300 .ds_src2_insts,
2301 .extended_image_insts,
2302 .gds,
2303 .gfx9,
2304 .image_gather4_d16_bug,
2305 .image_insts,
2306 .ldsbankcount32,
2307 .mad_mac_f32_insts,
2308 .mad_mix_insts,
2309 }),
2310 };
2311 pub const gfx904 = CpuModel{
2312 .name = "gfx904",
2313 .llvm_name = "gfx904",
2314 .features = featureSet(&[_]Feature{
2315 .ds_src2_insts,
2316 .extended_image_insts,
2317 .fma_mix_insts,
2318 .gds,
2319 .gfx9,
2320 .image_gather4_d16_bug,
2321 .image_insts,
2322 .ldsbankcount32,
2323 .mad_mac_f32_insts,
2324 }),
2325 };
2326 pub const gfx906 = CpuModel{
2327 .name = "gfx906",
2328 .llvm_name = "gfx906",
2329 .features = featureSet(&[_]Feature{
2330 .dl_insts,
2331 .dot10_insts,
2332 .dot1_insts,
2333 .dot2_insts,
2334 .dot7_insts,
2335 .ds_src2_insts,
2336 .extended_image_insts,
2337 .fma_mix_insts,
2338 .gds,
2339 .gfx9,
2340 .half_rate_64_ops,
2341 .image_gather4_d16_bug,
2342 .image_insts,
2343 .ldsbankcount32,
2344 .mad_mac_f32_insts,
2345 .sramecc_support,
2346 }),
2347 };
2348 pub const gfx908 = CpuModel{
2349 .name = "gfx908",
2350 .llvm_name = "gfx908",
2351 .features = featureSet(&[_]Feature{
2352 .atomic_buffer_global_pk_add_f16_no_rtn_insts,
2353 .atomic_fadd_no_rtn_insts,
2354 .dl_insts,
2355 .dot10_insts,
2356 .dot1_insts,
2357 .dot2_insts,
2358 .dot3_insts,
2359 .dot4_insts,
2360 .dot5_insts,
2361 .dot6_insts,
2362 .dot7_insts,
2363 .ds_src2_insts,
2364 .extended_image_insts,
2365 .fma_mix_insts,
2366 .gds,
2367 .gfx9,
2368 .half_rate_64_ops,
2369 .image_gather4_d16_bug,
2370 .image_insts,
2371 .ldsbankcount32,
2372 .mad_mac_f32_insts,
2373 .mai_insts,
2374 .mfma_inline_literal_bug,
2375 .pk_fmac_f16_inst,
2376 .sramecc_support,
2377 }),
2378 };
2379 pub const gfx909 = CpuModel{
2380 .name = "gfx909",
2381 .llvm_name = "gfx909",
2382 .features = featureSet(&[_]Feature{
2383 .ds_src2_insts,
2384 .extended_image_insts,
2385 .gds,
2386 .gfx9,
2387 .image_gather4_d16_bug,
2388 .image_insts,
2389 .ldsbankcount32,
2390 .mad_mac_f32_insts,
2391 .mad_mix_insts,
2392 }),
2393 };
2394 pub const gfx90a = CpuModel{
2395 .name = "gfx90a",
2396 .llvm_name = "gfx90a",
2397 .features = featureSet(&[_]Feature{
2398 .atomic_buffer_global_pk_add_f16_insts,
2399 .atomic_fadd_no_rtn_insts,
2400 .atomic_fadd_rtn_insts,
2401 .atomic_fmin_fmax_flat_f64,
2402 .atomic_fmin_fmax_global_f64,
2403 .back_off_barrier,
2404 .dl_insts,
2405 .dot10_insts,
2406 .dot1_insts,
2407 .dot2_insts,
2408 .dot3_insts,
2409 .dot4_insts,
2410 .dot5_insts,
2411 .dot6_insts,
2412 .dot7_insts,
2413 .dpp_64bit,
2414 .flat_buffer_global_fadd_f64_inst,
2415 .fma_mix_insts,
2416 .fmacf64_inst,
2417 .full_rate_64_ops,
2418 .gfx9,
2419 .gfx90a_insts,
2420 .image_insts,
2421 .kernarg_preload,
2422 .ldsbankcount32,
2423 .mad_mac_f32_insts,
2424 .mai_insts,
2425 .packed_fp32_ops,
2426 .packed_tid,
2427 .pk_fmac_f16_inst,
2428 .sramecc_support,
2429 }),
2430 };
2431 pub const gfx90c = CpuModel{
2432 .name = "gfx90c",
2433 .llvm_name = "gfx90c",
2434 .features = featureSet(&[_]Feature{
2435 .ds_src2_insts,
2436 .extended_image_insts,
2437 .gds,
2438 .gfx9,
2439 .image_gather4_d16_bug,
2440 .image_insts,
2441 .ldsbankcount32,
2442 .mad_mac_f32_insts,
2443 .mad_mix_insts,
2444 }),
2445 };
2446 pub const gfx940 = CpuModel{
2447 .name = "gfx940",
2448 .llvm_name = "gfx940",
2449 .features = featureSet(&[_]Feature{
2450 .agent_scope_fine_grained_remote_memory_atomics,
2451 .architected_flat_scratch,
2452 .atomic_buffer_global_pk_add_f16_insts,
2453 .atomic_ds_pk_add_16_insts,
2454 .atomic_fadd_no_rtn_insts,
2455 .atomic_fadd_rtn_insts,
2456 .atomic_flat_pk_add_16_insts,
2457 .atomic_fmin_fmax_flat_f64,
2458 .atomic_fmin_fmax_global_f64,
2459 .atomic_global_pk_add_bf16_inst,
2460 .back_off_barrier,
2461 .dl_insts,
2462 .dot10_insts,
2463 .dot1_insts,
2464 .dot2_insts,
2465 .dot3_insts,
2466 .dot4_insts,
2467 .dot5_insts,
2468 .dot6_insts,
2469 .dot7_insts,
2470 .dpp_64bit,
2471 .flat_atomic_fadd_f32_inst,
2472 .flat_buffer_global_fadd_f64_inst,
2473 .fma_mix_insts,
2474 .fmacf64_inst,
2475 .force_store_sc0_sc1,
2476 .fp8_conversion_insts,
2477 .fp8_insts,
2478 .full_rate_64_ops,
2479 .gfx9,
2480 .gfx90a_insts,
2481 .gfx940_insts,
2482 .kernarg_preload,
2483 .ldsbankcount32,
2484 .mai_insts,
2485 .memory_atomic_fadd_f32_denormal_support,
2486 .packed_fp32_ops,
2487 .packed_tid,
2488 .pk_fmac_f16_inst,
2489 .sramecc_support,
2490 }),
2491 };
2492 pub const gfx941 = CpuModel{
2493 .name = "gfx941",
2494 .llvm_name = "gfx941",
2495 .features = featureSet(&[_]Feature{
2496 .agent_scope_fine_grained_remote_memory_atomics,
2497 .architected_flat_scratch,
2498 .atomic_buffer_global_pk_add_f16_insts,
2499 .atomic_ds_pk_add_16_insts,
2500 .atomic_fadd_no_rtn_insts,
2501 .atomic_fadd_rtn_insts,
2502 .atomic_flat_pk_add_16_insts,
2503 .atomic_fmin_fmax_flat_f64,
2504 .atomic_fmin_fmax_global_f64,
2505 .atomic_global_pk_add_bf16_inst,
2506 .back_off_barrier,
2507 .dl_insts,
2508 .dot10_insts,
2509 .dot1_insts,
2510 .dot2_insts,
2511 .dot3_insts,
2512 .dot4_insts,
2513 .dot5_insts,
2514 .dot6_insts,
2515 .dot7_insts,
2516 .dpp_64bit,
2517 .flat_atomic_fadd_f32_inst,
2518 .flat_buffer_global_fadd_f64_inst,
2519 .fma_mix_insts,
2520 .fmacf64_inst,
2521 .force_store_sc0_sc1,
2522 .fp8_conversion_insts,
2523 .fp8_insts,
2524 .full_rate_64_ops,
2525 .gfx9,
2526 .gfx90a_insts,
2527 .gfx940_insts,
2528 .kernarg_preload,
2529 .ldsbankcount32,
2530 .mai_insts,
2531 .memory_atomic_fadd_f32_denormal_support,
2532 .packed_fp32_ops,
2533 .packed_tid,
2534 .pk_fmac_f16_inst,
2535 .sramecc_support,
2536 }),
2537 };
2538 pub const gfx942 = CpuModel{
2539 .name = "gfx942",
2540 .llvm_name = "gfx942",
2541 .features = featureSet(&[_]Feature{
2542 .agent_scope_fine_grained_remote_memory_atomics,
2543 .architected_flat_scratch,
2544 .atomic_buffer_global_pk_add_f16_insts,
2545 .atomic_ds_pk_add_16_insts,
2546 .atomic_fadd_no_rtn_insts,
2547 .atomic_fadd_rtn_insts,
2548 .atomic_flat_pk_add_16_insts,
2549 .atomic_fmin_fmax_flat_f64,
2550 .atomic_fmin_fmax_global_f64,
2551 .atomic_global_pk_add_bf16_inst,
2552 .back_off_barrier,
2553 .dl_insts,
2554 .dot10_insts,
2555 .dot1_insts,
2556 .dot2_insts,
2557 .dot3_insts,
2558 .dot4_insts,
2559 .dot5_insts,
2560 .dot6_insts,
2561 .dot7_insts,
2562 .dpp_64bit,
2563 .flat_atomic_fadd_f32_inst,
2564 .flat_buffer_global_fadd_f64_inst,
2565 .fma_mix_insts,
2566 .fmacf64_inst,
2567 .fp8_conversion_insts,
2568 .fp8_insts,
2569 .full_rate_64_ops,
2570 .gfx9,
2571 .gfx90a_insts,
2572 .gfx940_insts,
2573 .kernarg_preload,
2574 .ldsbankcount32,
2575 .mai_insts,
2576 .memory_atomic_fadd_f32_denormal_support,
2577 .packed_fp32_ops,
2578 .packed_tid,
2579 .pk_fmac_f16_inst,
2580 .sramecc_support,
2581 }),
2582 };
2583 pub const gfx9_generic = CpuModel{
2584 .name = "gfx9_generic",
2585 .llvm_name = "gfx9-generic",
2586 .features = featureSet(&[_]Feature{
2587 .ds_src2_insts,
2588 .extended_image_insts,
2589 .gds,
2590 .gfx9,
2591 .image_gather4_d16_bug,
2592 .image_insts,
2593 .ldsbankcount32,
2594 .mad_mac_f32_insts,
2595 .requires_cov6,
2596 }),
2597 };
2598 pub const hainan = CpuModel{
2599 .name = "hainan",
2600 .llvm_name = "hainan",
2601 .features = featureSet(&[_]Feature{
2602 .southern_islands,
2603 }),
2604 };
2605 pub const hawaii = CpuModel{
2606 .name = "hawaii",
2607 .llvm_name = "hawaii",
2608 .features = featureSet(&[_]Feature{
2609 .fast_fmaf,
2610 .half_rate_64_ops,
2611 .ldsbankcount32,
2612 .sea_islands,
2613 }),
2614 };
2615 pub const iceland = CpuModel{
2616 .name = "iceland",
2617 .llvm_name = "iceland",
2618 .features = featureSet(&[_]Feature{
2619 .ldsbankcount32,
2620 .sgpr_init_bug,
2621 .unpacked_d16_vmem,
2622 .volcanic_islands,
2623 }),
2624 };
2625 pub const kabini = CpuModel{
2626 .name = "kabini",
2627 .llvm_name = "kabini",
2628 .features = featureSet(&[_]Feature{
2629 .ldsbankcount16,
2630 .sea_islands,
2631 }),
2632 };
2633 pub const kaveri = CpuModel{
2634 .name = "kaveri",
2635 .llvm_name = "kaveri",
2636 .features = featureSet(&[_]Feature{
2637 .ldsbankcount32,
2638 .sea_islands,
2639 }),
2640 };
2641 pub const mullins = CpuModel{
2642 .name = "mullins",
2643 .llvm_name = "mullins",
2644 .features = featureSet(&[_]Feature{
2645 .ldsbankcount16,
2646 .sea_islands,
2647 }),
2648 };
2649 pub const oland = CpuModel{
2650 .name = "oland",
2651 .llvm_name = "oland",
2652 .features = featureSet(&[_]Feature{
2653 .southern_islands,
2654 }),
2655 };
2656 pub const pitcairn = CpuModel{
2657 .name = "pitcairn",
2658 .llvm_name = "pitcairn",
2659 .features = featureSet(&[_]Feature{
2660 .southern_islands,
2661 }),
2662 };
2663 pub const polaris10 = CpuModel{
2664 .name = "polaris10",
2665 .llvm_name = "polaris10",
2666 .features = featureSet(&[_]Feature{
2667 .ldsbankcount32,
2668 .unpacked_d16_vmem,
2669 .volcanic_islands,
2670 }),
2671 };
2672 pub const polaris11 = CpuModel{
2673 .name = "polaris11",
2674 .llvm_name = "polaris11",
2675 .features = featureSet(&[_]Feature{
2676 .ldsbankcount32,
2677 .unpacked_d16_vmem,
2678 .volcanic_islands,
2679 }),
2680 };
2681 pub const stoney = CpuModel{
2682 .name = "stoney",
2683 .llvm_name = "stoney",
2684 .features = featureSet(&[_]Feature{
2685 .image_gather4_d16_bug,
2686 .image_store_d16_bug,
2687 .ldsbankcount16,
2688 .volcanic_islands,
2689 .xnack_support,
2690 }),
2691 };
2692 pub const tahiti = CpuModel{
2693 .name = "tahiti",
2694 .llvm_name = "tahiti",
2695 .features = featureSet(&[_]Feature{
2696 .fast_fmaf,
2697 .half_rate_64_ops,
2698 .southern_islands,
2699 }),
2700 };
2701 pub const tonga = CpuModel{
2702 .name = "tonga",
2703 .llvm_name = "tonga",
2704 .features = featureSet(&[_]Feature{
2705 .ldsbankcount32,
2706 .sgpr_init_bug,
2707 .unpacked_d16_vmem,
2708 .volcanic_islands,
2709 }),
2710 };
2711 pub const tongapro = CpuModel{
2712 .name = "tongapro",
2713 .llvm_name = "tongapro",
2714 .features = featureSet(&[_]Feature{
2715 .ldsbankcount32,
2716 .sgpr_init_bug,
2717 .unpacked_d16_vmem,
2718 .volcanic_islands,
2719 }),
2720 };
2721 pub const verde = CpuModel{
2722 .name = "verde",
2723 .llvm_name = "verde",
2724 .features = featureSet(&[_]Feature{
2725 .southern_islands,
2726 }),
2727 };
2728};
tools/update_clang_options.zig+1-1
...@@ -576,7 +576,7 @@ fn knownOption(name: []const u8) ?[]const u8 {...@@ -576,7 +576,7 @@ fn knownOption(name: []const u8) ?[]const u8 {
576576
577const cpu_targets = struct {577const cpu_targets = struct {
578 pub const aarch64 = std.Target.aarch64;578 pub const aarch64 = std.Target.aarch64;
579 pub const amdgpu = std.Target.amdgpu;579 pub const amdgcn = std.Target.amdgcn;
580 pub const arc = std.Target.arc;580 pub const arc = std.Target.arc;
581 pub const arm = std.Target.arm;581 pub const arm = std.Target.arm;
582 pub const avr = std.Target.avr;582 pub const avr = std.Target.avr;
tools/update_cpu_features.zig+1-1
...@@ -390,7 +390,7 @@ const llvm_targets = [_]LlvmTarget{...@@ -390,7 +390,7 @@ const llvm_targets = [_]LlvmTarget{
390 },390 },
391 },391 },
392 .{392 .{
393 .zig_name = "amdgpu",393 .zig_name = "amdgcn",
394 .llvm_name = "AMDGPU",394 .llvm_name = "AMDGPU",
395 .td_name = "AMDGPU.td",395 .td_name = "AMDGPU.td",
396 .feature_overrides = &.{396 .feature_overrides = &.{