| ... | ... | @@ -2272,7 +2272,7 @@ pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize { |
| 2272 | 2272 | length_halves[0], |
| 2273 | 2273 | length_halves[1], |
| 2274 | 2274 | ); |
| 2275 | | } else if (comptime native_arch == .mips or native_arch == .mipsel) { |
| 2275 | } else if (native_arch.isMIPS32()) { |
| 2276 | 2276 | // MIPS O32 does not deal with the register alignment issue, so pass a dummy value. |
| 2277 | 2277 | |
| 2278 | 2278 | const offset_halves = splitValue64(offset); |
| ... | ... | @@ -2382,7 +2382,7 @@ pub fn map_shadow_stack(addr: u64, size: u64, flags: u32) usize { |
| 2382 | 2382 | } |
| 2383 | 2383 | |
| 2384 | 2384 | pub const E = switch (native_arch) { |
| 2385 | | .mips, .mipsel => enum(u16) { |
| 2385 | .mips, .mipsel, .mips64, .mips64el => enum(u16) { |
| 2386 | 2386 | /// No error occurred. |
| 2387 | 2387 | SUCCESS = 0, |
| 2388 | 2388 | |