Commit bf82929557f0b116979261c522c62cf6393a08f2 | zig

author	Andrew Kelley <andrew@ziglang.org> 2020-01-20 12:41:18-05:00
committer	Andrew Kelley <andrew@ziglang.org> 2020-01-20 12:41:18-05:00
log	bf82929557f0b116979261c522c62cf6393a08f2
tree	2d6a30785f9245cb06b2dbc36eaf7bfff028ee67
parent	8f29d1407350190e1e641ca55f870f00b53d0246
signature	Commit is signed but in an unrecognized format.

fix std.Target.Arch.parseCpuFeatureSet

2 files changed, 42 insertions(+), 22 deletions(-)

lib
- std
  - target.zig
src-self-hosted
- stage1.zig

lib/std/target.zig+41-21

 @@ -228,30 +228,40 @@ pub const Target = union(enum) {
             var it = mem.tokenize(features_text, ",");
             while (it.next()) |item_text| {
-                const feature_name = blk: {
+                var feature_name: []const u8 = undefined;
-                    if (mem.startsWith(u8, item_text, "+")) {
+                var op: enum {
-                        switch (mode) {
+                    add,
-                            .unknown, .baseline => mode = .baseline,
+                    sub,
-                            .whitelist => return error.InvalidCpuFeatures,
+                } = undefined;
-                        }
+                if (mem.startsWith(u8, item_text, "+")) {
-                        break :blk item_text[1..];
+                    switch (mode) {
-                    } else if (mem.startsWith(u8, item_text, "-")) {
+                        .unknown, .baseline => mode = .baseline,
-                        switch (mode) {
+                        .whitelist => return error.InvalidCpuFeatures,
-                            .unknown, .baseline => mode = .baseline,
-                            .whitelist => return error.InvalidCpuFeatures,
-                        }
-                        break :blk item_text[1..];
-                    } else {
-                        switch (mode) {
-                            .unknown, .whitelist => mode = .whitelist,
-                            .baseline => return error.InvalidCpuFeatures,
-                        }
-                        break :blk item_text;
                     }
-                };
+                    op = .add;
+                    feature_name = item_text[1..];
+                } else if (mem.startsWith(u8, item_text, "-")) {
+                    switch (mode) {
+                        .unknown, .baseline => mode = .baseline,
+                        .whitelist => return error.InvalidCpuFeatures,
+                    }
+                    op = .sub;
+                    feature_name = item_text[1..];
+                } else {
+                    switch (mode) {
+                        .unknown, .whitelist => mode = .whitelist,
+                        .baseline => return error.InvalidCpuFeatures,
+                    }
+                    op = .add;
+                    feature_name = item_text;
+                }
                 for (arch.allFeaturesList()) |feature, index| {
                     if (mem.eql(u8, feature_name, feature.name)) {
-                        set |= @splat(2, @as(Cpu.Feature.Set, 1) << @intCast(u7, index));
+                        const one_bit = @as(Cpu.Feature.Set, 1) << @intCast(u7, index);
+                        switch (op) {
+                            .add => set |= @splat(2, one_bit),
+                            .sub => set &= @splat(2, ~one_bit),
+                        }
                         break;
                     }
                 } else {
 @@ -1050,3 +1060,13 @@ pub const Target = union(enum) {
         return .unavailable;
     }
 };
+test "parseCpuFeatureSet" {
+    const set = try @as(Target.Arch, .x86_64).parseCpuFeatureSet("-sse,-avx,-cx8");
+    std.testing.expect(!Target.x86.featureSetHas(set, .sse));
+    std.testing.expect(!Target.x86.featureSetHas(set, .avx));
+    std.testing.expect(!Target.x86.featureSetHas(set, .cx8));
+    // These are expected because they are part of the baseline
+    std.testing.expect(Target.x86.featureSetHas(set, .cmov));
+    std.testing.expect(Target.x86.featureSetHas(set, .fxsr));
+}

src-self-hosted/stage1.zig+1-1

...	@@ -617,7 +617,7 @@ const Stage2CpuFeatures = struct {	...	@@ -617,7 +617,7 @@ const Stage2CpuFeatures = struct {
617	if (mem.eql(u8, llvm_feat, this_llvm_name)) {	617	if (mem.eql(u8, llvm_feat, this_llvm_name)) {
618	switch (op) {	618	switch (op) {
619	.add => set \|= @as(Target.Cpu.Feature.Set, 1) << @intCast(u7, index),	619	.add => set \|= @as(Target.Cpu.Feature.Set, 1) << @intCast(u7, index),
620	.sub => set &= ~@as(Target.Cpu.Feature.Set, 1) << @intCast(u7, index),	620	.sub => set &= ~(@as(Target.Cpu.Feature.Set, 1) << @intCast(u7, index)),
621	}	621	}
622	break;	622	break;
623	}	623	}