authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-31 14:00:46-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-07-31 16:57:30-07:00
logc08effc20abe2595ba5c83e25b78c274ec9c58ec
tree283522a4237c04638d8d4fb603da55c08111c17e
parenta69d403cb2c82ce6257bfa1ee7eba52f895c14e7

riscv: implement non-pow2 indirect loads

2 files changed, 4 insertions(+), 5 deletions(-)

src/arch/riscv64/CodeGen.zig+4-4
......@@ -6855,10 +6855,10 @@ fn genSetReg(func: *Func, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
68556855 else => return std.debug.panic("TODO: genSetReg for float size {d}", .{abi_size}),
68566856 },
68576857 .int => switch (abi_size) {
6858 1 => .lb,
6859 2 => .lh,
6860 4 => .lw,
6861 8 => .ld,
6858 1...1 => .lb,
6859 2...2 => .lh,
6860 3...4 => .lw,
6861 5...8 => .ld,
68626862 else => return std.debug.panic("TODO: genSetReg for int size {d}", .{abi_size}),
68636863 },
68646864 .vector => {
test/behavior/defer.zig-1
......@@ -94,7 +94,6 @@ test "mixing normal and error defers" {
9494 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
9595 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
9696 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
97 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
9897
9998 try expect(runSomeErrorDefers(true) catch unreachable);
10099 try expect(result[0] == 'c');