authorgravatar for lgustaf1@binghamton.eduLayne Gustafson <lgustaf1@binghamton.edu> 2019-12-20 19:27:13-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-19 20:53:18-05:00
logc131e50ea7ea0fb95d188c3d0f71ef77bcc96952
treece612c95d691e986fb60599f0fb3f568546c3893
parent9d66bda26421c2b687afc26122736515c9cc35da
signaturelock-open Commit is signed but in an unrecognized format.

Switch CPU/features to simple format

51 files changed, 21721 insertions(+), 13386 deletions(-)

lib/std/target.zig+75-3
......@@ -2,9 +2,6 @@ const std = @import("std.zig");
22const mem = std.mem;
33const builtin = std.builtin;
44
5pub const feature = @import("target/feature.zig");
6pub const cpu = @import("target/cpu.zig");
7
85/// TODO Nearly all the functions in this namespace would be
96/// better off if https://github.com/ziglang/zig/issues/425
107/// was solved.
......@@ -844,3 +841,78 @@ pub const Target = union(enum) {
844841 return .unavailable;
845842 }
846843};
844
845pub const aarch64 = @import("target/aarch64.zig");
846pub const amdgpu = @import("target/amdgpu.zig");
847pub const arm = @import("target/arm.zig");
848pub const avr = @import("target/avr.zig");
849pub const bpf = @import("target/bpf.zig");
850pub const hexagon = @import("target/hexagon.zig");
851pub const mips = @import("target/mips.zig");
852pub const msp430 = @import("target/msp430.zig");
853pub const nvptx = @import("target/nvptx.zig");
854pub const powerpc = @import("target/powerpc.zig");
855pub const riscv = @import("target/riscv.zig");
856pub const sparc = @import("target/sparc.zig");
857pub const systemz = @import("target/systemz.zig");
858pub const wasm = @import("target/wasm.zig");
859pub const x86 = @import("target/x86.zig");
860
861pub const Feature = struct {
862 name: []const u8,
863 description: []const u8,
864 llvm_name: []const u8,
865
866 subfeatures: []*const Feature,
867};
868
869pub const Cpu = struct {
870 name: []const u8,
871 llvm_name: []const u8,
872
873 subfeatures: []*const Feature,
874};
875
876pub fn getFeaturesForArch(arch: @TagType(Target.Arch)) []*const Feature {
877 return switch (arch) {
878 .arm, .armeb, .thumb, .thumbeb => arm.features,
879 .aarch64, .aarch64_be, .aarch64_32 => aarch64.features,
880 .avr => avr.features,
881 .bpfel, .bpfeb => bpf.features,
882 .hexagon => hexagon.features,
883 .mips, .mipsel, .mips64, .mips64el => mips.features,
884 .msp430 => msp430.features,
885 .powerpc, .powerpc64, .powerpc64le => powerpc.features,
886 .amdgcn => amdgpu.features,
887 .riscv32, .riscv64 => riscv.features,
888 .sparc, .sparcv9, .sparcel => sparc.features,
889 .s390x => systemz.features,
890 .i386, .x86_64 => x86.features,
891 .nvptx, .nvptx64 => nvptx.features,
892 .wasm32, .wasm64 => wasm.features,
893
894 else => &[_]*const Feature{},
895 };
896}
897
898pub fn getCpusForArch(arch: @TagType(Target.Arch)) []*const Cpu {
899 return switch (arch) {
900 .arm, .armeb, .thumb, .thumbeb => arm.cpus,
901 .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpus,
902 .avr => avr.cpus,
903 .bpfel, .bpfeb => bpf.cpus,
904 .hexagon => hexagon.cpus,
905 .mips, .mipsel, .mips64, .mips64el => mips.cpus,
906 .msp430 => msp430.cpus,
907 .powerpc, .powerpc64, .powerpc64le => powerpc.cpus,
908 .amdgcn => amdgpu.cpus,
909 .riscv32, .riscv64 => riscv.cpus,
910 .sparc, .sparcv9, .sparcel => sparc.cpus,
911 .s390x => systemz.cpus,
912 .i386, .x86_64 => x86.cpus,
913 .nvptx, .nvptx64 => nvptx.cpus,
914 .wasm32, .wasm64 => wasm.cpus,
915
916 else => &[_]*const Cpu{},
917 };
918}
lib/std/target/aarch64.zig created+2383
......@@ -0,0 +1,2383 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_aes = Feature{
5 .name = "aes",
6 .description = "Enable AES support",
7 .llvm_name = "aes",
8 .subfeatures = &[_]*const Feature {
9 &feature_fpArmv8,
10 },
11};
12
13pub const feature_am = Feature{
14 .name = "am",
15 .description = "Enable v8.4-A Activity Monitors extension",
16 .llvm_name = "am",
17 .subfeatures = &[_]*const Feature {
18 },
19};
20
21pub const feature_aggressiveFma = Feature{
22 .name = "aggressive-fma",
23 .description = "Enable Aggressive FMA for floating-point.",
24 .llvm_name = "aggressive-fma",
25 .subfeatures = &[_]*const Feature {
26 },
27};
28
29pub const feature_altnzcv = Feature{
30 .name = "altnzcv",
31 .description = "Enable alternative NZCV format for floating point comparisons",
32 .llvm_name = "altnzcv",
33 .subfeatures = &[_]*const Feature {
34 },
35};
36
37pub const feature_alternateSextloadCvtF32Pattern = Feature{
38 .name = "alternate-sextload-cvt-f32-pattern",
39 .description = "Use alternative pattern for sextload convert to f32",
40 .llvm_name = "alternate-sextload-cvt-f32-pattern",
41 .subfeatures = &[_]*const Feature {
42 },
43};
44
45pub const feature_arithBccFusion = Feature{
46 .name = "arith-bcc-fusion",
47 .description = "CPU fuses arithmetic+bcc operations",
48 .llvm_name = "arith-bcc-fusion",
49 .subfeatures = &[_]*const Feature {
50 },
51};
52
53pub const feature_arithCbzFusion = Feature{
54 .name = "arith-cbz-fusion",
55 .description = "CPU fuses arithmetic + cbz/cbnz operations",
56 .llvm_name = "arith-cbz-fusion",
57 .subfeatures = &[_]*const Feature {
58 },
59};
60
61pub const feature_balanceFpOps = Feature{
62 .name = "balance-fp-ops",
63 .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
64 .llvm_name = "balance-fp-ops",
65 .subfeatures = &[_]*const Feature {
66 },
67};
68
69pub const feature_bti = Feature{
70 .name = "bti",
71 .description = "Enable Branch Target Identification",
72 .llvm_name = "bti",
73 .subfeatures = &[_]*const Feature {
74 },
75};
76
77pub const feature_ccidx = Feature{
78 .name = "ccidx",
79 .description = "Enable v8.3-A Extend of the CCSIDR number of sets",
80 .llvm_name = "ccidx",
81 .subfeatures = &[_]*const Feature {
82 },
83};
84
85pub const feature_ccpp = Feature{
86 .name = "ccpp",
87 .description = "Enable v8.2 data Cache Clean to Point of Persistence",
88 .llvm_name = "ccpp",
89 .subfeatures = &[_]*const Feature {
90 },
91};
92
93pub const feature_crc = Feature{
94 .name = "crc",
95 .description = "Enable ARMv8 CRC-32 checksum instructions",
96 .llvm_name = "crc",
97 .subfeatures = &[_]*const Feature {
98 },
99};
100
101pub const feature_ccdp = Feature{
102 .name = "ccdp",
103 .description = "Enable v8.5 Cache Clean to Point of Deep Persistence",
104 .llvm_name = "ccdp",
105 .subfeatures = &[_]*const Feature {
106 },
107};
108
109pub const feature_callSavedX8 = Feature{
110 .name = "call-saved-x8",
111 .description = "Make X8 callee saved.",
112 .llvm_name = "call-saved-x8",
113 .subfeatures = &[_]*const Feature {
114 },
115};
116
117pub const feature_callSavedX9 = Feature{
118 .name = "call-saved-x9",
119 .description = "Make X9 callee saved.",
120 .llvm_name = "call-saved-x9",
121 .subfeatures = &[_]*const Feature {
122 },
123};
124
125pub const feature_callSavedX10 = Feature{
126 .name = "call-saved-x10",
127 .description = "Make X10 callee saved.",
128 .llvm_name = "call-saved-x10",
129 .subfeatures = &[_]*const Feature {
130 },
131};
132
133pub const feature_callSavedX11 = Feature{
134 .name = "call-saved-x11",
135 .description = "Make X11 callee saved.",
136 .llvm_name = "call-saved-x11",
137 .subfeatures = &[_]*const Feature {
138 },
139};
140
141pub const feature_callSavedX12 = Feature{
142 .name = "call-saved-x12",
143 .description = "Make X12 callee saved.",
144 .llvm_name = "call-saved-x12",
145 .subfeatures = &[_]*const Feature {
146 },
147};
148
149pub const feature_callSavedX13 = Feature{
150 .name = "call-saved-x13",
151 .description = "Make X13 callee saved.",
152 .llvm_name = "call-saved-x13",
153 .subfeatures = &[_]*const Feature {
154 },
155};
156
157pub const feature_callSavedX14 = Feature{
158 .name = "call-saved-x14",
159 .description = "Make X14 callee saved.",
160 .llvm_name = "call-saved-x14",
161 .subfeatures = &[_]*const Feature {
162 },
163};
164
165pub const feature_callSavedX15 = Feature{
166 .name = "call-saved-x15",
167 .description = "Make X15 callee saved.",
168 .llvm_name = "call-saved-x15",
169 .subfeatures = &[_]*const Feature {
170 },
171};
172
173pub const feature_callSavedX18 = Feature{
174 .name = "call-saved-x18",
175 .description = "Make X18 callee saved.",
176 .llvm_name = "call-saved-x18",
177 .subfeatures = &[_]*const Feature {
178 },
179};
180
181pub const feature_complxnum = Feature{
182 .name = "complxnum",
183 .description = "Enable v8.3-A Floating-point complex number support",
184 .llvm_name = "complxnum",
185 .subfeatures = &[_]*const Feature {
186 &feature_fpArmv8,
187 },
188};
189
190pub const feature_crypto = Feature{
191 .name = "crypto",
192 .description = "Enable cryptographic instructions",
193 .llvm_name = "crypto",
194 .subfeatures = &[_]*const Feature {
195 &feature_fpArmv8,
196 },
197};
198
199pub const feature_customCheapAsMove = Feature{
200 .name = "custom-cheap-as-move",
201 .description = "Use custom handling of cheap instructions",
202 .llvm_name = "custom-cheap-as-move",
203 .subfeatures = &[_]*const Feature {
204 },
205};
206
207pub const feature_dit = Feature{
208 .name = "dit",
209 .description = "Enable v8.4-A Data Independent Timing instructions",
210 .llvm_name = "dit",
211 .subfeatures = &[_]*const Feature {
212 },
213};
214
215pub const feature_disableLatencySchedHeuristic = Feature{
216 .name = "disable-latency-sched-heuristic",
217 .description = "Disable latency scheduling heuristic",
218 .llvm_name = "disable-latency-sched-heuristic",
219 .subfeatures = &[_]*const Feature {
220 },
221};
222
223pub const feature_dotprod = Feature{
224 .name = "dotprod",
225 .description = "Enable dot product support",
226 .llvm_name = "dotprod",
227 .subfeatures = &[_]*const Feature {
228 },
229};
230
231pub const feature_ete = Feature{
232 .name = "ete",
233 .description = "Enable Embedded Trace Extension",
234 .llvm_name = "ete",
235 .subfeatures = &[_]*const Feature {
236 &feature_trbe,
237 },
238};
239
240pub const feature_exynosCheapAsMove = Feature{
241 .name = "exynos-cheap-as-move",
242 .description = "Use Exynos specific handling of cheap instructions",
243 .llvm_name = "exynos-cheap-as-move",
244 .subfeatures = &[_]*const Feature {
245 &feature_customCheapAsMove,
246 },
247};
248
249pub const feature_fmi = Feature{
250 .name = "fmi",
251 .description = "Enable v8.4-A Flag Manipulation Instructions",
252 .llvm_name = "fmi",
253 .subfeatures = &[_]*const Feature {
254 },
255};
256
257pub const feature_fp16fml = Feature{
258 .name = "fp16fml",
259 .description = "Enable FP16 FML instructions",
260 .llvm_name = "fp16fml",
261 .subfeatures = &[_]*const Feature {
262 &feature_fpArmv8,
263 },
264};
265
266pub const feature_fpArmv8 = Feature{
267 .name = "fp-armv8",
268 .description = "Enable ARMv8 FP",
269 .llvm_name = "fp-armv8",
270 .subfeatures = &[_]*const Feature {
271 },
272};
273
274pub const feature_fptoint = Feature{
275 .name = "fptoint",
276 .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
277 .llvm_name = "fptoint",
278 .subfeatures = &[_]*const Feature {
279 },
280};
281
282pub const feature_force32bitJumpTables = Feature{
283 .name = "force-32bit-jump-tables",
284 .description = "Force jump table entries to be 32-bits wide except at MinSize",
285 .llvm_name = "force-32bit-jump-tables",
286 .subfeatures = &[_]*const Feature {
287 },
288};
289
290pub const feature_fullfp16 = Feature{
291 .name = "fullfp16",
292 .description = "Full FP16",
293 .llvm_name = "fullfp16",
294 .subfeatures = &[_]*const Feature {
295 &feature_fpArmv8,
296 },
297};
298
299pub const feature_fuseAes = Feature{
300 .name = "fuse-aes",
301 .description = "CPU fuses AES crypto operations",
302 .llvm_name = "fuse-aes",
303 .subfeatures = &[_]*const Feature {
304 },
305};
306
307pub const feature_fuseAddress = Feature{
308 .name = "fuse-address",
309 .description = "CPU fuses address generation and memory operations",
310 .llvm_name = "fuse-address",
311 .subfeatures = &[_]*const Feature {
312 },
313};
314
315pub const feature_fuseArithLogic = Feature{
316 .name = "fuse-arith-logic",
317 .description = "CPU fuses arithmetic and logic operations",
318 .llvm_name = "fuse-arith-logic",
319 .subfeatures = &[_]*const Feature {
320 },
321};
322
323pub const feature_fuseCsel = Feature{
324 .name = "fuse-csel",
325 .description = "CPU fuses conditional select operations",
326 .llvm_name = "fuse-csel",
327 .subfeatures = &[_]*const Feature {
328 },
329};
330
331pub const feature_fuseCryptoEor = Feature{
332 .name = "fuse-crypto-eor",
333 .description = "CPU fuses AES/PMULL and EOR operations",
334 .llvm_name = "fuse-crypto-eor",
335 .subfeatures = &[_]*const Feature {
336 },
337};
338
339pub const feature_fuseLiterals = Feature{
340 .name = "fuse-literals",
341 .description = "CPU fuses literal generation operations",
342 .llvm_name = "fuse-literals",
343 .subfeatures = &[_]*const Feature {
344 },
345};
346
347pub const feature_jsconv = Feature{
348 .name = "jsconv",
349 .description = "Enable v8.3-A JavaScript FP conversion enchancement",
350 .llvm_name = "jsconv",
351 .subfeatures = &[_]*const Feature {
352 &feature_fpArmv8,
353 },
354};
355
356pub const feature_lor = Feature{
357 .name = "lor",
358 .description = "Enables ARM v8.1 Limited Ordering Regions extension",
359 .llvm_name = "lor",
360 .subfeatures = &[_]*const Feature {
361 },
362};
363
364pub const feature_lse = Feature{
365 .name = "lse",
366 .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions",
367 .llvm_name = "lse",
368 .subfeatures = &[_]*const Feature {
369 },
370};
371
372pub const feature_lslFast = Feature{
373 .name = "lsl-fast",
374 .description = "CPU has a fastpath logical shift of up to 3 places",
375 .llvm_name = "lsl-fast",
376 .subfeatures = &[_]*const Feature {
377 },
378};
379
380pub const feature_mpam = Feature{
381 .name = "mpam",
382 .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension",
383 .llvm_name = "mpam",
384 .subfeatures = &[_]*const Feature {
385 },
386};
387
388pub const feature_mte = Feature{
389 .name = "mte",
390 .description = "Enable Memory Tagging Extension",
391 .llvm_name = "mte",
392 .subfeatures = &[_]*const Feature {
393 },
394};
395
396pub const feature_neon = Feature{
397 .name = "neon",
398 .description = "Enable Advanced SIMD instructions",
399 .llvm_name = "neon",
400 .subfeatures = &[_]*const Feature {
401 &feature_fpArmv8,
402 },
403};
404
405pub const feature_nv = Feature{
406 .name = "nv",
407 .description = "Enable v8.4-A Nested Virtualization Enchancement",
408 .llvm_name = "nv",
409 .subfeatures = &[_]*const Feature {
410 },
411};
412
413pub const feature_noNegImmediates = Feature{
414 .name = "no-neg-immediates",
415 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
416 .llvm_name = "no-neg-immediates",
417 .subfeatures = &[_]*const Feature {
418 },
419};
420
421pub const feature_pa = Feature{
422 .name = "pa",
423 .description = "Enable v8.3-A Pointer Authentication enchancement",
424 .llvm_name = "pa",
425 .subfeatures = &[_]*const Feature {
426 },
427};
428
429pub const feature_pan = Feature{
430 .name = "pan",
431 .description = "Enables ARM v8.1 Privileged Access-Never extension",
432 .llvm_name = "pan",
433 .subfeatures = &[_]*const Feature {
434 },
435};
436
437pub const feature_panRwv = Feature{
438 .name = "pan-rwv",
439 .description = "Enable v8.2 PAN s1e1R and s1e1W Variants",
440 .llvm_name = "pan-rwv",
441 .subfeatures = &[_]*const Feature {
442 &feature_pan,
443 },
444};
445
446pub const feature_perfmon = Feature{
447 .name = "perfmon",
448 .description = "Enable ARMv8 PMUv3 Performance Monitors extension",
449 .llvm_name = "perfmon",
450 .subfeatures = &[_]*const Feature {
451 },
452};
453
454pub const feature_usePostraScheduler = Feature{
455 .name = "use-postra-scheduler",
456 .description = "Schedule again after register allocation",
457 .llvm_name = "use-postra-scheduler",
458 .subfeatures = &[_]*const Feature {
459 },
460};
461
462pub const feature_predres = Feature{
463 .name = "predres",
464 .description = "Enable v8.5a execution and data prediction invalidation instructions",
465 .llvm_name = "predres",
466 .subfeatures = &[_]*const Feature {
467 },
468};
469
470pub const feature_predictableSelectExpensive = Feature{
471 .name = "predictable-select-expensive",
472 .description = "Prefer likely predicted branches over selects",
473 .llvm_name = "predictable-select-expensive",
474 .subfeatures = &[_]*const Feature {
475 },
476};
477
478pub const feature_uaops = Feature{
479 .name = "uaops",
480 .description = "Enable v8.2 UAO PState",
481 .llvm_name = "uaops",
482 .subfeatures = &[_]*const Feature {
483 },
484};
485
486pub const feature_ras = Feature{
487 .name = "ras",
488 .description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions",
489 .llvm_name = "ras",
490 .subfeatures = &[_]*const Feature {
491 },
492};
493
494pub const feature_rasv8_4 = Feature{
495 .name = "rasv8_4",
496 .description = "Enable v8.4-A Reliability, Availability and Serviceability extension",
497 .llvm_name = "rasv8_4",
498 .subfeatures = &[_]*const Feature {
499 &feature_ras,
500 },
501};
502
503pub const feature_rcpc = Feature{
504 .name = "rcpc",
505 .description = "Enable support for RCPC extension",
506 .llvm_name = "rcpc",
507 .subfeatures = &[_]*const Feature {
508 },
509};
510
511pub const feature_rcpcImmo = Feature{
512 .name = "rcpc-immo",
513 .description = "Enable v8.4-A RCPC instructions with Immediate Offsets",
514 .llvm_name = "rcpc-immo",
515 .subfeatures = &[_]*const Feature {
516 &feature_rcpc,
517 },
518};
519
520pub const feature_rdm = Feature{
521 .name = "rdm",
522 .description = "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
523 .llvm_name = "rdm",
524 .subfeatures = &[_]*const Feature {
525 },
526};
527
528pub const feature_rand = Feature{
529 .name = "rand",
530 .description = "Enable Random Number generation instructions",
531 .llvm_name = "rand",
532 .subfeatures = &[_]*const Feature {
533 },
534};
535
536pub const feature_reserveX1 = Feature{
537 .name = "reserve-x1",
538 .description = "Reserve X1, making it unavailable as a GPR",
539 .llvm_name = "reserve-x1",
540 .subfeatures = &[_]*const Feature {
541 },
542};
543
544pub const feature_reserveX2 = Feature{
545 .name = "reserve-x2",
546 .description = "Reserve X2, making it unavailable as a GPR",
547 .llvm_name = "reserve-x2",
548 .subfeatures = &[_]*const Feature {
549 },
550};
551
552pub const feature_reserveX3 = Feature{
553 .name = "reserve-x3",
554 .description = "Reserve X3, making it unavailable as a GPR",
555 .llvm_name = "reserve-x3",
556 .subfeatures = &[_]*const Feature {
557 },
558};
559
560pub const feature_reserveX4 = Feature{
561 .name = "reserve-x4",
562 .description = "Reserve X4, making it unavailable as a GPR",
563 .llvm_name = "reserve-x4",
564 .subfeatures = &[_]*const Feature {
565 },
566};
567
568pub const feature_reserveX5 = Feature{
569 .name = "reserve-x5",
570 .description = "Reserve X5, making it unavailable as a GPR",
571 .llvm_name = "reserve-x5",
572 .subfeatures = &[_]*const Feature {
573 },
574};
575
576pub const feature_reserveX6 = Feature{
577 .name = "reserve-x6",
578 .description = "Reserve X6, making it unavailable as a GPR",
579 .llvm_name = "reserve-x6",
580 .subfeatures = &[_]*const Feature {
581 },
582};
583
584pub const feature_reserveX7 = Feature{
585 .name = "reserve-x7",
586 .description = "Reserve X7, making it unavailable as a GPR",
587 .llvm_name = "reserve-x7",
588 .subfeatures = &[_]*const Feature {
589 },
590};
591
592pub const feature_reserveX9 = Feature{
593 .name = "reserve-x9",
594 .description = "Reserve X9, making it unavailable as a GPR",
595 .llvm_name = "reserve-x9",
596 .subfeatures = &[_]*const Feature {
597 },
598};
599
600pub const feature_reserveX10 = Feature{
601 .name = "reserve-x10",
602 .description = "Reserve X10, making it unavailable as a GPR",
603 .llvm_name = "reserve-x10",
604 .subfeatures = &[_]*const Feature {
605 },
606};
607
608pub const feature_reserveX11 = Feature{
609 .name = "reserve-x11",
610 .description = "Reserve X11, making it unavailable as a GPR",
611 .llvm_name = "reserve-x11",
612 .subfeatures = &[_]*const Feature {
613 },
614};
615
616pub const feature_reserveX12 = Feature{
617 .name = "reserve-x12",
618 .description = "Reserve X12, making it unavailable as a GPR",
619 .llvm_name = "reserve-x12",
620 .subfeatures = &[_]*const Feature {
621 },
622};
623
624pub const feature_reserveX13 = Feature{
625 .name = "reserve-x13",
626 .description = "Reserve X13, making it unavailable as a GPR",
627 .llvm_name = "reserve-x13",
628 .subfeatures = &[_]*const Feature {
629 },
630};
631
632pub const feature_reserveX14 = Feature{
633 .name = "reserve-x14",
634 .description = "Reserve X14, making it unavailable as a GPR",
635 .llvm_name = "reserve-x14",
636 .subfeatures = &[_]*const Feature {
637 },
638};
639
640pub const feature_reserveX15 = Feature{
641 .name = "reserve-x15",
642 .description = "Reserve X15, making it unavailable as a GPR",
643 .llvm_name = "reserve-x15",
644 .subfeatures = &[_]*const Feature {
645 },
646};
647
648pub const feature_reserveX18 = Feature{
649 .name = "reserve-x18",
650 .description = "Reserve X18, making it unavailable as a GPR",
651 .llvm_name = "reserve-x18",
652 .subfeatures = &[_]*const Feature {
653 },
654};
655
656pub const feature_reserveX20 = Feature{
657 .name = "reserve-x20",
658 .description = "Reserve X20, making it unavailable as a GPR",
659 .llvm_name = "reserve-x20",
660 .subfeatures = &[_]*const Feature {
661 },
662};
663
664pub const feature_reserveX21 = Feature{
665 .name = "reserve-x21",
666 .description = "Reserve X21, making it unavailable as a GPR",
667 .llvm_name = "reserve-x21",
668 .subfeatures = &[_]*const Feature {
669 },
670};
671
672pub const feature_reserveX22 = Feature{
673 .name = "reserve-x22",
674 .description = "Reserve X22, making it unavailable as a GPR",
675 .llvm_name = "reserve-x22",
676 .subfeatures = &[_]*const Feature {
677 },
678};
679
680pub const feature_reserveX23 = Feature{
681 .name = "reserve-x23",
682 .description = "Reserve X23, making it unavailable as a GPR",
683 .llvm_name = "reserve-x23",
684 .subfeatures = &[_]*const Feature {
685 },
686};
687
688pub const feature_reserveX24 = Feature{
689 .name = "reserve-x24",
690 .description = "Reserve X24, making it unavailable as a GPR",
691 .llvm_name = "reserve-x24",
692 .subfeatures = &[_]*const Feature {
693 },
694};
695
696pub const feature_reserveX25 = Feature{
697 .name = "reserve-x25",
698 .description = "Reserve X25, making it unavailable as a GPR",
699 .llvm_name = "reserve-x25",
700 .subfeatures = &[_]*const Feature {
701 },
702};
703
704pub const feature_reserveX26 = Feature{
705 .name = "reserve-x26",
706 .description = "Reserve X26, making it unavailable as a GPR",
707 .llvm_name = "reserve-x26",
708 .subfeatures = &[_]*const Feature {
709 },
710};
711
712pub const feature_reserveX27 = Feature{
713 .name = "reserve-x27",
714 .description = "Reserve X27, making it unavailable as a GPR",
715 .llvm_name = "reserve-x27",
716 .subfeatures = &[_]*const Feature {
717 },
718};
719
720pub const feature_reserveX28 = Feature{
721 .name = "reserve-x28",
722 .description = "Reserve X28, making it unavailable as a GPR",
723 .llvm_name = "reserve-x28",
724 .subfeatures = &[_]*const Feature {
725 },
726};
727
728pub const feature_sb = Feature{
729 .name = "sb",
730 .description = "Enable v8.5 Speculation Barrier",
731 .llvm_name = "sb",
732 .subfeatures = &[_]*const Feature {
733 },
734};
735
736pub const feature_sel2 = Feature{
737 .name = "sel2",
738 .description = "Enable v8.4-A Secure Exception Level 2 extension",
739 .llvm_name = "sel2",
740 .subfeatures = &[_]*const Feature {
741 },
742};
743
744pub const feature_sha2 = Feature{
745 .name = "sha2",
746 .description = "Enable SHA1 and SHA256 support",
747 .llvm_name = "sha2",
748 .subfeatures = &[_]*const Feature {
749 &feature_fpArmv8,
750 },
751};
752
753pub const feature_sha3 = Feature{
754 .name = "sha3",
755 .description = "Enable SHA512 and SHA3 support",
756 .llvm_name = "sha3",
757 .subfeatures = &[_]*const Feature {
758 &feature_fpArmv8,
759 },
760};
761
762pub const feature_sm4 = Feature{
763 .name = "sm4",
764 .description = "Enable SM3 and SM4 support",
765 .llvm_name = "sm4",
766 .subfeatures = &[_]*const Feature {
767 &feature_fpArmv8,
768 },
769};
770
771pub const feature_spe = Feature{
772 .name = "spe",
773 .description = "Enable Statistical Profiling extension",
774 .llvm_name = "spe",
775 .subfeatures = &[_]*const Feature {
776 },
777};
778
779pub const feature_ssbs = Feature{
780 .name = "ssbs",
781 .description = "Enable Speculative Store Bypass Safe bit",
782 .llvm_name = "ssbs",
783 .subfeatures = &[_]*const Feature {
784 },
785};
786
787pub const feature_sve = Feature{
788 .name = "sve",
789 .description = "Enable Scalable Vector Extension (SVE) instructions",
790 .llvm_name = "sve",
791 .subfeatures = &[_]*const Feature {
792 },
793};
794
795pub const feature_sve2 = Feature{
796 .name = "sve2",
797 .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
798 .llvm_name = "sve2",
799 .subfeatures = &[_]*const Feature {
800 &feature_sve,
801 },
802};
803
804pub const feature_sve2Aes = Feature{
805 .name = "sve2-aes",
806 .description = "Enable AES SVE2 instructions",
807 .llvm_name = "sve2-aes",
808 .subfeatures = &[_]*const Feature {
809 &feature_fpArmv8,
810 &feature_sve,
811 },
812};
813
814pub const feature_sve2Bitperm = Feature{
815 .name = "sve2-bitperm",
816 .description = "Enable bit permutation SVE2 instructions",
817 .llvm_name = "sve2-bitperm",
818 .subfeatures = &[_]*const Feature {
819 &feature_sve,
820 },
821};
822
823pub const feature_sve2Sha3 = Feature{
824 .name = "sve2-sha3",
825 .description = "Enable SHA3 SVE2 instructions",
826 .llvm_name = "sve2-sha3",
827 .subfeatures = &[_]*const Feature {
828 &feature_fpArmv8,
829 &feature_sve,
830 },
831};
832
833pub const feature_sve2Sm4 = Feature{
834 .name = "sve2-sm4",
835 .description = "Enable SM4 SVE2 instructions",
836 .llvm_name = "sve2-sm4",
837 .subfeatures = &[_]*const Feature {
838 &feature_fpArmv8,
839 &feature_sve,
840 },
841};
842
843pub const feature_slowMisaligned128store = Feature{
844 .name = "slow-misaligned-128store",
845 .description = "Misaligned 128 bit stores are slow",
846 .llvm_name = "slow-misaligned-128store",
847 .subfeatures = &[_]*const Feature {
848 },
849};
850
851pub const feature_slowPaired128 = Feature{
852 .name = "slow-paired-128",
853 .description = "Paired 128 bit loads and stores are slow",
854 .llvm_name = "slow-paired-128",
855 .subfeatures = &[_]*const Feature {
856 },
857};
858
859pub const feature_slowStrqroStore = Feature{
860 .name = "slow-strqro-store",
861 .description = "STR of Q register with register offset is slow",
862 .llvm_name = "slow-strqro-store",
863 .subfeatures = &[_]*const Feature {
864 },
865};
866
867pub const feature_specrestrict = Feature{
868 .name = "specrestrict",
869 .description = "Enable architectural speculation restriction",
870 .llvm_name = "specrestrict",
871 .subfeatures = &[_]*const Feature {
872 },
873};
874
875pub const feature_strictAlign = Feature{
876 .name = "strict-align",
877 .description = "Disallow all unaligned memory access",
878 .llvm_name = "strict-align",
879 .subfeatures = &[_]*const Feature {
880 },
881};
882
883pub const feature_tlbRmi = Feature{
884 .name = "tlb-rmi",
885 .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
886 .llvm_name = "tlb-rmi",
887 .subfeatures = &[_]*const Feature {
888 },
889};
890
891pub const feature_tme = Feature{
892 .name = "tme",
893 .description = "Enable Transactional Memory Extension",
894 .llvm_name = "tme",
895 .subfeatures = &[_]*const Feature {
896 },
897};
898
899pub const feature_tracev84 = Feature{
900 .name = "tracev8.4",
901 .description = "Enable v8.4-A Trace extension",
902 .llvm_name = "tracev8.4",
903 .subfeatures = &[_]*const Feature {
904 },
905};
906
907pub const feature_trbe = Feature{
908 .name = "trbe",
909 .description = "Enable Trace Buffer Extension",
910 .llvm_name = "trbe",
911 .subfeatures = &[_]*const Feature {
912 },
913};
914
915pub const feature_taggedGlobals = Feature{
916 .name = "tagged-globals",
917 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
918 .llvm_name = "tagged-globals",
919 .subfeatures = &[_]*const Feature {
920 },
921};
922
923pub const feature_useAa = Feature{
924 .name = "use-aa",
925 .description = "Use alias analysis during codegen",
926 .llvm_name = "use-aa",
927 .subfeatures = &[_]*const Feature {
928 },
929};
930
931pub const feature_tpidrEl1 = Feature{
932 .name = "tpidr-el1",
933 .description = "Permit use of TPIDR_EL1 for the TLS base",
934 .llvm_name = "tpidr-el1",
935 .subfeatures = &[_]*const Feature {
936 },
937};
938
939pub const feature_tpidrEl2 = Feature{
940 .name = "tpidr-el2",
941 .description = "Permit use of TPIDR_EL2 for the TLS base",
942 .llvm_name = "tpidr-el2",
943 .subfeatures = &[_]*const Feature {
944 },
945};
946
947pub const feature_tpidrEl3 = Feature{
948 .name = "tpidr-el3",
949 .description = "Permit use of TPIDR_EL3 for the TLS base",
950 .llvm_name = "tpidr-el3",
951 .subfeatures = &[_]*const Feature {
952 },
953};
954
955pub const feature_useReciprocalSquareRoot = Feature{
956 .name = "use-reciprocal-square-root",
957 .description = "Use the reciprocal square root approximation",
958 .llvm_name = "use-reciprocal-square-root",
959 .subfeatures = &[_]*const Feature {
960 },
961};
962
963pub const feature_vh = Feature{
964 .name = "vh",
965 .description = "Enables ARM v8.1 Virtual Host extension",
966 .llvm_name = "vh",
967 .subfeatures = &[_]*const Feature {
968 },
969};
970
971pub const feature_zcm = Feature{
972 .name = "zcm",
973 .description = "Has zero-cycle register moves",
974 .llvm_name = "zcm",
975 .subfeatures = &[_]*const Feature {
976 },
977};
978
979pub const feature_zcz = Feature{
980 .name = "zcz",
981 .description = "Has zero-cycle zeroing instructions",
982 .llvm_name = "zcz",
983 .subfeatures = &[_]*const Feature {
984 &feature_zczGp,
985 &feature_zczFp,
986 },
987};
988
989pub const feature_zczFp = Feature{
990 .name = "zcz-fp",
991 .description = "Has zero-cycle zeroing instructions for FP registers",
992 .llvm_name = "zcz-fp",
993 .subfeatures = &[_]*const Feature {
994 },
995};
996
997pub const feature_zczFpWorkaround = Feature{
998 .name = "zcz-fp-workaround",
999 .description = "The zero-cycle floating-point zeroing instruction has a bug",
1000 .llvm_name = "zcz-fp-workaround",
1001 .subfeatures = &[_]*const Feature {
1002 },
1003};
1004
1005pub const feature_zczGp = Feature{
1006 .name = "zcz-gp",
1007 .description = "Has zero-cycle zeroing instructions for generic registers",
1008 .llvm_name = "zcz-gp",
1009 .subfeatures = &[_]*const Feature {
1010 },
1011};
1012
1013pub const feature_v81a = Feature{
1014 .name = "v8.1a",
1015 .description = "Support ARM v8.1a instructions",
1016 .llvm_name = "v8.1a",
1017 .subfeatures = &[_]*const Feature {
1018 &feature_rdm,
1019 &feature_lse,
1020 &feature_lor,
1021 &feature_crc,
1022 &feature_pan,
1023 &feature_vh,
1024 },
1025};
1026
1027pub const feature_v82a = Feature{
1028 .name = "v8.2a",
1029 .description = "Support ARM v8.2a instructions",
1030 .llvm_name = "v8.2a",
1031 .subfeatures = &[_]*const Feature {
1032 &feature_rdm,
1033 &feature_ccpp,
1034 &feature_lse,
1035 &feature_ras,
1036 &feature_lor,
1037 &feature_crc,
1038 &feature_pan,
1039 &feature_uaops,
1040 &feature_vh,
1041 },
1042};
1043
1044pub const feature_v83a = Feature{
1045 .name = "v8.3a",
1046 .description = "Support ARM v8.3a instructions",
1047 .llvm_name = "v8.3a",
1048 .subfeatures = &[_]*const Feature {
1049 &feature_rdm,
1050 &feature_pa,
1051 &feature_ccpp,
1052 &feature_uaops,
1053 &feature_lse,
1054 &feature_fpArmv8,
1055 &feature_ras,
1056 &feature_lor,
1057 &feature_pan,
1058 &feature_crc,
1059 &feature_rcpc,
1060 &feature_ccidx,
1061 &feature_vh,
1062 },
1063};
1064
1065pub const feature_v84a = Feature{
1066 .name = "v8.4a",
1067 .description = "Support ARM v8.4a instructions",
1068 .llvm_name = "v8.4a",
1069 .subfeatures = &[_]*const Feature {
1070 &feature_am,
1071 &feature_nv,
1072 &feature_ccpp,
1073 &feature_dotprod,
1074 &feature_lse,
1075 &feature_rcpc,
1076 &feature_uaops,
1077 &feature_ccidx,
1078 &feature_vh,
1079 &feature_tracev84,
1080 &feature_rdm,
1081 &feature_fpArmv8,
1082 &feature_dit,
1083 &feature_mpam,
1084 &feature_ras,
1085 &feature_tlbRmi,
1086 &feature_fmi,
1087 &feature_crc,
1088 &feature_pa,
1089 &feature_sel2,
1090 &feature_lor,
1091 &feature_pan,
1092 },
1093};
1094
1095pub const feature_v85a = Feature{
1096 .name = "v8.5a",
1097 .description = "Support ARM v8.5a instructions",
1098 .llvm_name = "v8.5a",
1099 .subfeatures = &[_]*const Feature {
1100 &feature_am,
1101 &feature_nv,
1102 &feature_specrestrict,
1103 &feature_ccpp,
1104 &feature_dotprod,
1105 &feature_lse,
1106 &feature_ccdp,
1107 &feature_sb,
1108 &feature_rcpc,
1109 &feature_ccidx,
1110 &feature_uaops,
1111 &feature_vh,
1112 &feature_altnzcv,
1113 &feature_tracev84,
1114 &feature_rdm,
1115 &feature_ssbs,
1116 &feature_fpArmv8,
1117 &feature_dit,
1118 &feature_mpam,
1119 &feature_ras,
1120 &feature_tlbRmi,
1121 &feature_fmi,
1122 &feature_crc,
1123 &feature_predres,
1124 &feature_pa,
1125 &feature_sel2,
1126 &feature_lor,
1127 &feature_fptoint,
1128 &feature_bti,
1129 &feature_pan,
1130 },
1131};
1132
1133pub const feature_a35 = Feature{
1134 .name = "a35",
1135 .description = "Cortex-A35 ARM processors",
1136 .llvm_name = "a35",
1137 .subfeatures = &[_]*const Feature {
1138 &feature_fpArmv8,
1139 &feature_perfmon,
1140 &feature_crc,
1141 },
1142};
1143
1144pub const feature_a53 = Feature{
1145 .name = "a53",
1146 .description = "Cortex-A53 ARM processors",
1147 .llvm_name = "a53",
1148 .subfeatures = &[_]*const Feature {
1149 &feature_usePostraScheduler,
1150 &feature_customCheapAsMove,
1151 &feature_fuseAes,
1152 &feature_balanceFpOps,
1153 &feature_fpArmv8,
1154 &feature_perfmon,
1155 &feature_useAa,
1156 &feature_crc,
1157 },
1158};
1159
1160pub const feature_a55 = Feature{
1161 .name = "a55",
1162 .description = "Cortex-A55 ARM processors",
1163 .llvm_name = "a55",
1164 .subfeatures = &[_]*const Feature {
1165 &feature_rdm,
1166 &feature_fuseAes,
1167 &feature_ccpp,
1168 &feature_lse,
1169 &feature_fpArmv8,
1170 &feature_perfmon,
1171 &feature_ras,
1172 &feature_dotprod,
1173 &feature_lor,
1174 &feature_pan,
1175 &feature_crc,
1176 &feature_rcpc,
1177 &feature_uaops,
1178 &feature_vh,
1179 },
1180};
1181
1182pub const feature_a57 = Feature{
1183 .name = "a57",
1184 .description = "Cortex-A57 ARM processors",
1185 .llvm_name = "a57",
1186 .subfeatures = &[_]*const Feature {
1187 &feature_usePostraScheduler,
1188 &feature_customCheapAsMove,
1189 &feature_fuseAes,
1190 &feature_balanceFpOps,
1191 &feature_fpArmv8,
1192 &feature_perfmon,
1193 &feature_predictableSelectExpensive,
1194 &feature_fuseLiterals,
1195 &feature_crc,
1196 },
1197};
1198
1199pub const feature_a65 = Feature{
1200 .name = "a65",
1201 .description = "Cortex-A65 ARM processors",
1202 .llvm_name = "a65",
1203 .subfeatures = &[_]*const Feature {
1204 &feature_rdm,
1205 &feature_ccpp,
1206 &feature_lse,
1207 &feature_fpArmv8,
1208 &feature_ras,
1209 &feature_dotprod,
1210 &feature_lor,
1211 &feature_pan,
1212 &feature_crc,
1213 &feature_rcpc,
1214 &feature_uaops,
1215 &feature_vh,
1216 &feature_ssbs,
1217 },
1218};
1219
1220pub const feature_a72 = Feature{
1221 .name = "a72",
1222 .description = "Cortex-A72 ARM processors",
1223 .llvm_name = "a72",
1224 .subfeatures = &[_]*const Feature {
1225 &feature_fpArmv8,
1226 &feature_perfmon,
1227 &feature_crc,
1228 &feature_fuseAes,
1229 },
1230};
1231
1232pub const feature_a73 = Feature{
1233 .name = "a73",
1234 .description = "Cortex-A73 ARM processors",
1235 .llvm_name = "a73",
1236 .subfeatures = &[_]*const Feature {
1237 &feature_fpArmv8,
1238 &feature_perfmon,
1239 &feature_crc,
1240 &feature_fuseAes,
1241 },
1242};
1243
1244pub const feature_a75 = Feature{
1245 .name = "a75",
1246 .description = "Cortex-A75 ARM processors",
1247 .llvm_name = "a75",
1248 .subfeatures = &[_]*const Feature {
1249 &feature_rdm,
1250 &feature_fuseAes,
1251 &feature_ccpp,
1252 &feature_lse,
1253 &feature_fpArmv8,
1254 &feature_perfmon,
1255 &feature_ras,
1256 &feature_dotprod,
1257 &feature_lor,
1258 &feature_pan,
1259 &feature_crc,
1260 &feature_rcpc,
1261 &feature_uaops,
1262 &feature_vh,
1263 },
1264};
1265
1266pub const feature_a76 = Feature{
1267 .name = "a76",
1268 .description = "Cortex-A76 ARM processors",
1269 .llvm_name = "a76",
1270 .subfeatures = &[_]*const Feature {
1271 &feature_rdm,
1272 &feature_ccpp,
1273 &feature_lse,
1274 &feature_fpArmv8,
1275 &feature_ras,
1276 &feature_dotprod,
1277 &feature_lor,
1278 &feature_pan,
1279 &feature_crc,
1280 &feature_rcpc,
1281 &feature_uaops,
1282 &feature_vh,
1283 &feature_ssbs,
1284 },
1285};
1286
1287pub const feature_cyclone = Feature{
1288 .name = "cyclone",
1289 .description = "Cyclone",
1290 .llvm_name = "cyclone",
1291 .subfeatures = &[_]*const Feature {
1292 &feature_zczGp,
1293 &feature_arithBccFusion,
1294 &feature_fuseAes,
1295 &feature_zczFp,
1296 &feature_zczFpWorkaround,
1297 &feature_fpArmv8,
1298 &feature_perfmon,
1299 &feature_disableLatencySchedHeuristic,
1300 &feature_zcm,
1301 &feature_arithCbzFusion,
1302 &feature_fuseCryptoEor,
1303 &feature_alternateSextloadCvtF32Pattern,
1304 },
1305};
1306
1307pub const feature_exynosm1 = Feature{
1308 .name = "exynosm1",
1309 .description = "Samsung Exynos-M1 processors",
1310 .llvm_name = "exynosm1",
1311 .subfeatures = &[_]*const Feature {
1312 &feature_usePostraScheduler,
1313 &feature_slowMisaligned128store,
1314 &feature_customCheapAsMove,
1315 &feature_fuseAes,
1316 &feature_zczFp,
1317 &feature_fpArmv8,
1318 &feature_perfmon,
1319 &feature_slowPaired128,
1320 &feature_useReciprocalSquareRoot,
1321 &feature_force32bitJumpTables,
1322 &feature_crc,
1323 },
1324};
1325
1326pub const feature_exynosm2 = Feature{
1327 .name = "exynosm2",
1328 .description = "Samsung Exynos-M2 processors",
1329 .llvm_name = "exynosm2",
1330 .subfeatures = &[_]*const Feature {
1331 &feature_usePostraScheduler,
1332 &feature_slowMisaligned128store,
1333 &feature_customCheapAsMove,
1334 &feature_fuseAes,
1335 &feature_zczFp,
1336 &feature_fpArmv8,
1337 &feature_perfmon,
1338 &feature_slowPaired128,
1339 &feature_force32bitJumpTables,
1340 &feature_crc,
1341 },
1342};
1343
1344pub const feature_exynosm3 = Feature{
1345 .name = "exynosm3",
1346 .description = "Samsung Exynos-M3 processors",
1347 .llvm_name = "exynosm3",
1348 .subfeatures = &[_]*const Feature {
1349 &feature_usePostraScheduler,
1350 &feature_customCheapAsMove,
1351 &feature_fuseAes,
1352 &feature_fuseAddress,
1353 &feature_zczFp,
1354 &feature_fpArmv8,
1355 &feature_perfmon,
1356 &feature_predictableSelectExpensive,
1357 &feature_fuseLiterals,
1358 &feature_force32bitJumpTables,
1359 &feature_crc,
1360 &feature_lslFast,
1361 &feature_fuseCsel,
1362 },
1363};
1364
1365pub const feature_exynosm4 = Feature{
1366 .name = "exynosm4",
1367 .description = "Samsung Exynos-M4 processors",
1368 .llvm_name = "exynosm4",
1369 .subfeatures = &[_]*const Feature {
1370 &feature_ccpp,
1371 &feature_perfmon,
1372 &feature_dotprod,
1373 &feature_fuseArithLogic,
1374 &feature_force32bitJumpTables,
1375 &feature_lslFast,
1376 &feature_zczGp,
1377 &feature_customCheapAsMove,
1378 &feature_fuseAes,
1379 &feature_fuseAddress,
1380 &feature_lse,
1381 &feature_arithCbzFusion,
1382 &feature_uaops,
1383 &feature_fuseCsel,
1384 &feature_vh,
1385 &feature_rdm,
1386 &feature_fpArmv8,
1387 &feature_ras,
1388 &feature_fuseLiterals,
1389 &feature_crc,
1390 &feature_usePostraScheduler,
1391 &feature_arithBccFusion,
1392 &feature_zczFp,
1393 &feature_lor,
1394 &feature_pan,
1395 },
1396};
1397
1398pub const feature_falkor = Feature{
1399 .name = "falkor",
1400 .description = "Qualcomm Falkor processors",
1401 .llvm_name = "falkor",
1402 .subfeatures = &[_]*const Feature {
1403 &feature_rdm,
1404 &feature_usePostraScheduler,
1405 &feature_zczGp,
1406 &feature_slowStrqroStore,
1407 &feature_customCheapAsMove,
1408 &feature_zczFp,
1409 &feature_fpArmv8,
1410 &feature_perfmon,
1411 &feature_predictableSelectExpensive,
1412 &feature_crc,
1413 &feature_lslFast,
1414 },
1415};
1416
1417pub const feature_kryo = Feature{
1418 .name = "kryo",
1419 .description = "Qualcomm Kryo processors",
1420 .llvm_name = "kryo",
1421 .subfeatures = &[_]*const Feature {
1422 &feature_usePostraScheduler,
1423 &feature_zczGp,
1424 &feature_customCheapAsMove,
1425 &feature_zczFp,
1426 &feature_fpArmv8,
1427 &feature_perfmon,
1428 &feature_predictableSelectExpensive,
1429 &feature_crc,
1430 &feature_lslFast,
1431 },
1432};
1433
1434pub const feature_neoversee1 = Feature{
1435 .name = "neoversee1",
1436 .description = "Neoverse E1 ARM processors",
1437 .llvm_name = "neoversee1",
1438 .subfeatures = &[_]*const Feature {
1439 &feature_rdm,
1440 &feature_ccpp,
1441 &feature_lse,
1442 &feature_fpArmv8,
1443 &feature_ras,
1444 &feature_dotprod,
1445 &feature_lor,
1446 &feature_pan,
1447 &feature_crc,
1448 &feature_rcpc,
1449 &feature_uaops,
1450 &feature_vh,
1451 &feature_ssbs,
1452 },
1453};
1454
1455pub const feature_neoversen1 = Feature{
1456 .name = "neoversen1",
1457 .description = "Neoverse N1 ARM processors",
1458 .llvm_name = "neoversen1",
1459 .subfeatures = &[_]*const Feature {
1460 &feature_rdm,
1461 &feature_ccpp,
1462 &feature_lse,
1463 &feature_fpArmv8,
1464 &feature_ras,
1465 &feature_dotprod,
1466 &feature_lor,
1467 &feature_spe,
1468 &feature_pan,
1469 &feature_crc,
1470 &feature_rcpc,
1471 &feature_uaops,
1472 &feature_vh,
1473 &feature_ssbs,
1474 },
1475};
1476
1477pub const feature_saphira = Feature{
1478 .name = "saphira",
1479 .description = "Qualcomm Saphira processors",
1480 .llvm_name = "saphira",
1481 .subfeatures = &[_]*const Feature {
1482 &feature_am,
1483 &feature_nv,
1484 &feature_ccpp,
1485 &feature_predictableSelectExpensive,
1486 &feature_perfmon,
1487 &feature_dotprod,
1488 &feature_spe,
1489 &feature_lslFast,
1490 &feature_zczGp,
1491 &feature_customCheapAsMove,
1492 &feature_lse,
1493 &feature_rcpc,
1494 &feature_uaops,
1495 &feature_ccidx,
1496 &feature_vh,
1497 &feature_tracev84,
1498 &feature_rdm,
1499 &feature_fpArmv8,
1500 &feature_dit,
1501 &feature_mpam,
1502 &feature_ras,
1503 &feature_tlbRmi,
1504 &feature_fmi,
1505 &feature_crc,
1506 &feature_usePostraScheduler,
1507 &feature_pa,
1508 &feature_zczFp,
1509 &feature_sel2,
1510 &feature_lor,
1511 &feature_pan,
1512 },
1513};
1514
1515pub const feature_tsv110 = Feature{
1516 .name = "tsv110",
1517 .description = "HiSilicon TS-V110 processors",
1518 .llvm_name = "tsv110",
1519 .subfeatures = &[_]*const Feature {
1520 &feature_rdm,
1521 &feature_usePostraScheduler,
1522 &feature_customCheapAsMove,
1523 &feature_fuseAes,
1524 &feature_ccpp,
1525 &feature_lse,
1526 &feature_fpArmv8,
1527 &feature_perfmon,
1528 &feature_ras,
1529 &feature_dotprod,
1530 &feature_lor,
1531 &feature_spe,
1532 &feature_crc,
1533 &feature_pan,
1534 &feature_uaops,
1535 &feature_vh,
1536 },
1537};
1538
1539pub const feature_thunderx = Feature{
1540 .name = "thunderx",
1541 .description = "Cavium ThunderX processors",
1542 .llvm_name = "thunderx",
1543 .subfeatures = &[_]*const Feature {
1544 &feature_usePostraScheduler,
1545 &feature_predictableSelectExpensive,
1546 &feature_fpArmv8,
1547 &feature_perfmon,
1548 &feature_crc,
1549 },
1550};
1551
1552pub const feature_thunderx2t99 = Feature{
1553 .name = "thunderx2t99",
1554 .description = "Cavium ThunderX2 processors",
1555 .llvm_name = "thunderx2t99",
1556 .subfeatures = &[_]*const Feature {
1557 &feature_rdm,
1558 &feature_usePostraScheduler,
1559 &feature_arithBccFusion,
1560 &feature_lse,
1561 &feature_fpArmv8,
1562 &feature_predictableSelectExpensive,
1563 &feature_lor,
1564 &feature_crc,
1565 &feature_pan,
1566 &feature_aggressiveFma,
1567 &feature_vh,
1568 },
1569};
1570
1571pub const feature_thunderxt81 = Feature{
1572 .name = "thunderxt81",
1573 .description = "Cavium ThunderX processors",
1574 .llvm_name = "thunderxt81",
1575 .subfeatures = &[_]*const Feature {
1576 &feature_usePostraScheduler,
1577 &feature_predictableSelectExpensive,
1578 &feature_fpArmv8,
1579 &feature_perfmon,
1580 &feature_crc,
1581 },
1582};
1583
1584pub const feature_thunderxt83 = Feature{
1585 .name = "thunderxt83",
1586 .description = "Cavium ThunderX processors",
1587 .llvm_name = "thunderxt83",
1588 .subfeatures = &[_]*const Feature {
1589 &feature_usePostraScheduler,
1590 &feature_predictableSelectExpensive,
1591 &feature_fpArmv8,
1592 &feature_perfmon,
1593 &feature_crc,
1594 },
1595};
1596
1597pub const feature_thunderxt88 = Feature{
1598 .name = "thunderxt88",
1599 .description = "Cavium ThunderX processors",
1600 .llvm_name = "thunderxt88",
1601 .subfeatures = &[_]*const Feature {
1602 &feature_usePostraScheduler,
1603 &feature_predictableSelectExpensive,
1604 &feature_fpArmv8,
1605 &feature_perfmon,
1606 &feature_crc,
1607 },
1608};
1609
1610pub const features = &[_]*const Feature {
1611 &feature_aes,
1612 &feature_am,
1613 &feature_aggressiveFma,
1614 &feature_altnzcv,
1615 &feature_alternateSextloadCvtF32Pattern,
1616 &feature_arithBccFusion,
1617 &feature_arithCbzFusion,
1618 &feature_balanceFpOps,
1619 &feature_bti,
1620 &feature_ccidx,
1621 &feature_ccpp,
1622 &feature_crc,
1623 &feature_ccdp,
1624 &feature_callSavedX8,
1625 &feature_callSavedX9,
1626 &feature_callSavedX10,
1627 &feature_callSavedX11,
1628 &feature_callSavedX12,
1629 &feature_callSavedX13,
1630 &feature_callSavedX14,
1631 &feature_callSavedX15,
1632 &feature_callSavedX18,
1633 &feature_complxnum,
1634 &feature_crypto,
1635 &feature_customCheapAsMove,
1636 &feature_dit,
1637 &feature_disableLatencySchedHeuristic,
1638 &feature_dotprod,
1639 &feature_ete,
1640 &feature_exynosCheapAsMove,
1641 &feature_fmi,
1642 &feature_fp16fml,
1643 &feature_fpArmv8,
1644 &feature_fptoint,
1645 &feature_force32bitJumpTables,
1646 &feature_fullfp16,
1647 &feature_fuseAes,
1648 &feature_fuseAddress,
1649 &feature_fuseArithLogic,
1650 &feature_fuseCsel,
1651 &feature_fuseCryptoEor,
1652 &feature_fuseLiterals,
1653 &feature_jsconv,
1654 &feature_lor,
1655 &feature_lse,
1656 &feature_lslFast,
1657 &feature_mpam,
1658 &feature_mte,
1659 &feature_neon,
1660 &feature_nv,
1661 &feature_noNegImmediates,
1662 &feature_pa,
1663 &feature_pan,
1664 &feature_panRwv,
1665 &feature_perfmon,
1666 &feature_usePostraScheduler,
1667 &feature_predres,
1668 &feature_predictableSelectExpensive,
1669 &feature_uaops,
1670 &feature_ras,
1671 &feature_rasv8_4,
1672 &feature_rcpc,
1673 &feature_rcpcImmo,
1674 &feature_rdm,
1675 &feature_rand,
1676 &feature_reserveX1,
1677 &feature_reserveX2,
1678 &feature_reserveX3,
1679 &feature_reserveX4,
1680 &feature_reserveX5,
1681 &feature_reserveX6,
1682 &feature_reserveX7,
1683 &feature_reserveX9,
1684 &feature_reserveX10,
1685 &feature_reserveX11,
1686 &feature_reserveX12,
1687 &feature_reserveX13,
1688 &feature_reserveX14,
1689 &feature_reserveX15,
1690 &feature_reserveX18,
1691 &feature_reserveX20,
1692 &feature_reserveX21,
1693 &feature_reserveX22,
1694 &feature_reserveX23,
1695 &feature_reserveX24,
1696 &feature_reserveX25,
1697 &feature_reserveX26,
1698 &feature_reserveX27,
1699 &feature_reserveX28,
1700 &feature_sb,
1701 &feature_sel2,
1702 &feature_sha2,
1703 &feature_sha3,
1704 &feature_sm4,
1705 &feature_spe,
1706 &feature_ssbs,
1707 &feature_sve,
1708 &feature_sve2,
1709 &feature_sve2Aes,
1710 &feature_sve2Bitperm,
1711 &feature_sve2Sha3,
1712 &feature_sve2Sm4,
1713 &feature_slowMisaligned128store,
1714 &feature_slowPaired128,
1715 &feature_slowStrqroStore,
1716 &feature_specrestrict,
1717 &feature_strictAlign,
1718 &feature_tlbRmi,
1719 &feature_tme,
1720 &feature_tracev84,
1721 &feature_trbe,
1722 &feature_taggedGlobals,
1723 &feature_useAa,
1724 &feature_tpidrEl1,
1725 &feature_tpidrEl2,
1726 &feature_tpidrEl3,
1727 &feature_useReciprocalSquareRoot,
1728 &feature_vh,
1729 &feature_zcm,
1730 &feature_zcz,
1731 &feature_zczFp,
1732 &feature_zczFpWorkaround,
1733 &feature_zczGp,
1734 &feature_v81a,
1735 &feature_v82a,
1736 &feature_v83a,
1737 &feature_v84a,
1738 &feature_v85a,
1739 &feature_a35,
1740 &feature_a53,
1741 &feature_a55,
1742 &feature_a57,
1743 &feature_a65,
1744 &feature_a72,
1745 &feature_a73,
1746 &feature_a75,
1747 &feature_a76,
1748 &feature_cyclone,
1749 &feature_exynosm1,
1750 &feature_exynosm2,
1751 &feature_exynosm3,
1752 &feature_exynosm4,
1753 &feature_falkor,
1754 &feature_kryo,
1755 &feature_neoversee1,
1756 &feature_neoversen1,
1757 &feature_saphira,
1758 &feature_tsv110,
1759 &feature_thunderx,
1760 &feature_thunderx2t99,
1761 &feature_thunderxt81,
1762 &feature_thunderxt83,
1763 &feature_thunderxt88,
1764};
1765
1766pub const cpu_appleLatest = Cpu{
1767 .name = "apple-latest",
1768 .llvm_name = "apple-latest",
1769 .subfeatures = &[_]*const Feature {
1770 &feature_zczGp,
1771 &feature_arithBccFusion,
1772 &feature_fuseAes,
1773 &feature_zczFp,
1774 &feature_zczFpWorkaround,
1775 &feature_fpArmv8,
1776 &feature_perfmon,
1777 &feature_disableLatencySchedHeuristic,
1778 &feature_zcm,
1779 &feature_arithCbzFusion,
1780 &feature_fuseCryptoEor,
1781 &feature_alternateSextloadCvtF32Pattern,
1782 &feature_cyclone,
1783 },
1784};
1785
1786pub const cpu_cortexA35 = Cpu{
1787 .name = "cortex-a35",
1788 .llvm_name = "cortex-a35",
1789 .subfeatures = &[_]*const Feature {
1790 &feature_fpArmv8,
1791 &feature_perfmon,
1792 &feature_crc,
1793 &feature_a35,
1794 },
1795};
1796
1797pub const cpu_cortexA53 = Cpu{
1798 .name = "cortex-a53",
1799 .llvm_name = "cortex-a53",
1800 .subfeatures = &[_]*const Feature {
1801 &feature_usePostraScheduler,
1802 &feature_customCheapAsMove,
1803 &feature_fuseAes,
1804 &feature_balanceFpOps,
1805 &feature_fpArmv8,
1806 &feature_perfmon,
1807 &feature_useAa,
1808 &feature_crc,
1809 &feature_a53,
1810 },
1811};
1812
1813pub const cpu_cortexA55 = Cpu{
1814 .name = "cortex-a55",
1815 .llvm_name = "cortex-a55",
1816 .subfeatures = &[_]*const Feature {
1817 &feature_rdm,
1818 &feature_fuseAes,
1819 &feature_ccpp,
1820 &feature_lse,
1821 &feature_fpArmv8,
1822 &feature_perfmon,
1823 &feature_ras,
1824 &feature_dotprod,
1825 &feature_lor,
1826 &feature_pan,
1827 &feature_crc,
1828 &feature_rcpc,
1829 &feature_uaops,
1830 &feature_vh,
1831 &feature_a55,
1832 },
1833};
1834
1835pub const cpu_cortexA57 = Cpu{
1836 .name = "cortex-a57",
1837 .llvm_name = "cortex-a57",
1838 .subfeatures = &[_]*const Feature {
1839 &feature_usePostraScheduler,
1840 &feature_customCheapAsMove,
1841 &feature_fuseAes,
1842 &feature_balanceFpOps,
1843 &feature_fpArmv8,
1844 &feature_perfmon,
1845 &feature_predictableSelectExpensive,
1846 &feature_fuseLiterals,
1847 &feature_crc,
1848 &feature_a57,
1849 },
1850};
1851
1852pub const cpu_cortexA65 = Cpu{
1853 .name = "cortex-a65",
1854 .llvm_name = "cortex-a65",
1855 .subfeatures = &[_]*const Feature {
1856 &feature_rdm,
1857 &feature_ccpp,
1858 &feature_lse,
1859 &feature_fpArmv8,
1860 &feature_ras,
1861 &feature_dotprod,
1862 &feature_lor,
1863 &feature_pan,
1864 &feature_crc,
1865 &feature_rcpc,
1866 &feature_uaops,
1867 &feature_vh,
1868 &feature_ssbs,
1869 &feature_a65,
1870 },
1871};
1872
1873pub const cpu_cortexA65ae = Cpu{
1874 .name = "cortex-a65ae",
1875 .llvm_name = "cortex-a65ae",
1876 .subfeatures = &[_]*const Feature {
1877 &feature_rdm,
1878 &feature_ccpp,
1879 &feature_lse,
1880 &feature_fpArmv8,
1881 &feature_ras,
1882 &feature_dotprod,
1883 &feature_lor,
1884 &feature_pan,
1885 &feature_crc,
1886 &feature_rcpc,
1887 &feature_uaops,
1888 &feature_vh,
1889 &feature_ssbs,
1890 &feature_a65,
1891 },
1892};
1893
1894pub const cpu_cortexA72 = Cpu{
1895 .name = "cortex-a72",
1896 .llvm_name = "cortex-a72",
1897 .subfeatures = &[_]*const Feature {
1898 &feature_fpArmv8,
1899 &feature_perfmon,
1900 &feature_crc,
1901 &feature_fuseAes,
1902 &feature_a72,
1903 },
1904};
1905
1906pub const cpu_cortexA73 = Cpu{
1907 .name = "cortex-a73",
1908 .llvm_name = "cortex-a73",
1909 .subfeatures = &[_]*const Feature {
1910 &feature_fpArmv8,
1911 &feature_perfmon,
1912 &feature_crc,
1913 &feature_fuseAes,
1914 &feature_a73,
1915 },
1916};
1917
1918pub const cpu_cortexA75 = Cpu{
1919 .name = "cortex-a75",
1920 .llvm_name = "cortex-a75",
1921 .subfeatures = &[_]*const Feature {
1922 &feature_rdm,
1923 &feature_fuseAes,
1924 &feature_ccpp,
1925 &feature_lse,
1926 &feature_fpArmv8,
1927 &feature_perfmon,
1928 &feature_ras,
1929 &feature_dotprod,
1930 &feature_lor,
1931 &feature_pan,
1932 &feature_crc,
1933 &feature_rcpc,
1934 &feature_uaops,
1935 &feature_vh,
1936 &feature_a75,
1937 },
1938};
1939
1940pub const cpu_cortexA76 = Cpu{
1941 .name = "cortex-a76",
1942 .llvm_name = "cortex-a76",
1943 .subfeatures = &[_]*const Feature {
1944 &feature_rdm,
1945 &feature_ccpp,
1946 &feature_lse,
1947 &feature_fpArmv8,
1948 &feature_ras,
1949 &feature_dotprod,
1950 &feature_lor,
1951 &feature_pan,
1952 &feature_crc,
1953 &feature_rcpc,
1954 &feature_uaops,
1955 &feature_vh,
1956 &feature_ssbs,
1957 &feature_a76,
1958 },
1959};
1960
1961pub const cpu_cortexA76ae = Cpu{
1962 .name = "cortex-a76ae",
1963 .llvm_name = "cortex-a76ae",
1964 .subfeatures = &[_]*const Feature {
1965 &feature_rdm,
1966 &feature_ccpp,
1967 &feature_lse,
1968 &feature_fpArmv8,
1969 &feature_ras,
1970 &feature_dotprod,
1971 &feature_lor,
1972 &feature_pan,
1973 &feature_crc,
1974 &feature_rcpc,
1975 &feature_uaops,
1976 &feature_vh,
1977 &feature_ssbs,
1978 &feature_a76,
1979 },
1980};
1981
1982pub const cpu_cyclone = Cpu{
1983 .name = "cyclone",
1984 .llvm_name = "cyclone",
1985 .subfeatures = &[_]*const Feature {
1986 &feature_zczGp,
1987 &feature_arithBccFusion,
1988 &feature_fuseAes,
1989 &feature_zczFp,
1990 &feature_zczFpWorkaround,
1991 &feature_fpArmv8,
1992 &feature_perfmon,
1993 &feature_disableLatencySchedHeuristic,
1994 &feature_zcm,
1995 &feature_arithCbzFusion,
1996 &feature_fuseCryptoEor,
1997 &feature_alternateSextloadCvtF32Pattern,
1998 &feature_cyclone,
1999 },
2000};
2001
2002pub const cpu_exynosM1 = Cpu{
2003 .name = "exynos-m1",
2004 .llvm_name = "exynos-m1",
2005 .subfeatures = &[_]*const Feature {
2006 &feature_usePostraScheduler,
2007 &feature_slowMisaligned128store,
2008 &feature_customCheapAsMove,
2009 &feature_fuseAes,
2010 &feature_zczFp,
2011 &feature_fpArmv8,
2012 &feature_perfmon,
2013 &feature_slowPaired128,
2014 &feature_useReciprocalSquareRoot,
2015 &feature_force32bitJumpTables,
2016 &feature_crc,
2017 &feature_exynosm1,
2018 },
2019};
2020
2021pub const cpu_exynosM2 = Cpu{
2022 .name = "exynos-m2",
2023 .llvm_name = "exynos-m2",
2024 .subfeatures = &[_]*const Feature {
2025 &feature_usePostraScheduler,
2026 &feature_slowMisaligned128store,
2027 &feature_customCheapAsMove,
2028 &feature_fuseAes,
2029 &feature_zczFp,
2030 &feature_fpArmv8,
2031 &feature_perfmon,
2032 &feature_slowPaired128,
2033 &feature_force32bitJumpTables,
2034 &feature_crc,
2035 &feature_exynosm2,
2036 },
2037};
2038
2039pub const cpu_exynosM3 = Cpu{
2040 .name = "exynos-m3",
2041 .llvm_name = "exynos-m3",
2042 .subfeatures = &[_]*const Feature {
2043 &feature_usePostraScheduler,
2044 &feature_customCheapAsMove,
2045 &feature_fuseAes,
2046 &feature_fuseAddress,
2047 &feature_zczFp,
2048 &feature_fpArmv8,
2049 &feature_perfmon,
2050 &feature_predictableSelectExpensive,
2051 &feature_fuseLiterals,
2052 &feature_force32bitJumpTables,
2053 &feature_crc,
2054 &feature_lslFast,
2055 &feature_fuseCsel,
2056 &feature_exynosm3,
2057 },
2058};
2059
2060pub const cpu_exynosM4 = Cpu{
2061 .name = "exynos-m4",
2062 .llvm_name = "exynos-m4",
2063 .subfeatures = &[_]*const Feature {
2064 &feature_ccpp,
2065 &feature_perfmon,
2066 &feature_dotprod,
2067 &feature_fuseArithLogic,
2068 &feature_force32bitJumpTables,
2069 &feature_lslFast,
2070 &feature_zczGp,
2071 &feature_customCheapAsMove,
2072 &feature_fuseAes,
2073 &feature_fuseAddress,
2074 &feature_lse,
2075 &feature_arithCbzFusion,
2076 &feature_uaops,
2077 &feature_fuseCsel,
2078 &feature_vh,
2079 &feature_rdm,
2080 &feature_fpArmv8,
2081 &feature_ras,
2082 &feature_fuseLiterals,
2083 &feature_crc,
2084 &feature_usePostraScheduler,
2085 &feature_arithBccFusion,
2086 &feature_zczFp,
2087 &feature_lor,
2088 &feature_pan,
2089 &feature_exynosm4,
2090 },
2091};
2092
2093pub const cpu_exynosM5 = Cpu{
2094 .name = "exynos-m5",
2095 .llvm_name = "exynos-m5",
2096 .subfeatures = &[_]*const Feature {
2097 &feature_ccpp,
2098 &feature_perfmon,
2099 &feature_dotprod,
2100 &feature_fuseArithLogic,
2101 &feature_force32bitJumpTables,
2102 &feature_lslFast,
2103 &feature_zczGp,
2104 &feature_customCheapAsMove,
2105 &feature_fuseAes,
2106 &feature_fuseAddress,
2107 &feature_lse,
2108 &feature_arithCbzFusion,
2109 &feature_uaops,
2110 &feature_fuseCsel,
2111 &feature_vh,
2112 &feature_rdm,
2113 &feature_fpArmv8,
2114 &feature_ras,
2115 &feature_fuseLiterals,
2116 &feature_crc,
2117 &feature_usePostraScheduler,
2118 &feature_arithBccFusion,
2119 &feature_zczFp,
2120 &feature_lor,
2121 &feature_pan,
2122 &feature_exynosm4,
2123 },
2124};
2125
2126pub const cpu_falkor = Cpu{
2127 .name = "falkor",
2128 .llvm_name = "falkor",
2129 .subfeatures = &[_]*const Feature {
2130 &feature_rdm,
2131 &feature_usePostraScheduler,
2132 &feature_zczGp,
2133 &feature_slowStrqroStore,
2134 &feature_customCheapAsMove,
2135 &feature_zczFp,
2136 &feature_fpArmv8,
2137 &feature_perfmon,
2138 &feature_predictableSelectExpensive,
2139 &feature_crc,
2140 &feature_lslFast,
2141 &feature_falkor,
2142 },
2143};
2144
2145pub const cpu_generic = Cpu{
2146 .name = "generic",
2147 .llvm_name = "generic",
2148 .subfeatures = &[_]*const Feature {
2149 &feature_trbe,
2150 &feature_ete,
2151 &feature_fpArmv8,
2152 &feature_fuseAes,
2153 &feature_neon,
2154 &feature_perfmon,
2155 &feature_usePostraScheduler,
2156 },
2157};
2158
2159pub const cpu_kryo = Cpu{
2160 .name = "kryo",
2161 .llvm_name = "kryo",
2162 .subfeatures = &[_]*const Feature {
2163 &feature_usePostraScheduler,
2164 &feature_zczGp,
2165 &feature_customCheapAsMove,
2166 &feature_zczFp,
2167 &feature_fpArmv8,
2168 &feature_perfmon,
2169 &feature_predictableSelectExpensive,
2170 &feature_crc,
2171 &feature_lslFast,
2172 &feature_kryo,
2173 },
2174};
2175
2176pub const cpu_neoverseE1 = Cpu{
2177 .name = "neoverse-e1",
2178 .llvm_name = "neoverse-e1",
2179 .subfeatures = &[_]*const Feature {
2180 &feature_rdm,
2181 &feature_ccpp,
2182 &feature_lse,
2183 &feature_fpArmv8,
2184 &feature_ras,
2185 &feature_dotprod,
2186 &feature_lor,
2187 &feature_pan,
2188 &feature_crc,
2189 &feature_rcpc,
2190 &feature_uaops,
2191 &feature_vh,
2192 &feature_ssbs,
2193 &feature_neoversee1,
2194 },
2195};
2196
2197pub const cpu_neoverseN1 = Cpu{
2198 .name = "neoverse-n1",
2199 .llvm_name = "neoverse-n1",
2200 .subfeatures = &[_]*const Feature {
2201 &feature_rdm,
2202 &feature_ccpp,
2203 &feature_lse,
2204 &feature_fpArmv8,
2205 &feature_ras,
2206 &feature_dotprod,
2207 &feature_lor,
2208 &feature_spe,
2209 &feature_pan,
2210 &feature_crc,
2211 &feature_rcpc,
2212 &feature_uaops,
2213 &feature_vh,
2214 &feature_ssbs,
2215 &feature_neoversen1,
2216 },
2217};
2218
2219pub const cpu_saphira = Cpu{
2220 .name = "saphira",
2221 .llvm_name = "saphira",
2222 .subfeatures = &[_]*const Feature {
2223 &feature_am,
2224 &feature_nv,
2225 &feature_ccpp,
2226 &feature_predictableSelectExpensive,
2227 &feature_perfmon,
2228 &feature_dotprod,
2229 &feature_spe,
2230 &feature_lslFast,
2231 &feature_zczGp,
2232 &feature_customCheapAsMove,
2233 &feature_lse,
2234 &feature_rcpc,
2235 &feature_uaops,
2236 &feature_ccidx,
2237 &feature_vh,
2238 &feature_tracev84,
2239 &feature_rdm,
2240 &feature_fpArmv8,
2241 &feature_dit,
2242 &feature_mpam,
2243 &feature_ras,
2244 &feature_tlbRmi,
2245 &feature_fmi,
2246 &feature_crc,
2247 &feature_usePostraScheduler,
2248 &feature_pa,
2249 &feature_zczFp,
2250 &feature_sel2,
2251 &feature_lor,
2252 &feature_pan,
2253 &feature_saphira,
2254 },
2255};
2256
2257pub const cpu_thunderx = Cpu{
2258 .name = "thunderx",
2259 .llvm_name = "thunderx",
2260 .subfeatures = &[_]*const Feature {
2261 &feature_usePostraScheduler,
2262 &feature_predictableSelectExpensive,
2263 &feature_fpArmv8,
2264 &feature_perfmon,
2265 &feature_crc,
2266 &feature_thunderx,
2267 },
2268};
2269
2270pub const cpu_thunderx2t99 = Cpu{
2271 .name = "thunderx2t99",
2272 .llvm_name = "thunderx2t99",
2273 .subfeatures = &[_]*const Feature {
2274 &feature_rdm,
2275 &feature_usePostraScheduler,
2276 &feature_arithBccFusion,
2277 &feature_lse,
2278 &feature_fpArmv8,
2279 &feature_predictableSelectExpensive,
2280 &feature_lor,
2281 &feature_crc,
2282 &feature_pan,
2283 &feature_aggressiveFma,
2284 &feature_vh,
2285 &feature_thunderx2t99,
2286 },
2287};
2288
2289pub const cpu_thunderxt81 = Cpu{
2290 .name = "thunderxt81",
2291 .llvm_name = "thunderxt81",
2292 .subfeatures = &[_]*const Feature {
2293 &feature_usePostraScheduler,
2294 &feature_predictableSelectExpensive,
2295 &feature_fpArmv8,
2296 &feature_perfmon,
2297 &feature_crc,
2298 &feature_thunderxt81,
2299 },
2300};
2301
2302pub const cpu_thunderxt83 = Cpu{
2303 .name = "thunderxt83",
2304 .llvm_name = "thunderxt83",
2305 .subfeatures = &[_]*const Feature {
2306 &feature_usePostraScheduler,
2307 &feature_predictableSelectExpensive,
2308 &feature_fpArmv8,
2309 &feature_perfmon,
2310 &feature_crc,
2311 &feature_thunderxt83,
2312 },
2313};
2314
2315pub const cpu_thunderxt88 = Cpu{
2316 .name = "thunderxt88",
2317 .llvm_name = "thunderxt88",
2318 .subfeatures = &[_]*const Feature {
2319 &feature_usePostraScheduler,
2320 &feature_predictableSelectExpensive,
2321 &feature_fpArmv8,
2322 &feature_perfmon,
2323 &feature_crc,
2324 &feature_thunderxt88,
2325 },
2326};
2327
2328pub const cpu_tsv110 = Cpu{
2329 .name = "tsv110",
2330 .llvm_name = "tsv110",
2331 .subfeatures = &[_]*const Feature {
2332 &feature_rdm,
2333 &feature_usePostraScheduler,
2334 &feature_customCheapAsMove,
2335 &feature_fuseAes,
2336 &feature_ccpp,
2337 &feature_lse,
2338 &feature_fpArmv8,
2339 &feature_perfmon,
2340 &feature_ras,
2341 &feature_dotprod,
2342 &feature_lor,
2343 &feature_spe,
2344 &feature_crc,
2345 &feature_pan,
2346 &feature_uaops,
2347 &feature_vh,
2348 &feature_tsv110,
2349 },
2350};
2351
2352pub const cpus = &[_]*const Cpu {
2353 &cpu_appleLatest,
2354 &cpu_cortexA35,
2355 &cpu_cortexA53,
2356 &cpu_cortexA55,
2357 &cpu_cortexA57,
2358 &cpu_cortexA65,
2359 &cpu_cortexA65ae,
2360 &cpu_cortexA72,
2361 &cpu_cortexA73,
2362 &cpu_cortexA75,
2363 &cpu_cortexA76,
2364 &cpu_cortexA76ae,
2365 &cpu_cyclone,
2366 &cpu_exynosM1,
2367 &cpu_exynosM2,
2368 &cpu_exynosM3,
2369 &cpu_exynosM4,
2370 &cpu_exynosM5,
2371 &cpu_falkor,
2372 &cpu_generic,
2373 &cpu_kryo,
2374 &cpu_neoverseE1,
2375 &cpu_neoverseN1,
2376 &cpu_saphira,
2377 &cpu_thunderx,
2378 &cpu_thunderx2t99,
2379 &cpu_thunderxt81,
2380 &cpu_thunderxt83,
2381 &cpu_thunderxt88,
2382 &cpu_tsv110,
2383};
lib/std/target/amdgpu.zig created+2329
......@@ -0,0 +1,2329 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_BitInsts16 = Feature{
5 .name = "16-bit-insts",
6 .description = "Has i16/f16 instructions",
7 .llvm_name = "16-bit-insts",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_addNoCarryInsts = Feature{
13 .name = "add-no-carry-insts",
14 .description = "Have VALU add/sub instructions without carry out",
15 .llvm_name = "add-no-carry-insts",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_apertureRegs = Feature{
21 .name = "aperture-regs",
22 .description = "Has Memory Aperture Base and Size Registers",
23 .llvm_name = "aperture-regs",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_atomicFaddInsts = Feature{
29 .name = "atomic-fadd-insts",
30 .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",
31 .llvm_name = "atomic-fadd-insts",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_autoWaitcntBeforeBarrier = Feature{
37 .name = "auto-waitcnt-before-barrier",
38 .description = "Hardware automatically inserts waitcnt before barrier",
39 .llvm_name = "auto-waitcnt-before-barrier",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_ciInsts = Feature{
45 .name = "ci-insts",
46 .description = "Additional instructions for CI+",
47 .llvm_name = "ci-insts",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_codeObjectV3 = Feature{
53 .name = "code-object-v3",
54 .description = "Generate code object version 3",
55 .llvm_name = "code-object-v3",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_cumode = Feature{
61 .name = "cumode",
62 .description = "Enable CU wavefront execution mode",
63 .llvm_name = "cumode",
64 .subfeatures = &[_]*const Feature {
65 },
66};
67
68pub const feature_dlInsts = Feature{
69 .name = "dl-insts",
70 .description = "Has v_fmac_f32 and v_xnor_b32 instructions",
71 .llvm_name = "dl-insts",
72 .subfeatures = &[_]*const Feature {
73 },
74};
75
76pub const feature_dpp = Feature{
77 .name = "dpp",
78 .description = "Support DPP (Data Parallel Primitives) extension",
79 .llvm_name = "dpp",
80 .subfeatures = &[_]*const Feature {
81 },
82};
83
84pub const feature_dpp8 = Feature{
85 .name = "dpp8",
86 .description = "Support DPP8 (Data Parallel Primitives) extension",
87 .llvm_name = "dpp8",
88 .subfeatures = &[_]*const Feature {
89 },
90};
91
92pub const feature_noSramEccSupport = Feature{
93 .name = "no-sram-ecc-support",
94 .description = "Hardware does not support SRAM ECC",
95 .llvm_name = "no-sram-ecc-support",
96 .subfeatures = &[_]*const Feature {
97 },
98};
99
100pub const feature_noXnackSupport = Feature{
101 .name = "no-xnack-support",
102 .description = "Hardware does not support XNACK",
103 .llvm_name = "no-xnack-support",
104 .subfeatures = &[_]*const Feature {
105 },
106};
107
108pub const feature_dot1Insts = Feature{
109 .name = "dot1-insts",
110 .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
111 .llvm_name = "dot1-insts",
112 .subfeatures = &[_]*const Feature {
113 },
114};
115
116pub const feature_dot2Insts = Feature{
117 .name = "dot2-insts",
118 .description = "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
119 .llvm_name = "dot2-insts",
120 .subfeatures = &[_]*const Feature {
121 },
122};
123
124pub const feature_dot3Insts = Feature{
125 .name = "dot3-insts",
126 .description = "Has v_dot8c_i32_i4 instruction",
127 .llvm_name = "dot3-insts",
128 .subfeatures = &[_]*const Feature {
129 },
130};
131
132pub const feature_dot4Insts = Feature{
133 .name = "dot4-insts",
134 .description = "Has v_dot2c_i32_i16 instruction",
135 .llvm_name = "dot4-insts",
136 .subfeatures = &[_]*const Feature {
137 },
138};
139
140pub const feature_dot5Insts = Feature{
141 .name = "dot5-insts",
142 .description = "Has v_dot2c_f32_f16 instruction",
143 .llvm_name = "dot5-insts",
144 .subfeatures = &[_]*const Feature {
145 },
146};
147
148pub const feature_dot6Insts = Feature{
149 .name = "dot6-insts",
150 .description = "Has v_dot4c_i32_i8 instruction",
151 .llvm_name = "dot6-insts",
152 .subfeatures = &[_]*const Feature {
153 },
154};
155
156pub const feature_DumpCode = Feature{
157 .name = "DumpCode",
158 .description = "Dump MachineInstrs in the CodeEmitter",
159 .llvm_name = "DumpCode",
160 .subfeatures = &[_]*const Feature {
161 },
162};
163
164pub const feature_dumpcode = Feature{
165 .name = "dumpcode",
166 .description = "Dump MachineInstrs in the CodeEmitter",
167 .llvm_name = "dumpcode",
168 .subfeatures = &[_]*const Feature {
169 },
170};
171
172pub const feature_enableDs128 = Feature{
173 .name = "enable-ds128",
174 .description = "Use ds_{read|write}_b128",
175 .llvm_name = "enable-ds128",
176 .subfeatures = &[_]*const Feature {
177 },
178};
179
180pub const feature_loadStoreOpt = Feature{
181 .name = "load-store-opt",
182 .description = "Enable SI load/store optimizer pass",
183 .llvm_name = "load-store-opt",
184 .subfeatures = &[_]*const Feature {
185 },
186};
187
188pub const feature_enablePrtStrictNull = Feature{
189 .name = "enable-prt-strict-null",
190 .description = "Enable zeroing of result registers for sparse texture fetches",
191 .llvm_name = "enable-prt-strict-null",
192 .subfeatures = &[_]*const Feature {
193 },
194};
195
196pub const feature_siScheduler = Feature{
197 .name = "si-scheduler",
198 .description = "Enable SI Machine Scheduler",
199 .llvm_name = "si-scheduler",
200 .subfeatures = &[_]*const Feature {
201 },
202};
203
204pub const feature_unsafeDsOffsetFolding = Feature{
205 .name = "unsafe-ds-offset-folding",
206 .description = "Force using DS instruction immediate offsets on SI",
207 .llvm_name = "unsafe-ds-offset-folding",
208 .subfeatures = &[_]*const Feature {
209 },
210};
211
212pub const feature_fmaf = Feature{
213 .name = "fmaf",
214 .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
215 .llvm_name = "fmaf",
216 .subfeatures = &[_]*const Feature {
217 },
218};
219
220pub const feature_fp16Denormals = Feature{
221 .name = "fp16-denormals",
222 .description = "Enable half precision denormal handling",
223 .llvm_name = "fp16-denormals",
224 .subfeatures = &[_]*const Feature {
225 &feature_fp64,
226 },
227};
228
229pub const feature_fp32Denormals = Feature{
230 .name = "fp32-denormals",
231 .description = "Enable single precision denormal handling",
232 .llvm_name = "fp32-denormals",
233 .subfeatures = &[_]*const Feature {
234 },
235};
236
237pub const feature_fp64 = Feature{
238 .name = "fp64",
239 .description = "Enable double precision operations",
240 .llvm_name = "fp64",
241 .subfeatures = &[_]*const Feature {
242 },
243};
244
245pub const feature_fp64Denormals = Feature{
246 .name = "fp64-denormals",
247 .description = "Enable double and half precision denormal handling",
248 .llvm_name = "fp64-denormals",
249 .subfeatures = &[_]*const Feature {
250 &feature_fp64,
251 },
252};
253
254pub const feature_fp64Fp16Denormals = Feature{
255 .name = "fp64-fp16-denormals",
256 .description = "Enable double and half precision denormal handling",
257 .llvm_name = "fp64-fp16-denormals",
258 .subfeatures = &[_]*const Feature {
259 &feature_fp64,
260 },
261};
262
263pub const feature_fpExceptions = Feature{
264 .name = "fp-exceptions",
265 .description = "Enable floating point exceptions",
266 .llvm_name = "fp-exceptions",
267 .subfeatures = &[_]*const Feature {
268 },
269};
270
271pub const feature_fastFmaf = Feature{
272 .name = "fast-fmaf",
273 .description = "Assuming f32 fma is at least as fast as mul + add",
274 .llvm_name = "fast-fmaf",
275 .subfeatures = &[_]*const Feature {
276 },
277};
278
279pub const feature_flatAddressSpace = Feature{
280 .name = "flat-address-space",
281 .description = "Support flat address space",
282 .llvm_name = "flat-address-space",
283 .subfeatures = &[_]*const Feature {
284 },
285};
286
287pub const feature_flatForGlobal = Feature{
288 .name = "flat-for-global",
289 .description = "Force to generate flat instruction for global",
290 .llvm_name = "flat-for-global",
291 .subfeatures = &[_]*const Feature {
292 },
293};
294
295pub const feature_flatGlobalInsts = Feature{
296 .name = "flat-global-insts",
297 .description = "Have global_* flat memory instructions",
298 .llvm_name = "flat-global-insts",
299 .subfeatures = &[_]*const Feature {
300 },
301};
302
303pub const feature_flatInstOffsets = Feature{
304 .name = "flat-inst-offsets",
305 .description = "Flat instructions have immediate offset addressing mode",
306 .llvm_name = "flat-inst-offsets",
307 .subfeatures = &[_]*const Feature {
308 },
309};
310
311pub const feature_flatScratchInsts = Feature{
312 .name = "flat-scratch-insts",
313 .description = "Have scratch_* flat memory instructions",
314 .llvm_name = "flat-scratch-insts",
315 .subfeatures = &[_]*const Feature {
316 },
317};
318
319pub const feature_flatSegmentOffsetBug = Feature{
320 .name = "flat-segment-offset-bug",
321 .description = "GFX10 bug, inst_offset ignored in flat segment",
322 .llvm_name = "flat-segment-offset-bug",
323 .subfeatures = &[_]*const Feature {
324 },
325};
326
327pub const feature_fmaMixInsts = Feature{
328 .name = "fma-mix-insts",
329 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
330 .llvm_name = "fma-mix-insts",
331 .subfeatures = &[_]*const Feature {
332 },
333};
334
335pub const feature_gcn3Encoding = Feature{
336 .name = "gcn3-encoding",
337 .description = "Encoding format for VI",
338 .llvm_name = "gcn3-encoding",
339 .subfeatures = &[_]*const Feature {
340 },
341};
342
343pub const feature_gfx7Gfx8Gfx9Insts = Feature{
344 .name = "gfx7-gfx8-gfx9-insts",
345 .description = "Instructions shared in GFX7, GFX8, GFX9",
346 .llvm_name = "gfx7-gfx8-gfx9-insts",
347 .subfeatures = &[_]*const Feature {
348 },
349};
350
351pub const feature_gfx8Insts = Feature{
352 .name = "gfx8-insts",
353 .description = "Additional instructions for GFX8+",
354 .llvm_name = "gfx8-insts",
355 .subfeatures = &[_]*const Feature {
356 },
357};
358
359pub const feature_gfx9 = Feature{
360 .name = "gfx9",
361 .description = "GFX9 GPU generation",
362 .llvm_name = "gfx9",
363 .subfeatures = &[_]*const Feature {
364 &feature_gfx9Insts,
365 &feature_ciInsts,
366 &feature_sdwa,
367 &feature_localmemorysize65536,
368 &feature_scalarStores,
369 &feature_sdwaScalar,
370 &feature_sdwaSdst,
371 &feature_gcn3Encoding,
372 &feature_apertureRegs,
373 &feature_flatScratchInsts,
374 &feature_r128A16,
375 &feature_flatAddressSpace,
376 &feature_dpp,
377 &feature_addNoCarryInsts,
378 &feature_inv2piInlineImm,
379 &feature_fp64,
380 &feature_BitInsts16,
381 &feature_vgprIndexMode,
382 &feature_wavefrontsize64,
383 &feature_gfx8Insts,
384 &feature_flatGlobalInsts,
385 &feature_scalarFlatScratchInsts,
386 &feature_scalarAtomics,
387 &feature_flatInstOffsets,
388 &feature_gfx7Gfx8Gfx9Insts,
389 &feature_vop3p,
390 &feature_sMemrealtime,
391 &feature_intClampInsts,
392 &feature_fastFmaf,
393 &feature_sdwaOmod,
394 },
395};
396
397pub const feature_gfx9Insts = Feature{
398 .name = "gfx9-insts",
399 .description = "Additional instructions for GFX9+",
400 .llvm_name = "gfx9-insts",
401 .subfeatures = &[_]*const Feature {
402 },
403};
404
405pub const feature_gfx10 = Feature{
406 .name = "gfx10",
407 .description = "GFX10 GPU generation",
408 .llvm_name = "gfx10",
409 .subfeatures = &[_]*const Feature {
410 &feature_movrel,
411 &feature_gfx9Insts,
412 &feature_ciInsts,
413 &feature_noSramEccSupport,
414 &feature_noSdstCmpx,
415 &feature_fmaMixInsts,
416 &feature_sdwa,
417 &feature_localmemorysize65536,
418 &feature_sdwaScalar,
419 &feature_sdwaSdst,
420 &feature_apertureRegs,
421 &feature_flatScratchInsts,
422 &feature_vscnt,
423 &feature_noDataDepHazard,
424 &feature_flatAddressSpace,
425 &feature_dpp,
426 &feature_addNoCarryInsts,
427 &feature_inv2piInlineImm,
428 &feature_fp64,
429 &feature_dpp8,
430 &feature_BitInsts16,
431 &feature_registerBanking,
432 &feature_gfx8Insts,
433 &feature_flatGlobalInsts,
434 &feature_flatInstOffsets,
435 &feature_pkFmacF16Inst,
436 &feature_vop3p,
437 &feature_mimgR128,
438 &feature_intClampInsts,
439 &feature_sMemrealtime,
440 &feature_fastFmaf,
441 &feature_vop3Literal,
442 &feature_sdwaOmod,
443 &feature_gfx10Insts,
444 },
445};
446
447pub const feature_gfx10Insts = Feature{
448 .name = "gfx10-insts",
449 .description = "Additional instructions for GFX10+",
450 .llvm_name = "gfx10-insts",
451 .subfeatures = &[_]*const Feature {
452 },
453};
454
455pub const feature_instFwdPrefetchBug = Feature{
456 .name = "inst-fwd-prefetch-bug",
457 .description = "S_INST_PREFETCH instruction causes shader to hang",
458 .llvm_name = "inst-fwd-prefetch-bug",
459 .subfeatures = &[_]*const Feature {
460 },
461};
462
463pub const feature_intClampInsts = Feature{
464 .name = "int-clamp-insts",
465 .description = "Support clamp for integer destination",
466 .llvm_name = "int-clamp-insts",
467 .subfeatures = &[_]*const Feature {
468 },
469};
470
471pub const feature_inv2piInlineImm = Feature{
472 .name = "inv-2pi-inline-imm",
473 .description = "Has 1 / (2 * pi) as inline immediate",
474 .llvm_name = "inv-2pi-inline-imm",
475 .subfeatures = &[_]*const Feature {
476 },
477};
478
479pub const feature_ldsbankcount16 = Feature{
480 .name = "ldsbankcount16",
481 .description = "The number of LDS banks per compute unit.",
482 .llvm_name = "ldsbankcount16",
483 .subfeatures = &[_]*const Feature {
484 },
485};
486
487pub const feature_ldsbankcount32 = Feature{
488 .name = "ldsbankcount32",
489 .description = "The number of LDS banks per compute unit.",
490 .llvm_name = "ldsbankcount32",
491 .subfeatures = &[_]*const Feature {
492 },
493};
494
495pub const feature_ldsBranchVmemWarHazard = Feature{
496 .name = "lds-branch-vmem-war-hazard",
497 .description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
498 .llvm_name = "lds-branch-vmem-war-hazard",
499 .subfeatures = &[_]*const Feature {
500 },
501};
502
503pub const feature_ldsMisalignedBug = Feature{
504 .name = "lds-misaligned-bug",
505 .description = "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode",
506 .llvm_name = "lds-misaligned-bug",
507 .subfeatures = &[_]*const Feature {
508 },
509};
510
511pub const feature_localmemorysize0 = Feature{
512 .name = "localmemorysize0",
513 .description = "The size of local memory in bytes",
514 .llvm_name = "localmemorysize0",
515 .subfeatures = &[_]*const Feature {
516 },
517};
518
519pub const feature_localmemorysize32768 = Feature{
520 .name = "localmemorysize32768",
521 .description = "The size of local memory in bytes",
522 .llvm_name = "localmemorysize32768",
523 .subfeatures = &[_]*const Feature {
524 },
525};
526
527pub const feature_localmemorysize65536 = Feature{
528 .name = "localmemorysize65536",
529 .description = "The size of local memory in bytes",
530 .llvm_name = "localmemorysize65536",
531 .subfeatures = &[_]*const Feature {
532 },
533};
534
535pub const feature_maiInsts = Feature{
536 .name = "mai-insts",
537 .description = "Has mAI instructions",
538 .llvm_name = "mai-insts",
539 .subfeatures = &[_]*const Feature {
540 },
541};
542
543pub const feature_mfmaInlineLiteralBug = Feature{
544 .name = "mfma-inline-literal-bug",
545 .description = "MFMA cannot use inline literal as SrcC",
546 .llvm_name = "mfma-inline-literal-bug",
547 .subfeatures = &[_]*const Feature {
548 },
549};
550
551pub const feature_mimgR128 = Feature{
552 .name = "mimg-r128",
553 .description = "Support 128-bit texture resources",
554 .llvm_name = "mimg-r128",
555 .subfeatures = &[_]*const Feature {
556 },
557};
558
559pub const feature_madMixInsts = Feature{
560 .name = "mad-mix-insts",
561 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
562 .llvm_name = "mad-mix-insts",
563 .subfeatures = &[_]*const Feature {
564 },
565};
566
567pub const feature_maxPrivateElementSize4 = Feature{
568 .name = "max-private-element-size-4",
569 .description = "Maximum private access size may be 4",
570 .llvm_name = "max-private-element-size-4",
571 .subfeatures = &[_]*const Feature {
572 },
573};
574
575pub const feature_maxPrivateElementSize8 = Feature{
576 .name = "max-private-element-size-8",
577 .description = "Maximum private access size may be 8",
578 .llvm_name = "max-private-element-size-8",
579 .subfeatures = &[_]*const Feature {
580 },
581};
582
583pub const feature_maxPrivateElementSize16 = Feature{
584 .name = "max-private-element-size-16",
585 .description = "Maximum private access size may be 16",
586 .llvm_name = "max-private-element-size-16",
587 .subfeatures = &[_]*const Feature {
588 },
589};
590
591pub const feature_movrel = Feature{
592 .name = "movrel",
593 .description = "Has v_movrel*_b32 instructions",
594 .llvm_name = "movrel",
595 .subfeatures = &[_]*const Feature {
596 },
597};
598
599pub const feature_nsaEncoding = Feature{
600 .name = "nsa-encoding",
601 .description = "Support NSA encoding for image instructions",
602 .llvm_name = "nsa-encoding",
603 .subfeatures = &[_]*const Feature {
604 },
605};
606
607pub const feature_nsaToVmemBug = Feature{
608 .name = "nsa-to-vmem-bug",
609 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
610 .llvm_name = "nsa-to-vmem-bug",
611 .subfeatures = &[_]*const Feature {
612 },
613};
614
615pub const feature_noDataDepHazard = Feature{
616 .name = "no-data-dep-hazard",
617 .description = "Does not need SW waitstates",
618 .llvm_name = "no-data-dep-hazard",
619 .subfeatures = &[_]*const Feature {
620 },
621};
622
623pub const feature_noSdstCmpx = Feature{
624 .name = "no-sdst-cmpx",
625 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
626 .llvm_name = "no-sdst-cmpx",
627 .subfeatures = &[_]*const Feature {
628 },
629};
630
631pub const feature_offset3fBug = Feature{
632 .name = "offset-3f-bug",
633 .description = "Branch offset of 3f hardware bug",
634 .llvm_name = "offset-3f-bug",
635 .subfeatures = &[_]*const Feature {
636 },
637};
638
639pub const feature_pkFmacF16Inst = Feature{
640 .name = "pk-fmac-f16-inst",
641 .description = "Has v_pk_fmac_f16 instruction",
642 .llvm_name = "pk-fmac-f16-inst",
643 .subfeatures = &[_]*const Feature {
644 },
645};
646
647pub const feature_promoteAlloca = Feature{
648 .name = "promote-alloca",
649 .description = "Enable promote alloca pass",
650 .llvm_name = "promote-alloca",
651 .subfeatures = &[_]*const Feature {
652 },
653};
654
655pub const feature_r128A16 = Feature{
656 .name = "r128-a16",
657 .description = "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9",
658 .llvm_name = "r128-a16",
659 .subfeatures = &[_]*const Feature {
660 },
661};
662
663pub const feature_registerBanking = Feature{
664 .name = "register-banking",
665 .description = "Has register banking",
666 .llvm_name = "register-banking",
667 .subfeatures = &[_]*const Feature {
668 },
669};
670
671pub const feature_sdwa = Feature{
672 .name = "sdwa",
673 .description = "Support SDWA (Sub-DWORD Addressing) extension",
674 .llvm_name = "sdwa",
675 .subfeatures = &[_]*const Feature {
676 },
677};
678
679pub const feature_sdwaMav = Feature{
680 .name = "sdwa-mav",
681 .description = "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension",
682 .llvm_name = "sdwa-mav",
683 .subfeatures = &[_]*const Feature {
684 },
685};
686
687pub const feature_sdwaOmod = Feature{
688 .name = "sdwa-omod",
689 .description = "Support OMod with SDWA (Sub-DWORD Addressing) extension",
690 .llvm_name = "sdwa-omod",
691 .subfeatures = &[_]*const Feature {
692 },
693};
694
695pub const feature_sdwaOutModsVopc = Feature{
696 .name = "sdwa-out-mods-vopc",
697 .description = "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension",
698 .llvm_name = "sdwa-out-mods-vopc",
699 .subfeatures = &[_]*const Feature {
700 },
701};
702
703pub const feature_sdwaScalar = Feature{
704 .name = "sdwa-scalar",
705 .description = "Support scalar register with SDWA (Sub-DWORD Addressing) extension",
706 .llvm_name = "sdwa-scalar",
707 .subfeatures = &[_]*const Feature {
708 },
709};
710
711pub const feature_sdwaSdst = Feature{
712 .name = "sdwa-sdst",
713 .description = "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension",
714 .llvm_name = "sdwa-sdst",
715 .subfeatures = &[_]*const Feature {
716 },
717};
718
719pub const feature_sgprInitBug = Feature{
720 .name = "sgpr-init-bug",
721 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
722 .llvm_name = "sgpr-init-bug",
723 .subfeatures = &[_]*const Feature {
724 },
725};
726
727pub const feature_smemToVectorWriteHazard = Feature{
728 .name = "smem-to-vector-write-hazard",
729 .description = "s_load_dword followed by v_cmp page faults",
730 .llvm_name = "smem-to-vector-write-hazard",
731 .subfeatures = &[_]*const Feature {
732 },
733};
734
735pub const feature_sMemrealtime = Feature{
736 .name = "s-memrealtime",
737 .description = "Has s_memrealtime instruction",
738 .llvm_name = "s-memrealtime",
739 .subfeatures = &[_]*const Feature {
740 },
741};
742
743pub const feature_sramEcc = Feature{
744 .name = "sram-ecc",
745 .description = "Enable SRAM ECC",
746 .llvm_name = "sram-ecc",
747 .subfeatures = &[_]*const Feature {
748 },
749};
750
751pub const feature_scalarAtomics = Feature{
752 .name = "scalar-atomics",
753 .description = "Has atomic scalar memory instructions",
754 .llvm_name = "scalar-atomics",
755 .subfeatures = &[_]*const Feature {
756 },
757};
758
759pub const feature_scalarFlatScratchInsts = Feature{
760 .name = "scalar-flat-scratch-insts",
761 .description = "Have s_scratch_* flat memory instructions",
762 .llvm_name = "scalar-flat-scratch-insts",
763 .subfeatures = &[_]*const Feature {
764 },
765};
766
767pub const feature_scalarStores = Feature{
768 .name = "scalar-stores",
769 .description = "Has store scalar memory instructions",
770 .llvm_name = "scalar-stores",
771 .subfeatures = &[_]*const Feature {
772 },
773};
774
775pub const feature_seaIslands = Feature{
776 .name = "sea-islands",
777 .description = "SEA_ISLANDS GPU generation",
778 .llvm_name = "sea-islands",
779 .subfeatures = &[_]*const Feature {
780 &feature_gfx7Gfx8Gfx9Insts,
781 &feature_mimgR128,
782 &feature_localmemorysize65536,
783 &feature_movrel,
784 &feature_trigReducedRange,
785 &feature_wavefrontsize64,
786 &feature_flatAddressSpace,
787 &feature_ciInsts,
788 &feature_noSramEccSupport,
789 &feature_fp64,
790 },
791};
792
793pub const feature_southernIslands = Feature{
794 .name = "southern-islands",
795 .description = "SOUTHERN_ISLANDS GPU generation",
796 .llvm_name = "southern-islands",
797 .subfeatures = &[_]*const Feature {
798 &feature_mimgR128,
799 &feature_movrel,
800 &feature_localmemorysize32768,
801 &feature_trigReducedRange,
802 &feature_ldsbankcount32,
803 &feature_wavefrontsize64,
804 &feature_noSramEccSupport,
805 &feature_noXnackSupport,
806 &feature_fp64,
807 },
808};
809
810pub const feature_trapHandler = Feature{
811 .name = "trap-handler",
812 .description = "Trap handler support",
813 .llvm_name = "trap-handler",
814 .subfeatures = &[_]*const Feature {
815 },
816};
817
818pub const feature_trigReducedRange = Feature{
819 .name = "trig-reduced-range",
820 .description = "Requires use of fract on arguments to trig instructions",
821 .llvm_name = "trig-reduced-range",
822 .subfeatures = &[_]*const Feature {
823 },
824};
825
826pub const feature_unalignedBufferAccess = Feature{
827 .name = "unaligned-buffer-access",
828 .description = "Support unaligned global loads and stores",
829 .llvm_name = "unaligned-buffer-access",
830 .subfeatures = &[_]*const Feature {
831 },
832};
833
834pub const feature_unalignedScratchAccess = Feature{
835 .name = "unaligned-scratch-access",
836 .description = "Support unaligned scratch loads and stores",
837 .llvm_name = "unaligned-scratch-access",
838 .subfeatures = &[_]*const Feature {
839 },
840};
841
842pub const feature_unpackedD16Vmem = Feature{
843 .name = "unpacked-d16-vmem",
844 .description = "Has unpacked d16 vmem instructions",
845 .llvm_name = "unpacked-d16-vmem",
846 .subfeatures = &[_]*const Feature {
847 },
848};
849
850pub const feature_vgprIndexMode = Feature{
851 .name = "vgpr-index-mode",
852 .description = "Has VGPR mode register indexing",
853 .llvm_name = "vgpr-index-mode",
854 .subfeatures = &[_]*const Feature {
855 },
856};
857
858pub const feature_vmemToScalarWriteHazard = Feature{
859 .name = "vmem-to-scalar-write-hazard",
860 .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
861 .llvm_name = "vmem-to-scalar-write-hazard",
862 .subfeatures = &[_]*const Feature {
863 },
864};
865
866pub const feature_vop3Literal = Feature{
867 .name = "vop3-literal",
868 .description = "Can use one literal in VOP3",
869 .llvm_name = "vop3-literal",
870 .subfeatures = &[_]*const Feature {
871 },
872};
873
874pub const feature_vop3p = Feature{
875 .name = "vop3p",
876 .description = "Has VOP3P packed instructions",
877 .llvm_name = "vop3p",
878 .subfeatures = &[_]*const Feature {
879 },
880};
881
882pub const feature_vcmpxExecWarHazard = Feature{
883 .name = "vcmpx-exec-war-hazard",
884 .description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
885 .llvm_name = "vcmpx-exec-war-hazard",
886 .subfeatures = &[_]*const Feature {
887 },
888};
889
890pub const feature_vcmpxPermlaneHazard = Feature{
891 .name = "vcmpx-permlane-hazard",
892 .description = "TODO: describe me",
893 .llvm_name = "vcmpx-permlane-hazard",
894 .subfeatures = &[_]*const Feature {
895 },
896};
897
898pub const feature_volcanicIslands = Feature{
899 .name = "volcanic-islands",
900 .description = "VOLCANIC_ISLANDS GPU generation",
901 .llvm_name = "volcanic-islands",
902 .subfeatures = &[_]*const Feature {
903 &feature_movrel,
904 &feature_ciInsts,
905 &feature_noSramEccSupport,
906 &feature_sdwa,
907 &feature_localmemorysize65536,
908 &feature_scalarStores,
909 &feature_gcn3Encoding,
910 &feature_flatAddressSpace,
911 &feature_dpp,
912 &feature_inv2piInlineImm,
913 &feature_fp64,
914 &feature_BitInsts16,
915 &feature_trigReducedRange,
916 &feature_vgprIndexMode,
917 &feature_wavefrontsize64,
918 &feature_gfx8Insts,
919 &feature_gfx7Gfx8Gfx9Insts,
920 &feature_mimgR128,
921 &feature_intClampInsts,
922 &feature_sMemrealtime,
923 &feature_sdwaMav,
924 &feature_sdwaOutModsVopc,
925 },
926};
927
928pub const feature_vscnt = Feature{
929 .name = "vscnt",
930 .description = "Has separate store vscnt counter",
931 .llvm_name = "vscnt",
932 .subfeatures = &[_]*const Feature {
933 },
934};
935
936pub const feature_wavefrontsize16 = Feature{
937 .name = "wavefrontsize16",
938 .description = "The number of threads per wavefront",
939 .llvm_name = "wavefrontsize16",
940 .subfeatures = &[_]*const Feature {
941 },
942};
943
944pub const feature_wavefrontsize32 = Feature{
945 .name = "wavefrontsize32",
946 .description = "The number of threads per wavefront",
947 .llvm_name = "wavefrontsize32",
948 .subfeatures = &[_]*const Feature {
949 },
950};
951
952pub const feature_wavefrontsize64 = Feature{
953 .name = "wavefrontsize64",
954 .description = "The number of threads per wavefront",
955 .llvm_name = "wavefrontsize64",
956 .subfeatures = &[_]*const Feature {
957 },
958};
959
960pub const feature_xnack = Feature{
961 .name = "xnack",
962 .description = "Enable XNACK support",
963 .llvm_name = "xnack",
964 .subfeatures = &[_]*const Feature {
965 },
966};
967
968pub const feature_halfRate64Ops = Feature{
969 .name = "half-rate-64-ops",
970 .description = "Most fp64 instructions are half rate instead of quarter",
971 .llvm_name = "half-rate-64-ops",
972 .subfeatures = &[_]*const Feature {
973 },
974};
975
976pub const features = &[_]*const Feature {
977 &feature_BitInsts16,
978 &feature_addNoCarryInsts,
979 &feature_apertureRegs,
980 &feature_atomicFaddInsts,
981 &feature_autoWaitcntBeforeBarrier,
982 &feature_ciInsts,
983 &feature_codeObjectV3,
984 &feature_cumode,
985 &feature_dlInsts,
986 &feature_dpp,
987 &feature_dpp8,
988 &feature_noSramEccSupport,
989 &feature_noXnackSupport,
990 &feature_dot1Insts,
991 &feature_dot2Insts,
992 &feature_dot3Insts,
993 &feature_dot4Insts,
994 &feature_dot5Insts,
995 &feature_dot6Insts,
996 &feature_DumpCode,
997 &feature_dumpcode,
998 &feature_enableDs128,
999 &feature_loadStoreOpt,
1000 &feature_enablePrtStrictNull,
1001 &feature_siScheduler,
1002 &feature_unsafeDsOffsetFolding,
1003 &feature_fmaf,
1004 &feature_fp16Denormals,
1005 &feature_fp32Denormals,
1006 &feature_fp64,
1007 &feature_fp64Denormals,
1008 &feature_fp64Fp16Denormals,
1009 &feature_fpExceptions,
1010 &feature_fastFmaf,
1011 &feature_flatAddressSpace,
1012 &feature_flatForGlobal,
1013 &feature_flatGlobalInsts,
1014 &feature_flatInstOffsets,
1015 &feature_flatScratchInsts,
1016 &feature_flatSegmentOffsetBug,
1017 &feature_fmaMixInsts,
1018 &feature_gcn3Encoding,
1019 &feature_gfx7Gfx8Gfx9Insts,
1020 &feature_gfx8Insts,
1021 &feature_gfx9,
1022 &feature_gfx9Insts,
1023 &feature_gfx10,
1024 &feature_gfx10Insts,
1025 &feature_instFwdPrefetchBug,
1026 &feature_intClampInsts,
1027 &feature_inv2piInlineImm,
1028 &feature_ldsbankcount16,
1029 &feature_ldsbankcount32,
1030 &feature_ldsBranchVmemWarHazard,
1031 &feature_ldsMisalignedBug,
1032 &feature_localmemorysize0,
1033 &feature_localmemorysize32768,
1034 &feature_localmemorysize65536,
1035 &feature_maiInsts,
1036 &feature_mfmaInlineLiteralBug,
1037 &feature_mimgR128,
1038 &feature_madMixInsts,
1039 &feature_maxPrivateElementSize4,
1040 &feature_maxPrivateElementSize8,
1041 &feature_maxPrivateElementSize16,
1042 &feature_movrel,
1043 &feature_nsaEncoding,
1044 &feature_nsaToVmemBug,
1045 &feature_noDataDepHazard,
1046 &feature_noSdstCmpx,
1047 &feature_offset3fBug,
1048 &feature_pkFmacF16Inst,
1049 &feature_promoteAlloca,
1050 &feature_r128A16,
1051 &feature_registerBanking,
1052 &feature_sdwa,
1053 &feature_sdwaMav,
1054 &feature_sdwaOmod,
1055 &feature_sdwaOutModsVopc,
1056 &feature_sdwaScalar,
1057 &feature_sdwaSdst,
1058 &feature_sgprInitBug,
1059 &feature_smemToVectorWriteHazard,
1060 &feature_sMemrealtime,
1061 &feature_sramEcc,
1062 &feature_scalarAtomics,
1063 &feature_scalarFlatScratchInsts,
1064 &feature_scalarStores,
1065 &feature_seaIslands,
1066 &feature_southernIslands,
1067 &feature_trapHandler,
1068 &feature_trigReducedRange,
1069 &feature_unalignedBufferAccess,
1070 &feature_unalignedScratchAccess,
1071 &feature_unpackedD16Vmem,
1072 &feature_vgprIndexMode,
1073 &feature_vmemToScalarWriteHazard,
1074 &feature_vop3Literal,
1075 &feature_vop3p,
1076 &feature_vcmpxExecWarHazard,
1077 &feature_vcmpxPermlaneHazard,
1078 &feature_volcanicIslands,
1079 &feature_vscnt,
1080 &feature_wavefrontsize16,
1081 &feature_wavefrontsize32,
1082 &feature_wavefrontsize64,
1083 &feature_xnack,
1084 &feature_halfRate64Ops,
1085};
1086
1087pub const cpu_bonaire = Cpu{
1088 .name = "bonaire",
1089 .llvm_name = "bonaire",
1090 .subfeatures = &[_]*const Feature {
1091 &feature_codeObjectV3,
1092 &feature_noXnackSupport,
1093 &feature_ldsbankcount32,
1094 &feature_gfx7Gfx8Gfx9Insts,
1095 &feature_mimgR128,
1096 &feature_localmemorysize65536,
1097 &feature_movrel,
1098 &feature_trigReducedRange,
1099 &feature_wavefrontsize64,
1100 &feature_flatAddressSpace,
1101 &feature_ciInsts,
1102 &feature_noSramEccSupport,
1103 &feature_fp64,
1104 &feature_seaIslands,
1105 },
1106};
1107
1108pub const cpu_carrizo = Cpu{
1109 .name = "carrizo",
1110 .llvm_name = "carrizo",
1111 .subfeatures = &[_]*const Feature {
1112 &feature_codeObjectV3,
1113 &feature_fastFmaf,
1114 &feature_ldsbankcount32,
1115 &feature_unpackedD16Vmem,
1116 &feature_movrel,
1117 &feature_ciInsts,
1118 &feature_noSramEccSupport,
1119 &feature_sdwa,
1120 &feature_localmemorysize65536,
1121 &feature_scalarStores,
1122 &feature_gcn3Encoding,
1123 &feature_flatAddressSpace,
1124 &feature_dpp,
1125 &feature_inv2piInlineImm,
1126 &feature_fp64,
1127 &feature_BitInsts16,
1128 &feature_trigReducedRange,
1129 &feature_vgprIndexMode,
1130 &feature_wavefrontsize64,
1131 &feature_gfx8Insts,
1132 &feature_gfx7Gfx8Gfx9Insts,
1133 &feature_mimgR128,
1134 &feature_intClampInsts,
1135 &feature_sMemrealtime,
1136 &feature_sdwaMav,
1137 &feature_sdwaOutModsVopc,
1138 &feature_volcanicIslands,
1139 &feature_xnack,
1140 &feature_halfRate64Ops,
1141 },
1142};
1143
1144pub const cpu_fiji = Cpu{
1145 .name = "fiji",
1146 .llvm_name = "fiji",
1147 .subfeatures = &[_]*const Feature {
1148 &feature_codeObjectV3,
1149 &feature_noXnackSupport,
1150 &feature_ldsbankcount32,
1151 &feature_unpackedD16Vmem,
1152 &feature_movrel,
1153 &feature_ciInsts,
1154 &feature_noSramEccSupport,
1155 &feature_sdwa,
1156 &feature_localmemorysize65536,
1157 &feature_scalarStores,
1158 &feature_gcn3Encoding,
1159 &feature_flatAddressSpace,
1160 &feature_dpp,
1161 &feature_inv2piInlineImm,
1162 &feature_fp64,
1163 &feature_BitInsts16,
1164 &feature_trigReducedRange,
1165 &feature_vgprIndexMode,
1166 &feature_wavefrontsize64,
1167 &feature_gfx8Insts,
1168 &feature_gfx7Gfx8Gfx9Insts,
1169 &feature_mimgR128,
1170 &feature_intClampInsts,
1171 &feature_sMemrealtime,
1172 &feature_sdwaMav,
1173 &feature_sdwaOutModsVopc,
1174 &feature_volcanicIslands,
1175 },
1176};
1177
1178pub const cpu_generic = Cpu{
1179 .name = "generic",
1180 .llvm_name = "generic",
1181 .subfeatures = &[_]*const Feature {
1182 &feature_wavefrontsize64,
1183 },
1184};
1185
1186pub const cpu_genericHsa = Cpu{
1187 .name = "generic-hsa",
1188 .llvm_name = "generic-hsa",
1189 .subfeatures = &[_]*const Feature {
1190 &feature_flatAddressSpace,
1191 &feature_wavefrontsize64,
1192 },
1193};
1194
1195pub const cpu_gfx1010 = Cpu{
1196 .name = "gfx1010",
1197 .llvm_name = "gfx1010",
1198 .subfeatures = &[_]*const Feature {
1199 &feature_codeObjectV3,
1200 &feature_dlInsts,
1201 &feature_noXnackSupport,
1202 &feature_flatSegmentOffsetBug,
1203 &feature_movrel,
1204 &feature_gfx9Insts,
1205 &feature_ciInsts,
1206 &feature_noSramEccSupport,
1207 &feature_noSdstCmpx,
1208 &feature_fmaMixInsts,
1209 &feature_sdwa,
1210 &feature_localmemorysize65536,
1211 &feature_sdwaScalar,
1212 &feature_sdwaSdst,
1213 &feature_apertureRegs,
1214 &feature_flatScratchInsts,
1215 &feature_vscnt,
1216 &feature_noDataDepHazard,
1217 &feature_flatAddressSpace,
1218 &feature_dpp,
1219 &feature_addNoCarryInsts,
1220 &feature_inv2piInlineImm,
1221 &feature_fp64,
1222 &feature_dpp8,
1223 &feature_BitInsts16,
1224 &feature_registerBanking,
1225 &feature_gfx8Insts,
1226 &feature_flatGlobalInsts,
1227 &feature_flatInstOffsets,
1228 &feature_pkFmacF16Inst,
1229 &feature_vop3p,
1230 &feature_mimgR128,
1231 &feature_intClampInsts,
1232 &feature_sMemrealtime,
1233 &feature_fastFmaf,
1234 &feature_vop3Literal,
1235 &feature_sdwaOmod,
1236 &feature_gfx10Insts,
1237 &feature_gfx10,
1238 &feature_instFwdPrefetchBug,
1239 &feature_ldsbankcount32,
1240 &feature_ldsBranchVmemWarHazard,
1241 &feature_ldsMisalignedBug,
1242 &feature_nsaEncoding,
1243 &feature_nsaToVmemBug,
1244 &feature_offset3fBug,
1245 &feature_smemToVectorWriteHazard,
1246 &feature_scalarAtomics,
1247 &feature_scalarFlatScratchInsts,
1248 &feature_scalarStores,
1249 &feature_vmemToScalarWriteHazard,
1250 &feature_vcmpxExecWarHazard,
1251 &feature_vcmpxPermlaneHazard,
1252 &feature_wavefrontsize32,
1253 },
1254};
1255
1256pub const cpu_gfx1011 = Cpu{
1257 .name = "gfx1011",
1258 .llvm_name = "gfx1011",
1259 .subfeatures = &[_]*const Feature {
1260 &feature_codeObjectV3,
1261 &feature_dlInsts,
1262 &feature_noXnackSupport,
1263 &feature_dot1Insts,
1264 &feature_dot2Insts,
1265 &feature_dot5Insts,
1266 &feature_dot6Insts,
1267 &feature_flatSegmentOffsetBug,
1268 &feature_movrel,
1269 &feature_gfx9Insts,
1270 &feature_ciInsts,
1271 &feature_noSramEccSupport,
1272 &feature_noSdstCmpx,
1273 &feature_fmaMixInsts,
1274 &feature_sdwa,
1275 &feature_localmemorysize65536,
1276 &feature_sdwaScalar,
1277 &feature_sdwaSdst,
1278 &feature_apertureRegs,
1279 &feature_flatScratchInsts,
1280 &feature_vscnt,
1281 &feature_noDataDepHazard,
1282 &feature_flatAddressSpace,
1283 &feature_dpp,
1284 &feature_addNoCarryInsts,
1285 &feature_inv2piInlineImm,
1286 &feature_fp64,
1287 &feature_dpp8,
1288 &feature_BitInsts16,
1289 &feature_registerBanking,
1290 &feature_gfx8Insts,
1291 &feature_flatGlobalInsts,
1292 &feature_flatInstOffsets,
1293 &feature_pkFmacF16Inst,
1294 &feature_vop3p,
1295 &feature_mimgR128,
1296 &feature_intClampInsts,
1297 &feature_sMemrealtime,
1298 &feature_fastFmaf,
1299 &feature_vop3Literal,
1300 &feature_sdwaOmod,
1301 &feature_gfx10Insts,
1302 &feature_gfx10,
1303 &feature_instFwdPrefetchBug,
1304 &feature_ldsbankcount32,
1305 &feature_ldsBranchVmemWarHazard,
1306 &feature_nsaEncoding,
1307 &feature_nsaToVmemBug,
1308 &feature_offset3fBug,
1309 &feature_smemToVectorWriteHazard,
1310 &feature_scalarAtomics,
1311 &feature_scalarFlatScratchInsts,
1312 &feature_scalarStores,
1313 &feature_vmemToScalarWriteHazard,
1314 &feature_vcmpxExecWarHazard,
1315 &feature_vcmpxPermlaneHazard,
1316 &feature_wavefrontsize32,
1317 },
1318};
1319
1320pub const cpu_gfx1012 = Cpu{
1321 .name = "gfx1012",
1322 .llvm_name = "gfx1012",
1323 .subfeatures = &[_]*const Feature {
1324 &feature_codeObjectV3,
1325 &feature_dlInsts,
1326 &feature_noXnackSupport,
1327 &feature_dot1Insts,
1328 &feature_dot2Insts,
1329 &feature_dot5Insts,
1330 &feature_dot6Insts,
1331 &feature_flatSegmentOffsetBug,
1332 &feature_movrel,
1333 &feature_gfx9Insts,
1334 &feature_ciInsts,
1335 &feature_noSramEccSupport,
1336 &feature_noSdstCmpx,
1337 &feature_fmaMixInsts,
1338 &feature_sdwa,
1339 &feature_localmemorysize65536,
1340 &feature_sdwaScalar,
1341 &feature_sdwaSdst,
1342 &feature_apertureRegs,
1343 &feature_flatScratchInsts,
1344 &feature_vscnt,
1345 &feature_noDataDepHazard,
1346 &feature_flatAddressSpace,
1347 &feature_dpp,
1348 &feature_addNoCarryInsts,
1349 &feature_inv2piInlineImm,
1350 &feature_fp64,
1351 &feature_dpp8,
1352 &feature_BitInsts16,
1353 &feature_registerBanking,
1354 &feature_gfx8Insts,
1355 &feature_flatGlobalInsts,
1356 &feature_flatInstOffsets,
1357 &feature_pkFmacF16Inst,
1358 &feature_vop3p,
1359 &feature_mimgR128,
1360 &feature_intClampInsts,
1361 &feature_sMemrealtime,
1362 &feature_fastFmaf,
1363 &feature_vop3Literal,
1364 &feature_sdwaOmod,
1365 &feature_gfx10Insts,
1366 &feature_gfx10,
1367 &feature_instFwdPrefetchBug,
1368 &feature_ldsbankcount32,
1369 &feature_ldsBranchVmemWarHazard,
1370 &feature_ldsMisalignedBug,
1371 &feature_nsaEncoding,
1372 &feature_nsaToVmemBug,
1373 &feature_offset3fBug,
1374 &feature_smemToVectorWriteHazard,
1375 &feature_scalarAtomics,
1376 &feature_scalarFlatScratchInsts,
1377 &feature_scalarStores,
1378 &feature_vmemToScalarWriteHazard,
1379 &feature_vcmpxExecWarHazard,
1380 &feature_vcmpxPermlaneHazard,
1381 &feature_wavefrontsize32,
1382 },
1383};
1384
1385pub const cpu_gfx600 = Cpu{
1386 .name = "gfx600",
1387 .llvm_name = "gfx600",
1388 .subfeatures = &[_]*const Feature {
1389 &feature_codeObjectV3,
1390 &feature_noXnackSupport,
1391 &feature_fastFmaf,
1392 &feature_ldsbankcount32,
1393 &feature_mimgR128,
1394 &feature_movrel,
1395 &feature_localmemorysize32768,
1396 &feature_trigReducedRange,
1397 &feature_wavefrontsize64,
1398 &feature_noSramEccSupport,
1399 &feature_fp64,
1400 &feature_southernIslands,
1401 &feature_halfRate64Ops,
1402 },
1403};
1404
1405pub const cpu_gfx601 = Cpu{
1406 .name = "gfx601",
1407 .llvm_name = "gfx601",
1408 .subfeatures = &[_]*const Feature {
1409 &feature_codeObjectV3,
1410 &feature_noXnackSupport,
1411 &feature_ldsbankcount32,
1412 &feature_mimgR128,
1413 &feature_movrel,
1414 &feature_localmemorysize32768,
1415 &feature_trigReducedRange,
1416 &feature_wavefrontsize64,
1417 &feature_noSramEccSupport,
1418 &feature_fp64,
1419 &feature_southernIslands,
1420 },
1421};
1422
1423pub const cpu_gfx700 = Cpu{
1424 .name = "gfx700",
1425 .llvm_name = "gfx700",
1426 .subfeatures = &[_]*const Feature {
1427 &feature_codeObjectV3,
1428 &feature_noXnackSupport,
1429 &feature_ldsbankcount32,
1430 &feature_gfx7Gfx8Gfx9Insts,
1431 &feature_mimgR128,
1432 &feature_localmemorysize65536,
1433 &feature_movrel,
1434 &feature_trigReducedRange,
1435 &feature_wavefrontsize64,
1436 &feature_flatAddressSpace,
1437 &feature_ciInsts,
1438 &feature_noSramEccSupport,
1439 &feature_fp64,
1440 &feature_seaIslands,
1441 },
1442};
1443
1444pub const cpu_gfx701 = Cpu{
1445 .name = "gfx701",
1446 .llvm_name = "gfx701",
1447 .subfeatures = &[_]*const Feature {
1448 &feature_codeObjectV3,
1449 &feature_noXnackSupport,
1450 &feature_fastFmaf,
1451 &feature_ldsbankcount32,
1452 &feature_gfx7Gfx8Gfx9Insts,
1453 &feature_mimgR128,
1454 &feature_localmemorysize65536,
1455 &feature_movrel,
1456 &feature_trigReducedRange,
1457 &feature_wavefrontsize64,
1458 &feature_flatAddressSpace,
1459 &feature_ciInsts,
1460 &feature_noSramEccSupport,
1461 &feature_fp64,
1462 &feature_seaIslands,
1463 &feature_halfRate64Ops,
1464 },
1465};
1466
1467pub const cpu_gfx702 = Cpu{
1468 .name = "gfx702",
1469 .llvm_name = "gfx702",
1470 .subfeatures = &[_]*const Feature {
1471 &feature_codeObjectV3,
1472 &feature_noXnackSupport,
1473 &feature_fastFmaf,
1474 &feature_ldsbankcount16,
1475 &feature_gfx7Gfx8Gfx9Insts,
1476 &feature_mimgR128,
1477 &feature_localmemorysize65536,
1478 &feature_movrel,
1479 &feature_trigReducedRange,
1480 &feature_wavefrontsize64,
1481 &feature_flatAddressSpace,
1482 &feature_ciInsts,
1483 &feature_noSramEccSupport,
1484 &feature_fp64,
1485 &feature_seaIslands,
1486 },
1487};
1488
1489pub const cpu_gfx703 = Cpu{
1490 .name = "gfx703",
1491 .llvm_name = "gfx703",
1492 .subfeatures = &[_]*const Feature {
1493 &feature_codeObjectV3,
1494 &feature_noXnackSupport,
1495 &feature_ldsbankcount16,
1496 &feature_gfx7Gfx8Gfx9Insts,
1497 &feature_mimgR128,
1498 &feature_localmemorysize65536,
1499 &feature_movrel,
1500 &feature_trigReducedRange,
1501 &feature_wavefrontsize64,
1502 &feature_flatAddressSpace,
1503 &feature_ciInsts,
1504 &feature_noSramEccSupport,
1505 &feature_fp64,
1506 &feature_seaIslands,
1507 },
1508};
1509
1510pub const cpu_gfx704 = Cpu{
1511 .name = "gfx704",
1512 .llvm_name = "gfx704",
1513 .subfeatures = &[_]*const Feature {
1514 &feature_codeObjectV3,
1515 &feature_noXnackSupport,
1516 &feature_ldsbankcount32,
1517 &feature_gfx7Gfx8Gfx9Insts,
1518 &feature_mimgR128,
1519 &feature_localmemorysize65536,
1520 &feature_movrel,
1521 &feature_trigReducedRange,
1522 &feature_wavefrontsize64,
1523 &feature_flatAddressSpace,
1524 &feature_ciInsts,
1525 &feature_noSramEccSupport,
1526 &feature_fp64,
1527 &feature_seaIslands,
1528 },
1529};
1530
1531pub const cpu_gfx801 = Cpu{
1532 .name = "gfx801",
1533 .llvm_name = "gfx801",
1534 .subfeatures = &[_]*const Feature {
1535 &feature_codeObjectV3,
1536 &feature_fastFmaf,
1537 &feature_ldsbankcount32,
1538 &feature_unpackedD16Vmem,
1539 &feature_movrel,
1540 &feature_ciInsts,
1541 &feature_noSramEccSupport,
1542 &feature_sdwa,
1543 &feature_localmemorysize65536,
1544 &feature_scalarStores,
1545 &feature_gcn3Encoding,
1546 &feature_flatAddressSpace,
1547 &feature_dpp,
1548 &feature_inv2piInlineImm,
1549 &feature_fp64,
1550 &feature_BitInsts16,
1551 &feature_trigReducedRange,
1552 &feature_vgprIndexMode,
1553 &feature_wavefrontsize64,
1554 &feature_gfx8Insts,
1555 &feature_gfx7Gfx8Gfx9Insts,
1556 &feature_mimgR128,
1557 &feature_intClampInsts,
1558 &feature_sMemrealtime,
1559 &feature_sdwaMav,
1560 &feature_sdwaOutModsVopc,
1561 &feature_volcanicIslands,
1562 &feature_xnack,
1563 &feature_halfRate64Ops,
1564 },
1565};
1566
1567pub const cpu_gfx802 = Cpu{
1568 .name = "gfx802",
1569 .llvm_name = "gfx802",
1570 .subfeatures = &[_]*const Feature {
1571 &feature_codeObjectV3,
1572 &feature_noXnackSupport,
1573 &feature_ldsbankcount32,
1574 &feature_sgprInitBug,
1575 &feature_unpackedD16Vmem,
1576 &feature_movrel,
1577 &feature_ciInsts,
1578 &feature_noSramEccSupport,
1579 &feature_sdwa,
1580 &feature_localmemorysize65536,
1581 &feature_scalarStores,
1582 &feature_gcn3Encoding,
1583 &feature_flatAddressSpace,
1584 &feature_dpp,
1585 &feature_inv2piInlineImm,
1586 &feature_fp64,
1587 &feature_BitInsts16,
1588 &feature_trigReducedRange,
1589 &feature_vgprIndexMode,
1590 &feature_wavefrontsize64,
1591 &feature_gfx8Insts,
1592 &feature_gfx7Gfx8Gfx9Insts,
1593 &feature_mimgR128,
1594 &feature_intClampInsts,
1595 &feature_sMemrealtime,
1596 &feature_sdwaMav,
1597 &feature_sdwaOutModsVopc,
1598 &feature_volcanicIslands,
1599 },
1600};
1601
1602pub const cpu_gfx803 = Cpu{
1603 .name = "gfx803",
1604 .llvm_name = "gfx803",
1605 .subfeatures = &[_]*const Feature {
1606 &feature_codeObjectV3,
1607 &feature_noXnackSupport,
1608 &feature_ldsbankcount32,
1609 &feature_unpackedD16Vmem,
1610 &feature_movrel,
1611 &feature_ciInsts,
1612 &feature_noSramEccSupport,
1613 &feature_sdwa,
1614 &feature_localmemorysize65536,
1615 &feature_scalarStores,
1616 &feature_gcn3Encoding,
1617 &feature_flatAddressSpace,
1618 &feature_dpp,
1619 &feature_inv2piInlineImm,
1620 &feature_fp64,
1621 &feature_BitInsts16,
1622 &feature_trigReducedRange,
1623 &feature_vgprIndexMode,
1624 &feature_wavefrontsize64,
1625 &feature_gfx8Insts,
1626 &feature_gfx7Gfx8Gfx9Insts,
1627 &feature_mimgR128,
1628 &feature_intClampInsts,
1629 &feature_sMemrealtime,
1630 &feature_sdwaMav,
1631 &feature_sdwaOutModsVopc,
1632 &feature_volcanicIslands,
1633 },
1634};
1635
1636pub const cpu_gfx810 = Cpu{
1637 .name = "gfx810",
1638 .llvm_name = "gfx810",
1639 .subfeatures = &[_]*const Feature {
1640 &feature_codeObjectV3,
1641 &feature_ldsbankcount16,
1642 &feature_movrel,
1643 &feature_ciInsts,
1644 &feature_noSramEccSupport,
1645 &feature_sdwa,
1646 &feature_localmemorysize65536,
1647 &feature_scalarStores,
1648 &feature_gcn3Encoding,
1649 &feature_flatAddressSpace,
1650 &feature_dpp,
1651 &feature_inv2piInlineImm,
1652 &feature_fp64,
1653 &feature_BitInsts16,
1654 &feature_trigReducedRange,
1655 &feature_vgprIndexMode,
1656 &feature_wavefrontsize64,
1657 &feature_gfx8Insts,
1658 &feature_gfx7Gfx8Gfx9Insts,
1659 &feature_mimgR128,
1660 &feature_intClampInsts,
1661 &feature_sMemrealtime,
1662 &feature_sdwaMav,
1663 &feature_sdwaOutModsVopc,
1664 &feature_volcanicIslands,
1665 &feature_xnack,
1666 },
1667};
1668
1669pub const cpu_gfx900 = Cpu{
1670 .name = "gfx900",
1671 .llvm_name = "gfx900",
1672 .subfeatures = &[_]*const Feature {
1673 &feature_codeObjectV3,
1674 &feature_noSramEccSupport,
1675 &feature_noXnackSupport,
1676 &feature_gfx9Insts,
1677 &feature_ciInsts,
1678 &feature_sdwa,
1679 &feature_localmemorysize65536,
1680 &feature_scalarStores,
1681 &feature_sdwaScalar,
1682 &feature_sdwaSdst,
1683 &feature_gcn3Encoding,
1684 &feature_apertureRegs,
1685 &feature_flatScratchInsts,
1686 &feature_r128A16,
1687 &feature_flatAddressSpace,
1688 &feature_dpp,
1689 &feature_addNoCarryInsts,
1690 &feature_inv2piInlineImm,
1691 &feature_fp64,
1692 &feature_BitInsts16,
1693 &feature_vgprIndexMode,
1694 &feature_wavefrontsize64,
1695 &feature_gfx8Insts,
1696 &feature_flatGlobalInsts,
1697 &feature_scalarFlatScratchInsts,
1698 &feature_scalarAtomics,
1699 &feature_flatInstOffsets,
1700 &feature_gfx7Gfx8Gfx9Insts,
1701 &feature_vop3p,
1702 &feature_sMemrealtime,
1703 &feature_intClampInsts,
1704 &feature_fastFmaf,
1705 &feature_sdwaOmod,
1706 &feature_gfx9,
1707 &feature_ldsbankcount32,
1708 &feature_madMixInsts,
1709 },
1710};
1711
1712pub const cpu_gfx902 = Cpu{
1713 .name = "gfx902",
1714 .llvm_name = "gfx902",
1715 .subfeatures = &[_]*const Feature {
1716 &feature_codeObjectV3,
1717 &feature_noSramEccSupport,
1718 &feature_gfx9Insts,
1719 &feature_ciInsts,
1720 &feature_sdwa,
1721 &feature_localmemorysize65536,
1722 &feature_scalarStores,
1723 &feature_sdwaScalar,
1724 &feature_sdwaSdst,
1725 &feature_gcn3Encoding,
1726 &feature_apertureRegs,
1727 &feature_flatScratchInsts,
1728 &feature_r128A16,
1729 &feature_flatAddressSpace,
1730 &feature_dpp,
1731 &feature_addNoCarryInsts,
1732 &feature_inv2piInlineImm,
1733 &feature_fp64,
1734 &feature_BitInsts16,
1735 &feature_vgprIndexMode,
1736 &feature_wavefrontsize64,
1737 &feature_gfx8Insts,
1738 &feature_flatGlobalInsts,
1739 &feature_scalarFlatScratchInsts,
1740 &feature_scalarAtomics,
1741 &feature_flatInstOffsets,
1742 &feature_gfx7Gfx8Gfx9Insts,
1743 &feature_vop3p,
1744 &feature_sMemrealtime,
1745 &feature_intClampInsts,
1746 &feature_fastFmaf,
1747 &feature_sdwaOmod,
1748 &feature_gfx9,
1749 &feature_ldsbankcount32,
1750 &feature_madMixInsts,
1751 &feature_xnack,
1752 },
1753};
1754
1755pub const cpu_gfx904 = Cpu{
1756 .name = "gfx904",
1757 .llvm_name = "gfx904",
1758 .subfeatures = &[_]*const Feature {
1759 &feature_codeObjectV3,
1760 &feature_noSramEccSupport,
1761 &feature_noXnackSupport,
1762 &feature_fmaMixInsts,
1763 &feature_gfx9Insts,
1764 &feature_ciInsts,
1765 &feature_sdwa,
1766 &feature_localmemorysize65536,
1767 &feature_scalarStores,
1768 &feature_sdwaScalar,
1769 &feature_sdwaSdst,
1770 &feature_gcn3Encoding,
1771 &feature_apertureRegs,
1772 &feature_flatScratchInsts,
1773 &feature_r128A16,
1774 &feature_flatAddressSpace,
1775 &feature_dpp,
1776 &feature_addNoCarryInsts,
1777 &feature_inv2piInlineImm,
1778 &feature_fp64,
1779 &feature_BitInsts16,
1780 &feature_vgprIndexMode,
1781 &feature_wavefrontsize64,
1782 &feature_gfx8Insts,
1783 &feature_flatGlobalInsts,
1784 &feature_scalarFlatScratchInsts,
1785 &feature_scalarAtomics,
1786 &feature_flatInstOffsets,
1787 &feature_gfx7Gfx8Gfx9Insts,
1788 &feature_vop3p,
1789 &feature_sMemrealtime,
1790 &feature_intClampInsts,
1791 &feature_fastFmaf,
1792 &feature_sdwaOmod,
1793 &feature_gfx9,
1794 &feature_ldsbankcount32,
1795 },
1796};
1797
1798pub const cpu_gfx906 = Cpu{
1799 .name = "gfx906",
1800 .llvm_name = "gfx906",
1801 .subfeatures = &[_]*const Feature {
1802 &feature_codeObjectV3,
1803 &feature_dlInsts,
1804 &feature_noXnackSupport,
1805 &feature_dot1Insts,
1806 &feature_dot2Insts,
1807 &feature_fmaMixInsts,
1808 &feature_gfx9Insts,
1809 &feature_ciInsts,
1810 &feature_sdwa,
1811 &feature_localmemorysize65536,
1812 &feature_scalarStores,
1813 &feature_sdwaScalar,
1814 &feature_sdwaSdst,
1815 &feature_gcn3Encoding,
1816 &feature_apertureRegs,
1817 &feature_flatScratchInsts,
1818 &feature_r128A16,
1819 &feature_flatAddressSpace,
1820 &feature_dpp,
1821 &feature_addNoCarryInsts,
1822 &feature_inv2piInlineImm,
1823 &feature_fp64,
1824 &feature_BitInsts16,
1825 &feature_vgprIndexMode,
1826 &feature_wavefrontsize64,
1827 &feature_gfx8Insts,
1828 &feature_flatGlobalInsts,
1829 &feature_scalarFlatScratchInsts,
1830 &feature_scalarAtomics,
1831 &feature_flatInstOffsets,
1832 &feature_gfx7Gfx8Gfx9Insts,
1833 &feature_vop3p,
1834 &feature_sMemrealtime,
1835 &feature_intClampInsts,
1836 &feature_fastFmaf,
1837 &feature_sdwaOmod,
1838 &feature_gfx9,
1839 &feature_ldsbankcount32,
1840 &feature_halfRate64Ops,
1841 },
1842};
1843
1844pub const cpu_gfx908 = Cpu{
1845 .name = "gfx908",
1846 .llvm_name = "gfx908",
1847 .subfeatures = &[_]*const Feature {
1848 &feature_atomicFaddInsts,
1849 &feature_codeObjectV3,
1850 &feature_dlInsts,
1851 &feature_dot1Insts,
1852 &feature_dot2Insts,
1853 &feature_dot3Insts,
1854 &feature_dot4Insts,
1855 &feature_dot5Insts,
1856 &feature_dot6Insts,
1857 &feature_fmaMixInsts,
1858 &feature_gfx9Insts,
1859 &feature_ciInsts,
1860 &feature_sdwa,
1861 &feature_localmemorysize65536,
1862 &feature_scalarStores,
1863 &feature_sdwaScalar,
1864 &feature_sdwaSdst,
1865 &feature_gcn3Encoding,
1866 &feature_apertureRegs,
1867 &feature_flatScratchInsts,
1868 &feature_r128A16,
1869 &feature_flatAddressSpace,
1870 &feature_dpp,
1871 &feature_addNoCarryInsts,
1872 &feature_inv2piInlineImm,
1873 &feature_fp64,
1874 &feature_BitInsts16,
1875 &feature_vgprIndexMode,
1876 &feature_wavefrontsize64,
1877 &feature_gfx8Insts,
1878 &feature_flatGlobalInsts,
1879 &feature_scalarFlatScratchInsts,
1880 &feature_scalarAtomics,
1881 &feature_flatInstOffsets,
1882 &feature_gfx7Gfx8Gfx9Insts,
1883 &feature_vop3p,
1884 &feature_sMemrealtime,
1885 &feature_intClampInsts,
1886 &feature_fastFmaf,
1887 &feature_sdwaOmod,
1888 &feature_gfx9,
1889 &feature_ldsbankcount32,
1890 &feature_maiInsts,
1891 &feature_mfmaInlineLiteralBug,
1892 &feature_pkFmacF16Inst,
1893 &feature_sramEcc,
1894 &feature_halfRate64Ops,
1895 },
1896};
1897
1898pub const cpu_gfx909 = Cpu{
1899 .name = "gfx909",
1900 .llvm_name = "gfx909",
1901 .subfeatures = &[_]*const Feature {
1902 &feature_codeObjectV3,
1903 &feature_gfx9Insts,
1904 &feature_ciInsts,
1905 &feature_sdwa,
1906 &feature_localmemorysize65536,
1907 &feature_scalarStores,
1908 &feature_sdwaScalar,
1909 &feature_sdwaSdst,
1910 &feature_gcn3Encoding,
1911 &feature_apertureRegs,
1912 &feature_flatScratchInsts,
1913 &feature_r128A16,
1914 &feature_flatAddressSpace,
1915 &feature_dpp,
1916 &feature_addNoCarryInsts,
1917 &feature_inv2piInlineImm,
1918 &feature_fp64,
1919 &feature_BitInsts16,
1920 &feature_vgprIndexMode,
1921 &feature_wavefrontsize64,
1922 &feature_gfx8Insts,
1923 &feature_flatGlobalInsts,
1924 &feature_scalarFlatScratchInsts,
1925 &feature_scalarAtomics,
1926 &feature_flatInstOffsets,
1927 &feature_gfx7Gfx8Gfx9Insts,
1928 &feature_vop3p,
1929 &feature_sMemrealtime,
1930 &feature_intClampInsts,
1931 &feature_fastFmaf,
1932 &feature_sdwaOmod,
1933 &feature_gfx9,
1934 &feature_ldsbankcount32,
1935 &feature_madMixInsts,
1936 &feature_xnack,
1937 },
1938};
1939
1940pub const cpu_hainan = Cpu{
1941 .name = "hainan",
1942 .llvm_name = "hainan",
1943 .subfeatures = &[_]*const Feature {
1944 &feature_codeObjectV3,
1945 &feature_noXnackSupport,
1946 &feature_ldsbankcount32,
1947 &feature_mimgR128,
1948 &feature_movrel,
1949 &feature_localmemorysize32768,
1950 &feature_trigReducedRange,
1951 &feature_wavefrontsize64,
1952 &feature_noSramEccSupport,
1953 &feature_fp64,
1954 &feature_southernIslands,
1955 },
1956};
1957
1958pub const cpu_hawaii = Cpu{
1959 .name = "hawaii",
1960 .llvm_name = "hawaii",
1961 .subfeatures = &[_]*const Feature {
1962 &feature_codeObjectV3,
1963 &feature_noXnackSupport,
1964 &feature_fastFmaf,
1965 &feature_ldsbankcount32,
1966 &feature_gfx7Gfx8Gfx9Insts,
1967 &feature_mimgR128,
1968 &feature_localmemorysize65536,
1969 &feature_movrel,
1970 &feature_trigReducedRange,
1971 &feature_wavefrontsize64,
1972 &feature_flatAddressSpace,
1973 &feature_ciInsts,
1974 &feature_noSramEccSupport,
1975 &feature_fp64,
1976 &feature_seaIslands,
1977 &feature_halfRate64Ops,
1978 },
1979};
1980
1981pub const cpu_iceland = Cpu{
1982 .name = "iceland",
1983 .llvm_name = "iceland",
1984 .subfeatures = &[_]*const Feature {
1985 &feature_codeObjectV3,
1986 &feature_noXnackSupport,
1987 &feature_ldsbankcount32,
1988 &feature_sgprInitBug,
1989 &feature_unpackedD16Vmem,
1990 &feature_movrel,
1991 &feature_ciInsts,
1992 &feature_noSramEccSupport,
1993 &feature_sdwa,
1994 &feature_localmemorysize65536,
1995 &feature_scalarStores,
1996 &feature_gcn3Encoding,
1997 &feature_flatAddressSpace,
1998 &feature_dpp,
1999 &feature_inv2piInlineImm,
2000 &feature_fp64,
2001 &feature_BitInsts16,
2002 &feature_trigReducedRange,
2003 &feature_vgprIndexMode,
2004 &feature_wavefrontsize64,
2005 &feature_gfx8Insts,
2006 &feature_gfx7Gfx8Gfx9Insts,
2007 &feature_mimgR128,
2008 &feature_intClampInsts,
2009 &feature_sMemrealtime,
2010 &feature_sdwaMav,
2011 &feature_sdwaOutModsVopc,
2012 &feature_volcanicIslands,
2013 },
2014};
2015
2016pub const cpu_kabini = Cpu{
2017 .name = "kabini",
2018 .llvm_name = "kabini",
2019 .subfeatures = &[_]*const Feature {
2020 &feature_codeObjectV3,
2021 &feature_noXnackSupport,
2022 &feature_ldsbankcount16,
2023 &feature_gfx7Gfx8Gfx9Insts,
2024 &feature_mimgR128,
2025 &feature_localmemorysize65536,
2026 &feature_movrel,
2027 &feature_trigReducedRange,
2028 &feature_wavefrontsize64,
2029 &feature_flatAddressSpace,
2030 &feature_ciInsts,
2031 &feature_noSramEccSupport,
2032 &feature_fp64,
2033 &feature_seaIslands,
2034 },
2035};
2036
2037pub const cpu_kaveri = Cpu{
2038 .name = "kaveri",
2039 .llvm_name = "kaveri",
2040 .subfeatures = &[_]*const Feature {
2041 &feature_codeObjectV3,
2042 &feature_noXnackSupport,
2043 &feature_ldsbankcount32,
2044 &feature_gfx7Gfx8Gfx9Insts,
2045 &feature_mimgR128,
2046 &feature_localmemorysize65536,
2047 &feature_movrel,
2048 &feature_trigReducedRange,
2049 &feature_wavefrontsize64,
2050 &feature_flatAddressSpace,
2051 &feature_ciInsts,
2052 &feature_noSramEccSupport,
2053 &feature_fp64,
2054 &feature_seaIslands,
2055 },
2056};
2057
2058pub const cpu_mullins = Cpu{
2059 .name = "mullins",
2060 .llvm_name = "mullins",
2061 .subfeatures = &[_]*const Feature {
2062 &feature_codeObjectV3,
2063 &feature_noXnackSupport,
2064 &feature_ldsbankcount16,
2065 &feature_gfx7Gfx8Gfx9Insts,
2066 &feature_mimgR128,
2067 &feature_localmemorysize65536,
2068 &feature_movrel,
2069 &feature_trigReducedRange,
2070 &feature_wavefrontsize64,
2071 &feature_flatAddressSpace,
2072 &feature_ciInsts,
2073 &feature_noSramEccSupport,
2074 &feature_fp64,
2075 &feature_seaIslands,
2076 },
2077};
2078
2079pub const cpu_oland = Cpu{
2080 .name = "oland",
2081 .llvm_name = "oland",
2082 .subfeatures = &[_]*const Feature {
2083 &feature_codeObjectV3,
2084 &feature_noXnackSupport,
2085 &feature_ldsbankcount32,
2086 &feature_mimgR128,
2087 &feature_movrel,
2088 &feature_localmemorysize32768,
2089 &feature_trigReducedRange,
2090 &feature_wavefrontsize64,
2091 &feature_noSramEccSupport,
2092 &feature_fp64,
2093 &feature_southernIslands,
2094 },
2095};
2096
2097pub const cpu_pitcairn = Cpu{
2098 .name = "pitcairn",
2099 .llvm_name = "pitcairn",
2100 .subfeatures = &[_]*const Feature {
2101 &feature_codeObjectV3,
2102 &feature_noXnackSupport,
2103 &feature_ldsbankcount32,
2104 &feature_mimgR128,
2105 &feature_movrel,
2106 &feature_localmemorysize32768,
2107 &feature_trigReducedRange,
2108 &feature_wavefrontsize64,
2109 &feature_noSramEccSupport,
2110 &feature_fp64,
2111 &feature_southernIslands,
2112 },
2113};
2114
2115pub const cpu_polaris10 = Cpu{
2116 .name = "polaris10",
2117 .llvm_name = "polaris10",
2118 .subfeatures = &[_]*const Feature {
2119 &feature_codeObjectV3,
2120 &feature_noXnackSupport,
2121 &feature_ldsbankcount32,
2122 &feature_unpackedD16Vmem,
2123 &feature_movrel,
2124 &feature_ciInsts,
2125 &feature_noSramEccSupport,
2126 &feature_sdwa,
2127 &feature_localmemorysize65536,
2128 &feature_scalarStores,
2129 &feature_gcn3Encoding,
2130 &feature_flatAddressSpace,
2131 &feature_dpp,
2132 &feature_inv2piInlineImm,
2133 &feature_fp64,
2134 &feature_BitInsts16,
2135 &feature_trigReducedRange,
2136 &feature_vgprIndexMode,
2137 &feature_wavefrontsize64,
2138 &feature_gfx8Insts,
2139 &feature_gfx7Gfx8Gfx9Insts,
2140 &feature_mimgR128,
2141 &feature_intClampInsts,
2142 &feature_sMemrealtime,
2143 &feature_sdwaMav,
2144 &feature_sdwaOutModsVopc,
2145 &feature_volcanicIslands,
2146 },
2147};
2148
2149pub const cpu_polaris11 = Cpu{
2150 .name = "polaris11",
2151 .llvm_name = "polaris11",
2152 .subfeatures = &[_]*const Feature {
2153 &feature_codeObjectV3,
2154 &feature_noXnackSupport,
2155 &feature_ldsbankcount32,
2156 &feature_unpackedD16Vmem,
2157 &feature_movrel,
2158 &feature_ciInsts,
2159 &feature_noSramEccSupport,
2160 &feature_sdwa,
2161 &feature_localmemorysize65536,
2162 &feature_scalarStores,
2163 &feature_gcn3Encoding,
2164 &feature_flatAddressSpace,
2165 &feature_dpp,
2166 &feature_inv2piInlineImm,
2167 &feature_fp64,
2168 &feature_BitInsts16,
2169 &feature_trigReducedRange,
2170 &feature_vgprIndexMode,
2171 &feature_wavefrontsize64,
2172 &feature_gfx8Insts,
2173 &feature_gfx7Gfx8Gfx9Insts,
2174 &feature_mimgR128,
2175 &feature_intClampInsts,
2176 &feature_sMemrealtime,
2177 &feature_sdwaMav,
2178 &feature_sdwaOutModsVopc,
2179 &feature_volcanicIslands,
2180 },
2181};
2182
2183pub const cpu_stoney = Cpu{
2184 .name = "stoney",
2185 .llvm_name = "stoney",
2186 .subfeatures = &[_]*const Feature {
2187 &feature_codeObjectV3,
2188 &feature_ldsbankcount16,
2189 &feature_movrel,
2190 &feature_ciInsts,
2191 &feature_noSramEccSupport,
2192 &feature_sdwa,
2193 &feature_localmemorysize65536,
2194 &feature_scalarStores,
2195 &feature_gcn3Encoding,
2196 &feature_flatAddressSpace,
2197 &feature_dpp,
2198 &feature_inv2piInlineImm,
2199 &feature_fp64,
2200 &feature_BitInsts16,
2201 &feature_trigReducedRange,
2202 &feature_vgprIndexMode,
2203 &feature_wavefrontsize64,
2204 &feature_gfx8Insts,
2205 &feature_gfx7Gfx8Gfx9Insts,
2206 &feature_mimgR128,
2207 &feature_intClampInsts,
2208 &feature_sMemrealtime,
2209 &feature_sdwaMav,
2210 &feature_sdwaOutModsVopc,
2211 &feature_volcanicIslands,
2212 &feature_xnack,
2213 },
2214};
2215
2216pub const cpu_tahiti = Cpu{
2217 .name = "tahiti",
2218 .llvm_name = "tahiti",
2219 .subfeatures = &[_]*const Feature {
2220 &feature_codeObjectV3,
2221 &feature_noXnackSupport,
2222 &feature_fastFmaf,
2223 &feature_ldsbankcount32,
2224 &feature_mimgR128,
2225 &feature_movrel,
2226 &feature_localmemorysize32768,
2227 &feature_trigReducedRange,
2228 &feature_wavefrontsize64,
2229 &feature_noSramEccSupport,
2230 &feature_fp64,
2231 &feature_southernIslands,
2232 &feature_halfRate64Ops,
2233 },
2234};
2235
2236pub const cpu_tonga = Cpu{
2237 .name = "tonga",
2238 .llvm_name = "tonga",
2239 .subfeatures = &[_]*const Feature {
2240 &feature_codeObjectV3,
2241 &feature_noXnackSupport,
2242 &feature_ldsbankcount32,
2243 &feature_sgprInitBug,
2244 &feature_unpackedD16Vmem,
2245 &feature_movrel,
2246 &feature_ciInsts,
2247 &feature_noSramEccSupport,
2248 &feature_sdwa,
2249 &feature_localmemorysize65536,
2250 &feature_scalarStores,
2251 &feature_gcn3Encoding,
2252 &feature_flatAddressSpace,
2253 &feature_dpp,
2254 &feature_inv2piInlineImm,
2255 &feature_fp64,
2256 &feature_BitInsts16,
2257 &feature_trigReducedRange,
2258 &feature_vgprIndexMode,
2259 &feature_wavefrontsize64,
2260 &feature_gfx8Insts,
2261 &feature_gfx7Gfx8Gfx9Insts,
2262 &feature_mimgR128,
2263 &feature_intClampInsts,
2264 &feature_sMemrealtime,
2265 &feature_sdwaMav,
2266 &feature_sdwaOutModsVopc,
2267 &feature_volcanicIslands,
2268 },
2269};
2270
2271pub const cpu_verde = Cpu{
2272 .name = "verde",
2273 .llvm_name = "verde",
2274 .subfeatures = &[_]*const Feature {
2275 &feature_codeObjectV3,
2276 &feature_noXnackSupport,
2277 &feature_ldsbankcount32,
2278 &feature_mimgR128,
2279 &feature_movrel,
2280 &feature_localmemorysize32768,
2281 &feature_trigReducedRange,
2282 &feature_wavefrontsize64,
2283 &feature_noSramEccSupport,
2284 &feature_fp64,
2285 &feature_southernIslands,
2286 },
2287};
2288
2289pub const cpus = &[_]*const Cpu {
2290 &cpu_bonaire,
2291 &cpu_carrizo,
2292 &cpu_fiji,
2293 &cpu_generic,
2294 &cpu_genericHsa,
2295 &cpu_gfx1010,
2296 &cpu_gfx1011,
2297 &cpu_gfx1012,
2298 &cpu_gfx600,
2299 &cpu_gfx601,
2300 &cpu_gfx700,
2301 &cpu_gfx701,
2302 &cpu_gfx702,
2303 &cpu_gfx703,
2304 &cpu_gfx704,
2305 &cpu_gfx801,
2306 &cpu_gfx802,
2307 &cpu_gfx803,
2308 &cpu_gfx810,
2309 &cpu_gfx900,
2310 &cpu_gfx902,
2311 &cpu_gfx904,
2312 &cpu_gfx906,
2313 &cpu_gfx908,
2314 &cpu_gfx909,
2315 &cpu_hainan,
2316 &cpu_hawaii,
2317 &cpu_iceland,
2318 &cpu_kabini,
2319 &cpu_kaveri,
2320 &cpu_mullins,
2321 &cpu_oland,
2322 &cpu_pitcairn,
2323 &cpu_polaris10,
2324 &cpu_polaris11,
2325 &cpu_stoney,
2326 &cpu_tahiti,
2327 &cpu_tonga,
2328 &cpu_verde,
2329};
lib/std/target/arm.zig created+3595
......@@ -0,0 +1,3595 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_armv2 = Feature{
5 .name = "armv2",
6 .description = "ARMv2 architecture",
7 .llvm_name = "armv2",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_armv2a = Feature{
13 .name = "armv2a",
14 .description = "ARMv2a architecture",
15 .llvm_name = "armv2a",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_armv3 = Feature{
21 .name = "armv3",
22 .description = "ARMv3 architecture",
23 .llvm_name = "armv3",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_armv3m = Feature{
29 .name = "armv3m",
30 .description = "ARMv3m architecture",
31 .llvm_name = "armv3m",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_armv4 = Feature{
37 .name = "armv4",
38 .description = "ARMv4 architecture",
39 .llvm_name = "armv4",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_armv4t = Feature{
45 .name = "armv4t",
46 .description = "ARMv4t architecture",
47 .llvm_name = "armv4t",
48 .subfeatures = &[_]*const Feature {
49 &feature_v4t,
50 },
51};
52
53pub const feature_armv5t = Feature{
54 .name = "armv5t",
55 .description = "ARMv5t architecture",
56 .llvm_name = "armv5t",
57 .subfeatures = &[_]*const Feature {
58 &feature_v4t,
59 },
60};
61
62pub const feature_armv5te = Feature{
63 .name = "armv5te",
64 .description = "ARMv5te architecture",
65 .llvm_name = "armv5te",
66 .subfeatures = &[_]*const Feature {
67 &feature_v4t,
68 },
69};
70
71pub const feature_armv5tej = Feature{
72 .name = "armv5tej",
73 .description = "ARMv5tej architecture",
74 .llvm_name = "armv5tej",
75 .subfeatures = &[_]*const Feature {
76 &feature_v4t,
77 },
78};
79
80pub const feature_armv6 = Feature{
81 .name = "armv6",
82 .description = "ARMv6 architecture",
83 .llvm_name = "armv6",
84 .subfeatures = &[_]*const Feature {
85 &feature_v4t,
86 &feature_dsp,
87 },
88};
89
90pub const feature_armv6j = Feature{
91 .name = "armv6j",
92 .description = "ARMv7a architecture",
93 .llvm_name = "armv6j",
94 .subfeatures = &[_]*const Feature {
95 &feature_v4t,
96 &feature_dsp,
97 },
98};
99
100pub const feature_armv6k = Feature{
101 .name = "armv6k",
102 .description = "ARMv6k architecture",
103 .llvm_name = "armv6k",
104 .subfeatures = &[_]*const Feature {
105 &feature_v4t,
106 },
107};
108
109pub const feature_armv6kz = Feature{
110 .name = "armv6kz",
111 .description = "ARMv6kz architecture",
112 .llvm_name = "armv6kz",
113 .subfeatures = &[_]*const Feature {
114 &feature_v4t,
115 &feature_trustzone,
116 },
117};
118
119pub const feature_armv6M = Feature{
120 .name = "armv6-m",
121 .description = "ARMv6m architecture",
122 .llvm_name = "armv6-m",
123 .subfeatures = &[_]*const Feature {
124 &feature_db,
125 &feature_thumbMode,
126 &feature_mclass,
127 &feature_noarm,
128 &feature_v4t,
129 &feature_strictAlign,
130 },
131};
132
133pub const feature_armv6sM = Feature{
134 .name = "armv6s-m",
135 .description = "ARMv6sm architecture",
136 .llvm_name = "armv6s-m",
137 .subfeatures = &[_]*const Feature {
138 &feature_db,
139 &feature_thumbMode,
140 &feature_mclass,
141 &feature_noarm,
142 &feature_v4t,
143 &feature_strictAlign,
144 },
145};
146
147pub const feature_armv6t2 = Feature{
148 .name = "armv6t2",
149 .description = "ARMv6t2 architecture",
150 .llvm_name = "armv6t2",
151 .subfeatures = &[_]*const Feature {
152 &feature_v4t,
153 &feature_dsp,
154 &feature_thumb2,
155 },
156};
157
158pub const feature_armv7A = Feature{
159 .name = "armv7-a",
160 .description = "ARMv7a architecture",
161 .llvm_name = "armv7-a",
162 .subfeatures = &[_]*const Feature {
163 &feature_perfmon,
164 &feature_v7clrex,
165 &feature_db,
166 &feature_thumb2,
167 &feature_v4t,
168 &feature_d32,
169 &feature_aclass,
170 &feature_dsp,
171 &feature_fpregs,
172 },
173};
174
175pub const feature_armv7eM = Feature{
176 .name = "armv7e-m",
177 .description = "ARMv7em architecture",
178 .llvm_name = "armv7e-m",
179 .subfeatures = &[_]*const Feature {
180 &feature_perfmon,
181 &feature_v7clrex,
182 &feature_db,
183 &feature_thumb2,
184 &feature_mclass,
185 &feature_thumbMode,
186 &feature_noarm,
187 &feature_v4t,
188 &feature_dsp,
189 &feature_hwdiv,
190 },
191};
192
193pub const feature_armv7k = Feature{
194 .name = "armv7k",
195 .description = "ARMv7a architecture",
196 .llvm_name = "armv7k",
197 .subfeatures = &[_]*const Feature {
198 &feature_v7clrex,
199 &feature_db,
200 &feature_thumb2,
201 &feature_v4t,
202 &feature_d32,
203 &feature_dsp,
204 &feature_aclass,
205 &feature_perfmon,
206 &feature_fpregs,
207 },
208};
209
210pub const feature_armv7M = Feature{
211 .name = "armv7-m",
212 .description = "ARMv7m architecture",
213 .llvm_name = "armv7-m",
214 .subfeatures = &[_]*const Feature {
215 &feature_v7clrex,
216 &feature_db,
217 &feature_thumb2,
218 &feature_mclass,
219 &feature_thumbMode,
220 &feature_noarm,
221 &feature_v4t,
222 &feature_perfmon,
223 &feature_hwdiv,
224 },
225};
226
227pub const feature_armv7R = Feature{
228 .name = "armv7-r",
229 .description = "ARMv7r architecture",
230 .llvm_name = "armv7-r",
231 .subfeatures = &[_]*const Feature {
232 &feature_perfmon,
233 &feature_v7clrex,
234 &feature_db,
235 &feature_thumb2,
236 &feature_v4t,
237 &feature_dsp,
238 &feature_hwdiv,
239 &feature_rclass,
240 },
241};
242
243pub const feature_armv7s = Feature{
244 .name = "armv7s",
245 .description = "ARMv7a architecture",
246 .llvm_name = "armv7s",
247 .subfeatures = &[_]*const Feature {
248 &feature_v7clrex,
249 &feature_db,
250 &feature_thumb2,
251 &feature_v4t,
252 &feature_d32,
253 &feature_dsp,
254 &feature_aclass,
255 &feature_perfmon,
256 &feature_fpregs,
257 },
258};
259
260pub const feature_armv7ve = Feature{
261 .name = "armv7ve",
262 .description = "ARMv7ve architecture",
263 .llvm_name = "armv7ve",
264 .subfeatures = &[_]*const Feature {
265 &feature_mp,
266 &feature_perfmon,
267 &feature_hwdiv,
268 &feature_trustzone,
269 &feature_v7clrex,
270 &feature_db,
271 &feature_thumb2,
272 &feature_v4t,
273 &feature_d32,
274 &feature_aclass,
275 &feature_hwdivArm,
276 &feature_dsp,
277 &feature_fpregs,
278 },
279};
280
281pub const feature_armv8A = Feature{
282 .name = "armv8-a",
283 .description = "ARMv8a architecture",
284 .llvm_name = "armv8-a",
285 .subfeatures = &[_]*const Feature {
286 &feature_mp,
287 &feature_acquireRelease,
288 &feature_perfmon,
289 &feature_hwdiv,
290 &feature_trustzone,
291 &feature_v7clrex,
292 &feature_db,
293 &feature_thumb2,
294 &feature_fp16,
295 &feature_v4t,
296 &feature_d32,
297 &feature_aclass,
298 &feature_hwdivArm,
299 &feature_crc,
300 &feature_dsp,
301 &feature_fpregs,
302 },
303};
304
305pub const feature_armv8Mbase = Feature{
306 .name = "armv8-m.base",
307 .description = "ARMv8mBaseline architecture",
308 .llvm_name = "armv8-m.base",
309 .subfeatures = &[_]*const Feature {
310 &feature_acquireRelease,
311 &feature_v7clrex,
312 &feature_db,
313 &feature_msecext8,
314 &feature_thumbMode,
315 &feature_mclass,
316 &feature_noarm,
317 &feature_v4t,
318 &feature_strictAlign,
319 &feature_hwdiv,
320 },
321};
322
323pub const feature_armv8Mmain = Feature{
324 .name = "armv8-m.main",
325 .description = "ARMv8mMainline architecture",
326 .llvm_name = "armv8-m.main",
327 .subfeatures = &[_]*const Feature {
328 &feature_acquireRelease,
329 &feature_v7clrex,
330 &feature_db,
331 &feature_msecext8,
332 &feature_thumb2,
333 &feature_mclass,
334 &feature_thumbMode,
335 &feature_noarm,
336 &feature_v4t,
337 &feature_perfmon,
338 &feature_hwdiv,
339 },
340};
341
342pub const feature_armv8R = Feature{
343 .name = "armv8-r",
344 .description = "ARMv8r architecture",
345 .llvm_name = "armv8-r",
346 .subfeatures = &[_]*const Feature {
347 &feature_mp,
348 &feature_acquireRelease,
349 &feature_perfmon,
350 &feature_hwdiv,
351 &feature_v7clrex,
352 &feature_db,
353 &feature_thumb2,
354 &feature_fp16,
355 &feature_v4t,
356 &feature_d32,
357 &feature_dfb,
358 &feature_hwdivArm,
359 &feature_crc,
360 &feature_dsp,
361 &feature_fpregs,
362 &feature_rclass,
363 },
364};
365
366pub const feature_armv81A = Feature{
367 .name = "armv8.1-a",
368 .description = "ARMv81a architecture",
369 .llvm_name = "armv8.1-a",
370 .subfeatures = &[_]*const Feature {
371 &feature_mp,
372 &feature_acquireRelease,
373 &feature_perfmon,
374 &feature_hwdiv,
375 &feature_trustzone,
376 &feature_v7clrex,
377 &feature_db,
378 &feature_thumb2,
379 &feature_fp16,
380 &feature_v4t,
381 &feature_d32,
382 &feature_aclass,
383 &feature_hwdivArm,
384 &feature_crc,
385 &feature_dsp,
386 &feature_fpregs,
387 },
388};
389
390pub const feature_armv81Mmain = Feature{
391 .name = "armv8.1-m.main",
392 .description = "ARMv81mMainline architecture",
393 .llvm_name = "armv8.1-m.main",
394 .subfeatures = &[_]*const Feature {
395 &feature_acquireRelease,
396 &feature_lob,
397 &feature_v7clrex,
398 &feature_db,
399 &feature_msecext8,
400 &feature_thumb2,
401 &feature_mclass,
402 &feature_ras,
403 &feature_noarm,
404 &feature_v4t,
405 &feature_thumbMode,
406 &feature_perfmon,
407 &feature_hwdiv,
408 },
409};
410
411pub const feature_armv82A = Feature{
412 .name = "armv8.2-a",
413 .description = "ARMv82a architecture",
414 .llvm_name = "armv8.2-a",
415 .subfeatures = &[_]*const Feature {
416 &feature_mp,
417 &feature_acquireRelease,
418 &feature_perfmon,
419 &feature_hwdiv,
420 &feature_trustzone,
421 &feature_v7clrex,
422 &feature_db,
423 &feature_thumb2,
424 &feature_ras,
425 &feature_fp16,
426 &feature_v4t,
427 &feature_d32,
428 &feature_aclass,
429 &feature_hwdivArm,
430 &feature_crc,
431 &feature_dsp,
432 &feature_fpregs,
433 },
434};
435
436pub const feature_armv83A = Feature{
437 .name = "armv8.3-a",
438 .description = "ARMv83a architecture",
439 .llvm_name = "armv8.3-a",
440 .subfeatures = &[_]*const Feature {
441 &feature_mp,
442 &feature_acquireRelease,
443 &feature_perfmon,
444 &feature_hwdiv,
445 &feature_trustzone,
446 &feature_v7clrex,
447 &feature_db,
448 &feature_thumb2,
449 &feature_ras,
450 &feature_fp16,
451 &feature_v4t,
452 &feature_d32,
453 &feature_aclass,
454 &feature_hwdivArm,
455 &feature_crc,
456 &feature_dsp,
457 &feature_fpregs,
458 },
459};
460
461pub const feature_armv84A = Feature{
462 .name = "armv8.4-a",
463 .description = "ARMv84a architecture",
464 .llvm_name = "armv8.4-a",
465 .subfeatures = &[_]*const Feature {
466 &feature_mp,
467 &feature_acquireRelease,
468 &feature_perfmon,
469 &feature_hwdiv,
470 &feature_trustzone,
471 &feature_v7clrex,
472 &feature_db,
473 &feature_thumb2,
474 &feature_ras,
475 &feature_fp16,
476 &feature_v4t,
477 &feature_d32,
478 &feature_aclass,
479 &feature_hwdivArm,
480 &feature_crc,
481 &feature_dsp,
482 &feature_fpregs,
483 },
484};
485
486pub const feature_armv85A = Feature{
487 .name = "armv8.5-a",
488 .description = "ARMv85a architecture",
489 .llvm_name = "armv8.5-a",
490 .subfeatures = &[_]*const Feature {
491 &feature_mp,
492 &feature_acquireRelease,
493 &feature_perfmon,
494 &feature_hwdiv,
495 &feature_trustzone,
496 &feature_v7clrex,
497 &feature_db,
498 &feature_thumb2,
499 &feature_ras,
500 &feature_fp16,
501 &feature_v4t,
502 &feature_d32,
503 &feature_aclass,
504 &feature_hwdivArm,
505 &feature_sb,
506 &feature_crc,
507 &feature_dsp,
508 &feature_fpregs,
509 },
510};
511
512pub const feature_msecext8 = Feature{
513 .name = "8msecext",
514 .description = "Enable support for ARMv8-M Security Extensions",
515 .llvm_name = "8msecext",
516 .subfeatures = &[_]*const Feature {
517 },
518};
519
520pub const feature_aclass = Feature{
521 .name = "aclass",
522 .description = "Is application profile ('A' series)",
523 .llvm_name = "aclass",
524 .subfeatures = &[_]*const Feature {
525 },
526};
527
528pub const feature_aes = Feature{
529 .name = "aes",
530 .description = "Enable AES support",
531 .llvm_name = "aes",
532 .subfeatures = &[_]*const Feature {
533 &feature_d32,
534 &feature_fpregs,
535 },
536};
537
538pub const feature_acquireRelease = Feature{
539 .name = "acquire-release",
540 .description = "Has v8 acquire/release (lda/ldaex etc) instructions",
541 .llvm_name = "acquire-release",
542 .subfeatures = &[_]*const Feature {
543 },
544};
545
546pub const feature_avoidMovsShop = Feature{
547 .name = "avoid-movs-shop",
548 .description = "Avoid movs instructions with shifter operand",
549 .llvm_name = "avoid-movs-shop",
550 .subfeatures = &[_]*const Feature {
551 },
552};
553
554pub const feature_avoidPartialCpsr = Feature{
555 .name = "avoid-partial-cpsr",
556 .description = "Avoid CPSR partial update for OOO execution",
557 .llvm_name = "avoid-partial-cpsr",
558 .subfeatures = &[_]*const Feature {
559 },
560};
561
562pub const feature_crc = Feature{
563 .name = "crc",
564 .description = "Enable support for CRC instructions",
565 .llvm_name = "crc",
566 .subfeatures = &[_]*const Feature {
567 },
568};
569
570pub const feature_cheapPredicableCpsr = Feature{
571 .name = "cheap-predicable-cpsr",
572 .description = "Disable +1 predication cost for instructions updating CPSR",
573 .llvm_name = "cheap-predicable-cpsr",
574 .subfeatures = &[_]*const Feature {
575 },
576};
577
578pub const feature_vldnAlign = Feature{
579 .name = "vldn-align",
580 .description = "Check for VLDn unaligned access",
581 .llvm_name = "vldn-align",
582 .subfeatures = &[_]*const Feature {
583 },
584};
585
586pub const feature_crypto = Feature{
587 .name = "crypto",
588 .description = "Enable support for Cryptography extensions",
589 .llvm_name = "crypto",
590 .subfeatures = &[_]*const Feature {
591 &feature_d32,
592 &feature_fpregs,
593 },
594};
595
596pub const feature_d32 = Feature{
597 .name = "d32",
598 .description = "Extend FP to 32 double registers",
599 .llvm_name = "d32",
600 .subfeatures = &[_]*const Feature {
601 },
602};
603
604pub const feature_db = Feature{
605 .name = "db",
606 .description = "Has data barrier (dmb/dsb) instructions",
607 .llvm_name = "db",
608 .subfeatures = &[_]*const Feature {
609 },
610};
611
612pub const feature_dfb = Feature{
613 .name = "dfb",
614 .description = "Has full data barrier (dfb) instruction",
615 .llvm_name = "dfb",
616 .subfeatures = &[_]*const Feature {
617 },
618};
619
620pub const feature_dsp = Feature{
621 .name = "dsp",
622 .description = "Supports DSP instructions in ARM and/or Thumb2",
623 .llvm_name = "dsp",
624 .subfeatures = &[_]*const Feature {
625 },
626};
627
628pub const feature_dontWidenVmovs = Feature{
629 .name = "dont-widen-vmovs",
630 .description = "Don't widen VMOVS to VMOVD",
631 .llvm_name = "dont-widen-vmovs",
632 .subfeatures = &[_]*const Feature {
633 },
634};
635
636pub const feature_dotprod = Feature{
637 .name = "dotprod",
638 .description = "Enable support for dot product instructions",
639 .llvm_name = "dotprod",
640 .subfeatures = &[_]*const Feature {
641 &feature_d32,
642 &feature_fpregs,
643 },
644};
645
646pub const feature_executeOnly = Feature{
647 .name = "execute-only",
648 .description = "Enable the generation of execute only code.",
649 .llvm_name = "execute-only",
650 .subfeatures = &[_]*const Feature {
651 },
652};
653
654pub const feature_expandFpMlx = Feature{
655 .name = "expand-fp-mlx",
656 .description = "Expand VFP/NEON MLA/MLS instructions",
657 .llvm_name = "expand-fp-mlx",
658 .subfeatures = &[_]*const Feature {
659 },
660};
661
662pub const feature_fp16 = Feature{
663 .name = "fp16",
664 .description = "Enable half-precision floating point",
665 .llvm_name = "fp16",
666 .subfeatures = &[_]*const Feature {
667 },
668};
669
670pub const feature_fp16fml = Feature{
671 .name = "fp16fml",
672 .description = "Enable full half-precision floating point fml instructions",
673 .llvm_name = "fp16fml",
674 .subfeatures = &[_]*const Feature {
675 &feature_fp16,
676 &feature_fpregs,
677 },
678};
679
680pub const feature_fp64 = Feature{
681 .name = "fp64",
682 .description = "Floating point unit supports double precision",
683 .llvm_name = "fp64",
684 .subfeatures = &[_]*const Feature {
685 &feature_fpregs,
686 },
687};
688
689pub const feature_fpao = Feature{
690 .name = "fpao",
691 .description = "Enable fast computation of positive address offsets",
692 .llvm_name = "fpao",
693 .subfeatures = &[_]*const Feature {
694 },
695};
696
697pub const feature_fpArmv8 = Feature{
698 .name = "fp-armv8",
699 .description = "Enable ARMv8 FP",
700 .llvm_name = "fp-armv8",
701 .subfeatures = &[_]*const Feature {
702 &feature_fp16,
703 &feature_d32,
704 &feature_fpregs,
705 },
706};
707
708pub const feature_fpArmv8d16 = Feature{
709 .name = "fp-armv8d16",
710 .description = "Enable ARMv8 FP with only 16 d-registers",
711 .llvm_name = "fp-armv8d16",
712 .subfeatures = &[_]*const Feature {
713 &feature_fp16,
714 &feature_fpregs,
715 },
716};
717
718pub const feature_fpArmv8d16sp = Feature{
719 .name = "fp-armv8d16sp",
720 .description = "Enable ARMv8 FP with only 16 d-registers and no double precision",
721 .llvm_name = "fp-armv8d16sp",
722 .subfeatures = &[_]*const Feature {
723 &feature_fp16,
724 &feature_fpregs,
725 },
726};
727
728pub const feature_fpArmv8sp = Feature{
729 .name = "fp-armv8sp",
730 .description = "Enable ARMv8 FP with no double precision",
731 .llvm_name = "fp-armv8sp",
732 .subfeatures = &[_]*const Feature {
733 &feature_fp16,
734 &feature_d32,
735 &feature_fpregs,
736 },
737};
738
739pub const feature_fpregs = Feature{
740 .name = "fpregs",
741 .description = "Enable FP registers",
742 .llvm_name = "fpregs",
743 .subfeatures = &[_]*const Feature {
744 },
745};
746
747pub const feature_fpregs16 = Feature{
748 .name = "fpregs16",
749 .description = "Enable 16-bit FP registers",
750 .llvm_name = "fpregs16",
751 .subfeatures = &[_]*const Feature {
752 &feature_fpregs,
753 },
754};
755
756pub const feature_fpregs64 = Feature{
757 .name = "fpregs64",
758 .description = "Enable 64-bit FP registers",
759 .llvm_name = "fpregs64",
760 .subfeatures = &[_]*const Feature {
761 &feature_fpregs,
762 },
763};
764
765pub const feature_fullfp16 = Feature{
766 .name = "fullfp16",
767 .description = "Enable full half-precision floating point",
768 .llvm_name = "fullfp16",
769 .subfeatures = &[_]*const Feature {
770 &feature_fp16,
771 &feature_fpregs,
772 },
773};
774
775pub const feature_fuseAes = Feature{
776 .name = "fuse-aes",
777 .description = "CPU fuses AES crypto operations",
778 .llvm_name = "fuse-aes",
779 .subfeatures = &[_]*const Feature {
780 },
781};
782
783pub const feature_fuseLiterals = Feature{
784 .name = "fuse-literals",
785 .description = "CPU fuses literal generation operations",
786 .llvm_name = "fuse-literals",
787 .subfeatures = &[_]*const Feature {
788 },
789};
790
791pub const feature_hwdivArm = Feature{
792 .name = "hwdiv-arm",
793 .description = "Enable divide instructions in ARM mode",
794 .llvm_name = "hwdiv-arm",
795 .subfeatures = &[_]*const Feature {
796 },
797};
798
799pub const feature_hwdiv = Feature{
800 .name = "hwdiv",
801 .description = "Enable divide instructions in Thumb",
802 .llvm_name = "hwdiv",
803 .subfeatures = &[_]*const Feature {
804 },
805};
806
807pub const feature_noBranchPredictor = Feature{
808 .name = "no-branch-predictor",
809 .description = "Has no branch predictor",
810 .llvm_name = "no-branch-predictor",
811 .subfeatures = &[_]*const Feature {
812 },
813};
814
815pub const feature_retAddrStack = Feature{
816 .name = "ret-addr-stack",
817 .description = "Has return address stack",
818 .llvm_name = "ret-addr-stack",
819 .subfeatures = &[_]*const Feature {
820 },
821};
822
823pub const feature_slowfpvmlx = Feature{
824 .name = "slowfpvmlx",
825 .description = "Disable VFP / NEON MAC instructions",
826 .llvm_name = "slowfpvmlx",
827 .subfeatures = &[_]*const Feature {
828 },
829};
830
831pub const feature_vmlxHazards = Feature{
832 .name = "vmlx-hazards",
833 .description = "Has VMLx hazards",
834 .llvm_name = "vmlx-hazards",
835 .subfeatures = &[_]*const Feature {
836 },
837};
838
839pub const feature_lob = Feature{
840 .name = "lob",
841 .description = "Enable Low Overhead Branch extensions",
842 .llvm_name = "lob",
843 .subfeatures = &[_]*const Feature {
844 },
845};
846
847pub const feature_longCalls = Feature{
848 .name = "long-calls",
849 .description = "Generate calls via indirect call instructions",
850 .llvm_name = "long-calls",
851 .subfeatures = &[_]*const Feature {
852 },
853};
854
855pub const feature_mclass = Feature{
856 .name = "mclass",
857 .description = "Is microcontroller profile ('M' series)",
858 .llvm_name = "mclass",
859 .subfeatures = &[_]*const Feature {
860 },
861};
862
863pub const feature_mp = Feature{
864 .name = "mp",
865 .description = "Supports Multiprocessing extension",
866 .llvm_name = "mp",
867 .subfeatures = &[_]*const Feature {
868 },
869};
870
871pub const feature_mve1beat = Feature{
872 .name = "mve1beat",
873 .description = "Model MVE instructions as a 1 beat per tick architecture",
874 .llvm_name = "mve1beat",
875 .subfeatures = &[_]*const Feature {
876 },
877};
878
879pub const feature_mve2beat = Feature{
880 .name = "mve2beat",
881 .description = "Model MVE instructions as a 2 beats per tick architecture",
882 .llvm_name = "mve2beat",
883 .subfeatures = &[_]*const Feature {
884 },
885};
886
887pub const feature_mve4beat = Feature{
888 .name = "mve4beat",
889 .description = "Model MVE instructions as a 4 beats per tick architecture",
890 .llvm_name = "mve4beat",
891 .subfeatures = &[_]*const Feature {
892 },
893};
894
895pub const feature_muxedUnits = Feature{
896 .name = "muxed-units",
897 .description = "Has muxed AGU and NEON/FPU",
898 .llvm_name = "muxed-units",
899 .subfeatures = &[_]*const Feature {
900 },
901};
902
903pub const feature_neon = Feature{
904 .name = "neon",
905 .description = "Enable NEON instructions",
906 .llvm_name = "neon",
907 .subfeatures = &[_]*const Feature {
908 &feature_d32,
909 &feature_fpregs,
910 },
911};
912
913pub const feature_neonfp = Feature{
914 .name = "neonfp",
915 .description = "Use NEON for single precision FP",
916 .llvm_name = "neonfp",
917 .subfeatures = &[_]*const Feature {
918 },
919};
920
921pub const feature_neonFpmovs = Feature{
922 .name = "neon-fpmovs",
923 .description = "Convert VMOVSR, VMOVRS, VMOVS to NEON",
924 .llvm_name = "neon-fpmovs",
925 .subfeatures = &[_]*const Feature {
926 },
927};
928
929pub const feature_naclTrap = Feature{
930 .name = "nacl-trap",
931 .description = "NaCl trap",
932 .llvm_name = "nacl-trap",
933 .subfeatures = &[_]*const Feature {
934 },
935};
936
937pub const feature_noarm = Feature{
938 .name = "noarm",
939 .description = "Does not support ARM mode execution",
940 .llvm_name = "noarm",
941 .subfeatures = &[_]*const Feature {
942 },
943};
944
945pub const feature_noMovt = Feature{
946 .name = "no-movt",
947 .description = "Don't use movt/movw pairs for 32-bit imms",
948 .llvm_name = "no-movt",
949 .subfeatures = &[_]*const Feature {
950 },
951};
952
953pub const feature_noNegImmediates = Feature{
954 .name = "no-neg-immediates",
955 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
956 .llvm_name = "no-neg-immediates",
957 .subfeatures = &[_]*const Feature {
958 },
959};
960
961pub const feature_disablePostraScheduler = Feature{
962 .name = "disable-postra-scheduler",
963 .description = "Don't schedule again after register allocation",
964 .llvm_name = "disable-postra-scheduler",
965 .subfeatures = &[_]*const Feature {
966 },
967};
968
969pub const feature_nonpipelinedVfp = Feature{
970 .name = "nonpipelined-vfp",
971 .description = "VFP instructions are not pipelined",
972 .llvm_name = "nonpipelined-vfp",
973 .subfeatures = &[_]*const Feature {
974 },
975};
976
977pub const feature_perfmon = Feature{
978 .name = "perfmon",
979 .description = "Enable support for Performance Monitor extensions",
980 .llvm_name = "perfmon",
981 .subfeatures = &[_]*const Feature {
982 },
983};
984
985pub const feature_bit32 = Feature{
986 .name = "32bit",
987 .description = "Prefer 32-bit Thumb instrs",
988 .llvm_name = "32bit",
989 .subfeatures = &[_]*const Feature {
990 },
991};
992
993pub const feature_preferIshst = Feature{
994 .name = "prefer-ishst",
995 .description = "Prefer ISHST barriers",
996 .llvm_name = "prefer-ishst",
997 .subfeatures = &[_]*const Feature {
998 },
999};
1000
1001pub const feature_loopAlign = Feature{
1002 .name = "loop-align",
1003 .description = "Prefer 32-bit alignment for loops",
1004 .llvm_name = "loop-align",
1005 .subfeatures = &[_]*const Feature {
1006 },
1007};
1008
1009pub const feature_preferVmovsr = Feature{
1010 .name = "prefer-vmovsr",
1011 .description = "Prefer VMOVSR",
1012 .llvm_name = "prefer-vmovsr",
1013 .subfeatures = &[_]*const Feature {
1014 },
1015};
1016
1017pub const feature_profUnpr = Feature{
1018 .name = "prof-unpr",
1019 .description = "Is profitable to unpredicate",
1020 .llvm_name = "prof-unpr",
1021 .subfeatures = &[_]*const Feature {
1022 },
1023};
1024
1025pub const feature_ras = Feature{
1026 .name = "ras",
1027 .description = "Enable Reliability, Availability and Serviceability extensions",
1028 .llvm_name = "ras",
1029 .subfeatures = &[_]*const Feature {
1030 },
1031};
1032
1033pub const feature_rclass = Feature{
1034 .name = "rclass",
1035 .description = "Is realtime profile ('R' series)",
1036 .llvm_name = "rclass",
1037 .subfeatures = &[_]*const Feature {
1038 },
1039};
1040
1041pub const feature_readTpHard = Feature{
1042 .name = "read-tp-hard",
1043 .description = "Reading thread pointer from register",
1044 .llvm_name = "read-tp-hard",
1045 .subfeatures = &[_]*const Feature {
1046 },
1047};
1048
1049pub const feature_reserveR9 = Feature{
1050 .name = "reserve-r9",
1051 .description = "Reserve R9, making it unavailable as GPR",
1052 .llvm_name = "reserve-r9",
1053 .subfeatures = &[_]*const Feature {
1054 },
1055};
1056
1057pub const feature_sb = Feature{
1058 .name = "sb",
1059 .description = "Enable v8.5a Speculation Barrier",
1060 .llvm_name = "sb",
1061 .subfeatures = &[_]*const Feature {
1062 },
1063};
1064
1065pub const feature_sha2 = Feature{
1066 .name = "sha2",
1067 .description = "Enable SHA1 and SHA256 support",
1068 .llvm_name = "sha2",
1069 .subfeatures = &[_]*const Feature {
1070 &feature_d32,
1071 &feature_fpregs,
1072 },
1073};
1074
1075pub const feature_slowFpBrcc = Feature{
1076 .name = "slow-fp-brcc",
1077 .description = "FP compare + branch is slow",
1078 .llvm_name = "slow-fp-brcc",
1079 .subfeatures = &[_]*const Feature {
1080 },
1081};
1082
1083pub const feature_slowLoadDSubreg = Feature{
1084 .name = "slow-load-D-subreg",
1085 .description = "Loading into D subregs is slow",
1086 .llvm_name = "slow-load-D-subreg",
1087 .subfeatures = &[_]*const Feature {
1088 },
1089};
1090
1091pub const feature_slowOddReg = Feature{
1092 .name = "slow-odd-reg",
1093 .description = "VLDM/VSTM starting with an odd register is slow",
1094 .llvm_name = "slow-odd-reg",
1095 .subfeatures = &[_]*const Feature {
1096 },
1097};
1098
1099pub const feature_slowVdup32 = Feature{
1100 .name = "slow-vdup32",
1101 .description = "Has slow VDUP32 - prefer VMOV",
1102 .llvm_name = "slow-vdup32",
1103 .subfeatures = &[_]*const Feature {
1104 },
1105};
1106
1107pub const feature_slowVgetlni32 = Feature{
1108 .name = "slow-vgetlni32",
1109 .description = "Has slow VGETLNi32 - prefer VMOV",
1110 .llvm_name = "slow-vgetlni32",
1111 .subfeatures = &[_]*const Feature {
1112 },
1113};
1114
1115pub const feature_splatVfpNeon = Feature{
1116 .name = "splat-vfp-neon",
1117 .description = "Splat register from VFP to NEON",
1118 .llvm_name = "splat-vfp-neon",
1119 .subfeatures = &[_]*const Feature {
1120 &feature_dontWidenVmovs,
1121 },
1122};
1123
1124pub const feature_strictAlign = Feature{
1125 .name = "strict-align",
1126 .description = "Disallow all unaligned memory access",
1127 .llvm_name = "strict-align",
1128 .subfeatures = &[_]*const Feature {
1129 },
1130};
1131
1132pub const feature_thumb2 = Feature{
1133 .name = "thumb2",
1134 .description = "Enable Thumb2 instructions",
1135 .llvm_name = "thumb2",
1136 .subfeatures = &[_]*const Feature {
1137 },
1138};
1139
1140pub const feature_trustzone = Feature{
1141 .name = "trustzone",
1142 .description = "Enable support for TrustZone security extensions",
1143 .llvm_name = "trustzone",
1144 .subfeatures = &[_]*const Feature {
1145 },
1146};
1147
1148pub const feature_useAa = Feature{
1149 .name = "use-aa",
1150 .description = "Use alias analysis during codegen",
1151 .llvm_name = "use-aa",
1152 .subfeatures = &[_]*const Feature {
1153 },
1154};
1155
1156pub const feature_useMisched = Feature{
1157 .name = "use-misched",
1158 .description = "Use the MachineScheduler",
1159 .llvm_name = "use-misched",
1160 .subfeatures = &[_]*const Feature {
1161 },
1162};
1163
1164pub const feature_wideStrideVfp = Feature{
1165 .name = "wide-stride-vfp",
1166 .description = "Use a wide stride when allocating VFP registers",
1167 .llvm_name = "wide-stride-vfp",
1168 .subfeatures = &[_]*const Feature {
1169 },
1170};
1171
1172pub const feature_v7clrex = Feature{
1173 .name = "v7clrex",
1174 .description = "Has v7 clrex instruction",
1175 .llvm_name = "v7clrex",
1176 .subfeatures = &[_]*const Feature {
1177 },
1178};
1179
1180pub const feature_vfp2 = Feature{
1181 .name = "vfp2",
1182 .description = "Enable VFP2 instructions",
1183 .llvm_name = "vfp2",
1184 .subfeatures = &[_]*const Feature {
1185 &feature_fpregs,
1186 },
1187};
1188
1189pub const feature_vfp2sp = Feature{
1190 .name = "vfp2sp",
1191 .description = "Enable VFP2 instructions with no double precision",
1192 .llvm_name = "vfp2sp",
1193 .subfeatures = &[_]*const Feature {
1194 &feature_fpregs,
1195 },
1196};
1197
1198pub const feature_vfp3 = Feature{
1199 .name = "vfp3",
1200 .description = "Enable VFP3 instructions",
1201 .llvm_name = "vfp3",
1202 .subfeatures = &[_]*const Feature {
1203 &feature_d32,
1204 &feature_fpregs,
1205 },
1206};
1207
1208pub const feature_vfp3d16 = Feature{
1209 .name = "vfp3d16",
1210 .description = "Enable VFP3 instructions with only 16 d-registers",
1211 .llvm_name = "vfp3d16",
1212 .subfeatures = &[_]*const Feature {
1213 &feature_fpregs,
1214 },
1215};
1216
1217pub const feature_vfp3d16sp = Feature{
1218 .name = "vfp3d16sp",
1219 .description = "Enable VFP3 instructions with only 16 d-registers and no double precision",
1220 .llvm_name = "vfp3d16sp",
1221 .subfeatures = &[_]*const Feature {
1222 &feature_fpregs,
1223 },
1224};
1225
1226pub const feature_vfp3sp = Feature{
1227 .name = "vfp3sp",
1228 .description = "Enable VFP3 instructions with no double precision",
1229 .llvm_name = "vfp3sp",
1230 .subfeatures = &[_]*const Feature {
1231 &feature_d32,
1232 &feature_fpregs,
1233 },
1234};
1235
1236pub const feature_vfp4 = Feature{
1237 .name = "vfp4",
1238 .description = "Enable VFP4 instructions",
1239 .llvm_name = "vfp4",
1240 .subfeatures = &[_]*const Feature {
1241 &feature_fp16,
1242 &feature_d32,
1243 &feature_fpregs,
1244 },
1245};
1246
1247pub const feature_vfp4d16 = Feature{
1248 .name = "vfp4d16",
1249 .description = "Enable VFP4 instructions with only 16 d-registers",
1250 .llvm_name = "vfp4d16",
1251 .subfeatures = &[_]*const Feature {
1252 &feature_fp16,
1253 &feature_fpregs,
1254 },
1255};
1256
1257pub const feature_vfp4d16sp = Feature{
1258 .name = "vfp4d16sp",
1259 .description = "Enable VFP4 instructions with only 16 d-registers and no double precision",
1260 .llvm_name = "vfp4d16sp",
1261 .subfeatures = &[_]*const Feature {
1262 &feature_fp16,
1263 &feature_fpregs,
1264 },
1265};
1266
1267pub const feature_vfp4sp = Feature{
1268 .name = "vfp4sp",
1269 .description = "Enable VFP4 instructions with no double precision",
1270 .llvm_name = "vfp4sp",
1271 .subfeatures = &[_]*const Feature {
1272 &feature_fp16,
1273 &feature_d32,
1274 &feature_fpregs,
1275 },
1276};
1277
1278pub const feature_vmlxForwarding = Feature{
1279 .name = "vmlx-forwarding",
1280 .description = "Has multiplier accumulator forwarding",
1281 .llvm_name = "vmlx-forwarding",
1282 .subfeatures = &[_]*const Feature {
1283 },
1284};
1285
1286pub const feature_virtualization = Feature{
1287 .name = "virtualization",
1288 .description = "Supports Virtualization extension",
1289 .llvm_name = "virtualization",
1290 .subfeatures = &[_]*const Feature {
1291 &feature_hwdiv,
1292 &feature_hwdivArm,
1293 },
1294};
1295
1296pub const feature_zcz = Feature{
1297 .name = "zcz",
1298 .description = "Has zero-cycle zeroing instructions",
1299 .llvm_name = "zcz",
1300 .subfeatures = &[_]*const Feature {
1301 },
1302};
1303
1304pub const feature_mvefp = Feature{
1305 .name = "mve.fp",
1306 .description = "Support M-Class Vector Extension with integer and floating ops",
1307 .llvm_name = "mve.fp",
1308 .subfeatures = &[_]*const Feature {
1309 &feature_v7clrex,
1310 &feature_thumb2,
1311 &feature_fp16,
1312 &feature_v4t,
1313 &feature_dsp,
1314 &feature_perfmon,
1315 &feature_fpregs,
1316 },
1317};
1318
1319pub const feature_mve = Feature{
1320 .name = "mve",
1321 .description = "Support M-Class Vector Extension with integer ops",
1322 .llvm_name = "mve",
1323 .subfeatures = &[_]*const Feature {
1324 &feature_perfmon,
1325 &feature_v7clrex,
1326 &feature_thumb2,
1327 &feature_v4t,
1328 &feature_dsp,
1329 &feature_fpregs,
1330 },
1331};
1332
1333pub const feature_v4t = Feature{
1334 .name = "v4t",
1335 .description = "Support ARM v4T instructions",
1336 .llvm_name = "v4t",
1337 .subfeatures = &[_]*const Feature {
1338 },
1339};
1340
1341pub const feature_v5te = Feature{
1342 .name = "v5te",
1343 .description = "Support ARM v5TE, v5TEj, and v5TExp instructions",
1344 .llvm_name = "v5te",
1345 .subfeatures = &[_]*const Feature {
1346 &feature_v4t,
1347 },
1348};
1349
1350pub const feature_v5t = Feature{
1351 .name = "v5t",
1352 .description = "Support ARM v5T instructions",
1353 .llvm_name = "v5t",
1354 .subfeatures = &[_]*const Feature {
1355 &feature_v4t,
1356 },
1357};
1358
1359pub const feature_v6k = Feature{
1360 .name = "v6k",
1361 .description = "Support ARM v6k instructions",
1362 .llvm_name = "v6k",
1363 .subfeatures = &[_]*const Feature {
1364 &feature_v4t,
1365 },
1366};
1367
1368pub const feature_v6m = Feature{
1369 .name = "v6m",
1370 .description = "Support ARM v6M instructions",
1371 .llvm_name = "v6m",
1372 .subfeatures = &[_]*const Feature {
1373 &feature_v4t,
1374 },
1375};
1376
1377pub const feature_v6 = Feature{
1378 .name = "v6",
1379 .description = "Support ARM v6 instructions",
1380 .llvm_name = "v6",
1381 .subfeatures = &[_]*const Feature {
1382 &feature_v4t,
1383 },
1384};
1385
1386pub const feature_v6t2 = Feature{
1387 .name = "v6t2",
1388 .description = "Support ARM v6t2 instructions",
1389 .llvm_name = "v6t2",
1390 .subfeatures = &[_]*const Feature {
1391 &feature_v4t,
1392 &feature_thumb2,
1393 },
1394};
1395
1396pub const feature_v7 = Feature{
1397 .name = "v7",
1398 .description = "Support ARM v7 instructions",
1399 .llvm_name = "v7",
1400 .subfeatures = &[_]*const Feature {
1401 &feature_v4t,
1402 &feature_v7clrex,
1403 &feature_perfmon,
1404 &feature_thumb2,
1405 },
1406};
1407
1408pub const feature_v8m = Feature{
1409 .name = "v8m",
1410 .description = "Support ARM v8M Baseline instructions",
1411 .llvm_name = "v8m",
1412 .subfeatures = &[_]*const Feature {
1413 &feature_v4t,
1414 },
1415};
1416
1417pub const feature_v8mmain = Feature{
1418 .name = "v8m.main",
1419 .description = "Support ARM v8M Mainline instructions",
1420 .llvm_name = "v8m.main",
1421 .subfeatures = &[_]*const Feature {
1422 &feature_v4t,
1423 &feature_perfmon,
1424 &feature_v7clrex,
1425 &feature_thumb2,
1426 },
1427};
1428
1429pub const feature_v8 = Feature{
1430 .name = "v8",
1431 .description = "Support ARM v8 instructions",
1432 .llvm_name = "v8",
1433 .subfeatures = &[_]*const Feature {
1434 &feature_acquireRelease,
1435 &feature_v7clrex,
1436 &feature_thumb2,
1437 &feature_v4t,
1438 &feature_perfmon,
1439 },
1440};
1441
1442pub const feature_v81mmain = Feature{
1443 .name = "v8.1m.main",
1444 .description = "Support ARM v8-1M Mainline instructions",
1445 .llvm_name = "v8.1m.main",
1446 .subfeatures = &[_]*const Feature {
1447 &feature_v4t,
1448 &feature_v7clrex,
1449 &feature_perfmon,
1450 &feature_thumb2,
1451 },
1452};
1453
1454pub const feature_v81a = Feature{
1455 .name = "v8.1a",
1456 .description = "Support ARM v8.1a instructions",
1457 .llvm_name = "v8.1a",
1458 .subfeatures = &[_]*const Feature {
1459 &feature_acquireRelease,
1460 &feature_v7clrex,
1461 &feature_thumb2,
1462 &feature_v4t,
1463 &feature_perfmon,
1464 },
1465};
1466
1467pub const feature_v82a = Feature{
1468 .name = "v8.2a",
1469 .description = "Support ARM v8.2a instructions",
1470 .llvm_name = "v8.2a",
1471 .subfeatures = &[_]*const Feature {
1472 &feature_acquireRelease,
1473 &feature_v7clrex,
1474 &feature_thumb2,
1475 &feature_v4t,
1476 &feature_perfmon,
1477 },
1478};
1479
1480pub const feature_v83a = Feature{
1481 .name = "v8.3a",
1482 .description = "Support ARM v8.3a instructions",
1483 .llvm_name = "v8.3a",
1484 .subfeatures = &[_]*const Feature {
1485 &feature_acquireRelease,
1486 &feature_v7clrex,
1487 &feature_thumb2,
1488 &feature_v4t,
1489 &feature_perfmon,
1490 },
1491};
1492
1493pub const feature_v84a = Feature{
1494 .name = "v8.4a",
1495 .description = "Support ARM v8.4a instructions",
1496 .llvm_name = "v8.4a",
1497 .subfeatures = &[_]*const Feature {
1498 &feature_acquireRelease,
1499 &feature_v7clrex,
1500 &feature_thumb2,
1501 &feature_v4t,
1502 &feature_d32,
1503 &feature_perfmon,
1504 &feature_fpregs,
1505 },
1506};
1507
1508pub const feature_v85a = Feature{
1509 .name = "v8.5a",
1510 .description = "Support ARM v8.5a instructions",
1511 .llvm_name = "v8.5a",
1512 .subfeatures = &[_]*const Feature {
1513 &feature_acquireRelease,
1514 &feature_v7clrex,
1515 &feature_thumb2,
1516 &feature_v4t,
1517 &feature_d32,
1518 &feature_sb,
1519 &feature_perfmon,
1520 &feature_fpregs,
1521 },
1522};
1523
1524pub const feature_iwmmxt = Feature{
1525 .name = "iwmmxt",
1526 .description = "ARMv5te architecture",
1527 .llvm_name = "iwmmxt",
1528 .subfeatures = &[_]*const Feature {
1529 &feature_v4t,
1530 },
1531};
1532
1533pub const feature_iwmmxt2 = Feature{
1534 .name = "iwmmxt2",
1535 .description = "ARMv5te architecture",
1536 .llvm_name = "iwmmxt2",
1537 .subfeatures = &[_]*const Feature {
1538 &feature_v4t,
1539 },
1540};
1541
1542pub const feature_softFloat = Feature{
1543 .name = "soft-float",
1544 .description = "Use software floating point features.",
1545 .llvm_name = "soft-float",
1546 .subfeatures = &[_]*const Feature {
1547 },
1548};
1549
1550pub const feature_thumbMode = Feature{
1551 .name = "thumb-mode",
1552 .description = "Thumb mode",
1553 .llvm_name = "thumb-mode",
1554 .subfeatures = &[_]*const Feature {
1555 },
1556};
1557
1558pub const feature_a5 = Feature{
1559 .name = "a5",
1560 .description = "Cortex-A5 ARM processors",
1561 .llvm_name = "a5",
1562 .subfeatures = &[_]*const Feature {
1563 },
1564};
1565
1566pub const feature_a7 = Feature{
1567 .name = "a7",
1568 .description = "Cortex-A7 ARM processors",
1569 .llvm_name = "a7",
1570 .subfeatures = &[_]*const Feature {
1571 },
1572};
1573
1574pub const feature_a8 = Feature{
1575 .name = "a8",
1576 .description = "Cortex-A8 ARM processors",
1577 .llvm_name = "a8",
1578 .subfeatures = &[_]*const Feature {
1579 },
1580};
1581
1582pub const feature_a9 = Feature{
1583 .name = "a9",
1584 .description = "Cortex-A9 ARM processors",
1585 .llvm_name = "a9",
1586 .subfeatures = &[_]*const Feature {
1587 },
1588};
1589
1590pub const feature_a12 = Feature{
1591 .name = "a12",
1592 .description = "Cortex-A12 ARM processors",
1593 .llvm_name = "a12",
1594 .subfeatures = &[_]*const Feature {
1595 },
1596};
1597
1598pub const feature_a15 = Feature{
1599 .name = "a15",
1600 .description = "Cortex-A15 ARM processors",
1601 .llvm_name = "a15",
1602 .subfeatures = &[_]*const Feature {
1603 },
1604};
1605
1606pub const feature_a17 = Feature{
1607 .name = "a17",
1608 .description = "Cortex-A17 ARM processors",
1609 .llvm_name = "a17",
1610 .subfeatures = &[_]*const Feature {
1611 },
1612};
1613
1614pub const feature_a32 = Feature{
1615 .name = "a32",
1616 .description = "Cortex-A32 ARM processors",
1617 .llvm_name = "a32",
1618 .subfeatures = &[_]*const Feature {
1619 },
1620};
1621
1622pub const feature_a35 = Feature{
1623 .name = "a35",
1624 .description = "Cortex-A35 ARM processors",
1625 .llvm_name = "a35",
1626 .subfeatures = &[_]*const Feature {
1627 },
1628};
1629
1630pub const feature_a53 = Feature{
1631 .name = "a53",
1632 .description = "Cortex-A53 ARM processors",
1633 .llvm_name = "a53",
1634 .subfeatures = &[_]*const Feature {
1635 },
1636};
1637
1638pub const feature_a55 = Feature{
1639 .name = "a55",
1640 .description = "Cortex-A55 ARM processors",
1641 .llvm_name = "a55",
1642 .subfeatures = &[_]*const Feature {
1643 },
1644};
1645
1646pub const feature_a57 = Feature{
1647 .name = "a57",
1648 .description = "Cortex-A57 ARM processors",
1649 .llvm_name = "a57",
1650 .subfeatures = &[_]*const Feature {
1651 },
1652};
1653
1654pub const feature_a72 = Feature{
1655 .name = "a72",
1656 .description = "Cortex-A72 ARM processors",
1657 .llvm_name = "a72",
1658 .subfeatures = &[_]*const Feature {
1659 },
1660};
1661
1662pub const feature_a73 = Feature{
1663 .name = "a73",
1664 .description = "Cortex-A73 ARM processors",
1665 .llvm_name = "a73",
1666 .subfeatures = &[_]*const Feature {
1667 },
1668};
1669
1670pub const feature_a75 = Feature{
1671 .name = "a75",
1672 .description = "Cortex-A75 ARM processors",
1673 .llvm_name = "a75",
1674 .subfeatures = &[_]*const Feature {
1675 },
1676};
1677
1678pub const feature_a76 = Feature{
1679 .name = "a76",
1680 .description = "Cortex-A76 ARM processors",
1681 .llvm_name = "a76",
1682 .subfeatures = &[_]*const Feature {
1683 },
1684};
1685
1686pub const feature_exynos = Feature{
1687 .name = "exynos",
1688 .description = "Samsung Exynos processors",
1689 .llvm_name = "exynos",
1690 .subfeatures = &[_]*const Feature {
1691 &feature_slowFpBrcc,
1692 &feature_slowfpvmlx,
1693 &feature_hwdiv,
1694 &feature_slowVdup32,
1695 &feature_wideStrideVfp,
1696 &feature_fuseAes,
1697 &feature_slowVgetlni32,
1698 &feature_zcz,
1699 &feature_profUnpr,
1700 &feature_d32,
1701 &feature_hwdivArm,
1702 &feature_retAddrStack,
1703 &feature_crc,
1704 &feature_expandFpMlx,
1705 &feature_useAa,
1706 &feature_dontWidenVmovs,
1707 &feature_fpregs,
1708 &feature_fuseLiterals,
1709 },
1710};
1711
1712pub const feature_krait = Feature{
1713 .name = "krait",
1714 .description = "Qualcomm Krait processors",
1715 .llvm_name = "krait",
1716 .subfeatures = &[_]*const Feature {
1717 },
1718};
1719
1720pub const feature_kryo = Feature{
1721 .name = "kryo",
1722 .description = "Qualcomm Kryo processors",
1723 .llvm_name = "kryo",
1724 .subfeatures = &[_]*const Feature {
1725 },
1726};
1727
1728pub const feature_m3 = Feature{
1729 .name = "m3",
1730 .description = "Cortex-M3 ARM processors",
1731 .llvm_name = "m3",
1732 .subfeatures = &[_]*const Feature {
1733 },
1734};
1735
1736pub const feature_r4 = Feature{
1737 .name = "r4",
1738 .description = "Cortex-R4 ARM processors",
1739 .llvm_name = "r4",
1740 .subfeatures = &[_]*const Feature {
1741 },
1742};
1743
1744pub const feature_r5 = Feature{
1745 .name = "r5",
1746 .description = "Cortex-R5 ARM processors",
1747 .llvm_name = "r5",
1748 .subfeatures = &[_]*const Feature {
1749 },
1750};
1751
1752pub const feature_r7 = Feature{
1753 .name = "r7",
1754 .description = "Cortex-R7 ARM processors",
1755 .llvm_name = "r7",
1756 .subfeatures = &[_]*const Feature {
1757 },
1758};
1759
1760pub const feature_r52 = Feature{
1761 .name = "r52",
1762 .description = "Cortex-R52 ARM processors",
1763 .llvm_name = "r52",
1764 .subfeatures = &[_]*const Feature {
1765 },
1766};
1767
1768pub const feature_swift = Feature{
1769 .name = "swift",
1770 .description = "Swift ARM processors",
1771 .llvm_name = "swift",
1772 .subfeatures = &[_]*const Feature {
1773 },
1774};
1775
1776pub const feature_xscale = Feature{
1777 .name = "xscale",
1778 .description = "ARMv5te architecture",
1779 .llvm_name = "xscale",
1780 .subfeatures = &[_]*const Feature {
1781 &feature_v4t,
1782 },
1783};
1784
1785pub const features = &[_]*const Feature {
1786 &feature_armv2,
1787 &feature_armv2a,
1788 &feature_armv3,
1789 &feature_armv3m,
1790 &feature_armv4,
1791 &feature_armv4t,
1792 &feature_armv5t,
1793 &feature_armv5te,
1794 &feature_armv5tej,
1795 &feature_armv6,
1796 &feature_armv6j,
1797 &feature_armv6k,
1798 &feature_armv6kz,
1799 &feature_armv6M,
1800 &feature_armv6sM,
1801 &feature_armv6t2,
1802 &feature_armv7A,
1803 &feature_armv7eM,
1804 &feature_armv7k,
1805 &feature_armv7M,
1806 &feature_armv7R,
1807 &feature_armv7s,
1808 &feature_armv7ve,
1809 &feature_armv8A,
1810 &feature_armv8Mbase,
1811 &feature_armv8Mmain,
1812 &feature_armv8R,
1813 &feature_armv81A,
1814 &feature_armv81Mmain,
1815 &feature_armv82A,
1816 &feature_armv83A,
1817 &feature_armv84A,
1818 &feature_armv85A,
1819 &feature_msecext8,
1820 &feature_aclass,
1821 &feature_aes,
1822 &feature_acquireRelease,
1823 &feature_avoidMovsShop,
1824 &feature_avoidPartialCpsr,
1825 &feature_crc,
1826 &feature_cheapPredicableCpsr,
1827 &feature_vldnAlign,
1828 &feature_crypto,
1829 &feature_d32,
1830 &feature_db,
1831 &feature_dfb,
1832 &feature_dsp,
1833 &feature_dontWidenVmovs,
1834 &feature_dotprod,
1835 &feature_executeOnly,
1836 &feature_expandFpMlx,
1837 &feature_fp16,
1838 &feature_fp16fml,
1839 &feature_fp64,
1840 &feature_fpao,
1841 &feature_fpArmv8,
1842 &feature_fpArmv8d16,
1843 &feature_fpArmv8d16sp,
1844 &feature_fpArmv8sp,
1845 &feature_fpregs,
1846 &feature_fpregs16,
1847 &feature_fpregs64,
1848 &feature_fullfp16,
1849 &feature_fuseAes,
1850 &feature_fuseLiterals,
1851 &feature_hwdivArm,
1852 &feature_hwdiv,
1853 &feature_noBranchPredictor,
1854 &feature_retAddrStack,
1855 &feature_slowfpvmlx,
1856 &feature_vmlxHazards,
1857 &feature_lob,
1858 &feature_longCalls,
1859 &feature_mclass,
1860 &feature_mp,
1861 &feature_mve1beat,
1862 &feature_mve2beat,
1863 &feature_mve4beat,
1864 &feature_muxedUnits,
1865 &feature_neon,
1866 &feature_neonfp,
1867 &feature_neonFpmovs,
1868 &feature_naclTrap,
1869 &feature_noarm,
1870 &feature_noMovt,
1871 &feature_noNegImmediates,
1872 &feature_disablePostraScheduler,
1873 &feature_nonpipelinedVfp,
1874 &feature_perfmon,
1875 &feature_bit32,
1876 &feature_preferIshst,
1877 &feature_loopAlign,
1878 &feature_preferVmovsr,
1879 &feature_profUnpr,
1880 &feature_ras,
1881 &feature_rclass,
1882 &feature_readTpHard,
1883 &feature_reserveR9,
1884 &feature_sb,
1885 &feature_sha2,
1886 &feature_slowFpBrcc,
1887 &feature_slowLoadDSubreg,
1888 &feature_slowOddReg,
1889 &feature_slowVdup32,
1890 &feature_slowVgetlni32,
1891 &feature_splatVfpNeon,
1892 &feature_strictAlign,
1893 &feature_thumb2,
1894 &feature_trustzone,
1895 &feature_useAa,
1896 &feature_useMisched,
1897 &feature_wideStrideVfp,
1898 &feature_v7clrex,
1899 &feature_vfp2,
1900 &feature_vfp2sp,
1901 &feature_vfp3,
1902 &feature_vfp3d16,
1903 &feature_vfp3d16sp,
1904 &feature_vfp3sp,
1905 &feature_vfp4,
1906 &feature_vfp4d16,
1907 &feature_vfp4d16sp,
1908 &feature_vfp4sp,
1909 &feature_vmlxForwarding,
1910 &feature_virtualization,
1911 &feature_zcz,
1912 &feature_mvefp,
1913 &feature_mve,
1914 &feature_v4t,
1915 &feature_v5te,
1916 &feature_v5t,
1917 &feature_v6k,
1918 &feature_v6m,
1919 &feature_v6,
1920 &feature_v6t2,
1921 &feature_v7,
1922 &feature_v8m,
1923 &feature_v8mmain,
1924 &feature_v8,
1925 &feature_v81mmain,
1926 &feature_v81a,
1927 &feature_v82a,
1928 &feature_v83a,
1929 &feature_v84a,
1930 &feature_v85a,
1931 &feature_iwmmxt,
1932 &feature_iwmmxt2,
1933 &feature_softFloat,
1934 &feature_thumbMode,
1935 &feature_a5,
1936 &feature_a7,
1937 &feature_a8,
1938 &feature_a9,
1939 &feature_a12,
1940 &feature_a15,
1941 &feature_a17,
1942 &feature_a32,
1943 &feature_a35,
1944 &feature_a53,
1945 &feature_a55,
1946 &feature_a57,
1947 &feature_a72,
1948 &feature_a73,
1949 &feature_a75,
1950 &feature_a76,
1951 &feature_exynos,
1952 &feature_krait,
1953 &feature_kryo,
1954 &feature_m3,
1955 &feature_r4,
1956 &feature_r5,
1957 &feature_r7,
1958 &feature_r52,
1959 &feature_swift,
1960 &feature_xscale,
1961};
1962
1963pub const cpu_arm1020e = Cpu{
1964 .name = "arm1020e",
1965 .llvm_name = "arm1020e",
1966 .subfeatures = &[_]*const Feature {
1967 &feature_v4t,
1968 &feature_armv5te,
1969 },
1970};
1971
1972pub const cpu_arm1020t = Cpu{
1973 .name = "arm1020t",
1974 .llvm_name = "arm1020t",
1975 .subfeatures = &[_]*const Feature {
1976 &feature_v4t,
1977 &feature_armv5t,
1978 },
1979};
1980
1981pub const cpu_arm1022e = Cpu{
1982 .name = "arm1022e",
1983 .llvm_name = "arm1022e",
1984 .subfeatures = &[_]*const Feature {
1985 &feature_v4t,
1986 &feature_armv5te,
1987 },
1988};
1989
1990pub const cpu_arm10e = Cpu{
1991 .name = "arm10e",
1992 .llvm_name = "arm10e",
1993 .subfeatures = &[_]*const Feature {
1994 &feature_v4t,
1995 &feature_armv5te,
1996 },
1997};
1998
1999pub const cpu_arm10tdmi = Cpu{
2000 .name = "arm10tdmi",
2001 .llvm_name = "arm10tdmi",
2002 .subfeatures = &[_]*const Feature {
2003 &feature_v4t,
2004 &feature_armv5t,
2005 },
2006};
2007
2008pub const cpu_arm1136jS = Cpu{
2009 .name = "arm1136j-s",
2010 .llvm_name = "arm1136j-s",
2011 .subfeatures = &[_]*const Feature {
2012 &feature_v4t,
2013 &feature_dsp,
2014 &feature_armv6,
2015 },
2016};
2017
2018pub const cpu_arm1136jfS = Cpu{
2019 .name = "arm1136jf-s",
2020 .llvm_name = "arm1136jf-s",
2021 .subfeatures = &[_]*const Feature {
2022 &feature_v4t,
2023 &feature_dsp,
2024 &feature_armv6,
2025 &feature_slowfpvmlx,
2026 &feature_fpregs,
2027 &feature_vfp2,
2028 },
2029};
2030
2031pub const cpu_arm1156t2S = Cpu{
2032 .name = "arm1156t2-s",
2033 .llvm_name = "arm1156t2-s",
2034 .subfeatures = &[_]*const Feature {
2035 &feature_v4t,
2036 &feature_dsp,
2037 &feature_thumb2,
2038 &feature_armv6t2,
2039 },
2040};
2041
2042pub const cpu_arm1156t2fS = Cpu{
2043 .name = "arm1156t2f-s",
2044 .llvm_name = "arm1156t2f-s",
2045 .subfeatures = &[_]*const Feature {
2046 &feature_v4t,
2047 &feature_dsp,
2048 &feature_thumb2,
2049 &feature_armv6t2,
2050 &feature_slowfpvmlx,
2051 &feature_fpregs,
2052 &feature_vfp2,
2053 },
2054};
2055
2056pub const cpu_arm1176jS = Cpu{
2057 .name = "arm1176j-s",
2058 .llvm_name = "arm1176j-s",
2059 .subfeatures = &[_]*const Feature {
2060 &feature_v4t,
2061 &feature_trustzone,
2062 &feature_armv6kz,
2063 },
2064};
2065
2066pub const cpu_arm1176jzS = Cpu{
2067 .name = "arm1176jz-s",
2068 .llvm_name = "arm1176jz-s",
2069 .subfeatures = &[_]*const Feature {
2070 &feature_v4t,
2071 &feature_trustzone,
2072 &feature_armv6kz,
2073 },
2074};
2075
2076pub const cpu_arm1176jzfS = Cpu{
2077 .name = "arm1176jzf-s",
2078 .llvm_name = "arm1176jzf-s",
2079 .subfeatures = &[_]*const Feature {
2080 &feature_v4t,
2081 &feature_trustzone,
2082 &feature_armv6kz,
2083 &feature_slowfpvmlx,
2084 &feature_fpregs,
2085 &feature_vfp2,
2086 },
2087};
2088
2089pub const cpu_arm710t = Cpu{
2090 .name = "arm710t",
2091 .llvm_name = "arm710t",
2092 .subfeatures = &[_]*const Feature {
2093 &feature_v4t,
2094 &feature_armv4t,
2095 },
2096};
2097
2098pub const cpu_arm720t = Cpu{
2099 .name = "arm720t",
2100 .llvm_name = "arm720t",
2101 .subfeatures = &[_]*const Feature {
2102 &feature_v4t,
2103 &feature_armv4t,
2104 },
2105};
2106
2107pub const cpu_arm7tdmi = Cpu{
2108 .name = "arm7tdmi",
2109 .llvm_name = "arm7tdmi",
2110 .subfeatures = &[_]*const Feature {
2111 &feature_v4t,
2112 &feature_armv4t,
2113 },
2114};
2115
2116pub const cpu_arm7tdmiS = Cpu{
2117 .name = "arm7tdmi-s",
2118 .llvm_name = "arm7tdmi-s",
2119 .subfeatures = &[_]*const Feature {
2120 &feature_v4t,
2121 &feature_armv4t,
2122 },
2123};
2124
2125pub const cpu_arm8 = Cpu{
2126 .name = "arm8",
2127 .llvm_name = "arm8",
2128 .subfeatures = &[_]*const Feature {
2129 &feature_armv4,
2130 },
2131};
2132
2133pub const cpu_arm810 = Cpu{
2134 .name = "arm810",
2135 .llvm_name = "arm810",
2136 .subfeatures = &[_]*const Feature {
2137 &feature_armv4,
2138 },
2139};
2140
2141pub const cpu_arm9 = Cpu{
2142 .name = "arm9",
2143 .llvm_name = "arm9",
2144 .subfeatures = &[_]*const Feature {
2145 &feature_v4t,
2146 &feature_armv4t,
2147 },
2148};
2149
2150pub const cpu_arm920 = Cpu{
2151 .name = "arm920",
2152 .llvm_name = "arm920",
2153 .subfeatures = &[_]*const Feature {
2154 &feature_v4t,
2155 &feature_armv4t,
2156 },
2157};
2158
2159pub const cpu_arm920t = Cpu{
2160 .name = "arm920t",
2161 .llvm_name = "arm920t",
2162 .subfeatures = &[_]*const Feature {
2163 &feature_v4t,
2164 &feature_armv4t,
2165 },
2166};
2167
2168pub const cpu_arm922t = Cpu{
2169 .name = "arm922t",
2170 .llvm_name = "arm922t",
2171 .subfeatures = &[_]*const Feature {
2172 &feature_v4t,
2173 &feature_armv4t,
2174 },
2175};
2176
2177pub const cpu_arm926ejS = Cpu{
2178 .name = "arm926ej-s",
2179 .llvm_name = "arm926ej-s",
2180 .subfeatures = &[_]*const Feature {
2181 &feature_v4t,
2182 &feature_armv5te,
2183 },
2184};
2185
2186pub const cpu_arm940t = Cpu{
2187 .name = "arm940t",
2188 .llvm_name = "arm940t",
2189 .subfeatures = &[_]*const Feature {
2190 &feature_v4t,
2191 &feature_armv4t,
2192 },
2193};
2194
2195pub const cpu_arm946eS = Cpu{
2196 .name = "arm946e-s",
2197 .llvm_name = "arm946e-s",
2198 .subfeatures = &[_]*const Feature {
2199 &feature_v4t,
2200 &feature_armv5te,
2201 },
2202};
2203
2204pub const cpu_arm966eS = Cpu{
2205 .name = "arm966e-s",
2206 .llvm_name = "arm966e-s",
2207 .subfeatures = &[_]*const Feature {
2208 &feature_v4t,
2209 &feature_armv5te,
2210 },
2211};
2212
2213pub const cpu_arm968eS = Cpu{
2214 .name = "arm968e-s",
2215 .llvm_name = "arm968e-s",
2216 .subfeatures = &[_]*const Feature {
2217 &feature_v4t,
2218 &feature_armv5te,
2219 },
2220};
2221
2222pub const cpu_arm9e = Cpu{
2223 .name = "arm9e",
2224 .llvm_name = "arm9e",
2225 .subfeatures = &[_]*const Feature {
2226 &feature_v4t,
2227 &feature_armv5te,
2228 },
2229};
2230
2231pub const cpu_arm9tdmi = Cpu{
2232 .name = "arm9tdmi",
2233 .llvm_name = "arm9tdmi",
2234 .subfeatures = &[_]*const Feature {
2235 &feature_v4t,
2236 &feature_armv4t,
2237 },
2238};
2239
2240pub const cpu_cortexA12 = Cpu{
2241 .name = "cortex-a12",
2242 .llvm_name = "cortex-a12",
2243 .subfeatures = &[_]*const Feature {
2244 &feature_perfmon,
2245 &feature_v7clrex,
2246 &feature_db,
2247 &feature_thumb2,
2248 &feature_v4t,
2249 &feature_d32,
2250 &feature_aclass,
2251 &feature_dsp,
2252 &feature_fpregs,
2253 &feature_armv7A,
2254 &feature_avoidPartialCpsr,
2255 &feature_retAddrStack,
2256 &feature_mp,
2257 &feature_trustzone,
2258 &feature_fp16,
2259 &feature_vfp4,
2260 &feature_vmlxForwarding,
2261 &feature_hwdiv,
2262 &feature_hwdivArm,
2263 &feature_virtualization,
2264 &feature_a12,
2265 },
2266};
2267
2268pub const cpu_cortexA15 = Cpu{
2269 .name = "cortex-a15",
2270 .llvm_name = "cortex-a15",
2271 .subfeatures = &[_]*const Feature {
2272 &feature_perfmon,
2273 &feature_v7clrex,
2274 &feature_db,
2275 &feature_thumb2,
2276 &feature_v4t,
2277 &feature_d32,
2278 &feature_aclass,
2279 &feature_dsp,
2280 &feature_fpregs,
2281 &feature_armv7A,
2282 &feature_avoidPartialCpsr,
2283 &feature_vldnAlign,
2284 &feature_dontWidenVmovs,
2285 &feature_retAddrStack,
2286 &feature_mp,
2287 &feature_muxedUnits,
2288 &feature_splatVfpNeon,
2289 &feature_trustzone,
2290 &feature_fp16,
2291 &feature_vfp4,
2292 &feature_hwdiv,
2293 &feature_hwdivArm,
2294 &feature_virtualization,
2295 &feature_a15,
2296 },
2297};
2298
2299pub const cpu_cortexA17 = Cpu{
2300 .name = "cortex-a17",
2301 .llvm_name = "cortex-a17",
2302 .subfeatures = &[_]*const Feature {
2303 &feature_perfmon,
2304 &feature_v7clrex,
2305 &feature_db,
2306 &feature_thumb2,
2307 &feature_v4t,
2308 &feature_d32,
2309 &feature_aclass,
2310 &feature_dsp,
2311 &feature_fpregs,
2312 &feature_armv7A,
2313 &feature_avoidPartialCpsr,
2314 &feature_retAddrStack,
2315 &feature_mp,
2316 &feature_trustzone,
2317 &feature_fp16,
2318 &feature_vfp4,
2319 &feature_vmlxForwarding,
2320 &feature_hwdiv,
2321 &feature_hwdivArm,
2322 &feature_virtualization,
2323 &feature_a17,
2324 },
2325};
2326
2327pub const cpu_cortexA32 = Cpu{
2328 .name = "cortex-a32",
2329 .llvm_name = "cortex-a32",
2330 .subfeatures = &[_]*const Feature {
2331 &feature_mp,
2332 &feature_acquireRelease,
2333 &feature_perfmon,
2334 &feature_hwdiv,
2335 &feature_trustzone,
2336 &feature_v7clrex,
2337 &feature_db,
2338 &feature_thumb2,
2339 &feature_fp16,
2340 &feature_v4t,
2341 &feature_d32,
2342 &feature_aclass,
2343 &feature_hwdivArm,
2344 &feature_crc,
2345 &feature_dsp,
2346 &feature_fpregs,
2347 &feature_armv8A,
2348 &feature_crypto,
2349 },
2350};
2351
2352pub const cpu_cortexA35 = Cpu{
2353 .name = "cortex-a35",
2354 .llvm_name = "cortex-a35",
2355 .subfeatures = &[_]*const Feature {
2356 &feature_mp,
2357 &feature_acquireRelease,
2358 &feature_perfmon,
2359 &feature_hwdiv,
2360 &feature_trustzone,
2361 &feature_v7clrex,
2362 &feature_db,
2363 &feature_thumb2,
2364 &feature_fp16,
2365 &feature_v4t,
2366 &feature_d32,
2367 &feature_aclass,
2368 &feature_hwdivArm,
2369 &feature_crc,
2370 &feature_dsp,
2371 &feature_fpregs,
2372 &feature_armv8A,
2373 &feature_crypto,
2374 &feature_a35,
2375 },
2376};
2377
2378pub const cpu_cortexA5 = Cpu{
2379 .name = "cortex-a5",
2380 .llvm_name = "cortex-a5",
2381 .subfeatures = &[_]*const Feature {
2382 &feature_perfmon,
2383 &feature_v7clrex,
2384 &feature_db,
2385 &feature_thumb2,
2386 &feature_v4t,
2387 &feature_d32,
2388 &feature_aclass,
2389 &feature_dsp,
2390 &feature_fpregs,
2391 &feature_armv7A,
2392 &feature_retAddrStack,
2393 &feature_slowfpvmlx,
2394 &feature_mp,
2395 &feature_slowFpBrcc,
2396 &feature_trustzone,
2397 &feature_fp16,
2398 &feature_vfp4,
2399 &feature_vmlxForwarding,
2400 &feature_a5,
2401 },
2402};
2403
2404pub const cpu_cortexA53 = Cpu{
2405 .name = "cortex-a53",
2406 .llvm_name = "cortex-a53",
2407 .subfeatures = &[_]*const Feature {
2408 &feature_mp,
2409 &feature_acquireRelease,
2410 &feature_perfmon,
2411 &feature_hwdiv,
2412 &feature_trustzone,
2413 &feature_v7clrex,
2414 &feature_db,
2415 &feature_thumb2,
2416 &feature_fp16,
2417 &feature_v4t,
2418 &feature_d32,
2419 &feature_aclass,
2420 &feature_hwdivArm,
2421 &feature_crc,
2422 &feature_dsp,
2423 &feature_fpregs,
2424 &feature_armv8A,
2425 &feature_crypto,
2426 &feature_fpao,
2427 &feature_a53,
2428 },
2429};
2430
2431pub const cpu_cortexA55 = Cpu{
2432 .name = "cortex-a55",
2433 .llvm_name = "cortex-a55",
2434 .subfeatures = &[_]*const Feature {
2435 &feature_mp,
2436 &feature_acquireRelease,
2437 &feature_perfmon,
2438 &feature_hwdiv,
2439 &feature_trustzone,
2440 &feature_v7clrex,
2441 &feature_db,
2442 &feature_thumb2,
2443 &feature_ras,
2444 &feature_fp16,
2445 &feature_v4t,
2446 &feature_d32,
2447 &feature_aclass,
2448 &feature_hwdivArm,
2449 &feature_crc,
2450 &feature_dsp,
2451 &feature_fpregs,
2452 &feature_armv82A,
2453 &feature_dotprod,
2454 &feature_a55,
2455 },
2456};
2457
2458pub const cpu_cortexA57 = Cpu{
2459 .name = "cortex-a57",
2460 .llvm_name = "cortex-a57",
2461 .subfeatures = &[_]*const Feature {
2462 &feature_mp,
2463 &feature_acquireRelease,
2464 &feature_perfmon,
2465 &feature_hwdiv,
2466 &feature_trustzone,
2467 &feature_v7clrex,
2468 &feature_db,
2469 &feature_thumb2,
2470 &feature_fp16,
2471 &feature_v4t,
2472 &feature_d32,
2473 &feature_aclass,
2474 &feature_hwdivArm,
2475 &feature_crc,
2476 &feature_dsp,
2477 &feature_fpregs,
2478 &feature_armv8A,
2479 &feature_avoidPartialCpsr,
2480 &feature_cheapPredicableCpsr,
2481 &feature_crypto,
2482 &feature_fpao,
2483 &feature_a57,
2484 },
2485};
2486
2487pub const cpu_cortexA7 = Cpu{
2488 .name = "cortex-a7",
2489 .llvm_name = "cortex-a7",
2490 .subfeatures = &[_]*const Feature {
2491 &feature_perfmon,
2492 &feature_v7clrex,
2493 &feature_db,
2494 &feature_thumb2,
2495 &feature_v4t,
2496 &feature_d32,
2497 &feature_aclass,
2498 &feature_dsp,
2499 &feature_fpregs,
2500 &feature_armv7A,
2501 &feature_retAddrStack,
2502 &feature_slowfpvmlx,
2503 &feature_vmlxHazards,
2504 &feature_mp,
2505 &feature_slowFpBrcc,
2506 &feature_trustzone,
2507 &feature_fp16,
2508 &feature_vfp4,
2509 &feature_vmlxForwarding,
2510 &feature_hwdiv,
2511 &feature_hwdivArm,
2512 &feature_virtualization,
2513 &feature_a7,
2514 },
2515};
2516
2517pub const cpu_cortexA72 = Cpu{
2518 .name = "cortex-a72",
2519 .llvm_name = "cortex-a72",
2520 .subfeatures = &[_]*const Feature {
2521 &feature_mp,
2522 &feature_acquireRelease,
2523 &feature_perfmon,
2524 &feature_hwdiv,
2525 &feature_trustzone,
2526 &feature_v7clrex,
2527 &feature_db,
2528 &feature_thumb2,
2529 &feature_fp16,
2530 &feature_v4t,
2531 &feature_d32,
2532 &feature_aclass,
2533 &feature_hwdivArm,
2534 &feature_crc,
2535 &feature_dsp,
2536 &feature_fpregs,
2537 &feature_armv8A,
2538 &feature_crypto,
2539 &feature_a72,
2540 },
2541};
2542
2543pub const cpu_cortexA73 = Cpu{
2544 .name = "cortex-a73",
2545 .llvm_name = "cortex-a73",
2546 .subfeatures = &[_]*const Feature {
2547 &feature_mp,
2548 &feature_acquireRelease,
2549 &feature_perfmon,
2550 &feature_hwdiv,
2551 &feature_trustzone,
2552 &feature_v7clrex,
2553 &feature_db,
2554 &feature_thumb2,
2555 &feature_fp16,
2556 &feature_v4t,
2557 &feature_d32,
2558 &feature_aclass,
2559 &feature_hwdivArm,
2560 &feature_crc,
2561 &feature_dsp,
2562 &feature_fpregs,
2563 &feature_armv8A,
2564 &feature_crypto,
2565 &feature_a73,
2566 },
2567};
2568
2569pub const cpu_cortexA75 = Cpu{
2570 .name = "cortex-a75",
2571 .llvm_name = "cortex-a75",
2572 .subfeatures = &[_]*const Feature {
2573 &feature_mp,
2574 &feature_acquireRelease,
2575 &feature_perfmon,
2576 &feature_hwdiv,
2577 &feature_trustzone,
2578 &feature_v7clrex,
2579 &feature_db,
2580 &feature_thumb2,
2581 &feature_ras,
2582 &feature_fp16,
2583 &feature_v4t,
2584 &feature_d32,
2585 &feature_aclass,
2586 &feature_hwdivArm,
2587 &feature_crc,
2588 &feature_dsp,
2589 &feature_fpregs,
2590 &feature_armv82A,
2591 &feature_dotprod,
2592 &feature_a75,
2593 },
2594};
2595
2596pub const cpu_cortexA76 = Cpu{
2597 .name = "cortex-a76",
2598 .llvm_name = "cortex-a76",
2599 .subfeatures = &[_]*const Feature {
2600 &feature_mp,
2601 &feature_acquireRelease,
2602 &feature_perfmon,
2603 &feature_hwdiv,
2604 &feature_trustzone,
2605 &feature_v7clrex,
2606 &feature_db,
2607 &feature_thumb2,
2608 &feature_ras,
2609 &feature_fp16,
2610 &feature_v4t,
2611 &feature_d32,
2612 &feature_aclass,
2613 &feature_hwdivArm,
2614 &feature_crc,
2615 &feature_dsp,
2616 &feature_fpregs,
2617 &feature_armv82A,
2618 &feature_crypto,
2619 &feature_dotprod,
2620 &feature_fullfp16,
2621 &feature_a76,
2622 },
2623};
2624
2625pub const cpu_cortexA76ae = Cpu{
2626 .name = "cortex-a76ae",
2627 .llvm_name = "cortex-a76ae",
2628 .subfeatures = &[_]*const Feature {
2629 &feature_mp,
2630 &feature_acquireRelease,
2631 &feature_perfmon,
2632 &feature_hwdiv,
2633 &feature_trustzone,
2634 &feature_v7clrex,
2635 &feature_db,
2636 &feature_thumb2,
2637 &feature_ras,
2638 &feature_fp16,
2639 &feature_v4t,
2640 &feature_d32,
2641 &feature_aclass,
2642 &feature_hwdivArm,
2643 &feature_crc,
2644 &feature_dsp,
2645 &feature_fpregs,
2646 &feature_armv82A,
2647 &feature_crypto,
2648 &feature_dotprod,
2649 &feature_fullfp16,
2650 &feature_a76,
2651 },
2652};
2653
2654pub const cpu_cortexA8 = Cpu{
2655 .name = "cortex-a8",
2656 .llvm_name = "cortex-a8",
2657 .subfeatures = &[_]*const Feature {
2658 &feature_perfmon,
2659 &feature_v7clrex,
2660 &feature_db,
2661 &feature_thumb2,
2662 &feature_v4t,
2663 &feature_d32,
2664 &feature_aclass,
2665 &feature_dsp,
2666 &feature_fpregs,
2667 &feature_armv7A,
2668 &feature_retAddrStack,
2669 &feature_slowfpvmlx,
2670 &feature_vmlxHazards,
2671 &feature_nonpipelinedVfp,
2672 &feature_slowFpBrcc,
2673 &feature_trustzone,
2674 &feature_vmlxForwarding,
2675 &feature_a8,
2676 },
2677};
2678
2679pub const cpu_cortexA9 = Cpu{
2680 .name = "cortex-a9",
2681 .llvm_name = "cortex-a9",
2682 .subfeatures = &[_]*const Feature {
2683 &feature_perfmon,
2684 &feature_v7clrex,
2685 &feature_db,
2686 &feature_thumb2,
2687 &feature_v4t,
2688 &feature_d32,
2689 &feature_aclass,
2690 &feature_dsp,
2691 &feature_fpregs,
2692 &feature_armv7A,
2693 &feature_avoidPartialCpsr,
2694 &feature_vldnAlign,
2695 &feature_expandFpMlx,
2696 &feature_fp16,
2697 &feature_retAddrStack,
2698 &feature_vmlxHazards,
2699 &feature_mp,
2700 &feature_muxedUnits,
2701 &feature_neonFpmovs,
2702 &feature_preferVmovsr,
2703 &feature_trustzone,
2704 &feature_vmlxForwarding,
2705 &feature_a9,
2706 },
2707};
2708
2709pub const cpu_cortexM0 = Cpu{
2710 .name = "cortex-m0",
2711 .llvm_name = "cortex-m0",
2712 .subfeatures = &[_]*const Feature {
2713 &feature_db,
2714 &feature_thumbMode,
2715 &feature_mclass,
2716 &feature_noarm,
2717 &feature_v4t,
2718 &feature_strictAlign,
2719 &feature_armv6M,
2720 },
2721};
2722
2723pub const cpu_cortexM0plus = Cpu{
2724 .name = "cortex-m0plus",
2725 .llvm_name = "cortex-m0plus",
2726 .subfeatures = &[_]*const Feature {
2727 &feature_db,
2728 &feature_thumbMode,
2729 &feature_mclass,
2730 &feature_noarm,
2731 &feature_v4t,
2732 &feature_strictAlign,
2733 &feature_armv6M,
2734 },
2735};
2736
2737pub const cpu_cortexM1 = Cpu{
2738 .name = "cortex-m1",
2739 .llvm_name = "cortex-m1",
2740 .subfeatures = &[_]*const Feature {
2741 &feature_db,
2742 &feature_thumbMode,
2743 &feature_mclass,
2744 &feature_noarm,
2745 &feature_v4t,
2746 &feature_strictAlign,
2747 &feature_armv6M,
2748 },
2749};
2750
2751pub const cpu_cortexM23 = Cpu{
2752 .name = "cortex-m23",
2753 .llvm_name = "cortex-m23",
2754 .subfeatures = &[_]*const Feature {
2755 &feature_acquireRelease,
2756 &feature_v7clrex,
2757 &feature_db,
2758 &feature_msecext8,
2759 &feature_thumbMode,
2760 &feature_mclass,
2761 &feature_noarm,
2762 &feature_v4t,
2763 &feature_strictAlign,
2764 &feature_hwdiv,
2765 &feature_armv8Mbase,
2766 &feature_noMovt,
2767 },
2768};
2769
2770pub const cpu_cortexM3 = Cpu{
2771 .name = "cortex-m3",
2772 .llvm_name = "cortex-m3",
2773 .subfeatures = &[_]*const Feature {
2774 &feature_v7clrex,
2775 &feature_db,
2776 &feature_thumb2,
2777 &feature_mclass,
2778 &feature_thumbMode,
2779 &feature_noarm,
2780 &feature_v4t,
2781 &feature_perfmon,
2782 &feature_hwdiv,
2783 &feature_armv7M,
2784 &feature_noBranchPredictor,
2785 &feature_loopAlign,
2786 &feature_useAa,
2787 &feature_useMisched,
2788 &feature_m3,
2789 },
2790};
2791
2792pub const cpu_cortexM33 = Cpu{
2793 .name = "cortex-m33",
2794 .llvm_name = "cortex-m33",
2795 .subfeatures = &[_]*const Feature {
2796 &feature_acquireRelease,
2797 &feature_v7clrex,
2798 &feature_db,
2799 &feature_msecext8,
2800 &feature_thumb2,
2801 &feature_mclass,
2802 &feature_thumbMode,
2803 &feature_noarm,
2804 &feature_v4t,
2805 &feature_perfmon,
2806 &feature_hwdiv,
2807 &feature_armv8Mmain,
2808 &feature_dsp,
2809 &feature_fp16,
2810 &feature_fpregs,
2811 &feature_fpArmv8d16sp,
2812 &feature_noBranchPredictor,
2813 &feature_slowfpvmlx,
2814 &feature_loopAlign,
2815 &feature_useAa,
2816 &feature_useMisched,
2817 },
2818};
2819
2820pub const cpu_cortexM35p = Cpu{
2821 .name = "cortex-m35p",
2822 .llvm_name = "cortex-m35p",
2823 .subfeatures = &[_]*const Feature {
2824 &feature_acquireRelease,
2825 &feature_v7clrex,
2826 &feature_db,
2827 &feature_msecext8,
2828 &feature_thumb2,
2829 &feature_mclass,
2830 &feature_thumbMode,
2831 &feature_noarm,
2832 &feature_v4t,
2833 &feature_perfmon,
2834 &feature_hwdiv,
2835 &feature_armv8Mmain,
2836 &feature_dsp,
2837 &feature_fp16,
2838 &feature_fpregs,
2839 &feature_fpArmv8d16sp,
2840 &feature_noBranchPredictor,
2841 &feature_slowfpvmlx,
2842 &feature_loopAlign,
2843 &feature_useAa,
2844 &feature_useMisched,
2845 },
2846};
2847
2848pub const cpu_cortexM4 = Cpu{
2849 .name = "cortex-m4",
2850 .llvm_name = "cortex-m4",
2851 .subfeatures = &[_]*const Feature {
2852 &feature_perfmon,
2853 &feature_v7clrex,
2854 &feature_db,
2855 &feature_thumb2,
2856 &feature_mclass,
2857 &feature_thumbMode,
2858 &feature_noarm,
2859 &feature_v4t,
2860 &feature_dsp,
2861 &feature_hwdiv,
2862 &feature_armv7eM,
2863 &feature_noBranchPredictor,
2864 &feature_slowfpvmlx,
2865 &feature_loopAlign,
2866 &feature_useAa,
2867 &feature_useMisched,
2868 &feature_fp16,
2869 &feature_fpregs,
2870 &feature_vfp4d16sp,
2871 },
2872};
2873
2874pub const cpu_cortexM7 = Cpu{
2875 .name = "cortex-m7",
2876 .llvm_name = "cortex-m7",
2877 .subfeatures = &[_]*const Feature {
2878 &feature_perfmon,
2879 &feature_v7clrex,
2880 &feature_db,
2881 &feature_thumb2,
2882 &feature_mclass,
2883 &feature_thumbMode,
2884 &feature_noarm,
2885 &feature_v4t,
2886 &feature_dsp,
2887 &feature_hwdiv,
2888 &feature_armv7eM,
2889 &feature_fp16,
2890 &feature_fpregs,
2891 &feature_fpArmv8d16,
2892 },
2893};
2894
2895pub const cpu_cortexR4 = Cpu{
2896 .name = "cortex-r4",
2897 .llvm_name = "cortex-r4",
2898 .subfeatures = &[_]*const Feature {
2899 &feature_perfmon,
2900 &feature_v7clrex,
2901 &feature_db,
2902 &feature_thumb2,
2903 &feature_v4t,
2904 &feature_dsp,
2905 &feature_hwdiv,
2906 &feature_rclass,
2907 &feature_armv7R,
2908 &feature_avoidPartialCpsr,
2909 &feature_retAddrStack,
2910 &feature_r4,
2911 },
2912};
2913
2914pub const cpu_cortexR4f = Cpu{
2915 .name = "cortex-r4f",
2916 .llvm_name = "cortex-r4f",
2917 .subfeatures = &[_]*const Feature {
2918 &feature_perfmon,
2919 &feature_v7clrex,
2920 &feature_db,
2921 &feature_thumb2,
2922 &feature_v4t,
2923 &feature_dsp,
2924 &feature_hwdiv,
2925 &feature_rclass,
2926 &feature_armv7R,
2927 &feature_avoidPartialCpsr,
2928 &feature_retAddrStack,
2929 &feature_slowfpvmlx,
2930 &feature_slowFpBrcc,
2931 &feature_fpregs,
2932 &feature_vfp3d16,
2933 &feature_r4,
2934 },
2935};
2936
2937pub const cpu_cortexR5 = Cpu{
2938 .name = "cortex-r5",
2939 .llvm_name = "cortex-r5",
2940 .subfeatures = &[_]*const Feature {
2941 &feature_perfmon,
2942 &feature_v7clrex,
2943 &feature_db,
2944 &feature_thumb2,
2945 &feature_v4t,
2946 &feature_dsp,
2947 &feature_hwdiv,
2948 &feature_rclass,
2949 &feature_armv7R,
2950 &feature_avoidPartialCpsr,
2951 &feature_hwdivArm,
2952 &feature_retAddrStack,
2953 &feature_slowfpvmlx,
2954 &feature_slowFpBrcc,
2955 &feature_fpregs,
2956 &feature_vfp3d16,
2957 &feature_r5,
2958 },
2959};
2960
2961pub const cpu_cortexR52 = Cpu{
2962 .name = "cortex-r52",
2963 .llvm_name = "cortex-r52",
2964 .subfeatures = &[_]*const Feature {
2965 &feature_mp,
2966 &feature_acquireRelease,
2967 &feature_perfmon,
2968 &feature_hwdiv,
2969 &feature_v7clrex,
2970 &feature_db,
2971 &feature_thumb2,
2972 &feature_fp16,
2973 &feature_v4t,
2974 &feature_d32,
2975 &feature_dfb,
2976 &feature_hwdivArm,
2977 &feature_crc,
2978 &feature_dsp,
2979 &feature_fpregs,
2980 &feature_rclass,
2981 &feature_armv8R,
2982 &feature_fpao,
2983 &feature_useAa,
2984 &feature_useMisched,
2985 &feature_r52,
2986 },
2987};
2988
2989pub const cpu_cortexR7 = Cpu{
2990 .name = "cortex-r7",
2991 .llvm_name = "cortex-r7",
2992 .subfeatures = &[_]*const Feature {
2993 &feature_perfmon,
2994 &feature_v7clrex,
2995 &feature_db,
2996 &feature_thumb2,
2997 &feature_v4t,
2998 &feature_dsp,
2999 &feature_hwdiv,
3000 &feature_rclass,
3001 &feature_armv7R,
3002 &feature_avoidPartialCpsr,
3003 &feature_fp16,
3004 &feature_hwdivArm,
3005 &feature_retAddrStack,
3006 &feature_slowfpvmlx,
3007 &feature_mp,
3008 &feature_slowFpBrcc,
3009 &feature_fpregs,
3010 &feature_vfp3d16,
3011 &feature_r7,
3012 },
3013};
3014
3015pub const cpu_cortexR8 = Cpu{
3016 .name = "cortex-r8",
3017 .llvm_name = "cortex-r8",
3018 .subfeatures = &[_]*const Feature {
3019 &feature_perfmon,
3020 &feature_v7clrex,
3021 &feature_db,
3022 &feature_thumb2,
3023 &feature_v4t,
3024 &feature_dsp,
3025 &feature_hwdiv,
3026 &feature_rclass,
3027 &feature_armv7R,
3028 &feature_avoidPartialCpsr,
3029 &feature_fp16,
3030 &feature_hwdivArm,
3031 &feature_retAddrStack,
3032 &feature_slowfpvmlx,
3033 &feature_mp,
3034 &feature_slowFpBrcc,
3035 &feature_fpregs,
3036 &feature_vfp3d16,
3037 },
3038};
3039
3040pub const cpu_cyclone = Cpu{
3041 .name = "cyclone",
3042 .llvm_name = "cyclone",
3043 .subfeatures = &[_]*const Feature {
3044 &feature_mp,
3045 &feature_acquireRelease,
3046 &feature_perfmon,
3047 &feature_hwdiv,
3048 &feature_trustzone,
3049 &feature_v7clrex,
3050 &feature_db,
3051 &feature_thumb2,
3052 &feature_fp16,
3053 &feature_v4t,
3054 &feature_d32,
3055 &feature_aclass,
3056 &feature_hwdivArm,
3057 &feature_crc,
3058 &feature_dsp,
3059 &feature_fpregs,
3060 &feature_armv8A,
3061 &feature_avoidMovsShop,
3062 &feature_avoidPartialCpsr,
3063 &feature_crypto,
3064 &feature_retAddrStack,
3065 &feature_slowfpvmlx,
3066 &feature_neonfp,
3067 &feature_disablePostraScheduler,
3068 &feature_useMisched,
3069 &feature_vfp4,
3070 &feature_zcz,
3071 &feature_swift,
3072 },
3073};
3074
3075pub const cpu_ep9312 = Cpu{
3076 .name = "ep9312",
3077 .llvm_name = "ep9312",
3078 .subfeatures = &[_]*const Feature {
3079 &feature_v4t,
3080 &feature_armv4t,
3081 },
3082};
3083
3084pub const cpu_exynosM1 = Cpu{
3085 .name = "exynos-m1",
3086 .llvm_name = "exynos-m1",
3087 .subfeatures = &[_]*const Feature {
3088 &feature_mp,
3089 &feature_acquireRelease,
3090 &feature_perfmon,
3091 &feature_hwdiv,
3092 &feature_trustzone,
3093 &feature_v7clrex,
3094 &feature_db,
3095 &feature_thumb2,
3096 &feature_fp16,
3097 &feature_v4t,
3098 &feature_d32,
3099 &feature_aclass,
3100 &feature_hwdivArm,
3101 &feature_crc,
3102 &feature_dsp,
3103 &feature_fpregs,
3104 &feature_armv8A,
3105 &feature_slowFpBrcc,
3106 &feature_slowfpvmlx,
3107 &feature_slowVdup32,
3108 &feature_wideStrideVfp,
3109 &feature_fuseAes,
3110 &feature_slowVgetlni32,
3111 &feature_zcz,
3112 &feature_profUnpr,
3113 &feature_retAddrStack,
3114 &feature_expandFpMlx,
3115 &feature_useAa,
3116 &feature_dontWidenVmovs,
3117 &feature_fuseLiterals,
3118 &feature_exynos,
3119 },
3120};
3121
3122pub const cpu_exynosM2 = Cpu{
3123 .name = "exynos-m2",
3124 .llvm_name = "exynos-m2",
3125 .subfeatures = &[_]*const Feature {
3126 &feature_mp,
3127 &feature_acquireRelease,
3128 &feature_perfmon,
3129 &feature_hwdiv,
3130 &feature_trustzone,
3131 &feature_v7clrex,
3132 &feature_db,
3133 &feature_thumb2,
3134 &feature_fp16,
3135 &feature_v4t,
3136 &feature_d32,
3137 &feature_aclass,
3138 &feature_hwdivArm,
3139 &feature_crc,
3140 &feature_dsp,
3141 &feature_fpregs,
3142 &feature_armv8A,
3143 &feature_slowFpBrcc,
3144 &feature_slowfpvmlx,
3145 &feature_slowVdup32,
3146 &feature_wideStrideVfp,
3147 &feature_fuseAes,
3148 &feature_slowVgetlni32,
3149 &feature_zcz,
3150 &feature_profUnpr,
3151 &feature_retAddrStack,
3152 &feature_expandFpMlx,
3153 &feature_useAa,
3154 &feature_dontWidenVmovs,
3155 &feature_fuseLiterals,
3156 &feature_exynos,
3157 },
3158};
3159
3160pub const cpu_exynosM3 = Cpu{
3161 .name = "exynos-m3",
3162 .llvm_name = "exynos-m3",
3163 .subfeatures = &[_]*const Feature {
3164 &feature_mp,
3165 &feature_acquireRelease,
3166 &feature_perfmon,
3167 &feature_hwdiv,
3168 &feature_trustzone,
3169 &feature_v7clrex,
3170 &feature_db,
3171 &feature_thumb2,
3172 &feature_fp16,
3173 &feature_v4t,
3174 &feature_d32,
3175 &feature_aclass,
3176 &feature_hwdivArm,
3177 &feature_crc,
3178 &feature_dsp,
3179 &feature_fpregs,
3180 &feature_armv8A,
3181 &feature_slowFpBrcc,
3182 &feature_slowfpvmlx,
3183 &feature_slowVdup32,
3184 &feature_wideStrideVfp,
3185 &feature_fuseAes,
3186 &feature_slowVgetlni32,
3187 &feature_zcz,
3188 &feature_profUnpr,
3189 &feature_retAddrStack,
3190 &feature_expandFpMlx,
3191 &feature_useAa,
3192 &feature_dontWidenVmovs,
3193 &feature_fuseLiterals,
3194 &feature_exynos,
3195 },
3196};
3197
3198pub const cpu_exynosM4 = Cpu{
3199 .name = "exynos-m4",
3200 .llvm_name = "exynos-m4",
3201 .subfeatures = &[_]*const Feature {
3202 &feature_mp,
3203 &feature_acquireRelease,
3204 &feature_perfmon,
3205 &feature_hwdiv,
3206 &feature_trustzone,
3207 &feature_v7clrex,
3208 &feature_db,
3209 &feature_thumb2,
3210 &feature_ras,
3211 &feature_fp16,
3212 &feature_v4t,
3213 &feature_d32,
3214 &feature_aclass,
3215 &feature_hwdivArm,
3216 &feature_crc,
3217 &feature_dsp,
3218 &feature_fpregs,
3219 &feature_armv82A,
3220 &feature_dotprod,
3221 &feature_fullfp16,
3222 &feature_slowFpBrcc,
3223 &feature_slowfpvmlx,
3224 &feature_slowVdup32,
3225 &feature_wideStrideVfp,
3226 &feature_fuseAes,
3227 &feature_slowVgetlni32,
3228 &feature_zcz,
3229 &feature_profUnpr,
3230 &feature_retAddrStack,
3231 &feature_expandFpMlx,
3232 &feature_useAa,
3233 &feature_dontWidenVmovs,
3234 &feature_fuseLiterals,
3235 &feature_exynos,
3236 },
3237};
3238
3239pub const cpu_exynosM5 = Cpu{
3240 .name = "exynos-m5",
3241 .llvm_name = "exynos-m5",
3242 .subfeatures = &[_]*const Feature {
3243 &feature_mp,
3244 &feature_acquireRelease,
3245 &feature_perfmon,
3246 &feature_hwdiv,
3247 &feature_trustzone,
3248 &feature_v7clrex,
3249 &feature_db,
3250 &feature_thumb2,
3251 &feature_ras,
3252 &feature_fp16,
3253 &feature_v4t,
3254 &feature_d32,
3255 &feature_aclass,
3256 &feature_hwdivArm,
3257 &feature_crc,
3258 &feature_dsp,
3259 &feature_fpregs,
3260 &feature_armv82A,
3261 &feature_dotprod,
3262 &feature_fullfp16,
3263 &feature_slowFpBrcc,
3264 &feature_slowfpvmlx,
3265 &feature_slowVdup32,
3266 &feature_wideStrideVfp,
3267 &feature_fuseAes,
3268 &feature_slowVgetlni32,
3269 &feature_zcz,
3270 &feature_profUnpr,
3271 &feature_retAddrStack,
3272 &feature_expandFpMlx,
3273 &feature_useAa,
3274 &feature_dontWidenVmovs,
3275 &feature_fuseLiterals,
3276 &feature_exynos,
3277 },
3278};
3279
3280pub const cpu_generic = Cpu{
3281 .name = "generic",
3282 .llvm_name = "generic",
3283 .subfeatures = &[_]*const Feature {
3284 },
3285};
3286
3287pub const cpu_iwmmxt = Cpu{
3288 .name = "iwmmxt",
3289 .llvm_name = "iwmmxt",
3290 .subfeatures = &[_]*const Feature {
3291 &feature_v4t,
3292 &feature_armv5te,
3293 },
3294};
3295
3296pub const cpu_krait = Cpu{
3297 .name = "krait",
3298 .llvm_name = "krait",
3299 .subfeatures = &[_]*const Feature {
3300 &feature_perfmon,
3301 &feature_v7clrex,
3302 &feature_db,
3303 &feature_thumb2,
3304 &feature_v4t,
3305 &feature_d32,
3306 &feature_aclass,
3307 &feature_dsp,
3308 &feature_fpregs,
3309 &feature_armv7A,
3310 &feature_avoidPartialCpsr,
3311 &feature_vldnAlign,
3312 &feature_fp16,
3313 &feature_hwdivArm,
3314 &feature_hwdiv,
3315 &feature_retAddrStack,
3316 &feature_muxedUnits,
3317 &feature_vfp4,
3318 &feature_vmlxForwarding,
3319 &feature_krait,
3320 },
3321};
3322
3323pub const cpu_kryo = Cpu{
3324 .name = "kryo",
3325 .llvm_name = "kryo",
3326 .subfeatures = &[_]*const Feature {
3327 &feature_mp,
3328 &feature_acquireRelease,
3329 &feature_perfmon,
3330 &feature_hwdiv,
3331 &feature_trustzone,
3332 &feature_v7clrex,
3333 &feature_db,
3334 &feature_thumb2,
3335 &feature_fp16,
3336 &feature_v4t,
3337 &feature_d32,
3338 &feature_aclass,
3339 &feature_hwdivArm,
3340 &feature_crc,
3341 &feature_dsp,
3342 &feature_fpregs,
3343 &feature_armv8A,
3344 &feature_crypto,
3345 &feature_kryo,
3346 },
3347};
3348
3349pub const cpu_mpcore = Cpu{
3350 .name = "mpcore",
3351 .llvm_name = "mpcore",
3352 .subfeatures = &[_]*const Feature {
3353 &feature_v4t,
3354 &feature_armv6k,
3355 &feature_slowfpvmlx,
3356 &feature_fpregs,
3357 &feature_vfp2,
3358 },
3359};
3360
3361pub const cpu_mpcorenovfp = Cpu{
3362 .name = "mpcorenovfp",
3363 .llvm_name = "mpcorenovfp",
3364 .subfeatures = &[_]*const Feature {
3365 &feature_v4t,
3366 &feature_armv6k,
3367 },
3368};
3369
3370pub const cpu_neoverseN1 = Cpu{
3371 .name = "neoverse-n1",
3372 .llvm_name = "neoverse-n1",
3373 .subfeatures = &[_]*const Feature {
3374 &feature_mp,
3375 &feature_acquireRelease,
3376 &feature_perfmon,
3377 &feature_hwdiv,
3378 &feature_trustzone,
3379 &feature_v7clrex,
3380 &feature_db,
3381 &feature_thumb2,
3382 &feature_ras,
3383 &feature_fp16,
3384 &feature_v4t,
3385 &feature_d32,
3386 &feature_aclass,
3387 &feature_hwdivArm,
3388 &feature_crc,
3389 &feature_dsp,
3390 &feature_fpregs,
3391 &feature_armv82A,
3392 &feature_crypto,
3393 &feature_dotprod,
3394 },
3395};
3396
3397pub const cpu_sc000 = Cpu{
3398 .name = "sc000",
3399 .llvm_name = "sc000",
3400 .subfeatures = &[_]*const Feature {
3401 &feature_db,
3402 &feature_thumbMode,
3403 &feature_mclass,
3404 &feature_noarm,
3405 &feature_v4t,
3406 &feature_strictAlign,
3407 &feature_armv6M,
3408 },
3409};
3410
3411pub const cpu_sc300 = Cpu{
3412 .name = "sc300",
3413 .llvm_name = "sc300",
3414 .subfeatures = &[_]*const Feature {
3415 &feature_v7clrex,
3416 &feature_db,
3417 &feature_thumb2,
3418 &feature_mclass,
3419 &feature_thumbMode,
3420 &feature_noarm,
3421 &feature_v4t,
3422 &feature_perfmon,
3423 &feature_hwdiv,
3424 &feature_armv7M,
3425 &feature_noBranchPredictor,
3426 &feature_useAa,
3427 &feature_useMisched,
3428 &feature_m3,
3429 },
3430};
3431
3432pub const cpu_strongarm = Cpu{
3433 .name = "strongarm",
3434 .llvm_name = "strongarm",
3435 .subfeatures = &[_]*const Feature {
3436 &feature_armv4,
3437 },
3438};
3439
3440pub const cpu_strongarm110 = Cpu{
3441 .name = "strongarm110",
3442 .llvm_name = "strongarm110",
3443 .subfeatures = &[_]*const Feature {
3444 &feature_armv4,
3445 },
3446};
3447
3448pub const cpu_strongarm1100 = Cpu{
3449 .name = "strongarm1100",
3450 .llvm_name = "strongarm1100",
3451 .subfeatures = &[_]*const Feature {
3452 &feature_armv4,
3453 },
3454};
3455
3456pub const cpu_strongarm1110 = Cpu{
3457 .name = "strongarm1110",
3458 .llvm_name = "strongarm1110",
3459 .subfeatures = &[_]*const Feature {
3460 &feature_armv4,
3461 },
3462};
3463
3464pub const cpu_swift = Cpu{
3465 .name = "swift",
3466 .llvm_name = "swift",
3467 .subfeatures = &[_]*const Feature {
3468 &feature_perfmon,
3469 &feature_v7clrex,
3470 &feature_db,
3471 &feature_thumb2,
3472 &feature_v4t,
3473 &feature_d32,
3474 &feature_aclass,
3475 &feature_dsp,
3476 &feature_fpregs,
3477 &feature_armv7A,
3478 &feature_avoidMovsShop,
3479 &feature_avoidPartialCpsr,
3480 &feature_hwdivArm,
3481 &feature_hwdiv,
3482 &feature_retAddrStack,
3483 &feature_slowfpvmlx,
3484 &feature_vmlxHazards,
3485 &feature_mp,
3486 &feature_neonfp,
3487 &feature_disablePostraScheduler,
3488 &feature_preferIshst,
3489 &feature_profUnpr,
3490 &feature_slowLoadDSubreg,
3491 &feature_slowOddReg,
3492 &feature_slowVdup32,
3493 &feature_slowVgetlni32,
3494 &feature_useMisched,
3495 &feature_wideStrideVfp,
3496 &feature_fp16,
3497 &feature_vfp4,
3498 &feature_swift,
3499 },
3500};
3501
3502pub const cpu_xscale = Cpu{
3503 .name = "xscale",
3504 .llvm_name = "xscale",
3505 .subfeatures = &[_]*const Feature {
3506 &feature_v4t,
3507 &feature_armv5te,
3508 },
3509};
3510
3511pub const cpus = &[_]*const Cpu {
3512 &cpu_arm1020e,
3513 &cpu_arm1020t,
3514 &cpu_arm1022e,
3515 &cpu_arm10e,
3516 &cpu_arm10tdmi,
3517 &cpu_arm1136jS,
3518 &cpu_arm1136jfS,
3519 &cpu_arm1156t2S,
3520 &cpu_arm1156t2fS,
3521 &cpu_arm1176jS,
3522 &cpu_arm1176jzS,
3523 &cpu_arm1176jzfS,
3524 &cpu_arm710t,
3525 &cpu_arm720t,
3526 &cpu_arm7tdmi,
3527 &cpu_arm7tdmiS,
3528 &cpu_arm8,
3529 &cpu_arm810,
3530 &cpu_arm9,
3531 &cpu_arm920,
3532 &cpu_arm920t,
3533 &cpu_arm922t,
3534 &cpu_arm926ejS,
3535 &cpu_arm940t,
3536 &cpu_arm946eS,
3537 &cpu_arm966eS,
3538 &cpu_arm968eS,
3539 &cpu_arm9e,
3540 &cpu_arm9tdmi,
3541 &cpu_cortexA12,
3542 &cpu_cortexA15,
3543 &cpu_cortexA17,
3544 &cpu_cortexA32,
3545 &cpu_cortexA35,
3546 &cpu_cortexA5,
3547 &cpu_cortexA53,
3548 &cpu_cortexA55,
3549 &cpu_cortexA57,
3550 &cpu_cortexA7,
3551 &cpu_cortexA72,
3552 &cpu_cortexA73,
3553 &cpu_cortexA75,
3554 &cpu_cortexA76,
3555 &cpu_cortexA76ae,
3556 &cpu_cortexA8,
3557 &cpu_cortexA9,
3558 &cpu_cortexM0,
3559 &cpu_cortexM0plus,
3560 &cpu_cortexM1,
3561 &cpu_cortexM23,
3562 &cpu_cortexM3,
3563 &cpu_cortexM33,
3564 &cpu_cortexM35p,
3565 &cpu_cortexM4,
3566 &cpu_cortexM7,
3567 &cpu_cortexR4,
3568 &cpu_cortexR4f,
3569 &cpu_cortexR5,
3570 &cpu_cortexR52,
3571 &cpu_cortexR7,
3572 &cpu_cortexR8,
3573 &cpu_cyclone,
3574 &cpu_ep9312,
3575 &cpu_exynosM1,
3576 &cpu_exynosM2,
3577 &cpu_exynosM3,
3578 &cpu_exynosM4,
3579 &cpu_exynosM5,
3580 &cpu_generic,
3581 &cpu_iwmmxt,
3582 &cpu_krait,
3583 &cpu_kryo,
3584 &cpu_mpcore,
3585 &cpu_mpcorenovfp,
3586 &cpu_neoverseN1,
3587 &cpu_sc000,
3588 &cpu_sc300,
3589 &cpu_strongarm,
3590 &cpu_strongarm110,
3591 &cpu_strongarm1100,
3592 &cpu_strongarm1110,
3593 &cpu_swift,
3594 &cpu_xscale,
3595};
lib/std/target/avr.zig created+5578
......@@ -0,0 +1,5578 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_avr0 = Feature{
5 .name = "avr0",
6 .description = "The device is a part of the avr0 family",
7 .llvm_name = "avr0",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_avr1 = Feature{
13 .name = "avr1",
14 .description = "The device is a part of the avr1 family",
15 .llvm_name = "avr1",
16 .subfeatures = &[_]*const Feature {
17 &feature_avr0,
18 &feature_lpm,
19 },
20};
21
22pub const feature_avr2 = Feature{
23 .name = "avr2",
24 .description = "The device is a part of the avr2 family",
25 .llvm_name = "avr2",
26 .subfeatures = &[_]*const Feature {
27 &feature_ijmpcall,
28 &feature_sram,
29 &feature_avr0,
30 &feature_lpm,
31 &feature_addsubiw,
32 },
33};
34
35pub const feature_avr3 = Feature{
36 .name = "avr3",
37 .description = "The device is a part of the avr3 family",
38 .llvm_name = "avr3",
39 .subfeatures = &[_]*const Feature {
40 &feature_ijmpcall,
41 &feature_jmpcall,
42 &feature_sram,
43 &feature_avr0,
44 &feature_lpm,
45 &feature_addsubiw,
46 },
47};
48
49pub const feature_avr4 = Feature{
50 .name = "avr4",
51 .description = "The device is a part of the avr4 family",
52 .llvm_name = "avr4",
53 .subfeatures = &[_]*const Feature {
54 &feature_lpmx,
55 &feature_ijmpcall,
56 &feature_movw,
57 &feature_sram,
58 &feature_mul,
59 &feature_avr0,
60 &feature_lpm,
61 &feature_break,
62 &feature_spm,
63 &feature_addsubiw,
64 },
65};
66
67pub const feature_avr5 = Feature{
68 .name = "avr5",
69 .description = "The device is a part of the avr5 family",
70 .llvm_name = "avr5",
71 .subfeatures = &[_]*const Feature {
72 &feature_lpmx,
73 &feature_jmpcall,
74 &feature_ijmpcall,
75 &feature_movw,
76 &feature_sram,
77 &feature_mul,
78 &feature_avr0,
79 &feature_lpm,
80 &feature_break,
81 &feature_spm,
82 &feature_addsubiw,
83 },
84};
85
86pub const feature_avr6 = Feature{
87 .name = "avr6",
88 .description = "The device is a part of the avr6 family",
89 .llvm_name = "avr6",
90 .subfeatures = &[_]*const Feature {
91 &feature_lpmx,
92 &feature_jmpcall,
93 &feature_ijmpcall,
94 &feature_movw,
95 &feature_sram,
96 &feature_mul,
97 &feature_avr0,
98 &feature_lpm,
99 &feature_break,
100 &feature_spm,
101 &feature_elpmx,
102 &feature_elpm,
103 &feature_addsubiw,
104 },
105};
106
107pub const feature_avr25 = Feature{
108 .name = "avr25",
109 .description = "The device is a part of the avr25 family",
110 .llvm_name = "avr25",
111 .subfeatures = &[_]*const Feature {
112 &feature_lpmx,
113 &feature_ijmpcall,
114 &feature_movw,
115 &feature_sram,
116 &feature_avr0,
117 &feature_lpm,
118 &feature_break,
119 &feature_spm,
120 &feature_addsubiw,
121 },
122};
123
124pub const feature_avr31 = Feature{
125 .name = "avr31",
126 .description = "The device is a part of the avr31 family",
127 .llvm_name = "avr31",
128 .subfeatures = &[_]*const Feature {
129 &feature_jmpcall,
130 &feature_ijmpcall,
131 &feature_sram,
132 &feature_avr0,
133 &feature_lpm,
134 &feature_elpm,
135 &feature_addsubiw,
136 },
137};
138
139pub const feature_avr35 = Feature{
140 .name = "avr35",
141 .description = "The device is a part of the avr35 family",
142 .llvm_name = "avr35",
143 .subfeatures = &[_]*const Feature {
144 &feature_lpmx,
145 &feature_jmpcall,
146 &feature_ijmpcall,
147 &feature_movw,
148 &feature_sram,
149 &feature_avr0,
150 &feature_lpm,
151 &feature_break,
152 &feature_spm,
153 &feature_addsubiw,
154 },
155};
156
157pub const feature_avr51 = Feature{
158 .name = "avr51",
159 .description = "The device is a part of the avr51 family",
160 .llvm_name = "avr51",
161 .subfeatures = &[_]*const Feature {
162 &feature_lpmx,
163 &feature_ijmpcall,
164 &feature_jmpcall,
165 &feature_movw,
166 &feature_sram,
167 &feature_mul,
168 &feature_avr0,
169 &feature_lpm,
170 &feature_break,
171 &feature_spm,
172 &feature_elpmx,
173 &feature_elpm,
174 &feature_addsubiw,
175 },
176};
177
178pub const feature_avrtiny = Feature{
179 .name = "avrtiny",
180 .description = "The device is a part of the avrtiny family",
181 .llvm_name = "avrtiny",
182 .subfeatures = &[_]*const Feature {
183 &feature_tinyencoding,
184 &feature_sram,
185 &feature_break,
186 &feature_avr0,
187 },
188};
189
190pub const feature_xmega = Feature{
191 .name = "xmega",
192 .description = "The device is a part of the xmega family",
193 .llvm_name = "xmega",
194 .subfeatures = &[_]*const Feature {
195 &feature_lpmx,
196 &feature_jmpcall,
197 &feature_ijmpcall,
198 &feature_movw,
199 &feature_sram,
200 &feature_mul,
201 &feature_avr0,
202 &feature_spmx,
203 &feature_lpm,
204 &feature_eijmpcall,
205 &feature_break,
206 &feature_spm,
207 &feature_elpmx,
208 &feature_elpm,
209 &feature_addsubiw,
210 &feature_des,
211 },
212};
213
214pub const feature_xmegau = Feature{
215 .name = "xmegau",
216 .description = "The device is a part of the xmegau family",
217 .llvm_name = "xmegau",
218 .subfeatures = &[_]*const Feature {
219 &feature_lpmx,
220 &feature_ijmpcall,
221 &feature_jmpcall,
222 &feature_movw,
223 &feature_sram,
224 &feature_mul,
225 &feature_avr0,
226 &feature_spmx,
227 &feature_lpm,
228 &feature_rmw,
229 &feature_eijmpcall,
230 &feature_break,
231 &feature_spm,
232 &feature_elpmx,
233 &feature_elpm,
234 &feature_addsubiw,
235 &feature_des,
236 },
237};
238
239pub const feature_addsubiw = Feature{
240 .name = "addsubiw",
241 .description = "Enable 16-bit register-immediate addition and subtraction instructions",
242 .llvm_name = "addsubiw",
243 .subfeatures = &[_]*const Feature {
244 },
245};
246
247pub const feature_break = Feature{
248 .name = "break",
249 .description = "The device supports the `BREAK` debugging instruction",
250 .llvm_name = "break",
251 .subfeatures = &[_]*const Feature {
252 },
253};
254
255pub const feature_des = Feature{
256 .name = "des",
257 .description = "The device supports the `DES k` encryption instruction",
258 .llvm_name = "des",
259 .subfeatures = &[_]*const Feature {
260 },
261};
262
263pub const feature_eijmpcall = Feature{
264 .name = "eijmpcall",
265 .description = "The device supports the `EIJMP`/`EICALL` instructions",
266 .llvm_name = "eijmpcall",
267 .subfeatures = &[_]*const Feature {
268 },
269};
270
271pub const feature_elpm = Feature{
272 .name = "elpm",
273 .description = "The device supports the ELPM instruction",
274 .llvm_name = "elpm",
275 .subfeatures = &[_]*const Feature {
276 },
277};
278
279pub const feature_elpmx = Feature{
280 .name = "elpmx",
281 .description = "The device supports the `ELPM Rd, Z[+]` instructions",
282 .llvm_name = "elpmx",
283 .subfeatures = &[_]*const Feature {
284 },
285};
286
287pub const feature_ijmpcall = Feature{
288 .name = "ijmpcall",
289 .description = "The device supports `IJMP`/`ICALL`instructions",
290 .llvm_name = "ijmpcall",
291 .subfeatures = &[_]*const Feature {
292 },
293};
294
295pub const feature_jmpcall = Feature{
296 .name = "jmpcall",
297 .description = "The device supports the `JMP` and `CALL` instructions",
298 .llvm_name = "jmpcall",
299 .subfeatures = &[_]*const Feature {
300 },
301};
302
303pub const feature_lpm = Feature{
304 .name = "lpm",
305 .description = "The device supports the `LPM` instruction",
306 .llvm_name = "lpm",
307 .subfeatures = &[_]*const Feature {
308 },
309};
310
311pub const feature_lpmx = Feature{
312 .name = "lpmx",
313 .description = "The device supports the `LPM Rd, Z[+]` instruction",
314 .llvm_name = "lpmx",
315 .subfeatures = &[_]*const Feature {
316 },
317};
318
319pub const feature_movw = Feature{
320 .name = "movw",
321 .description = "The device supports the 16-bit MOVW instruction",
322 .llvm_name = "movw",
323 .subfeatures = &[_]*const Feature {
324 },
325};
326
327pub const feature_mul = Feature{
328 .name = "mul",
329 .description = "The device supports the multiplication instructions",
330 .llvm_name = "mul",
331 .subfeatures = &[_]*const Feature {
332 },
333};
334
335pub const feature_rmw = Feature{
336 .name = "rmw",
337 .description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT",
338 .llvm_name = "rmw",
339 .subfeatures = &[_]*const Feature {
340 },
341};
342
343pub const feature_spm = Feature{
344 .name = "spm",
345 .description = "The device supports the `SPM` instruction",
346 .llvm_name = "spm",
347 .subfeatures = &[_]*const Feature {
348 },
349};
350
351pub const feature_spmx = Feature{
352 .name = "spmx",
353 .description = "The device supports the `SPM Z+` instruction",
354 .llvm_name = "spmx",
355 .subfeatures = &[_]*const Feature {
356 },
357};
358
359pub const feature_sram = Feature{
360 .name = "sram",
361 .description = "The device has random access memory",
362 .llvm_name = "sram",
363 .subfeatures = &[_]*const Feature {
364 },
365};
366
367pub const feature_special = Feature{
368 .name = "special",
369 .description = "Enable use of the entire instruction set - used for debugging",
370 .llvm_name = "special",
371 .subfeatures = &[_]*const Feature {
372 &feature_lpmx,
373 &feature_ijmpcall,
374 &feature_jmpcall,
375 &feature_movw,
376 &feature_sram,
377 &feature_mul,
378 &feature_rmw,
379 &feature_spmx,
380 &feature_lpm,
381 &feature_eijmpcall,
382 &feature_break,
383 &feature_spm,
384 &feature_elpmx,
385 &feature_elpm,
386 &feature_addsubiw,
387 &feature_des,
388 },
389};
390
391pub const feature_smallstack = Feature{
392 .name = "smallstack",
393 .description = "The device has an 8-bit stack pointer",
394 .llvm_name = "smallstack",
395 .subfeatures = &[_]*const Feature {
396 },
397};
398
399pub const feature_tinyencoding = Feature{
400 .name = "tinyencoding",
401 .description = "The device has Tiny core specific instruction encodings",
402 .llvm_name = "tinyencoding",
403 .subfeatures = &[_]*const Feature {
404 },
405};
406
407pub const features = &[_]*const Feature {
408 &feature_avr0,
409 &feature_avr1,
410 &feature_avr2,
411 &feature_avr3,
412 &feature_avr4,
413 &feature_avr5,
414 &feature_avr6,
415 &feature_avr25,
416 &feature_avr31,
417 &feature_avr35,
418 &feature_avr51,
419 &feature_avrtiny,
420 &feature_xmega,
421 &feature_xmegau,
422 &feature_addsubiw,
423 &feature_break,
424 &feature_des,
425 &feature_eijmpcall,
426 &feature_elpm,
427 &feature_elpmx,
428 &feature_ijmpcall,
429 &feature_jmpcall,
430 &feature_lpm,
431 &feature_lpmx,
432 &feature_movw,
433 &feature_mul,
434 &feature_rmw,
435 &feature_spm,
436 &feature_spmx,
437 &feature_sram,
438 &feature_special,
439 &feature_smallstack,
440 &feature_tinyencoding,
441};
442
443pub const cpu_at43usb320 = Cpu{
444 .name = "at43usb320",
445 .llvm_name = "at43usb320",
446 .subfeatures = &[_]*const Feature {
447 &feature_jmpcall,
448 &feature_ijmpcall,
449 &feature_sram,
450 &feature_avr0,
451 &feature_lpm,
452 &feature_elpm,
453 &feature_addsubiw,
454 &feature_avr31,
455 },
456};
457
458pub const cpu_at43usb355 = Cpu{
459 .name = "at43usb355",
460 .llvm_name = "at43usb355",
461 .subfeatures = &[_]*const Feature {
462 &feature_ijmpcall,
463 &feature_jmpcall,
464 &feature_sram,
465 &feature_avr0,
466 &feature_lpm,
467 &feature_addsubiw,
468 &feature_avr3,
469 },
470};
471
472pub const cpu_at76c711 = Cpu{
473 .name = "at76c711",
474 .llvm_name = "at76c711",
475 .subfeatures = &[_]*const Feature {
476 &feature_ijmpcall,
477 &feature_jmpcall,
478 &feature_sram,
479 &feature_avr0,
480 &feature_lpm,
481 &feature_addsubiw,
482 &feature_avr3,
483 },
484};
485
486pub const cpu_at86rf401 = Cpu{
487 .name = "at86rf401",
488 .llvm_name = "at86rf401",
489 .subfeatures = &[_]*const Feature {
490 &feature_ijmpcall,
491 &feature_sram,
492 &feature_avr0,
493 &feature_lpm,
494 &feature_addsubiw,
495 &feature_avr2,
496 &feature_lpmx,
497 &feature_movw,
498 },
499};
500
501pub const cpu_at90c8534 = Cpu{
502 .name = "at90c8534",
503 .llvm_name = "at90c8534",
504 .subfeatures = &[_]*const Feature {
505 &feature_ijmpcall,
506 &feature_sram,
507 &feature_avr0,
508 &feature_lpm,
509 &feature_addsubiw,
510 &feature_avr2,
511 },
512};
513
514pub const cpu_at90can128 = Cpu{
515 .name = "at90can128",
516 .llvm_name = "at90can128",
517 .subfeatures = &[_]*const Feature {
518 &feature_lpmx,
519 &feature_ijmpcall,
520 &feature_jmpcall,
521 &feature_movw,
522 &feature_sram,
523 &feature_mul,
524 &feature_avr0,
525 &feature_lpm,
526 &feature_break,
527 &feature_spm,
528 &feature_elpmx,
529 &feature_elpm,
530 &feature_addsubiw,
531 &feature_avr51,
532 },
533};
534
535pub const cpu_at90can32 = Cpu{
536 .name = "at90can32",
537 .llvm_name = "at90can32",
538 .subfeatures = &[_]*const Feature {
539 &feature_lpmx,
540 &feature_jmpcall,
541 &feature_ijmpcall,
542 &feature_movw,
543 &feature_sram,
544 &feature_mul,
545 &feature_avr0,
546 &feature_lpm,
547 &feature_break,
548 &feature_spm,
549 &feature_addsubiw,
550 &feature_avr5,
551 },
552};
553
554pub const cpu_at90can64 = Cpu{
555 .name = "at90can64",
556 .llvm_name = "at90can64",
557 .subfeatures = &[_]*const Feature {
558 &feature_lpmx,
559 &feature_jmpcall,
560 &feature_ijmpcall,
561 &feature_movw,
562 &feature_sram,
563 &feature_mul,
564 &feature_avr0,
565 &feature_lpm,
566 &feature_break,
567 &feature_spm,
568 &feature_addsubiw,
569 &feature_avr5,
570 },
571};
572
573pub const cpu_at90pwm1 = Cpu{
574 .name = "at90pwm1",
575 .llvm_name = "at90pwm1",
576 .subfeatures = &[_]*const Feature {
577 &feature_lpmx,
578 &feature_ijmpcall,
579 &feature_movw,
580 &feature_sram,
581 &feature_mul,
582 &feature_avr0,
583 &feature_lpm,
584 &feature_break,
585 &feature_spm,
586 &feature_addsubiw,
587 &feature_avr4,
588 },
589};
590
591pub const cpu_at90pwm161 = Cpu{
592 .name = "at90pwm161",
593 .llvm_name = "at90pwm161",
594 .subfeatures = &[_]*const Feature {
595 &feature_lpmx,
596 &feature_jmpcall,
597 &feature_ijmpcall,
598 &feature_movw,
599 &feature_sram,
600 &feature_mul,
601 &feature_avr0,
602 &feature_lpm,
603 &feature_break,
604 &feature_spm,
605 &feature_addsubiw,
606 &feature_avr5,
607 },
608};
609
610pub const cpu_at90pwm2 = Cpu{
611 .name = "at90pwm2",
612 .llvm_name = "at90pwm2",
613 .subfeatures = &[_]*const Feature {
614 &feature_lpmx,
615 &feature_ijmpcall,
616 &feature_movw,
617 &feature_sram,
618 &feature_mul,
619 &feature_avr0,
620 &feature_lpm,
621 &feature_break,
622 &feature_spm,
623 &feature_addsubiw,
624 &feature_avr4,
625 },
626};
627
628pub const cpu_at90pwm216 = Cpu{
629 .name = "at90pwm216",
630 .llvm_name = "at90pwm216",
631 .subfeatures = &[_]*const Feature {
632 &feature_lpmx,
633 &feature_jmpcall,
634 &feature_ijmpcall,
635 &feature_movw,
636 &feature_sram,
637 &feature_mul,
638 &feature_avr0,
639 &feature_lpm,
640 &feature_break,
641 &feature_spm,
642 &feature_addsubiw,
643 &feature_avr5,
644 },
645};
646
647pub const cpu_at90pwm2b = Cpu{
648 .name = "at90pwm2b",
649 .llvm_name = "at90pwm2b",
650 .subfeatures = &[_]*const Feature {
651 &feature_lpmx,
652 &feature_ijmpcall,
653 &feature_movw,
654 &feature_sram,
655 &feature_mul,
656 &feature_avr0,
657 &feature_lpm,
658 &feature_break,
659 &feature_spm,
660 &feature_addsubiw,
661 &feature_avr4,
662 },
663};
664
665pub const cpu_at90pwm3 = Cpu{
666 .name = "at90pwm3",
667 .llvm_name = "at90pwm3",
668 .subfeatures = &[_]*const Feature {
669 &feature_lpmx,
670 &feature_ijmpcall,
671 &feature_movw,
672 &feature_sram,
673 &feature_mul,
674 &feature_avr0,
675 &feature_lpm,
676 &feature_break,
677 &feature_spm,
678 &feature_addsubiw,
679 &feature_avr4,
680 },
681};
682
683pub const cpu_at90pwm316 = Cpu{
684 .name = "at90pwm316",
685 .llvm_name = "at90pwm316",
686 .subfeatures = &[_]*const Feature {
687 &feature_lpmx,
688 &feature_jmpcall,
689 &feature_ijmpcall,
690 &feature_movw,
691 &feature_sram,
692 &feature_mul,
693 &feature_avr0,
694 &feature_lpm,
695 &feature_break,
696 &feature_spm,
697 &feature_addsubiw,
698 &feature_avr5,
699 },
700};
701
702pub const cpu_at90pwm3b = Cpu{
703 .name = "at90pwm3b",
704 .llvm_name = "at90pwm3b",
705 .subfeatures = &[_]*const Feature {
706 &feature_lpmx,
707 &feature_ijmpcall,
708 &feature_movw,
709 &feature_sram,
710 &feature_mul,
711 &feature_avr0,
712 &feature_lpm,
713 &feature_break,
714 &feature_spm,
715 &feature_addsubiw,
716 &feature_avr4,
717 },
718};
719
720pub const cpu_at90pwm81 = Cpu{
721 .name = "at90pwm81",
722 .llvm_name = "at90pwm81",
723 .subfeatures = &[_]*const Feature {
724 &feature_lpmx,
725 &feature_ijmpcall,
726 &feature_movw,
727 &feature_sram,
728 &feature_mul,
729 &feature_avr0,
730 &feature_lpm,
731 &feature_break,
732 &feature_spm,
733 &feature_addsubiw,
734 &feature_avr4,
735 },
736};
737
738pub const cpu_at90s1200 = Cpu{
739 .name = "at90s1200",
740 .llvm_name = "at90s1200",
741 .subfeatures = &[_]*const Feature {
742 &feature_avr0,
743 },
744};
745
746pub const cpu_at90s2313 = Cpu{
747 .name = "at90s2313",
748 .llvm_name = "at90s2313",
749 .subfeatures = &[_]*const Feature {
750 &feature_ijmpcall,
751 &feature_sram,
752 &feature_avr0,
753 &feature_lpm,
754 &feature_addsubiw,
755 &feature_avr2,
756 },
757};
758
759pub const cpu_at90s2323 = Cpu{
760 .name = "at90s2323",
761 .llvm_name = "at90s2323",
762 .subfeatures = &[_]*const Feature {
763 &feature_ijmpcall,
764 &feature_sram,
765 &feature_avr0,
766 &feature_lpm,
767 &feature_addsubiw,
768 &feature_avr2,
769 },
770};
771
772pub const cpu_at90s2333 = Cpu{
773 .name = "at90s2333",
774 .llvm_name = "at90s2333",
775 .subfeatures = &[_]*const Feature {
776 &feature_ijmpcall,
777 &feature_sram,
778 &feature_avr0,
779 &feature_lpm,
780 &feature_addsubiw,
781 &feature_avr2,
782 },
783};
784
785pub const cpu_at90s2343 = Cpu{
786 .name = "at90s2343",
787 .llvm_name = "at90s2343",
788 .subfeatures = &[_]*const Feature {
789 &feature_ijmpcall,
790 &feature_sram,
791 &feature_avr0,
792 &feature_lpm,
793 &feature_addsubiw,
794 &feature_avr2,
795 },
796};
797
798pub const cpu_at90s4414 = Cpu{
799 .name = "at90s4414",
800 .llvm_name = "at90s4414",
801 .subfeatures = &[_]*const Feature {
802 &feature_ijmpcall,
803 &feature_sram,
804 &feature_avr0,
805 &feature_lpm,
806 &feature_addsubiw,
807 &feature_avr2,
808 },
809};
810
811pub const cpu_at90s4433 = Cpu{
812 .name = "at90s4433",
813 .llvm_name = "at90s4433",
814 .subfeatures = &[_]*const Feature {
815 &feature_ijmpcall,
816 &feature_sram,
817 &feature_avr0,
818 &feature_lpm,
819 &feature_addsubiw,
820 &feature_avr2,
821 },
822};
823
824pub const cpu_at90s4434 = Cpu{
825 .name = "at90s4434",
826 .llvm_name = "at90s4434",
827 .subfeatures = &[_]*const Feature {
828 &feature_ijmpcall,
829 &feature_sram,
830 &feature_avr0,
831 &feature_lpm,
832 &feature_addsubiw,
833 &feature_avr2,
834 },
835};
836
837pub const cpu_at90s8515 = Cpu{
838 .name = "at90s8515",
839 .llvm_name = "at90s8515",
840 .subfeatures = &[_]*const Feature {
841 &feature_ijmpcall,
842 &feature_sram,
843 &feature_avr0,
844 &feature_lpm,
845 &feature_addsubiw,
846 &feature_avr2,
847 },
848};
849
850pub const cpu_at90s8535 = Cpu{
851 .name = "at90s8535",
852 .llvm_name = "at90s8535",
853 .subfeatures = &[_]*const Feature {
854 &feature_ijmpcall,
855 &feature_sram,
856 &feature_avr0,
857 &feature_lpm,
858 &feature_addsubiw,
859 &feature_avr2,
860 },
861};
862
863pub const cpu_at90scr100 = Cpu{
864 .name = "at90scr100",
865 .llvm_name = "at90scr100",
866 .subfeatures = &[_]*const Feature {
867 &feature_lpmx,
868 &feature_jmpcall,
869 &feature_ijmpcall,
870 &feature_movw,
871 &feature_sram,
872 &feature_mul,
873 &feature_avr0,
874 &feature_lpm,
875 &feature_break,
876 &feature_spm,
877 &feature_addsubiw,
878 &feature_avr5,
879 },
880};
881
882pub const cpu_at90usb1286 = Cpu{
883 .name = "at90usb1286",
884 .llvm_name = "at90usb1286",
885 .subfeatures = &[_]*const Feature {
886 &feature_lpmx,
887 &feature_ijmpcall,
888 &feature_jmpcall,
889 &feature_movw,
890 &feature_sram,
891 &feature_mul,
892 &feature_avr0,
893 &feature_lpm,
894 &feature_break,
895 &feature_spm,
896 &feature_elpmx,
897 &feature_elpm,
898 &feature_addsubiw,
899 &feature_avr51,
900 },
901};
902
903pub const cpu_at90usb1287 = Cpu{
904 .name = "at90usb1287",
905 .llvm_name = "at90usb1287",
906 .subfeatures = &[_]*const Feature {
907 &feature_lpmx,
908 &feature_ijmpcall,
909 &feature_jmpcall,
910 &feature_movw,
911 &feature_sram,
912 &feature_mul,
913 &feature_avr0,
914 &feature_lpm,
915 &feature_break,
916 &feature_spm,
917 &feature_elpmx,
918 &feature_elpm,
919 &feature_addsubiw,
920 &feature_avr51,
921 },
922};
923
924pub const cpu_at90usb162 = Cpu{
925 .name = "at90usb162",
926 .llvm_name = "at90usb162",
927 .subfeatures = &[_]*const Feature {
928 &feature_lpmx,
929 &feature_jmpcall,
930 &feature_ijmpcall,
931 &feature_movw,
932 &feature_sram,
933 &feature_avr0,
934 &feature_lpm,
935 &feature_break,
936 &feature_spm,
937 &feature_addsubiw,
938 &feature_avr35,
939 },
940};
941
942pub const cpu_at90usb646 = Cpu{
943 .name = "at90usb646",
944 .llvm_name = "at90usb646",
945 .subfeatures = &[_]*const Feature {
946 &feature_lpmx,
947 &feature_jmpcall,
948 &feature_ijmpcall,
949 &feature_movw,
950 &feature_sram,
951 &feature_mul,
952 &feature_avr0,
953 &feature_lpm,
954 &feature_break,
955 &feature_spm,
956 &feature_addsubiw,
957 &feature_avr5,
958 },
959};
960
961pub const cpu_at90usb647 = Cpu{
962 .name = "at90usb647",
963 .llvm_name = "at90usb647",
964 .subfeatures = &[_]*const Feature {
965 &feature_lpmx,
966 &feature_jmpcall,
967 &feature_ijmpcall,
968 &feature_movw,
969 &feature_sram,
970 &feature_mul,
971 &feature_avr0,
972 &feature_lpm,
973 &feature_break,
974 &feature_spm,
975 &feature_addsubiw,
976 &feature_avr5,
977 },
978};
979
980pub const cpu_at90usb82 = Cpu{
981 .name = "at90usb82",
982 .llvm_name = "at90usb82",
983 .subfeatures = &[_]*const Feature {
984 &feature_lpmx,
985 &feature_jmpcall,
986 &feature_ijmpcall,
987 &feature_movw,
988 &feature_sram,
989 &feature_avr0,
990 &feature_lpm,
991 &feature_break,
992 &feature_spm,
993 &feature_addsubiw,
994 &feature_avr35,
995 },
996};
997
998pub const cpu_at94k = Cpu{
999 .name = "at94k",
1000 .llvm_name = "at94k",
1001 .subfeatures = &[_]*const Feature {
1002 &feature_ijmpcall,
1003 &feature_jmpcall,
1004 &feature_sram,
1005 &feature_avr0,
1006 &feature_lpm,
1007 &feature_addsubiw,
1008 &feature_avr3,
1009 &feature_lpmx,
1010 &feature_movw,
1011 &feature_mul,
1012 },
1013};
1014
1015pub const cpu_ata5272 = Cpu{
1016 .name = "ata5272",
1017 .llvm_name = "ata5272",
1018 .subfeatures = &[_]*const Feature {
1019 &feature_lpmx,
1020 &feature_ijmpcall,
1021 &feature_movw,
1022 &feature_sram,
1023 &feature_avr0,
1024 &feature_lpm,
1025 &feature_break,
1026 &feature_spm,
1027 &feature_addsubiw,
1028 &feature_avr25,
1029 },
1030};
1031
1032pub const cpu_ata5505 = Cpu{
1033 .name = "ata5505",
1034 .llvm_name = "ata5505",
1035 .subfeatures = &[_]*const Feature {
1036 &feature_lpmx,
1037 &feature_jmpcall,
1038 &feature_ijmpcall,
1039 &feature_movw,
1040 &feature_sram,
1041 &feature_avr0,
1042 &feature_lpm,
1043 &feature_break,
1044 &feature_spm,
1045 &feature_addsubiw,
1046 &feature_avr35,
1047 },
1048};
1049
1050pub const cpu_ata5790 = Cpu{
1051 .name = "ata5790",
1052 .llvm_name = "ata5790",
1053 .subfeatures = &[_]*const Feature {
1054 &feature_lpmx,
1055 &feature_jmpcall,
1056 &feature_ijmpcall,
1057 &feature_movw,
1058 &feature_sram,
1059 &feature_mul,
1060 &feature_avr0,
1061 &feature_lpm,
1062 &feature_break,
1063 &feature_spm,
1064 &feature_addsubiw,
1065 &feature_avr5,
1066 },
1067};
1068
1069pub const cpu_ata5795 = Cpu{
1070 .name = "ata5795",
1071 .llvm_name = "ata5795",
1072 .subfeatures = &[_]*const Feature {
1073 &feature_lpmx,
1074 &feature_jmpcall,
1075 &feature_ijmpcall,
1076 &feature_movw,
1077 &feature_sram,
1078 &feature_mul,
1079 &feature_avr0,
1080 &feature_lpm,
1081 &feature_break,
1082 &feature_spm,
1083 &feature_addsubiw,
1084 &feature_avr5,
1085 },
1086};
1087
1088pub const cpu_ata6285 = Cpu{
1089 .name = "ata6285",
1090 .llvm_name = "ata6285",
1091 .subfeatures = &[_]*const Feature {
1092 &feature_lpmx,
1093 &feature_ijmpcall,
1094 &feature_movw,
1095 &feature_sram,
1096 &feature_mul,
1097 &feature_avr0,
1098 &feature_lpm,
1099 &feature_break,
1100 &feature_spm,
1101 &feature_addsubiw,
1102 &feature_avr4,
1103 },
1104};
1105
1106pub const cpu_ata6286 = Cpu{
1107 .name = "ata6286",
1108 .llvm_name = "ata6286",
1109 .subfeatures = &[_]*const Feature {
1110 &feature_lpmx,
1111 &feature_ijmpcall,
1112 &feature_movw,
1113 &feature_sram,
1114 &feature_mul,
1115 &feature_avr0,
1116 &feature_lpm,
1117 &feature_break,
1118 &feature_spm,
1119 &feature_addsubiw,
1120 &feature_avr4,
1121 },
1122};
1123
1124pub const cpu_ata6289 = Cpu{
1125 .name = "ata6289",
1126 .llvm_name = "ata6289",
1127 .subfeatures = &[_]*const Feature {
1128 &feature_lpmx,
1129 &feature_ijmpcall,
1130 &feature_movw,
1131 &feature_sram,
1132 &feature_mul,
1133 &feature_avr0,
1134 &feature_lpm,
1135 &feature_break,
1136 &feature_spm,
1137 &feature_addsubiw,
1138 &feature_avr4,
1139 },
1140};
1141
1142pub const cpu_atmega103 = Cpu{
1143 .name = "atmega103",
1144 .llvm_name = "atmega103",
1145 .subfeatures = &[_]*const Feature {
1146 &feature_jmpcall,
1147 &feature_ijmpcall,
1148 &feature_sram,
1149 &feature_avr0,
1150 &feature_lpm,
1151 &feature_elpm,
1152 &feature_addsubiw,
1153 &feature_avr31,
1154 },
1155};
1156
1157pub const cpu_atmega128 = Cpu{
1158 .name = "atmega128",
1159 .llvm_name = "atmega128",
1160 .subfeatures = &[_]*const Feature {
1161 &feature_lpmx,
1162 &feature_ijmpcall,
1163 &feature_jmpcall,
1164 &feature_movw,
1165 &feature_sram,
1166 &feature_mul,
1167 &feature_avr0,
1168 &feature_lpm,
1169 &feature_break,
1170 &feature_spm,
1171 &feature_elpmx,
1172 &feature_elpm,
1173 &feature_addsubiw,
1174 &feature_avr51,
1175 },
1176};
1177
1178pub const cpu_atmega1280 = Cpu{
1179 .name = "atmega1280",
1180 .llvm_name = "atmega1280",
1181 .subfeatures = &[_]*const Feature {
1182 &feature_lpmx,
1183 &feature_ijmpcall,
1184 &feature_jmpcall,
1185 &feature_movw,
1186 &feature_sram,
1187 &feature_mul,
1188 &feature_avr0,
1189 &feature_lpm,
1190 &feature_break,
1191 &feature_spm,
1192 &feature_elpmx,
1193 &feature_elpm,
1194 &feature_addsubiw,
1195 &feature_avr51,
1196 },
1197};
1198
1199pub const cpu_atmega1281 = Cpu{
1200 .name = "atmega1281",
1201 .llvm_name = "atmega1281",
1202 .subfeatures = &[_]*const Feature {
1203 &feature_lpmx,
1204 &feature_ijmpcall,
1205 &feature_jmpcall,
1206 &feature_movw,
1207 &feature_sram,
1208 &feature_mul,
1209 &feature_avr0,
1210 &feature_lpm,
1211 &feature_break,
1212 &feature_spm,
1213 &feature_elpmx,
1214 &feature_elpm,
1215 &feature_addsubiw,
1216 &feature_avr51,
1217 },
1218};
1219
1220pub const cpu_atmega1284 = Cpu{
1221 .name = "atmega1284",
1222 .llvm_name = "atmega1284",
1223 .subfeatures = &[_]*const Feature {
1224 &feature_lpmx,
1225 &feature_ijmpcall,
1226 &feature_jmpcall,
1227 &feature_movw,
1228 &feature_sram,
1229 &feature_mul,
1230 &feature_avr0,
1231 &feature_lpm,
1232 &feature_break,
1233 &feature_spm,
1234 &feature_elpmx,
1235 &feature_elpm,
1236 &feature_addsubiw,
1237 &feature_avr51,
1238 },
1239};
1240
1241pub const cpu_atmega1284p = Cpu{
1242 .name = "atmega1284p",
1243 .llvm_name = "atmega1284p",
1244 .subfeatures = &[_]*const Feature {
1245 &feature_lpmx,
1246 &feature_ijmpcall,
1247 &feature_jmpcall,
1248 &feature_movw,
1249 &feature_sram,
1250 &feature_mul,
1251 &feature_avr0,
1252 &feature_lpm,
1253 &feature_break,
1254 &feature_spm,
1255 &feature_elpmx,
1256 &feature_elpm,
1257 &feature_addsubiw,
1258 &feature_avr51,
1259 },
1260};
1261
1262pub const cpu_atmega1284rfr2 = Cpu{
1263 .name = "atmega1284rfr2",
1264 .llvm_name = "atmega1284rfr2",
1265 .subfeatures = &[_]*const Feature {
1266 &feature_lpmx,
1267 &feature_ijmpcall,
1268 &feature_jmpcall,
1269 &feature_movw,
1270 &feature_sram,
1271 &feature_mul,
1272 &feature_avr0,
1273 &feature_lpm,
1274 &feature_break,
1275 &feature_spm,
1276 &feature_elpmx,
1277 &feature_elpm,
1278 &feature_addsubiw,
1279 &feature_avr51,
1280 },
1281};
1282
1283pub const cpu_atmega128a = Cpu{
1284 .name = "atmega128a",
1285 .llvm_name = "atmega128a",
1286 .subfeatures = &[_]*const Feature {
1287 &feature_lpmx,
1288 &feature_ijmpcall,
1289 &feature_jmpcall,
1290 &feature_movw,
1291 &feature_sram,
1292 &feature_mul,
1293 &feature_avr0,
1294 &feature_lpm,
1295 &feature_break,
1296 &feature_spm,
1297 &feature_elpmx,
1298 &feature_elpm,
1299 &feature_addsubiw,
1300 &feature_avr51,
1301 },
1302};
1303
1304pub const cpu_atmega128rfa1 = Cpu{
1305 .name = "atmega128rfa1",
1306 .llvm_name = "atmega128rfa1",
1307 .subfeatures = &[_]*const Feature {
1308 &feature_lpmx,
1309 &feature_ijmpcall,
1310 &feature_jmpcall,
1311 &feature_movw,
1312 &feature_sram,
1313 &feature_mul,
1314 &feature_avr0,
1315 &feature_lpm,
1316 &feature_break,
1317 &feature_spm,
1318 &feature_elpmx,
1319 &feature_elpm,
1320 &feature_addsubiw,
1321 &feature_avr51,
1322 },
1323};
1324
1325pub const cpu_atmega128rfr2 = Cpu{
1326 .name = "atmega128rfr2",
1327 .llvm_name = "atmega128rfr2",
1328 .subfeatures = &[_]*const Feature {
1329 &feature_lpmx,
1330 &feature_ijmpcall,
1331 &feature_jmpcall,
1332 &feature_movw,
1333 &feature_sram,
1334 &feature_mul,
1335 &feature_avr0,
1336 &feature_lpm,
1337 &feature_break,
1338 &feature_spm,
1339 &feature_elpmx,
1340 &feature_elpm,
1341 &feature_addsubiw,
1342 &feature_avr51,
1343 },
1344};
1345
1346pub const cpu_atmega16 = Cpu{
1347 .name = "atmega16",
1348 .llvm_name = "atmega16",
1349 .subfeatures = &[_]*const Feature {
1350 &feature_lpmx,
1351 &feature_jmpcall,
1352 &feature_ijmpcall,
1353 &feature_movw,
1354 &feature_sram,
1355 &feature_mul,
1356 &feature_avr0,
1357 &feature_lpm,
1358 &feature_break,
1359 &feature_spm,
1360 &feature_addsubiw,
1361 &feature_avr5,
1362 },
1363};
1364
1365pub const cpu_atmega161 = Cpu{
1366 .name = "atmega161",
1367 .llvm_name = "atmega161",
1368 .subfeatures = &[_]*const Feature {
1369 &feature_ijmpcall,
1370 &feature_jmpcall,
1371 &feature_sram,
1372 &feature_avr0,
1373 &feature_lpm,
1374 &feature_addsubiw,
1375 &feature_avr3,
1376 &feature_lpmx,
1377 &feature_movw,
1378 &feature_mul,
1379 &feature_spm,
1380 },
1381};
1382
1383pub const cpu_atmega162 = Cpu{
1384 .name = "atmega162",
1385 .llvm_name = "atmega162",
1386 .subfeatures = &[_]*const Feature {
1387 &feature_lpmx,
1388 &feature_jmpcall,
1389 &feature_ijmpcall,
1390 &feature_movw,
1391 &feature_sram,
1392 &feature_mul,
1393 &feature_avr0,
1394 &feature_lpm,
1395 &feature_break,
1396 &feature_spm,
1397 &feature_addsubiw,
1398 &feature_avr5,
1399 },
1400};
1401
1402pub const cpu_atmega163 = Cpu{
1403 .name = "atmega163",
1404 .llvm_name = "atmega163",
1405 .subfeatures = &[_]*const Feature {
1406 &feature_ijmpcall,
1407 &feature_jmpcall,
1408 &feature_sram,
1409 &feature_avr0,
1410 &feature_lpm,
1411 &feature_addsubiw,
1412 &feature_avr3,
1413 &feature_lpmx,
1414 &feature_movw,
1415 &feature_mul,
1416 &feature_spm,
1417 },
1418};
1419
1420pub const cpu_atmega164a = Cpu{
1421 .name = "atmega164a",
1422 .llvm_name = "atmega164a",
1423 .subfeatures = &[_]*const Feature {
1424 &feature_lpmx,
1425 &feature_jmpcall,
1426 &feature_ijmpcall,
1427 &feature_movw,
1428 &feature_sram,
1429 &feature_mul,
1430 &feature_avr0,
1431 &feature_lpm,
1432 &feature_break,
1433 &feature_spm,
1434 &feature_addsubiw,
1435 &feature_avr5,
1436 },
1437};
1438
1439pub const cpu_atmega164p = Cpu{
1440 .name = "atmega164p",
1441 .llvm_name = "atmega164p",
1442 .subfeatures = &[_]*const Feature {
1443 &feature_lpmx,
1444 &feature_jmpcall,
1445 &feature_ijmpcall,
1446 &feature_movw,
1447 &feature_sram,
1448 &feature_mul,
1449 &feature_avr0,
1450 &feature_lpm,
1451 &feature_break,
1452 &feature_spm,
1453 &feature_addsubiw,
1454 &feature_avr5,
1455 },
1456};
1457
1458pub const cpu_atmega164pa = Cpu{
1459 .name = "atmega164pa",
1460 .llvm_name = "atmega164pa",
1461 .subfeatures = &[_]*const Feature {
1462 &feature_lpmx,
1463 &feature_jmpcall,
1464 &feature_ijmpcall,
1465 &feature_movw,
1466 &feature_sram,
1467 &feature_mul,
1468 &feature_avr0,
1469 &feature_lpm,
1470 &feature_break,
1471 &feature_spm,
1472 &feature_addsubiw,
1473 &feature_avr5,
1474 },
1475};
1476
1477pub const cpu_atmega165 = Cpu{
1478 .name = "atmega165",
1479 .llvm_name = "atmega165",
1480 .subfeatures = &[_]*const Feature {
1481 &feature_lpmx,
1482 &feature_jmpcall,
1483 &feature_ijmpcall,
1484 &feature_movw,
1485 &feature_sram,
1486 &feature_mul,
1487 &feature_avr0,
1488 &feature_lpm,
1489 &feature_break,
1490 &feature_spm,
1491 &feature_addsubiw,
1492 &feature_avr5,
1493 },
1494};
1495
1496pub const cpu_atmega165a = Cpu{
1497 .name = "atmega165a",
1498 .llvm_name = "atmega165a",
1499 .subfeatures = &[_]*const Feature {
1500 &feature_lpmx,
1501 &feature_jmpcall,
1502 &feature_ijmpcall,
1503 &feature_movw,
1504 &feature_sram,
1505 &feature_mul,
1506 &feature_avr0,
1507 &feature_lpm,
1508 &feature_break,
1509 &feature_spm,
1510 &feature_addsubiw,
1511 &feature_avr5,
1512 },
1513};
1514
1515pub const cpu_atmega165p = Cpu{
1516 .name = "atmega165p",
1517 .llvm_name = "atmega165p",
1518 .subfeatures = &[_]*const Feature {
1519 &feature_lpmx,
1520 &feature_jmpcall,
1521 &feature_ijmpcall,
1522 &feature_movw,
1523 &feature_sram,
1524 &feature_mul,
1525 &feature_avr0,
1526 &feature_lpm,
1527 &feature_break,
1528 &feature_spm,
1529 &feature_addsubiw,
1530 &feature_avr5,
1531 },
1532};
1533
1534pub const cpu_atmega165pa = Cpu{
1535 .name = "atmega165pa",
1536 .llvm_name = "atmega165pa",
1537 .subfeatures = &[_]*const Feature {
1538 &feature_lpmx,
1539 &feature_jmpcall,
1540 &feature_ijmpcall,
1541 &feature_movw,
1542 &feature_sram,
1543 &feature_mul,
1544 &feature_avr0,
1545 &feature_lpm,
1546 &feature_break,
1547 &feature_spm,
1548 &feature_addsubiw,
1549 &feature_avr5,
1550 },
1551};
1552
1553pub const cpu_atmega168 = Cpu{
1554 .name = "atmega168",
1555 .llvm_name = "atmega168",
1556 .subfeatures = &[_]*const Feature {
1557 &feature_lpmx,
1558 &feature_jmpcall,
1559 &feature_ijmpcall,
1560 &feature_movw,
1561 &feature_sram,
1562 &feature_mul,
1563 &feature_avr0,
1564 &feature_lpm,
1565 &feature_break,
1566 &feature_spm,
1567 &feature_addsubiw,
1568 &feature_avr5,
1569 },
1570};
1571
1572pub const cpu_atmega168a = Cpu{
1573 .name = "atmega168a",
1574 .llvm_name = "atmega168a",
1575 .subfeatures = &[_]*const Feature {
1576 &feature_lpmx,
1577 &feature_jmpcall,
1578 &feature_ijmpcall,
1579 &feature_movw,
1580 &feature_sram,
1581 &feature_mul,
1582 &feature_avr0,
1583 &feature_lpm,
1584 &feature_break,
1585 &feature_spm,
1586 &feature_addsubiw,
1587 &feature_avr5,
1588 },
1589};
1590
1591pub const cpu_atmega168p = Cpu{
1592 .name = "atmega168p",
1593 .llvm_name = "atmega168p",
1594 .subfeatures = &[_]*const Feature {
1595 &feature_lpmx,
1596 &feature_jmpcall,
1597 &feature_ijmpcall,
1598 &feature_movw,
1599 &feature_sram,
1600 &feature_mul,
1601 &feature_avr0,
1602 &feature_lpm,
1603 &feature_break,
1604 &feature_spm,
1605 &feature_addsubiw,
1606 &feature_avr5,
1607 },
1608};
1609
1610pub const cpu_atmega168pa = Cpu{
1611 .name = "atmega168pa",
1612 .llvm_name = "atmega168pa",
1613 .subfeatures = &[_]*const Feature {
1614 &feature_lpmx,
1615 &feature_jmpcall,
1616 &feature_ijmpcall,
1617 &feature_movw,
1618 &feature_sram,
1619 &feature_mul,
1620 &feature_avr0,
1621 &feature_lpm,
1622 &feature_break,
1623 &feature_spm,
1624 &feature_addsubiw,
1625 &feature_avr5,
1626 },
1627};
1628
1629pub const cpu_atmega169 = Cpu{
1630 .name = "atmega169",
1631 .llvm_name = "atmega169",
1632 .subfeatures = &[_]*const Feature {
1633 &feature_lpmx,
1634 &feature_jmpcall,
1635 &feature_ijmpcall,
1636 &feature_movw,
1637 &feature_sram,
1638 &feature_mul,
1639 &feature_avr0,
1640 &feature_lpm,
1641 &feature_break,
1642 &feature_spm,
1643 &feature_addsubiw,
1644 &feature_avr5,
1645 },
1646};
1647
1648pub const cpu_atmega169a = Cpu{
1649 .name = "atmega169a",
1650 .llvm_name = "atmega169a",
1651 .subfeatures = &[_]*const Feature {
1652 &feature_lpmx,
1653 &feature_jmpcall,
1654 &feature_ijmpcall,
1655 &feature_movw,
1656 &feature_sram,
1657 &feature_mul,
1658 &feature_avr0,
1659 &feature_lpm,
1660 &feature_break,
1661 &feature_spm,
1662 &feature_addsubiw,
1663 &feature_avr5,
1664 },
1665};
1666
1667pub const cpu_atmega169p = Cpu{
1668 .name = "atmega169p",
1669 .llvm_name = "atmega169p",
1670 .subfeatures = &[_]*const Feature {
1671 &feature_lpmx,
1672 &feature_jmpcall,
1673 &feature_ijmpcall,
1674 &feature_movw,
1675 &feature_sram,
1676 &feature_mul,
1677 &feature_avr0,
1678 &feature_lpm,
1679 &feature_break,
1680 &feature_spm,
1681 &feature_addsubiw,
1682 &feature_avr5,
1683 },
1684};
1685
1686pub const cpu_atmega169pa = Cpu{
1687 .name = "atmega169pa",
1688 .llvm_name = "atmega169pa",
1689 .subfeatures = &[_]*const Feature {
1690 &feature_lpmx,
1691 &feature_jmpcall,
1692 &feature_ijmpcall,
1693 &feature_movw,
1694 &feature_sram,
1695 &feature_mul,
1696 &feature_avr0,
1697 &feature_lpm,
1698 &feature_break,
1699 &feature_spm,
1700 &feature_addsubiw,
1701 &feature_avr5,
1702 },
1703};
1704
1705pub const cpu_atmega16a = Cpu{
1706 .name = "atmega16a",
1707 .llvm_name = "atmega16a",
1708 .subfeatures = &[_]*const Feature {
1709 &feature_lpmx,
1710 &feature_jmpcall,
1711 &feature_ijmpcall,
1712 &feature_movw,
1713 &feature_sram,
1714 &feature_mul,
1715 &feature_avr0,
1716 &feature_lpm,
1717 &feature_break,
1718 &feature_spm,
1719 &feature_addsubiw,
1720 &feature_avr5,
1721 },
1722};
1723
1724pub const cpu_atmega16hva = Cpu{
1725 .name = "atmega16hva",
1726 .llvm_name = "atmega16hva",
1727 .subfeatures = &[_]*const Feature {
1728 &feature_lpmx,
1729 &feature_jmpcall,
1730 &feature_ijmpcall,
1731 &feature_movw,
1732 &feature_sram,
1733 &feature_mul,
1734 &feature_avr0,
1735 &feature_lpm,
1736 &feature_break,
1737 &feature_spm,
1738 &feature_addsubiw,
1739 &feature_avr5,
1740 },
1741};
1742
1743pub const cpu_atmega16hva2 = Cpu{
1744 .name = "atmega16hva2",
1745 .llvm_name = "atmega16hva2",
1746 .subfeatures = &[_]*const Feature {
1747 &feature_lpmx,
1748 &feature_jmpcall,
1749 &feature_ijmpcall,
1750 &feature_movw,
1751 &feature_sram,
1752 &feature_mul,
1753 &feature_avr0,
1754 &feature_lpm,
1755 &feature_break,
1756 &feature_spm,
1757 &feature_addsubiw,
1758 &feature_avr5,
1759 },
1760};
1761
1762pub const cpu_atmega16hvb = Cpu{
1763 .name = "atmega16hvb",
1764 .llvm_name = "atmega16hvb",
1765 .subfeatures = &[_]*const Feature {
1766 &feature_lpmx,
1767 &feature_jmpcall,
1768 &feature_ijmpcall,
1769 &feature_movw,
1770 &feature_sram,
1771 &feature_mul,
1772 &feature_avr0,
1773 &feature_lpm,
1774 &feature_break,
1775 &feature_spm,
1776 &feature_addsubiw,
1777 &feature_avr5,
1778 },
1779};
1780
1781pub const cpu_atmega16hvbrevb = Cpu{
1782 .name = "atmega16hvbrevb",
1783 .llvm_name = "atmega16hvbrevb",
1784 .subfeatures = &[_]*const Feature {
1785 &feature_lpmx,
1786 &feature_jmpcall,
1787 &feature_ijmpcall,
1788 &feature_movw,
1789 &feature_sram,
1790 &feature_mul,
1791 &feature_avr0,
1792 &feature_lpm,
1793 &feature_break,
1794 &feature_spm,
1795 &feature_addsubiw,
1796 &feature_avr5,
1797 },
1798};
1799
1800pub const cpu_atmega16m1 = Cpu{
1801 .name = "atmega16m1",
1802 .llvm_name = "atmega16m1",
1803 .subfeatures = &[_]*const Feature {
1804 &feature_lpmx,
1805 &feature_jmpcall,
1806 &feature_ijmpcall,
1807 &feature_movw,
1808 &feature_sram,
1809 &feature_mul,
1810 &feature_avr0,
1811 &feature_lpm,
1812 &feature_break,
1813 &feature_spm,
1814 &feature_addsubiw,
1815 &feature_avr5,
1816 },
1817};
1818
1819pub const cpu_atmega16u2 = Cpu{
1820 .name = "atmega16u2",
1821 .llvm_name = "atmega16u2",
1822 .subfeatures = &[_]*const Feature {
1823 &feature_lpmx,
1824 &feature_jmpcall,
1825 &feature_ijmpcall,
1826 &feature_movw,
1827 &feature_sram,
1828 &feature_avr0,
1829 &feature_lpm,
1830 &feature_break,
1831 &feature_spm,
1832 &feature_addsubiw,
1833 &feature_avr35,
1834 },
1835};
1836
1837pub const cpu_atmega16u4 = Cpu{
1838 .name = "atmega16u4",
1839 .llvm_name = "atmega16u4",
1840 .subfeatures = &[_]*const Feature {
1841 &feature_lpmx,
1842 &feature_jmpcall,
1843 &feature_ijmpcall,
1844 &feature_movw,
1845 &feature_sram,
1846 &feature_mul,
1847 &feature_avr0,
1848 &feature_lpm,
1849 &feature_break,
1850 &feature_spm,
1851 &feature_addsubiw,
1852 &feature_avr5,
1853 },
1854};
1855
1856pub const cpu_atmega2560 = Cpu{
1857 .name = "atmega2560",
1858 .llvm_name = "atmega2560",
1859 .subfeatures = &[_]*const Feature {
1860 &feature_lpmx,
1861 &feature_jmpcall,
1862 &feature_ijmpcall,
1863 &feature_movw,
1864 &feature_sram,
1865 &feature_mul,
1866 &feature_avr0,
1867 &feature_lpm,
1868 &feature_break,
1869 &feature_spm,
1870 &feature_elpmx,
1871 &feature_elpm,
1872 &feature_addsubiw,
1873 &feature_avr6,
1874 },
1875};
1876
1877pub const cpu_atmega2561 = Cpu{
1878 .name = "atmega2561",
1879 .llvm_name = "atmega2561",
1880 .subfeatures = &[_]*const Feature {
1881 &feature_lpmx,
1882 &feature_jmpcall,
1883 &feature_ijmpcall,
1884 &feature_movw,
1885 &feature_sram,
1886 &feature_mul,
1887 &feature_avr0,
1888 &feature_lpm,
1889 &feature_break,
1890 &feature_spm,
1891 &feature_elpmx,
1892 &feature_elpm,
1893 &feature_addsubiw,
1894 &feature_avr6,
1895 },
1896};
1897
1898pub const cpu_atmega2564rfr2 = Cpu{
1899 .name = "atmega2564rfr2",
1900 .llvm_name = "atmega2564rfr2",
1901 .subfeatures = &[_]*const Feature {
1902 &feature_lpmx,
1903 &feature_jmpcall,
1904 &feature_ijmpcall,
1905 &feature_movw,
1906 &feature_sram,
1907 &feature_mul,
1908 &feature_avr0,
1909 &feature_lpm,
1910 &feature_break,
1911 &feature_spm,
1912 &feature_elpmx,
1913 &feature_elpm,
1914 &feature_addsubiw,
1915 &feature_avr6,
1916 },
1917};
1918
1919pub const cpu_atmega256rfr2 = Cpu{
1920 .name = "atmega256rfr2",
1921 .llvm_name = "atmega256rfr2",
1922 .subfeatures = &[_]*const Feature {
1923 &feature_lpmx,
1924 &feature_jmpcall,
1925 &feature_ijmpcall,
1926 &feature_movw,
1927 &feature_sram,
1928 &feature_mul,
1929 &feature_avr0,
1930 &feature_lpm,
1931 &feature_break,
1932 &feature_spm,
1933 &feature_elpmx,
1934 &feature_elpm,
1935 &feature_addsubiw,
1936 &feature_avr6,
1937 },
1938};
1939
1940pub const cpu_atmega32 = Cpu{
1941 .name = "atmega32",
1942 .llvm_name = "atmega32",
1943 .subfeatures = &[_]*const Feature {
1944 &feature_lpmx,
1945 &feature_jmpcall,
1946 &feature_ijmpcall,
1947 &feature_movw,
1948 &feature_sram,
1949 &feature_mul,
1950 &feature_avr0,
1951 &feature_lpm,
1952 &feature_break,
1953 &feature_spm,
1954 &feature_addsubiw,
1955 &feature_avr5,
1956 },
1957};
1958
1959pub const cpu_atmega323 = Cpu{
1960 .name = "atmega323",
1961 .llvm_name = "atmega323",
1962 .subfeatures = &[_]*const Feature {
1963 &feature_lpmx,
1964 &feature_jmpcall,
1965 &feature_ijmpcall,
1966 &feature_movw,
1967 &feature_sram,
1968 &feature_mul,
1969 &feature_avr0,
1970 &feature_lpm,
1971 &feature_break,
1972 &feature_spm,
1973 &feature_addsubiw,
1974 &feature_avr5,
1975 },
1976};
1977
1978pub const cpu_atmega324a = Cpu{
1979 .name = "atmega324a",
1980 .llvm_name = "atmega324a",
1981 .subfeatures = &[_]*const Feature {
1982 &feature_lpmx,
1983 &feature_jmpcall,
1984 &feature_ijmpcall,
1985 &feature_movw,
1986 &feature_sram,
1987 &feature_mul,
1988 &feature_avr0,
1989 &feature_lpm,
1990 &feature_break,
1991 &feature_spm,
1992 &feature_addsubiw,
1993 &feature_avr5,
1994 },
1995};
1996
1997pub const cpu_atmega324p = Cpu{
1998 .name = "atmega324p",
1999 .llvm_name = "atmega324p",
2000 .subfeatures = &[_]*const Feature {
2001 &feature_lpmx,
2002 &feature_jmpcall,
2003 &feature_ijmpcall,
2004 &feature_movw,
2005 &feature_sram,
2006 &feature_mul,
2007 &feature_avr0,
2008 &feature_lpm,
2009 &feature_break,
2010 &feature_spm,
2011 &feature_addsubiw,
2012 &feature_avr5,
2013 },
2014};
2015
2016pub const cpu_atmega324pa = Cpu{
2017 .name = "atmega324pa",
2018 .llvm_name = "atmega324pa",
2019 .subfeatures = &[_]*const Feature {
2020 &feature_lpmx,
2021 &feature_jmpcall,
2022 &feature_ijmpcall,
2023 &feature_movw,
2024 &feature_sram,
2025 &feature_mul,
2026 &feature_avr0,
2027 &feature_lpm,
2028 &feature_break,
2029 &feature_spm,
2030 &feature_addsubiw,
2031 &feature_avr5,
2032 },
2033};
2034
2035pub const cpu_atmega325 = Cpu{
2036 .name = "atmega325",
2037 .llvm_name = "atmega325",
2038 .subfeatures = &[_]*const Feature {
2039 &feature_lpmx,
2040 &feature_jmpcall,
2041 &feature_ijmpcall,
2042 &feature_movw,
2043 &feature_sram,
2044 &feature_mul,
2045 &feature_avr0,
2046 &feature_lpm,
2047 &feature_break,
2048 &feature_spm,
2049 &feature_addsubiw,
2050 &feature_avr5,
2051 },
2052};
2053
2054pub const cpu_atmega3250 = Cpu{
2055 .name = "atmega3250",
2056 .llvm_name = "atmega3250",
2057 .subfeatures = &[_]*const Feature {
2058 &feature_lpmx,
2059 &feature_jmpcall,
2060 &feature_ijmpcall,
2061 &feature_movw,
2062 &feature_sram,
2063 &feature_mul,
2064 &feature_avr0,
2065 &feature_lpm,
2066 &feature_break,
2067 &feature_spm,
2068 &feature_addsubiw,
2069 &feature_avr5,
2070 },
2071};
2072
2073pub const cpu_atmega3250a = Cpu{
2074 .name = "atmega3250a",
2075 .llvm_name = "atmega3250a",
2076 .subfeatures = &[_]*const Feature {
2077 &feature_lpmx,
2078 &feature_jmpcall,
2079 &feature_ijmpcall,
2080 &feature_movw,
2081 &feature_sram,
2082 &feature_mul,
2083 &feature_avr0,
2084 &feature_lpm,
2085 &feature_break,
2086 &feature_spm,
2087 &feature_addsubiw,
2088 &feature_avr5,
2089 },
2090};
2091
2092pub const cpu_atmega3250p = Cpu{
2093 .name = "atmega3250p",
2094 .llvm_name = "atmega3250p",
2095 .subfeatures = &[_]*const Feature {
2096 &feature_lpmx,
2097 &feature_jmpcall,
2098 &feature_ijmpcall,
2099 &feature_movw,
2100 &feature_sram,
2101 &feature_mul,
2102 &feature_avr0,
2103 &feature_lpm,
2104 &feature_break,
2105 &feature_spm,
2106 &feature_addsubiw,
2107 &feature_avr5,
2108 },
2109};
2110
2111pub const cpu_atmega3250pa = Cpu{
2112 .name = "atmega3250pa",
2113 .llvm_name = "atmega3250pa",
2114 .subfeatures = &[_]*const Feature {
2115 &feature_lpmx,
2116 &feature_jmpcall,
2117 &feature_ijmpcall,
2118 &feature_movw,
2119 &feature_sram,
2120 &feature_mul,
2121 &feature_avr0,
2122 &feature_lpm,
2123 &feature_break,
2124 &feature_spm,
2125 &feature_addsubiw,
2126 &feature_avr5,
2127 },
2128};
2129
2130pub const cpu_atmega325a = Cpu{
2131 .name = "atmega325a",
2132 .llvm_name = "atmega325a",
2133 .subfeatures = &[_]*const Feature {
2134 &feature_lpmx,
2135 &feature_jmpcall,
2136 &feature_ijmpcall,
2137 &feature_movw,
2138 &feature_sram,
2139 &feature_mul,
2140 &feature_avr0,
2141 &feature_lpm,
2142 &feature_break,
2143 &feature_spm,
2144 &feature_addsubiw,
2145 &feature_avr5,
2146 },
2147};
2148
2149pub const cpu_atmega325p = Cpu{
2150 .name = "atmega325p",
2151 .llvm_name = "atmega325p",
2152 .subfeatures = &[_]*const Feature {
2153 &feature_lpmx,
2154 &feature_jmpcall,
2155 &feature_ijmpcall,
2156 &feature_movw,
2157 &feature_sram,
2158 &feature_mul,
2159 &feature_avr0,
2160 &feature_lpm,
2161 &feature_break,
2162 &feature_spm,
2163 &feature_addsubiw,
2164 &feature_avr5,
2165 },
2166};
2167
2168pub const cpu_atmega325pa = Cpu{
2169 .name = "atmega325pa",
2170 .llvm_name = "atmega325pa",
2171 .subfeatures = &[_]*const Feature {
2172 &feature_lpmx,
2173 &feature_jmpcall,
2174 &feature_ijmpcall,
2175 &feature_movw,
2176 &feature_sram,
2177 &feature_mul,
2178 &feature_avr0,
2179 &feature_lpm,
2180 &feature_break,
2181 &feature_spm,
2182 &feature_addsubiw,
2183 &feature_avr5,
2184 },
2185};
2186
2187pub const cpu_atmega328 = Cpu{
2188 .name = "atmega328",
2189 .llvm_name = "atmega328",
2190 .subfeatures = &[_]*const Feature {
2191 &feature_lpmx,
2192 &feature_jmpcall,
2193 &feature_ijmpcall,
2194 &feature_movw,
2195 &feature_sram,
2196 &feature_mul,
2197 &feature_avr0,
2198 &feature_lpm,
2199 &feature_break,
2200 &feature_spm,
2201 &feature_addsubiw,
2202 &feature_avr5,
2203 },
2204};
2205
2206pub const cpu_atmega328p = Cpu{
2207 .name = "atmega328p",
2208 .llvm_name = "atmega328p",
2209 .subfeatures = &[_]*const Feature {
2210 &feature_lpmx,
2211 &feature_jmpcall,
2212 &feature_ijmpcall,
2213 &feature_movw,
2214 &feature_sram,
2215 &feature_mul,
2216 &feature_avr0,
2217 &feature_lpm,
2218 &feature_break,
2219 &feature_spm,
2220 &feature_addsubiw,
2221 &feature_avr5,
2222 },
2223};
2224
2225pub const cpu_atmega329 = Cpu{
2226 .name = "atmega329",
2227 .llvm_name = "atmega329",
2228 .subfeatures = &[_]*const Feature {
2229 &feature_lpmx,
2230 &feature_jmpcall,
2231 &feature_ijmpcall,
2232 &feature_movw,
2233 &feature_sram,
2234 &feature_mul,
2235 &feature_avr0,
2236 &feature_lpm,
2237 &feature_break,
2238 &feature_spm,
2239 &feature_addsubiw,
2240 &feature_avr5,
2241 },
2242};
2243
2244pub const cpu_atmega3290 = Cpu{
2245 .name = "atmega3290",
2246 .llvm_name = "atmega3290",
2247 .subfeatures = &[_]*const Feature {
2248 &feature_lpmx,
2249 &feature_jmpcall,
2250 &feature_ijmpcall,
2251 &feature_movw,
2252 &feature_sram,
2253 &feature_mul,
2254 &feature_avr0,
2255 &feature_lpm,
2256 &feature_break,
2257 &feature_spm,
2258 &feature_addsubiw,
2259 &feature_avr5,
2260 },
2261};
2262
2263pub const cpu_atmega3290a = Cpu{
2264 .name = "atmega3290a",
2265 .llvm_name = "atmega3290a",
2266 .subfeatures = &[_]*const Feature {
2267 &feature_lpmx,
2268 &feature_jmpcall,
2269 &feature_ijmpcall,
2270 &feature_movw,
2271 &feature_sram,
2272 &feature_mul,
2273 &feature_avr0,
2274 &feature_lpm,
2275 &feature_break,
2276 &feature_spm,
2277 &feature_addsubiw,
2278 &feature_avr5,
2279 },
2280};
2281
2282pub const cpu_atmega3290p = Cpu{
2283 .name = "atmega3290p",
2284 .llvm_name = "atmega3290p",
2285 .subfeatures = &[_]*const Feature {
2286 &feature_lpmx,
2287 &feature_jmpcall,
2288 &feature_ijmpcall,
2289 &feature_movw,
2290 &feature_sram,
2291 &feature_mul,
2292 &feature_avr0,
2293 &feature_lpm,
2294 &feature_break,
2295 &feature_spm,
2296 &feature_addsubiw,
2297 &feature_avr5,
2298 },
2299};
2300
2301pub const cpu_atmega3290pa = Cpu{
2302 .name = "atmega3290pa",
2303 .llvm_name = "atmega3290pa",
2304 .subfeatures = &[_]*const Feature {
2305 &feature_lpmx,
2306 &feature_jmpcall,
2307 &feature_ijmpcall,
2308 &feature_movw,
2309 &feature_sram,
2310 &feature_mul,
2311 &feature_avr0,
2312 &feature_lpm,
2313 &feature_break,
2314 &feature_spm,
2315 &feature_addsubiw,
2316 &feature_avr5,
2317 },
2318};
2319
2320pub const cpu_atmega329a = Cpu{
2321 .name = "atmega329a",
2322 .llvm_name = "atmega329a",
2323 .subfeatures = &[_]*const Feature {
2324 &feature_lpmx,
2325 &feature_jmpcall,
2326 &feature_ijmpcall,
2327 &feature_movw,
2328 &feature_sram,
2329 &feature_mul,
2330 &feature_avr0,
2331 &feature_lpm,
2332 &feature_break,
2333 &feature_spm,
2334 &feature_addsubiw,
2335 &feature_avr5,
2336 },
2337};
2338
2339pub const cpu_atmega329p = Cpu{
2340 .name = "atmega329p",
2341 .llvm_name = "atmega329p",
2342 .subfeatures = &[_]*const Feature {
2343 &feature_lpmx,
2344 &feature_jmpcall,
2345 &feature_ijmpcall,
2346 &feature_movw,
2347 &feature_sram,
2348 &feature_mul,
2349 &feature_avr0,
2350 &feature_lpm,
2351 &feature_break,
2352 &feature_spm,
2353 &feature_addsubiw,
2354 &feature_avr5,
2355 },
2356};
2357
2358pub const cpu_atmega329pa = Cpu{
2359 .name = "atmega329pa",
2360 .llvm_name = "atmega329pa",
2361 .subfeatures = &[_]*const Feature {
2362 &feature_lpmx,
2363 &feature_jmpcall,
2364 &feature_ijmpcall,
2365 &feature_movw,
2366 &feature_sram,
2367 &feature_mul,
2368 &feature_avr0,
2369 &feature_lpm,
2370 &feature_break,
2371 &feature_spm,
2372 &feature_addsubiw,
2373 &feature_avr5,
2374 },
2375};
2376
2377pub const cpu_atmega32a = Cpu{
2378 .name = "atmega32a",
2379 .llvm_name = "atmega32a",
2380 .subfeatures = &[_]*const Feature {
2381 &feature_lpmx,
2382 &feature_jmpcall,
2383 &feature_ijmpcall,
2384 &feature_movw,
2385 &feature_sram,
2386 &feature_mul,
2387 &feature_avr0,
2388 &feature_lpm,
2389 &feature_break,
2390 &feature_spm,
2391 &feature_addsubiw,
2392 &feature_avr5,
2393 },
2394};
2395
2396pub const cpu_atmega32c1 = Cpu{
2397 .name = "atmega32c1",
2398 .llvm_name = "atmega32c1",
2399 .subfeatures = &[_]*const Feature {
2400 &feature_lpmx,
2401 &feature_jmpcall,
2402 &feature_ijmpcall,
2403 &feature_movw,
2404 &feature_sram,
2405 &feature_mul,
2406 &feature_avr0,
2407 &feature_lpm,
2408 &feature_break,
2409 &feature_spm,
2410 &feature_addsubiw,
2411 &feature_avr5,
2412 },
2413};
2414
2415pub const cpu_atmega32hvb = Cpu{
2416 .name = "atmega32hvb",
2417 .llvm_name = "atmega32hvb",
2418 .subfeatures = &[_]*const Feature {
2419 &feature_lpmx,
2420 &feature_jmpcall,
2421 &feature_ijmpcall,
2422 &feature_movw,
2423 &feature_sram,
2424 &feature_mul,
2425 &feature_avr0,
2426 &feature_lpm,
2427 &feature_break,
2428 &feature_spm,
2429 &feature_addsubiw,
2430 &feature_avr5,
2431 },
2432};
2433
2434pub const cpu_atmega32hvbrevb = Cpu{
2435 .name = "atmega32hvbrevb",
2436 .llvm_name = "atmega32hvbrevb",
2437 .subfeatures = &[_]*const Feature {
2438 &feature_lpmx,
2439 &feature_jmpcall,
2440 &feature_ijmpcall,
2441 &feature_movw,
2442 &feature_sram,
2443 &feature_mul,
2444 &feature_avr0,
2445 &feature_lpm,
2446 &feature_break,
2447 &feature_spm,
2448 &feature_addsubiw,
2449 &feature_avr5,
2450 },
2451};
2452
2453pub const cpu_atmega32m1 = Cpu{
2454 .name = "atmega32m1",
2455 .llvm_name = "atmega32m1",
2456 .subfeatures = &[_]*const Feature {
2457 &feature_lpmx,
2458 &feature_jmpcall,
2459 &feature_ijmpcall,
2460 &feature_movw,
2461 &feature_sram,
2462 &feature_mul,
2463 &feature_avr0,
2464 &feature_lpm,
2465 &feature_break,
2466 &feature_spm,
2467 &feature_addsubiw,
2468 &feature_avr5,
2469 },
2470};
2471
2472pub const cpu_atmega32u2 = Cpu{
2473 .name = "atmega32u2",
2474 .llvm_name = "atmega32u2",
2475 .subfeatures = &[_]*const Feature {
2476 &feature_lpmx,
2477 &feature_jmpcall,
2478 &feature_ijmpcall,
2479 &feature_movw,
2480 &feature_sram,
2481 &feature_avr0,
2482 &feature_lpm,
2483 &feature_break,
2484 &feature_spm,
2485 &feature_addsubiw,
2486 &feature_avr35,
2487 },
2488};
2489
2490pub const cpu_atmega32u4 = Cpu{
2491 .name = "atmega32u4",
2492 .llvm_name = "atmega32u4",
2493 .subfeatures = &[_]*const Feature {
2494 &feature_lpmx,
2495 &feature_jmpcall,
2496 &feature_ijmpcall,
2497 &feature_movw,
2498 &feature_sram,
2499 &feature_mul,
2500 &feature_avr0,
2501 &feature_lpm,
2502 &feature_break,
2503 &feature_spm,
2504 &feature_addsubiw,
2505 &feature_avr5,
2506 },
2507};
2508
2509pub const cpu_atmega32u6 = Cpu{
2510 .name = "atmega32u6",
2511 .llvm_name = "atmega32u6",
2512 .subfeatures = &[_]*const Feature {
2513 &feature_lpmx,
2514 &feature_jmpcall,
2515 &feature_ijmpcall,
2516 &feature_movw,
2517 &feature_sram,
2518 &feature_mul,
2519 &feature_avr0,
2520 &feature_lpm,
2521 &feature_break,
2522 &feature_spm,
2523 &feature_addsubiw,
2524 &feature_avr5,
2525 },
2526};
2527
2528pub const cpu_atmega406 = Cpu{
2529 .name = "atmega406",
2530 .llvm_name = "atmega406",
2531 .subfeatures = &[_]*const Feature {
2532 &feature_lpmx,
2533 &feature_jmpcall,
2534 &feature_ijmpcall,
2535 &feature_movw,
2536 &feature_sram,
2537 &feature_mul,
2538 &feature_avr0,
2539 &feature_lpm,
2540 &feature_break,
2541 &feature_spm,
2542 &feature_addsubiw,
2543 &feature_avr5,
2544 },
2545};
2546
2547pub const cpu_atmega48 = Cpu{
2548 .name = "atmega48",
2549 .llvm_name = "atmega48",
2550 .subfeatures = &[_]*const Feature {
2551 &feature_lpmx,
2552 &feature_ijmpcall,
2553 &feature_movw,
2554 &feature_sram,
2555 &feature_mul,
2556 &feature_avr0,
2557 &feature_lpm,
2558 &feature_break,
2559 &feature_spm,
2560 &feature_addsubiw,
2561 &feature_avr4,
2562 },
2563};
2564
2565pub const cpu_atmega48a = Cpu{
2566 .name = "atmega48a",
2567 .llvm_name = "atmega48a",
2568 .subfeatures = &[_]*const Feature {
2569 &feature_lpmx,
2570 &feature_ijmpcall,
2571 &feature_movw,
2572 &feature_sram,
2573 &feature_mul,
2574 &feature_avr0,
2575 &feature_lpm,
2576 &feature_break,
2577 &feature_spm,
2578 &feature_addsubiw,
2579 &feature_avr4,
2580 },
2581};
2582
2583pub const cpu_atmega48p = Cpu{
2584 .name = "atmega48p",
2585 .llvm_name = "atmega48p",
2586 .subfeatures = &[_]*const Feature {
2587 &feature_lpmx,
2588 &feature_ijmpcall,
2589 &feature_movw,
2590 &feature_sram,
2591 &feature_mul,
2592 &feature_avr0,
2593 &feature_lpm,
2594 &feature_break,
2595 &feature_spm,
2596 &feature_addsubiw,
2597 &feature_avr4,
2598 },
2599};
2600
2601pub const cpu_atmega48pa = Cpu{
2602 .name = "atmega48pa",
2603 .llvm_name = "atmega48pa",
2604 .subfeatures = &[_]*const Feature {
2605 &feature_lpmx,
2606 &feature_ijmpcall,
2607 &feature_movw,
2608 &feature_sram,
2609 &feature_mul,
2610 &feature_avr0,
2611 &feature_lpm,
2612 &feature_break,
2613 &feature_spm,
2614 &feature_addsubiw,
2615 &feature_avr4,
2616 },
2617};
2618
2619pub const cpu_atmega64 = Cpu{
2620 .name = "atmega64",
2621 .llvm_name = "atmega64",
2622 .subfeatures = &[_]*const Feature {
2623 &feature_lpmx,
2624 &feature_jmpcall,
2625 &feature_ijmpcall,
2626 &feature_movw,
2627 &feature_sram,
2628 &feature_mul,
2629 &feature_avr0,
2630 &feature_lpm,
2631 &feature_break,
2632 &feature_spm,
2633 &feature_addsubiw,
2634 &feature_avr5,
2635 },
2636};
2637
2638pub const cpu_atmega640 = Cpu{
2639 .name = "atmega640",
2640 .llvm_name = "atmega640",
2641 .subfeatures = &[_]*const Feature {
2642 &feature_lpmx,
2643 &feature_jmpcall,
2644 &feature_ijmpcall,
2645 &feature_movw,
2646 &feature_sram,
2647 &feature_mul,
2648 &feature_avr0,
2649 &feature_lpm,
2650 &feature_break,
2651 &feature_spm,
2652 &feature_addsubiw,
2653 &feature_avr5,
2654 },
2655};
2656
2657pub const cpu_atmega644 = Cpu{
2658 .name = "atmega644",
2659 .llvm_name = "atmega644",
2660 .subfeatures = &[_]*const Feature {
2661 &feature_lpmx,
2662 &feature_jmpcall,
2663 &feature_ijmpcall,
2664 &feature_movw,
2665 &feature_sram,
2666 &feature_mul,
2667 &feature_avr0,
2668 &feature_lpm,
2669 &feature_break,
2670 &feature_spm,
2671 &feature_addsubiw,
2672 &feature_avr5,
2673 },
2674};
2675
2676pub const cpu_atmega644a = Cpu{
2677 .name = "atmega644a",
2678 .llvm_name = "atmega644a",
2679 .subfeatures = &[_]*const Feature {
2680 &feature_lpmx,
2681 &feature_jmpcall,
2682 &feature_ijmpcall,
2683 &feature_movw,
2684 &feature_sram,
2685 &feature_mul,
2686 &feature_avr0,
2687 &feature_lpm,
2688 &feature_break,
2689 &feature_spm,
2690 &feature_addsubiw,
2691 &feature_avr5,
2692 },
2693};
2694
2695pub const cpu_atmega644p = Cpu{
2696 .name = "atmega644p",
2697 .llvm_name = "atmega644p",
2698 .subfeatures = &[_]*const Feature {
2699 &feature_lpmx,
2700 &feature_jmpcall,
2701 &feature_ijmpcall,
2702 &feature_movw,
2703 &feature_sram,
2704 &feature_mul,
2705 &feature_avr0,
2706 &feature_lpm,
2707 &feature_break,
2708 &feature_spm,
2709 &feature_addsubiw,
2710 &feature_avr5,
2711 },
2712};
2713
2714pub const cpu_atmega644pa = Cpu{
2715 .name = "atmega644pa",
2716 .llvm_name = "atmega644pa",
2717 .subfeatures = &[_]*const Feature {
2718 &feature_lpmx,
2719 &feature_jmpcall,
2720 &feature_ijmpcall,
2721 &feature_movw,
2722 &feature_sram,
2723 &feature_mul,
2724 &feature_avr0,
2725 &feature_lpm,
2726 &feature_break,
2727 &feature_spm,
2728 &feature_addsubiw,
2729 &feature_avr5,
2730 },
2731};
2732
2733pub const cpu_atmega644rfr2 = Cpu{
2734 .name = "atmega644rfr2",
2735 .llvm_name = "atmega644rfr2",
2736 .subfeatures = &[_]*const Feature {
2737 &feature_lpmx,
2738 &feature_jmpcall,
2739 &feature_ijmpcall,
2740 &feature_movw,
2741 &feature_sram,
2742 &feature_mul,
2743 &feature_avr0,
2744 &feature_lpm,
2745 &feature_break,
2746 &feature_spm,
2747 &feature_addsubiw,
2748 &feature_avr5,
2749 },
2750};
2751
2752pub const cpu_atmega645 = Cpu{
2753 .name = "atmega645",
2754 .llvm_name = "atmega645",
2755 .subfeatures = &[_]*const Feature {
2756 &feature_lpmx,
2757 &feature_jmpcall,
2758 &feature_ijmpcall,
2759 &feature_movw,
2760 &feature_sram,
2761 &feature_mul,
2762 &feature_avr0,
2763 &feature_lpm,
2764 &feature_break,
2765 &feature_spm,
2766 &feature_addsubiw,
2767 &feature_avr5,
2768 },
2769};
2770
2771pub const cpu_atmega6450 = Cpu{
2772 .name = "atmega6450",
2773 .llvm_name = "atmega6450",
2774 .subfeatures = &[_]*const Feature {
2775 &feature_lpmx,
2776 &feature_jmpcall,
2777 &feature_ijmpcall,
2778 &feature_movw,
2779 &feature_sram,
2780 &feature_mul,
2781 &feature_avr0,
2782 &feature_lpm,
2783 &feature_break,
2784 &feature_spm,
2785 &feature_addsubiw,
2786 &feature_avr5,
2787 },
2788};
2789
2790pub const cpu_atmega6450a = Cpu{
2791 .name = "atmega6450a",
2792 .llvm_name = "atmega6450a",
2793 .subfeatures = &[_]*const Feature {
2794 &feature_lpmx,
2795 &feature_jmpcall,
2796 &feature_ijmpcall,
2797 &feature_movw,
2798 &feature_sram,
2799 &feature_mul,
2800 &feature_avr0,
2801 &feature_lpm,
2802 &feature_break,
2803 &feature_spm,
2804 &feature_addsubiw,
2805 &feature_avr5,
2806 },
2807};
2808
2809pub const cpu_atmega6450p = Cpu{
2810 .name = "atmega6450p",
2811 .llvm_name = "atmega6450p",
2812 .subfeatures = &[_]*const Feature {
2813 &feature_lpmx,
2814 &feature_jmpcall,
2815 &feature_ijmpcall,
2816 &feature_movw,
2817 &feature_sram,
2818 &feature_mul,
2819 &feature_avr0,
2820 &feature_lpm,
2821 &feature_break,
2822 &feature_spm,
2823 &feature_addsubiw,
2824 &feature_avr5,
2825 },
2826};
2827
2828pub const cpu_atmega645a = Cpu{
2829 .name = "atmega645a",
2830 .llvm_name = "atmega645a",
2831 .subfeatures = &[_]*const Feature {
2832 &feature_lpmx,
2833 &feature_jmpcall,
2834 &feature_ijmpcall,
2835 &feature_movw,
2836 &feature_sram,
2837 &feature_mul,
2838 &feature_avr0,
2839 &feature_lpm,
2840 &feature_break,
2841 &feature_spm,
2842 &feature_addsubiw,
2843 &feature_avr5,
2844 },
2845};
2846
2847pub const cpu_atmega645p = Cpu{
2848 .name = "atmega645p",
2849 .llvm_name = "atmega645p",
2850 .subfeatures = &[_]*const Feature {
2851 &feature_lpmx,
2852 &feature_jmpcall,
2853 &feature_ijmpcall,
2854 &feature_movw,
2855 &feature_sram,
2856 &feature_mul,
2857 &feature_avr0,
2858 &feature_lpm,
2859 &feature_break,
2860 &feature_spm,
2861 &feature_addsubiw,
2862 &feature_avr5,
2863 },
2864};
2865
2866pub const cpu_atmega649 = Cpu{
2867 .name = "atmega649",
2868 .llvm_name = "atmega649",
2869 .subfeatures = &[_]*const Feature {
2870 &feature_lpmx,
2871 &feature_jmpcall,
2872 &feature_ijmpcall,
2873 &feature_movw,
2874 &feature_sram,
2875 &feature_mul,
2876 &feature_avr0,
2877 &feature_lpm,
2878 &feature_break,
2879 &feature_spm,
2880 &feature_addsubiw,
2881 &feature_avr5,
2882 },
2883};
2884
2885pub const cpu_atmega6490 = Cpu{
2886 .name = "atmega6490",
2887 .llvm_name = "atmega6490",
2888 .subfeatures = &[_]*const Feature {
2889 &feature_lpmx,
2890 &feature_jmpcall,
2891 &feature_ijmpcall,
2892 &feature_movw,
2893 &feature_sram,
2894 &feature_mul,
2895 &feature_avr0,
2896 &feature_lpm,
2897 &feature_break,
2898 &feature_spm,
2899 &feature_addsubiw,
2900 &feature_avr5,
2901 },
2902};
2903
2904pub const cpu_atmega6490a = Cpu{
2905 .name = "atmega6490a",
2906 .llvm_name = "atmega6490a",
2907 .subfeatures = &[_]*const Feature {
2908 &feature_lpmx,
2909 &feature_jmpcall,
2910 &feature_ijmpcall,
2911 &feature_movw,
2912 &feature_sram,
2913 &feature_mul,
2914 &feature_avr0,
2915 &feature_lpm,
2916 &feature_break,
2917 &feature_spm,
2918 &feature_addsubiw,
2919 &feature_avr5,
2920 },
2921};
2922
2923pub const cpu_atmega6490p = Cpu{
2924 .name = "atmega6490p",
2925 .llvm_name = "atmega6490p",
2926 .subfeatures = &[_]*const Feature {
2927 &feature_lpmx,
2928 &feature_jmpcall,
2929 &feature_ijmpcall,
2930 &feature_movw,
2931 &feature_sram,
2932 &feature_mul,
2933 &feature_avr0,
2934 &feature_lpm,
2935 &feature_break,
2936 &feature_spm,
2937 &feature_addsubiw,
2938 &feature_avr5,
2939 },
2940};
2941
2942pub const cpu_atmega649a = Cpu{
2943 .name = "atmega649a",
2944 .llvm_name = "atmega649a",
2945 .subfeatures = &[_]*const Feature {
2946 &feature_lpmx,
2947 &feature_jmpcall,
2948 &feature_ijmpcall,
2949 &feature_movw,
2950 &feature_sram,
2951 &feature_mul,
2952 &feature_avr0,
2953 &feature_lpm,
2954 &feature_break,
2955 &feature_spm,
2956 &feature_addsubiw,
2957 &feature_avr5,
2958 },
2959};
2960
2961pub const cpu_atmega649p = Cpu{
2962 .name = "atmega649p",
2963 .llvm_name = "atmega649p",
2964 .subfeatures = &[_]*const Feature {
2965 &feature_lpmx,
2966 &feature_jmpcall,
2967 &feature_ijmpcall,
2968 &feature_movw,
2969 &feature_sram,
2970 &feature_mul,
2971 &feature_avr0,
2972 &feature_lpm,
2973 &feature_break,
2974 &feature_spm,
2975 &feature_addsubiw,
2976 &feature_avr5,
2977 },
2978};
2979
2980pub const cpu_atmega64a = Cpu{
2981 .name = "atmega64a",
2982 .llvm_name = "atmega64a",
2983 .subfeatures = &[_]*const Feature {
2984 &feature_lpmx,
2985 &feature_jmpcall,
2986 &feature_ijmpcall,
2987 &feature_movw,
2988 &feature_sram,
2989 &feature_mul,
2990 &feature_avr0,
2991 &feature_lpm,
2992 &feature_break,
2993 &feature_spm,
2994 &feature_addsubiw,
2995 &feature_avr5,
2996 },
2997};
2998
2999pub const cpu_atmega64c1 = Cpu{
3000 .name = "atmega64c1",
3001 .llvm_name = "atmega64c1",
3002 .subfeatures = &[_]*const Feature {
3003 &feature_lpmx,
3004 &feature_jmpcall,
3005 &feature_ijmpcall,
3006 &feature_movw,
3007 &feature_sram,
3008 &feature_mul,
3009 &feature_avr0,
3010 &feature_lpm,
3011 &feature_break,
3012 &feature_spm,
3013 &feature_addsubiw,
3014 &feature_avr5,
3015 },
3016};
3017
3018pub const cpu_atmega64hve = Cpu{
3019 .name = "atmega64hve",
3020 .llvm_name = "atmega64hve",
3021 .subfeatures = &[_]*const Feature {
3022 &feature_lpmx,
3023 &feature_jmpcall,
3024 &feature_ijmpcall,
3025 &feature_movw,
3026 &feature_sram,
3027 &feature_mul,
3028 &feature_avr0,
3029 &feature_lpm,
3030 &feature_break,
3031 &feature_spm,
3032 &feature_addsubiw,
3033 &feature_avr5,
3034 },
3035};
3036
3037pub const cpu_atmega64m1 = Cpu{
3038 .name = "atmega64m1",
3039 .llvm_name = "atmega64m1",
3040 .subfeatures = &[_]*const Feature {
3041 &feature_lpmx,
3042 &feature_jmpcall,
3043 &feature_ijmpcall,
3044 &feature_movw,
3045 &feature_sram,
3046 &feature_mul,
3047 &feature_avr0,
3048 &feature_lpm,
3049 &feature_break,
3050 &feature_spm,
3051 &feature_addsubiw,
3052 &feature_avr5,
3053 },
3054};
3055
3056pub const cpu_atmega64rfr2 = Cpu{
3057 .name = "atmega64rfr2",
3058 .llvm_name = "atmega64rfr2",
3059 .subfeatures = &[_]*const Feature {
3060 &feature_lpmx,
3061 &feature_jmpcall,
3062 &feature_ijmpcall,
3063 &feature_movw,
3064 &feature_sram,
3065 &feature_mul,
3066 &feature_avr0,
3067 &feature_lpm,
3068 &feature_break,
3069 &feature_spm,
3070 &feature_addsubiw,
3071 &feature_avr5,
3072 },
3073};
3074
3075pub const cpu_atmega8 = Cpu{
3076 .name = "atmega8",
3077 .llvm_name = "atmega8",
3078 .subfeatures = &[_]*const Feature {
3079 &feature_lpmx,
3080 &feature_ijmpcall,
3081 &feature_movw,
3082 &feature_sram,
3083 &feature_mul,
3084 &feature_avr0,
3085 &feature_lpm,
3086 &feature_break,
3087 &feature_spm,
3088 &feature_addsubiw,
3089 &feature_avr4,
3090 },
3091};
3092
3093pub const cpu_atmega8515 = Cpu{
3094 .name = "atmega8515",
3095 .llvm_name = "atmega8515",
3096 .subfeatures = &[_]*const Feature {
3097 &feature_ijmpcall,
3098 &feature_sram,
3099 &feature_avr0,
3100 &feature_lpm,
3101 &feature_addsubiw,
3102 &feature_avr2,
3103 &feature_lpmx,
3104 &feature_movw,
3105 &feature_mul,
3106 &feature_spm,
3107 },
3108};
3109
3110pub const cpu_atmega8535 = Cpu{
3111 .name = "atmega8535",
3112 .llvm_name = "atmega8535",
3113 .subfeatures = &[_]*const Feature {
3114 &feature_ijmpcall,
3115 &feature_sram,
3116 &feature_avr0,
3117 &feature_lpm,
3118 &feature_addsubiw,
3119 &feature_avr2,
3120 &feature_lpmx,
3121 &feature_movw,
3122 &feature_mul,
3123 &feature_spm,
3124 },
3125};
3126
3127pub const cpu_atmega88 = Cpu{
3128 .name = "atmega88",
3129 .llvm_name = "atmega88",
3130 .subfeatures = &[_]*const Feature {
3131 &feature_lpmx,
3132 &feature_ijmpcall,
3133 &feature_movw,
3134 &feature_sram,
3135 &feature_mul,
3136 &feature_avr0,
3137 &feature_lpm,
3138 &feature_break,
3139 &feature_spm,
3140 &feature_addsubiw,
3141 &feature_avr4,
3142 },
3143};
3144
3145pub const cpu_atmega88a = Cpu{
3146 .name = "atmega88a",
3147 .llvm_name = "atmega88a",
3148 .subfeatures = &[_]*const Feature {
3149 &feature_lpmx,
3150 &feature_ijmpcall,
3151 &feature_movw,
3152 &feature_sram,
3153 &feature_mul,
3154 &feature_avr0,
3155 &feature_lpm,
3156 &feature_break,
3157 &feature_spm,
3158 &feature_addsubiw,
3159 &feature_avr4,
3160 },
3161};
3162
3163pub const cpu_atmega88p = Cpu{
3164 .name = "atmega88p",
3165 .llvm_name = "atmega88p",
3166 .subfeatures = &[_]*const Feature {
3167 &feature_lpmx,
3168 &feature_ijmpcall,
3169 &feature_movw,
3170 &feature_sram,
3171 &feature_mul,
3172 &feature_avr0,
3173 &feature_lpm,
3174 &feature_break,
3175 &feature_spm,
3176 &feature_addsubiw,
3177 &feature_avr4,
3178 },
3179};
3180
3181pub const cpu_atmega88pa = Cpu{
3182 .name = "atmega88pa",
3183 .llvm_name = "atmega88pa",
3184 .subfeatures = &[_]*const Feature {
3185 &feature_lpmx,
3186 &feature_ijmpcall,
3187 &feature_movw,
3188 &feature_sram,
3189 &feature_mul,
3190 &feature_avr0,
3191 &feature_lpm,
3192 &feature_break,
3193 &feature_spm,
3194 &feature_addsubiw,
3195 &feature_avr4,
3196 },
3197};
3198
3199pub const cpu_atmega8a = Cpu{
3200 .name = "atmega8a",
3201 .llvm_name = "atmega8a",
3202 .subfeatures = &[_]*const Feature {
3203 &feature_lpmx,
3204 &feature_ijmpcall,
3205 &feature_movw,
3206 &feature_sram,
3207 &feature_mul,
3208 &feature_avr0,
3209 &feature_lpm,
3210 &feature_break,
3211 &feature_spm,
3212 &feature_addsubiw,
3213 &feature_avr4,
3214 },
3215};
3216
3217pub const cpu_atmega8hva = Cpu{
3218 .name = "atmega8hva",
3219 .llvm_name = "atmega8hva",
3220 .subfeatures = &[_]*const Feature {
3221 &feature_lpmx,
3222 &feature_ijmpcall,
3223 &feature_movw,
3224 &feature_sram,
3225 &feature_mul,
3226 &feature_avr0,
3227 &feature_lpm,
3228 &feature_break,
3229 &feature_spm,
3230 &feature_addsubiw,
3231 &feature_avr4,
3232 },
3233};
3234
3235pub const cpu_atmega8u2 = Cpu{
3236 .name = "atmega8u2",
3237 .llvm_name = "atmega8u2",
3238 .subfeatures = &[_]*const Feature {
3239 &feature_lpmx,
3240 &feature_jmpcall,
3241 &feature_ijmpcall,
3242 &feature_movw,
3243 &feature_sram,
3244 &feature_avr0,
3245 &feature_lpm,
3246 &feature_break,
3247 &feature_spm,
3248 &feature_addsubiw,
3249 &feature_avr35,
3250 },
3251};
3252
3253pub const cpu_attiny10 = Cpu{
3254 .name = "attiny10",
3255 .llvm_name = "attiny10",
3256 .subfeatures = &[_]*const Feature {
3257 &feature_tinyencoding,
3258 &feature_sram,
3259 &feature_break,
3260 &feature_avr0,
3261 &feature_avrtiny,
3262 },
3263};
3264
3265pub const cpu_attiny102 = Cpu{
3266 .name = "attiny102",
3267 .llvm_name = "attiny102",
3268 .subfeatures = &[_]*const Feature {
3269 &feature_tinyencoding,
3270 &feature_sram,
3271 &feature_break,
3272 &feature_avr0,
3273 &feature_avrtiny,
3274 },
3275};
3276
3277pub const cpu_attiny104 = Cpu{
3278 .name = "attiny104",
3279 .llvm_name = "attiny104",
3280 .subfeatures = &[_]*const Feature {
3281 &feature_tinyencoding,
3282 &feature_sram,
3283 &feature_break,
3284 &feature_avr0,
3285 &feature_avrtiny,
3286 },
3287};
3288
3289pub const cpu_attiny11 = Cpu{
3290 .name = "attiny11",
3291 .llvm_name = "attiny11",
3292 .subfeatures = &[_]*const Feature {
3293 &feature_avr0,
3294 &feature_lpm,
3295 &feature_avr1,
3296 },
3297};
3298
3299pub const cpu_attiny12 = Cpu{
3300 .name = "attiny12",
3301 .llvm_name = "attiny12",
3302 .subfeatures = &[_]*const Feature {
3303 &feature_avr0,
3304 &feature_lpm,
3305 &feature_avr1,
3306 },
3307};
3308
3309pub const cpu_attiny13 = Cpu{
3310 .name = "attiny13",
3311 .llvm_name = "attiny13",
3312 .subfeatures = &[_]*const Feature {
3313 &feature_lpmx,
3314 &feature_ijmpcall,
3315 &feature_movw,
3316 &feature_sram,
3317 &feature_avr0,
3318 &feature_lpm,
3319 &feature_break,
3320 &feature_spm,
3321 &feature_addsubiw,
3322 &feature_avr25,
3323 },
3324};
3325
3326pub const cpu_attiny13a = Cpu{
3327 .name = "attiny13a",
3328 .llvm_name = "attiny13a",
3329 .subfeatures = &[_]*const Feature {
3330 &feature_lpmx,
3331 &feature_ijmpcall,
3332 &feature_movw,
3333 &feature_sram,
3334 &feature_avr0,
3335 &feature_lpm,
3336 &feature_break,
3337 &feature_spm,
3338 &feature_addsubiw,
3339 &feature_avr25,
3340 },
3341};
3342
3343pub const cpu_attiny15 = Cpu{
3344 .name = "attiny15",
3345 .llvm_name = "attiny15",
3346 .subfeatures = &[_]*const Feature {
3347 &feature_avr0,
3348 &feature_lpm,
3349 &feature_avr1,
3350 },
3351};
3352
3353pub const cpu_attiny1634 = Cpu{
3354 .name = "attiny1634",
3355 .llvm_name = "attiny1634",
3356 .subfeatures = &[_]*const Feature {
3357 &feature_lpmx,
3358 &feature_jmpcall,
3359 &feature_ijmpcall,
3360 &feature_movw,
3361 &feature_sram,
3362 &feature_avr0,
3363 &feature_lpm,
3364 &feature_break,
3365 &feature_spm,
3366 &feature_addsubiw,
3367 &feature_avr35,
3368 },
3369};
3370
3371pub const cpu_attiny167 = Cpu{
3372 .name = "attiny167",
3373 .llvm_name = "attiny167",
3374 .subfeatures = &[_]*const Feature {
3375 &feature_lpmx,
3376 &feature_jmpcall,
3377 &feature_ijmpcall,
3378 &feature_movw,
3379 &feature_sram,
3380 &feature_avr0,
3381 &feature_lpm,
3382 &feature_break,
3383 &feature_spm,
3384 &feature_addsubiw,
3385 &feature_avr35,
3386 },
3387};
3388
3389pub const cpu_attiny20 = Cpu{
3390 .name = "attiny20",
3391 .llvm_name = "attiny20",
3392 .subfeatures = &[_]*const Feature {
3393 &feature_tinyencoding,
3394 &feature_sram,
3395 &feature_break,
3396 &feature_avr0,
3397 &feature_avrtiny,
3398 },
3399};
3400
3401pub const cpu_attiny22 = Cpu{
3402 .name = "attiny22",
3403 .llvm_name = "attiny22",
3404 .subfeatures = &[_]*const Feature {
3405 &feature_ijmpcall,
3406 &feature_sram,
3407 &feature_avr0,
3408 &feature_lpm,
3409 &feature_addsubiw,
3410 &feature_avr2,
3411 },
3412};
3413
3414pub const cpu_attiny2313 = Cpu{
3415 .name = "attiny2313",
3416 .llvm_name = "attiny2313",
3417 .subfeatures = &[_]*const Feature {
3418 &feature_lpmx,
3419 &feature_ijmpcall,
3420 &feature_movw,
3421 &feature_sram,
3422 &feature_avr0,
3423 &feature_lpm,
3424 &feature_break,
3425 &feature_spm,
3426 &feature_addsubiw,
3427 &feature_avr25,
3428 },
3429};
3430
3431pub const cpu_attiny2313a = Cpu{
3432 .name = "attiny2313a",
3433 .llvm_name = "attiny2313a",
3434 .subfeatures = &[_]*const Feature {
3435 &feature_lpmx,
3436 &feature_ijmpcall,
3437 &feature_movw,
3438 &feature_sram,
3439 &feature_avr0,
3440 &feature_lpm,
3441 &feature_break,
3442 &feature_spm,
3443 &feature_addsubiw,
3444 &feature_avr25,
3445 },
3446};
3447
3448pub const cpu_attiny24 = Cpu{
3449 .name = "attiny24",
3450 .llvm_name = "attiny24",
3451 .subfeatures = &[_]*const Feature {
3452 &feature_lpmx,
3453 &feature_ijmpcall,
3454 &feature_movw,
3455 &feature_sram,
3456 &feature_avr0,
3457 &feature_lpm,
3458 &feature_break,
3459 &feature_spm,
3460 &feature_addsubiw,
3461 &feature_avr25,
3462 },
3463};
3464
3465pub const cpu_attiny24a = Cpu{
3466 .name = "attiny24a",
3467 .llvm_name = "attiny24a",
3468 .subfeatures = &[_]*const Feature {
3469 &feature_lpmx,
3470 &feature_ijmpcall,
3471 &feature_movw,
3472 &feature_sram,
3473 &feature_avr0,
3474 &feature_lpm,
3475 &feature_break,
3476 &feature_spm,
3477 &feature_addsubiw,
3478 &feature_avr25,
3479 },
3480};
3481
3482pub const cpu_attiny25 = Cpu{
3483 .name = "attiny25",
3484 .llvm_name = "attiny25",
3485 .subfeatures = &[_]*const Feature {
3486 &feature_lpmx,
3487 &feature_ijmpcall,
3488 &feature_movw,
3489 &feature_sram,
3490 &feature_avr0,
3491 &feature_lpm,
3492 &feature_break,
3493 &feature_spm,
3494 &feature_addsubiw,
3495 &feature_avr25,
3496 },
3497};
3498
3499pub const cpu_attiny26 = Cpu{
3500 .name = "attiny26",
3501 .llvm_name = "attiny26",
3502 .subfeatures = &[_]*const Feature {
3503 &feature_ijmpcall,
3504 &feature_sram,
3505 &feature_avr0,
3506 &feature_lpm,
3507 &feature_addsubiw,
3508 &feature_avr2,
3509 &feature_lpmx,
3510 },
3511};
3512
3513pub const cpu_attiny261 = Cpu{
3514 .name = "attiny261",
3515 .llvm_name = "attiny261",
3516 .subfeatures = &[_]*const Feature {
3517 &feature_lpmx,
3518 &feature_ijmpcall,
3519 &feature_movw,
3520 &feature_sram,
3521 &feature_avr0,
3522 &feature_lpm,
3523 &feature_break,
3524 &feature_spm,
3525 &feature_addsubiw,
3526 &feature_avr25,
3527 },
3528};
3529
3530pub const cpu_attiny261a = Cpu{
3531 .name = "attiny261a",
3532 .llvm_name = "attiny261a",
3533 .subfeatures = &[_]*const Feature {
3534 &feature_lpmx,
3535 &feature_ijmpcall,
3536 &feature_movw,
3537 &feature_sram,
3538 &feature_avr0,
3539 &feature_lpm,
3540 &feature_break,
3541 &feature_spm,
3542 &feature_addsubiw,
3543 &feature_avr25,
3544 },
3545};
3546
3547pub const cpu_attiny28 = Cpu{
3548 .name = "attiny28",
3549 .llvm_name = "attiny28",
3550 .subfeatures = &[_]*const Feature {
3551 &feature_avr0,
3552 &feature_lpm,
3553 &feature_avr1,
3554 },
3555};
3556
3557pub const cpu_attiny4 = Cpu{
3558 .name = "attiny4",
3559 .llvm_name = "attiny4",
3560 .subfeatures = &[_]*const Feature {
3561 &feature_tinyencoding,
3562 &feature_sram,
3563 &feature_break,
3564 &feature_avr0,
3565 &feature_avrtiny,
3566 },
3567};
3568
3569pub const cpu_attiny40 = Cpu{
3570 .name = "attiny40",
3571 .llvm_name = "attiny40",
3572 .subfeatures = &[_]*const Feature {
3573 &feature_tinyencoding,
3574 &feature_sram,
3575 &feature_break,
3576 &feature_avr0,
3577 &feature_avrtiny,
3578 },
3579};
3580
3581pub const cpu_attiny4313 = Cpu{
3582 .name = "attiny4313",
3583 .llvm_name = "attiny4313",
3584 .subfeatures = &[_]*const Feature {
3585 &feature_lpmx,
3586 &feature_ijmpcall,
3587 &feature_movw,
3588 &feature_sram,
3589 &feature_avr0,
3590 &feature_lpm,
3591 &feature_break,
3592 &feature_spm,
3593 &feature_addsubiw,
3594 &feature_avr25,
3595 },
3596};
3597
3598pub const cpu_attiny43u = Cpu{
3599 .name = "attiny43u",
3600 .llvm_name = "attiny43u",
3601 .subfeatures = &[_]*const Feature {
3602 &feature_lpmx,
3603 &feature_ijmpcall,
3604 &feature_movw,
3605 &feature_sram,
3606 &feature_avr0,
3607 &feature_lpm,
3608 &feature_break,
3609 &feature_spm,
3610 &feature_addsubiw,
3611 &feature_avr25,
3612 },
3613};
3614
3615pub const cpu_attiny44 = Cpu{
3616 .name = "attiny44",
3617 .llvm_name = "attiny44",
3618 .subfeatures = &[_]*const Feature {
3619 &feature_lpmx,
3620 &feature_ijmpcall,
3621 &feature_movw,
3622 &feature_sram,
3623 &feature_avr0,
3624 &feature_lpm,
3625 &feature_break,
3626 &feature_spm,
3627 &feature_addsubiw,
3628 &feature_avr25,
3629 },
3630};
3631
3632pub const cpu_attiny44a = Cpu{
3633 .name = "attiny44a",
3634 .llvm_name = "attiny44a",
3635 .subfeatures = &[_]*const Feature {
3636 &feature_lpmx,
3637 &feature_ijmpcall,
3638 &feature_movw,
3639 &feature_sram,
3640 &feature_avr0,
3641 &feature_lpm,
3642 &feature_break,
3643 &feature_spm,
3644 &feature_addsubiw,
3645 &feature_avr25,
3646 },
3647};
3648
3649pub const cpu_attiny45 = Cpu{
3650 .name = "attiny45",
3651 .llvm_name = "attiny45",
3652 .subfeatures = &[_]*const Feature {
3653 &feature_lpmx,
3654 &feature_ijmpcall,
3655 &feature_movw,
3656 &feature_sram,
3657 &feature_avr0,
3658 &feature_lpm,
3659 &feature_break,
3660 &feature_spm,
3661 &feature_addsubiw,
3662 &feature_avr25,
3663 },
3664};
3665
3666pub const cpu_attiny461 = Cpu{
3667 .name = "attiny461",
3668 .llvm_name = "attiny461",
3669 .subfeatures = &[_]*const Feature {
3670 &feature_lpmx,
3671 &feature_ijmpcall,
3672 &feature_movw,
3673 &feature_sram,
3674 &feature_avr0,
3675 &feature_lpm,
3676 &feature_break,
3677 &feature_spm,
3678 &feature_addsubiw,
3679 &feature_avr25,
3680 },
3681};
3682
3683pub const cpu_attiny461a = Cpu{
3684 .name = "attiny461a",
3685 .llvm_name = "attiny461a",
3686 .subfeatures = &[_]*const Feature {
3687 &feature_lpmx,
3688 &feature_ijmpcall,
3689 &feature_movw,
3690 &feature_sram,
3691 &feature_avr0,
3692 &feature_lpm,
3693 &feature_break,
3694 &feature_spm,
3695 &feature_addsubiw,
3696 &feature_avr25,
3697 },
3698};
3699
3700pub const cpu_attiny48 = Cpu{
3701 .name = "attiny48",
3702 .llvm_name = "attiny48",
3703 .subfeatures = &[_]*const Feature {
3704 &feature_lpmx,
3705 &feature_ijmpcall,
3706 &feature_movw,
3707 &feature_sram,
3708 &feature_avr0,
3709 &feature_lpm,
3710 &feature_break,
3711 &feature_spm,
3712 &feature_addsubiw,
3713 &feature_avr25,
3714 },
3715};
3716
3717pub const cpu_attiny5 = Cpu{
3718 .name = "attiny5",
3719 .llvm_name = "attiny5",
3720 .subfeatures = &[_]*const Feature {
3721 &feature_tinyencoding,
3722 &feature_sram,
3723 &feature_break,
3724 &feature_avr0,
3725 &feature_avrtiny,
3726 },
3727};
3728
3729pub const cpu_attiny828 = Cpu{
3730 .name = "attiny828",
3731 .llvm_name = "attiny828",
3732 .subfeatures = &[_]*const Feature {
3733 &feature_lpmx,
3734 &feature_ijmpcall,
3735 &feature_movw,
3736 &feature_sram,
3737 &feature_avr0,
3738 &feature_lpm,
3739 &feature_break,
3740 &feature_spm,
3741 &feature_addsubiw,
3742 &feature_avr25,
3743 },
3744};
3745
3746pub const cpu_attiny84 = Cpu{
3747 .name = "attiny84",
3748 .llvm_name = "attiny84",
3749 .subfeatures = &[_]*const Feature {
3750 &feature_lpmx,
3751 &feature_ijmpcall,
3752 &feature_movw,
3753 &feature_sram,
3754 &feature_avr0,
3755 &feature_lpm,
3756 &feature_break,
3757 &feature_spm,
3758 &feature_addsubiw,
3759 &feature_avr25,
3760 },
3761};
3762
3763pub const cpu_attiny84a = Cpu{
3764 .name = "attiny84a",
3765 .llvm_name = "attiny84a",
3766 .subfeatures = &[_]*const Feature {
3767 &feature_lpmx,
3768 &feature_ijmpcall,
3769 &feature_movw,
3770 &feature_sram,
3771 &feature_avr0,
3772 &feature_lpm,
3773 &feature_break,
3774 &feature_spm,
3775 &feature_addsubiw,
3776 &feature_avr25,
3777 },
3778};
3779
3780pub const cpu_attiny85 = Cpu{
3781 .name = "attiny85",
3782 .llvm_name = "attiny85",
3783 .subfeatures = &[_]*const Feature {
3784 &feature_lpmx,
3785 &feature_ijmpcall,
3786 &feature_movw,
3787 &feature_sram,
3788 &feature_avr0,
3789 &feature_lpm,
3790 &feature_break,
3791 &feature_spm,
3792 &feature_addsubiw,
3793 &feature_avr25,
3794 },
3795};
3796
3797pub const cpu_attiny861 = Cpu{
3798 .name = "attiny861",
3799 .llvm_name = "attiny861",
3800 .subfeatures = &[_]*const Feature {
3801 &feature_lpmx,
3802 &feature_ijmpcall,
3803 &feature_movw,
3804 &feature_sram,
3805 &feature_avr0,
3806 &feature_lpm,
3807 &feature_break,
3808 &feature_spm,
3809 &feature_addsubiw,
3810 &feature_avr25,
3811 },
3812};
3813
3814pub const cpu_attiny861a = Cpu{
3815 .name = "attiny861a",
3816 .llvm_name = "attiny861a",
3817 .subfeatures = &[_]*const Feature {
3818 &feature_lpmx,
3819 &feature_ijmpcall,
3820 &feature_movw,
3821 &feature_sram,
3822 &feature_avr0,
3823 &feature_lpm,
3824 &feature_break,
3825 &feature_spm,
3826 &feature_addsubiw,
3827 &feature_avr25,
3828 },
3829};
3830
3831pub const cpu_attiny87 = Cpu{
3832 .name = "attiny87",
3833 .llvm_name = "attiny87",
3834 .subfeatures = &[_]*const Feature {
3835 &feature_lpmx,
3836 &feature_ijmpcall,
3837 &feature_movw,
3838 &feature_sram,
3839 &feature_avr0,
3840 &feature_lpm,
3841 &feature_break,
3842 &feature_spm,
3843 &feature_addsubiw,
3844 &feature_avr25,
3845 },
3846};
3847
3848pub const cpu_attiny88 = Cpu{
3849 .name = "attiny88",
3850 .llvm_name = "attiny88",
3851 .subfeatures = &[_]*const Feature {
3852 &feature_lpmx,
3853 &feature_ijmpcall,
3854 &feature_movw,
3855 &feature_sram,
3856 &feature_avr0,
3857 &feature_lpm,
3858 &feature_break,
3859 &feature_spm,
3860 &feature_addsubiw,
3861 &feature_avr25,
3862 },
3863};
3864
3865pub const cpu_attiny9 = Cpu{
3866 .name = "attiny9",
3867 .llvm_name = "attiny9",
3868 .subfeatures = &[_]*const Feature {
3869 &feature_tinyencoding,
3870 &feature_sram,
3871 &feature_break,
3872 &feature_avr0,
3873 &feature_avrtiny,
3874 },
3875};
3876
3877pub const cpu_atxmega128a1 = Cpu{
3878 .name = "atxmega128a1",
3879 .llvm_name = "atxmega128a1",
3880 .subfeatures = &[_]*const Feature {
3881 &feature_lpmx,
3882 &feature_jmpcall,
3883 &feature_ijmpcall,
3884 &feature_movw,
3885 &feature_sram,
3886 &feature_mul,
3887 &feature_avr0,
3888 &feature_spmx,
3889 &feature_lpm,
3890 &feature_eijmpcall,
3891 &feature_break,
3892 &feature_spm,
3893 &feature_elpmx,
3894 &feature_elpm,
3895 &feature_addsubiw,
3896 &feature_des,
3897 &feature_xmega,
3898 },
3899};
3900
3901pub const cpu_atxmega128a1u = Cpu{
3902 .name = "atxmega128a1u",
3903 .llvm_name = "atxmega128a1u",
3904 .subfeatures = &[_]*const Feature {
3905 &feature_lpmx,
3906 &feature_ijmpcall,
3907 &feature_jmpcall,
3908 &feature_movw,
3909 &feature_sram,
3910 &feature_mul,
3911 &feature_avr0,
3912 &feature_spmx,
3913 &feature_lpm,
3914 &feature_rmw,
3915 &feature_eijmpcall,
3916 &feature_break,
3917 &feature_spm,
3918 &feature_elpmx,
3919 &feature_elpm,
3920 &feature_addsubiw,
3921 &feature_des,
3922 &feature_xmegau,
3923 },
3924};
3925
3926pub const cpu_atxmega128a3 = Cpu{
3927 .name = "atxmega128a3",
3928 .llvm_name = "atxmega128a3",
3929 .subfeatures = &[_]*const Feature {
3930 &feature_lpmx,
3931 &feature_jmpcall,
3932 &feature_ijmpcall,
3933 &feature_movw,
3934 &feature_sram,
3935 &feature_mul,
3936 &feature_avr0,
3937 &feature_spmx,
3938 &feature_lpm,
3939 &feature_eijmpcall,
3940 &feature_break,
3941 &feature_spm,
3942 &feature_elpmx,
3943 &feature_elpm,
3944 &feature_addsubiw,
3945 &feature_des,
3946 &feature_xmega,
3947 },
3948};
3949
3950pub const cpu_atxmega128a3u = Cpu{
3951 .name = "atxmega128a3u",
3952 .llvm_name = "atxmega128a3u",
3953 .subfeatures = &[_]*const Feature {
3954 &feature_lpmx,
3955 &feature_ijmpcall,
3956 &feature_jmpcall,
3957 &feature_movw,
3958 &feature_sram,
3959 &feature_mul,
3960 &feature_avr0,
3961 &feature_spmx,
3962 &feature_lpm,
3963 &feature_rmw,
3964 &feature_eijmpcall,
3965 &feature_break,
3966 &feature_spm,
3967 &feature_elpmx,
3968 &feature_elpm,
3969 &feature_addsubiw,
3970 &feature_des,
3971 &feature_xmegau,
3972 },
3973};
3974
3975pub const cpu_atxmega128a4u = Cpu{
3976 .name = "atxmega128a4u",
3977 .llvm_name = "atxmega128a4u",
3978 .subfeatures = &[_]*const Feature {
3979 &feature_lpmx,
3980 &feature_ijmpcall,
3981 &feature_jmpcall,
3982 &feature_movw,
3983 &feature_sram,
3984 &feature_mul,
3985 &feature_avr0,
3986 &feature_spmx,
3987 &feature_lpm,
3988 &feature_rmw,
3989 &feature_eijmpcall,
3990 &feature_break,
3991 &feature_spm,
3992 &feature_elpmx,
3993 &feature_elpm,
3994 &feature_addsubiw,
3995 &feature_des,
3996 &feature_xmegau,
3997 },
3998};
3999
4000pub const cpu_atxmega128b1 = Cpu{
4001 .name = "atxmega128b1",
4002 .llvm_name = "atxmega128b1",
4003 .subfeatures = &[_]*const Feature {
4004 &feature_lpmx,
4005 &feature_ijmpcall,
4006 &feature_jmpcall,
4007 &feature_movw,
4008 &feature_sram,
4009 &feature_mul,
4010 &feature_avr0,
4011 &feature_spmx,
4012 &feature_lpm,
4013 &feature_rmw,
4014 &feature_eijmpcall,
4015 &feature_break,
4016 &feature_spm,
4017 &feature_elpmx,
4018 &feature_elpm,
4019 &feature_addsubiw,
4020 &feature_des,
4021 &feature_xmegau,
4022 },
4023};
4024
4025pub const cpu_atxmega128b3 = Cpu{
4026 .name = "atxmega128b3",
4027 .llvm_name = "atxmega128b3",
4028 .subfeatures = &[_]*const Feature {
4029 &feature_lpmx,
4030 &feature_ijmpcall,
4031 &feature_jmpcall,
4032 &feature_movw,
4033 &feature_sram,
4034 &feature_mul,
4035 &feature_avr0,
4036 &feature_spmx,
4037 &feature_lpm,
4038 &feature_rmw,
4039 &feature_eijmpcall,
4040 &feature_break,
4041 &feature_spm,
4042 &feature_elpmx,
4043 &feature_elpm,
4044 &feature_addsubiw,
4045 &feature_des,
4046 &feature_xmegau,
4047 },
4048};
4049
4050pub const cpu_atxmega128c3 = Cpu{
4051 .name = "atxmega128c3",
4052 .llvm_name = "atxmega128c3",
4053 .subfeatures = &[_]*const Feature {
4054 &feature_lpmx,
4055 &feature_ijmpcall,
4056 &feature_jmpcall,
4057 &feature_movw,
4058 &feature_sram,
4059 &feature_mul,
4060 &feature_avr0,
4061 &feature_spmx,
4062 &feature_lpm,
4063 &feature_rmw,
4064 &feature_eijmpcall,
4065 &feature_break,
4066 &feature_spm,
4067 &feature_elpmx,
4068 &feature_elpm,
4069 &feature_addsubiw,
4070 &feature_des,
4071 &feature_xmegau,
4072 },
4073};
4074
4075pub const cpu_atxmega128d3 = Cpu{
4076 .name = "atxmega128d3",
4077 .llvm_name = "atxmega128d3",
4078 .subfeatures = &[_]*const Feature {
4079 &feature_lpmx,
4080 &feature_jmpcall,
4081 &feature_ijmpcall,
4082 &feature_movw,
4083 &feature_sram,
4084 &feature_mul,
4085 &feature_avr0,
4086 &feature_spmx,
4087 &feature_lpm,
4088 &feature_eijmpcall,
4089 &feature_break,
4090 &feature_spm,
4091 &feature_elpmx,
4092 &feature_elpm,
4093 &feature_addsubiw,
4094 &feature_des,
4095 &feature_xmega,
4096 },
4097};
4098
4099pub const cpu_atxmega128d4 = Cpu{
4100 .name = "atxmega128d4",
4101 .llvm_name = "atxmega128d4",
4102 .subfeatures = &[_]*const Feature {
4103 &feature_lpmx,
4104 &feature_jmpcall,
4105 &feature_ijmpcall,
4106 &feature_movw,
4107 &feature_sram,
4108 &feature_mul,
4109 &feature_avr0,
4110 &feature_spmx,
4111 &feature_lpm,
4112 &feature_eijmpcall,
4113 &feature_break,
4114 &feature_spm,
4115 &feature_elpmx,
4116 &feature_elpm,
4117 &feature_addsubiw,
4118 &feature_des,
4119 &feature_xmega,
4120 },
4121};
4122
4123pub const cpu_atxmega16a4 = Cpu{
4124 .name = "atxmega16a4",
4125 .llvm_name = "atxmega16a4",
4126 .subfeatures = &[_]*const Feature {
4127 &feature_lpmx,
4128 &feature_jmpcall,
4129 &feature_ijmpcall,
4130 &feature_movw,
4131 &feature_sram,
4132 &feature_mul,
4133 &feature_avr0,
4134 &feature_spmx,
4135 &feature_lpm,
4136 &feature_eijmpcall,
4137 &feature_break,
4138 &feature_spm,
4139 &feature_elpmx,
4140 &feature_elpm,
4141 &feature_addsubiw,
4142 &feature_des,
4143 &feature_xmega,
4144 },
4145};
4146
4147pub const cpu_atxmega16a4u = Cpu{
4148 .name = "atxmega16a4u",
4149 .llvm_name = "atxmega16a4u",
4150 .subfeatures = &[_]*const Feature {
4151 &feature_lpmx,
4152 &feature_ijmpcall,
4153 &feature_jmpcall,
4154 &feature_movw,
4155 &feature_sram,
4156 &feature_mul,
4157 &feature_avr0,
4158 &feature_spmx,
4159 &feature_lpm,
4160 &feature_rmw,
4161 &feature_eijmpcall,
4162 &feature_break,
4163 &feature_spm,
4164 &feature_elpmx,
4165 &feature_elpm,
4166 &feature_addsubiw,
4167 &feature_des,
4168 &feature_xmegau,
4169 },
4170};
4171
4172pub const cpu_atxmega16c4 = Cpu{
4173 .name = "atxmega16c4",
4174 .llvm_name = "atxmega16c4",
4175 .subfeatures = &[_]*const Feature {
4176 &feature_lpmx,
4177 &feature_ijmpcall,
4178 &feature_jmpcall,
4179 &feature_movw,
4180 &feature_sram,
4181 &feature_mul,
4182 &feature_avr0,
4183 &feature_spmx,
4184 &feature_lpm,
4185 &feature_rmw,
4186 &feature_eijmpcall,
4187 &feature_break,
4188 &feature_spm,
4189 &feature_elpmx,
4190 &feature_elpm,
4191 &feature_addsubiw,
4192 &feature_des,
4193 &feature_xmegau,
4194 },
4195};
4196
4197pub const cpu_atxmega16d4 = Cpu{
4198 .name = "atxmega16d4",
4199 .llvm_name = "atxmega16d4",
4200 .subfeatures = &[_]*const Feature {
4201 &feature_lpmx,
4202 &feature_jmpcall,
4203 &feature_ijmpcall,
4204 &feature_movw,
4205 &feature_sram,
4206 &feature_mul,
4207 &feature_avr0,
4208 &feature_spmx,
4209 &feature_lpm,
4210 &feature_eijmpcall,
4211 &feature_break,
4212 &feature_spm,
4213 &feature_elpmx,
4214 &feature_elpm,
4215 &feature_addsubiw,
4216 &feature_des,
4217 &feature_xmega,
4218 },
4219};
4220
4221pub const cpu_atxmega16e5 = Cpu{
4222 .name = "atxmega16e5",
4223 .llvm_name = "atxmega16e5",
4224 .subfeatures = &[_]*const Feature {
4225 &feature_lpmx,
4226 &feature_jmpcall,
4227 &feature_ijmpcall,
4228 &feature_movw,
4229 &feature_sram,
4230 &feature_mul,
4231 &feature_avr0,
4232 &feature_spmx,
4233 &feature_lpm,
4234 &feature_eijmpcall,
4235 &feature_break,
4236 &feature_spm,
4237 &feature_elpmx,
4238 &feature_elpm,
4239 &feature_addsubiw,
4240 &feature_des,
4241 &feature_xmega,
4242 },
4243};
4244
4245pub const cpu_atxmega192a3 = Cpu{
4246 .name = "atxmega192a3",
4247 .llvm_name = "atxmega192a3",
4248 .subfeatures = &[_]*const Feature {
4249 &feature_lpmx,
4250 &feature_jmpcall,
4251 &feature_ijmpcall,
4252 &feature_movw,
4253 &feature_sram,
4254 &feature_mul,
4255 &feature_avr0,
4256 &feature_spmx,
4257 &feature_lpm,
4258 &feature_eijmpcall,
4259 &feature_break,
4260 &feature_spm,
4261 &feature_elpmx,
4262 &feature_elpm,
4263 &feature_addsubiw,
4264 &feature_des,
4265 &feature_xmega,
4266 },
4267};
4268
4269pub const cpu_atxmega192a3u = Cpu{
4270 .name = "atxmega192a3u",
4271 .llvm_name = "atxmega192a3u",
4272 .subfeatures = &[_]*const Feature {
4273 &feature_lpmx,
4274 &feature_ijmpcall,
4275 &feature_jmpcall,
4276 &feature_movw,
4277 &feature_sram,
4278 &feature_mul,
4279 &feature_avr0,
4280 &feature_spmx,
4281 &feature_lpm,
4282 &feature_rmw,
4283 &feature_eijmpcall,
4284 &feature_break,
4285 &feature_spm,
4286 &feature_elpmx,
4287 &feature_elpm,
4288 &feature_addsubiw,
4289 &feature_des,
4290 &feature_xmegau,
4291 },
4292};
4293
4294pub const cpu_atxmega192c3 = Cpu{
4295 .name = "atxmega192c3",
4296 .llvm_name = "atxmega192c3",
4297 .subfeatures = &[_]*const Feature {
4298 &feature_lpmx,
4299 &feature_ijmpcall,
4300 &feature_jmpcall,
4301 &feature_movw,
4302 &feature_sram,
4303 &feature_mul,
4304 &feature_avr0,
4305 &feature_spmx,
4306 &feature_lpm,
4307 &feature_rmw,
4308 &feature_eijmpcall,
4309 &feature_break,
4310 &feature_spm,
4311 &feature_elpmx,
4312 &feature_elpm,
4313 &feature_addsubiw,
4314 &feature_des,
4315 &feature_xmegau,
4316 },
4317};
4318
4319pub const cpu_atxmega192d3 = Cpu{
4320 .name = "atxmega192d3",
4321 .llvm_name = "atxmega192d3",
4322 .subfeatures = &[_]*const Feature {
4323 &feature_lpmx,
4324 &feature_jmpcall,
4325 &feature_ijmpcall,
4326 &feature_movw,
4327 &feature_sram,
4328 &feature_mul,
4329 &feature_avr0,
4330 &feature_spmx,
4331 &feature_lpm,
4332 &feature_eijmpcall,
4333 &feature_break,
4334 &feature_spm,
4335 &feature_elpmx,
4336 &feature_elpm,
4337 &feature_addsubiw,
4338 &feature_des,
4339 &feature_xmega,
4340 },
4341};
4342
4343pub const cpu_atxmega256a3 = Cpu{
4344 .name = "atxmega256a3",
4345 .llvm_name = "atxmega256a3",
4346 .subfeatures = &[_]*const Feature {
4347 &feature_lpmx,
4348 &feature_jmpcall,
4349 &feature_ijmpcall,
4350 &feature_movw,
4351 &feature_sram,
4352 &feature_mul,
4353 &feature_avr0,
4354 &feature_spmx,
4355 &feature_lpm,
4356 &feature_eijmpcall,
4357 &feature_break,
4358 &feature_spm,
4359 &feature_elpmx,
4360 &feature_elpm,
4361 &feature_addsubiw,
4362 &feature_des,
4363 &feature_xmega,
4364 },
4365};
4366
4367pub const cpu_atxmega256a3b = Cpu{
4368 .name = "atxmega256a3b",
4369 .llvm_name = "atxmega256a3b",
4370 .subfeatures = &[_]*const Feature {
4371 &feature_lpmx,
4372 &feature_jmpcall,
4373 &feature_ijmpcall,
4374 &feature_movw,
4375 &feature_sram,
4376 &feature_mul,
4377 &feature_avr0,
4378 &feature_spmx,
4379 &feature_lpm,
4380 &feature_eijmpcall,
4381 &feature_break,
4382 &feature_spm,
4383 &feature_elpmx,
4384 &feature_elpm,
4385 &feature_addsubiw,
4386 &feature_des,
4387 &feature_xmega,
4388 },
4389};
4390
4391pub const cpu_atxmega256a3bu = Cpu{
4392 .name = "atxmega256a3bu",
4393 .llvm_name = "atxmega256a3bu",
4394 .subfeatures = &[_]*const Feature {
4395 &feature_lpmx,
4396 &feature_ijmpcall,
4397 &feature_jmpcall,
4398 &feature_movw,
4399 &feature_sram,
4400 &feature_mul,
4401 &feature_avr0,
4402 &feature_spmx,
4403 &feature_lpm,
4404 &feature_rmw,
4405 &feature_eijmpcall,
4406 &feature_break,
4407 &feature_spm,
4408 &feature_elpmx,
4409 &feature_elpm,
4410 &feature_addsubiw,
4411 &feature_des,
4412 &feature_xmegau,
4413 },
4414};
4415
4416pub const cpu_atxmega256a3u = Cpu{
4417 .name = "atxmega256a3u",
4418 .llvm_name = "atxmega256a3u",
4419 .subfeatures = &[_]*const Feature {
4420 &feature_lpmx,
4421 &feature_ijmpcall,
4422 &feature_jmpcall,
4423 &feature_movw,
4424 &feature_sram,
4425 &feature_mul,
4426 &feature_avr0,
4427 &feature_spmx,
4428 &feature_lpm,
4429 &feature_rmw,
4430 &feature_eijmpcall,
4431 &feature_break,
4432 &feature_spm,
4433 &feature_elpmx,
4434 &feature_elpm,
4435 &feature_addsubiw,
4436 &feature_des,
4437 &feature_xmegau,
4438 },
4439};
4440
4441pub const cpu_atxmega256c3 = Cpu{
4442 .name = "atxmega256c3",
4443 .llvm_name = "atxmega256c3",
4444 .subfeatures = &[_]*const Feature {
4445 &feature_lpmx,
4446 &feature_ijmpcall,
4447 &feature_jmpcall,
4448 &feature_movw,
4449 &feature_sram,
4450 &feature_mul,
4451 &feature_avr0,
4452 &feature_spmx,
4453 &feature_lpm,
4454 &feature_rmw,
4455 &feature_eijmpcall,
4456 &feature_break,
4457 &feature_spm,
4458 &feature_elpmx,
4459 &feature_elpm,
4460 &feature_addsubiw,
4461 &feature_des,
4462 &feature_xmegau,
4463 },
4464};
4465
4466pub const cpu_atxmega256d3 = Cpu{
4467 .name = "atxmega256d3",
4468 .llvm_name = "atxmega256d3",
4469 .subfeatures = &[_]*const Feature {
4470 &feature_lpmx,
4471 &feature_jmpcall,
4472 &feature_ijmpcall,
4473 &feature_movw,
4474 &feature_sram,
4475 &feature_mul,
4476 &feature_avr0,
4477 &feature_spmx,
4478 &feature_lpm,
4479 &feature_eijmpcall,
4480 &feature_break,
4481 &feature_spm,
4482 &feature_elpmx,
4483 &feature_elpm,
4484 &feature_addsubiw,
4485 &feature_des,
4486 &feature_xmega,
4487 },
4488};
4489
4490pub const cpu_atxmega32a4 = Cpu{
4491 .name = "atxmega32a4",
4492 .llvm_name = "atxmega32a4",
4493 .subfeatures = &[_]*const Feature {
4494 &feature_lpmx,
4495 &feature_jmpcall,
4496 &feature_ijmpcall,
4497 &feature_movw,
4498 &feature_sram,
4499 &feature_mul,
4500 &feature_avr0,
4501 &feature_spmx,
4502 &feature_lpm,
4503 &feature_eijmpcall,
4504 &feature_break,
4505 &feature_spm,
4506 &feature_elpmx,
4507 &feature_elpm,
4508 &feature_addsubiw,
4509 &feature_des,
4510 &feature_xmega,
4511 },
4512};
4513
4514pub const cpu_atxmega32a4u = Cpu{
4515 .name = "atxmega32a4u",
4516 .llvm_name = "atxmega32a4u",
4517 .subfeatures = &[_]*const Feature {
4518 &feature_lpmx,
4519 &feature_ijmpcall,
4520 &feature_jmpcall,
4521 &feature_movw,
4522 &feature_sram,
4523 &feature_mul,
4524 &feature_avr0,
4525 &feature_spmx,
4526 &feature_lpm,
4527 &feature_rmw,
4528 &feature_eijmpcall,
4529 &feature_break,
4530 &feature_spm,
4531 &feature_elpmx,
4532 &feature_elpm,
4533 &feature_addsubiw,
4534 &feature_des,
4535 &feature_xmegau,
4536 },
4537};
4538
4539pub const cpu_atxmega32c4 = Cpu{
4540 .name = "atxmega32c4",
4541 .llvm_name = "atxmega32c4",
4542 .subfeatures = &[_]*const Feature {
4543 &feature_lpmx,
4544 &feature_ijmpcall,
4545 &feature_jmpcall,
4546 &feature_movw,
4547 &feature_sram,
4548 &feature_mul,
4549 &feature_avr0,
4550 &feature_spmx,
4551 &feature_lpm,
4552 &feature_rmw,
4553 &feature_eijmpcall,
4554 &feature_break,
4555 &feature_spm,
4556 &feature_elpmx,
4557 &feature_elpm,
4558 &feature_addsubiw,
4559 &feature_des,
4560 &feature_xmegau,
4561 },
4562};
4563
4564pub const cpu_atxmega32d4 = Cpu{
4565 .name = "atxmega32d4",
4566 .llvm_name = "atxmega32d4",
4567 .subfeatures = &[_]*const Feature {
4568 &feature_lpmx,
4569 &feature_jmpcall,
4570 &feature_ijmpcall,
4571 &feature_movw,
4572 &feature_sram,
4573 &feature_mul,
4574 &feature_avr0,
4575 &feature_spmx,
4576 &feature_lpm,
4577 &feature_eijmpcall,
4578 &feature_break,
4579 &feature_spm,
4580 &feature_elpmx,
4581 &feature_elpm,
4582 &feature_addsubiw,
4583 &feature_des,
4584 &feature_xmega,
4585 },
4586};
4587
4588pub const cpu_atxmega32e5 = Cpu{
4589 .name = "atxmega32e5",
4590 .llvm_name = "atxmega32e5",
4591 .subfeatures = &[_]*const Feature {
4592 &feature_lpmx,
4593 &feature_jmpcall,
4594 &feature_ijmpcall,
4595 &feature_movw,
4596 &feature_sram,
4597 &feature_mul,
4598 &feature_avr0,
4599 &feature_spmx,
4600 &feature_lpm,
4601 &feature_eijmpcall,
4602 &feature_break,
4603 &feature_spm,
4604 &feature_elpmx,
4605 &feature_elpm,
4606 &feature_addsubiw,
4607 &feature_des,
4608 &feature_xmega,
4609 },
4610};
4611
4612pub const cpu_atxmega32x1 = Cpu{
4613 .name = "atxmega32x1",
4614 .llvm_name = "atxmega32x1",
4615 .subfeatures = &[_]*const Feature {
4616 &feature_lpmx,
4617 &feature_jmpcall,
4618 &feature_ijmpcall,
4619 &feature_movw,
4620 &feature_sram,
4621 &feature_mul,
4622 &feature_avr0,
4623 &feature_spmx,
4624 &feature_lpm,
4625 &feature_eijmpcall,
4626 &feature_break,
4627 &feature_spm,
4628 &feature_elpmx,
4629 &feature_elpm,
4630 &feature_addsubiw,
4631 &feature_des,
4632 &feature_xmega,
4633 },
4634};
4635
4636pub const cpu_atxmega384c3 = Cpu{
4637 .name = "atxmega384c3",
4638 .llvm_name = "atxmega384c3",
4639 .subfeatures = &[_]*const Feature {
4640 &feature_lpmx,
4641 &feature_ijmpcall,
4642 &feature_jmpcall,
4643 &feature_movw,
4644 &feature_sram,
4645 &feature_mul,
4646 &feature_avr0,
4647 &feature_spmx,
4648 &feature_lpm,
4649 &feature_rmw,
4650 &feature_eijmpcall,
4651 &feature_break,
4652 &feature_spm,
4653 &feature_elpmx,
4654 &feature_elpm,
4655 &feature_addsubiw,
4656 &feature_des,
4657 &feature_xmegau,
4658 },
4659};
4660
4661pub const cpu_atxmega384d3 = Cpu{
4662 .name = "atxmega384d3",
4663 .llvm_name = "atxmega384d3",
4664 .subfeatures = &[_]*const Feature {
4665 &feature_lpmx,
4666 &feature_jmpcall,
4667 &feature_ijmpcall,
4668 &feature_movw,
4669 &feature_sram,
4670 &feature_mul,
4671 &feature_avr0,
4672 &feature_spmx,
4673 &feature_lpm,
4674 &feature_eijmpcall,
4675 &feature_break,
4676 &feature_spm,
4677 &feature_elpmx,
4678 &feature_elpm,
4679 &feature_addsubiw,
4680 &feature_des,
4681 &feature_xmega,
4682 },
4683};
4684
4685pub const cpu_atxmega64a1 = Cpu{
4686 .name = "atxmega64a1",
4687 .llvm_name = "atxmega64a1",
4688 .subfeatures = &[_]*const Feature {
4689 &feature_lpmx,
4690 &feature_jmpcall,
4691 &feature_ijmpcall,
4692 &feature_movw,
4693 &feature_sram,
4694 &feature_mul,
4695 &feature_avr0,
4696 &feature_spmx,
4697 &feature_lpm,
4698 &feature_eijmpcall,
4699 &feature_break,
4700 &feature_spm,
4701 &feature_elpmx,
4702 &feature_elpm,
4703 &feature_addsubiw,
4704 &feature_des,
4705 &feature_xmega,
4706 },
4707};
4708
4709pub const cpu_atxmega64a1u = Cpu{
4710 .name = "atxmega64a1u",
4711 .llvm_name = "atxmega64a1u",
4712 .subfeatures = &[_]*const Feature {
4713 &feature_lpmx,
4714 &feature_ijmpcall,
4715 &feature_jmpcall,
4716 &feature_movw,
4717 &feature_sram,
4718 &feature_mul,
4719 &feature_avr0,
4720 &feature_spmx,
4721 &feature_lpm,
4722 &feature_rmw,
4723 &feature_eijmpcall,
4724 &feature_break,
4725 &feature_spm,
4726 &feature_elpmx,
4727 &feature_elpm,
4728 &feature_addsubiw,
4729 &feature_des,
4730 &feature_xmegau,
4731 },
4732};
4733
4734pub const cpu_atxmega64a3 = Cpu{
4735 .name = "atxmega64a3",
4736 .llvm_name = "atxmega64a3",
4737 .subfeatures = &[_]*const Feature {
4738 &feature_lpmx,
4739 &feature_jmpcall,
4740 &feature_ijmpcall,
4741 &feature_movw,
4742 &feature_sram,
4743 &feature_mul,
4744 &feature_avr0,
4745 &feature_spmx,
4746 &feature_lpm,
4747 &feature_eijmpcall,
4748 &feature_break,
4749 &feature_spm,
4750 &feature_elpmx,
4751 &feature_elpm,
4752 &feature_addsubiw,
4753 &feature_des,
4754 &feature_xmega,
4755 },
4756};
4757
4758pub const cpu_atxmega64a3u = Cpu{
4759 .name = "atxmega64a3u",
4760 .llvm_name = "atxmega64a3u",
4761 .subfeatures = &[_]*const Feature {
4762 &feature_lpmx,
4763 &feature_ijmpcall,
4764 &feature_jmpcall,
4765 &feature_movw,
4766 &feature_sram,
4767 &feature_mul,
4768 &feature_avr0,
4769 &feature_spmx,
4770 &feature_lpm,
4771 &feature_rmw,
4772 &feature_eijmpcall,
4773 &feature_break,
4774 &feature_spm,
4775 &feature_elpmx,
4776 &feature_elpm,
4777 &feature_addsubiw,
4778 &feature_des,
4779 &feature_xmegau,
4780 },
4781};
4782
4783pub const cpu_atxmega64a4u = Cpu{
4784 .name = "atxmega64a4u",
4785 .llvm_name = "atxmega64a4u",
4786 .subfeatures = &[_]*const Feature {
4787 &feature_lpmx,
4788 &feature_ijmpcall,
4789 &feature_jmpcall,
4790 &feature_movw,
4791 &feature_sram,
4792 &feature_mul,
4793 &feature_avr0,
4794 &feature_spmx,
4795 &feature_lpm,
4796 &feature_rmw,
4797 &feature_eijmpcall,
4798 &feature_break,
4799 &feature_spm,
4800 &feature_elpmx,
4801 &feature_elpm,
4802 &feature_addsubiw,
4803 &feature_des,
4804 &feature_xmegau,
4805 },
4806};
4807
4808pub const cpu_atxmega64b1 = Cpu{
4809 .name = "atxmega64b1",
4810 .llvm_name = "atxmega64b1",
4811 .subfeatures = &[_]*const Feature {
4812 &feature_lpmx,
4813 &feature_ijmpcall,
4814 &feature_jmpcall,
4815 &feature_movw,
4816 &feature_sram,
4817 &feature_mul,
4818 &feature_avr0,
4819 &feature_spmx,
4820 &feature_lpm,
4821 &feature_rmw,
4822 &feature_eijmpcall,
4823 &feature_break,
4824 &feature_spm,
4825 &feature_elpmx,
4826 &feature_elpm,
4827 &feature_addsubiw,
4828 &feature_des,
4829 &feature_xmegau,
4830 },
4831};
4832
4833pub const cpu_atxmega64b3 = Cpu{
4834 .name = "atxmega64b3",
4835 .llvm_name = "atxmega64b3",
4836 .subfeatures = &[_]*const Feature {
4837 &feature_lpmx,
4838 &feature_ijmpcall,
4839 &feature_jmpcall,
4840 &feature_movw,
4841 &feature_sram,
4842 &feature_mul,
4843 &feature_avr0,
4844 &feature_spmx,
4845 &feature_lpm,
4846 &feature_rmw,
4847 &feature_eijmpcall,
4848 &feature_break,
4849 &feature_spm,
4850 &feature_elpmx,
4851 &feature_elpm,
4852 &feature_addsubiw,
4853 &feature_des,
4854 &feature_xmegau,
4855 },
4856};
4857
4858pub const cpu_atxmega64c3 = Cpu{
4859 .name = "atxmega64c3",
4860 .llvm_name = "atxmega64c3",
4861 .subfeatures = &[_]*const Feature {
4862 &feature_lpmx,
4863 &feature_ijmpcall,
4864 &feature_jmpcall,
4865 &feature_movw,
4866 &feature_sram,
4867 &feature_mul,
4868 &feature_avr0,
4869 &feature_spmx,
4870 &feature_lpm,
4871 &feature_rmw,
4872 &feature_eijmpcall,
4873 &feature_break,
4874 &feature_spm,
4875 &feature_elpmx,
4876 &feature_elpm,
4877 &feature_addsubiw,
4878 &feature_des,
4879 &feature_xmegau,
4880 },
4881};
4882
4883pub const cpu_atxmega64d3 = Cpu{
4884 .name = "atxmega64d3",
4885 .llvm_name = "atxmega64d3",
4886 .subfeatures = &[_]*const Feature {
4887 &feature_lpmx,
4888 &feature_jmpcall,
4889 &feature_ijmpcall,
4890 &feature_movw,
4891 &feature_sram,
4892 &feature_mul,
4893 &feature_avr0,
4894 &feature_spmx,
4895 &feature_lpm,
4896 &feature_eijmpcall,
4897 &feature_break,
4898 &feature_spm,
4899 &feature_elpmx,
4900 &feature_elpm,
4901 &feature_addsubiw,
4902 &feature_des,
4903 &feature_xmega,
4904 },
4905};
4906
4907pub const cpu_atxmega64d4 = Cpu{
4908 .name = "atxmega64d4",
4909 .llvm_name = "atxmega64d4",
4910 .subfeatures = &[_]*const Feature {
4911 &feature_lpmx,
4912 &feature_jmpcall,
4913 &feature_ijmpcall,
4914 &feature_movw,
4915 &feature_sram,
4916 &feature_mul,
4917 &feature_avr0,
4918 &feature_spmx,
4919 &feature_lpm,
4920 &feature_eijmpcall,
4921 &feature_break,
4922 &feature_spm,
4923 &feature_elpmx,
4924 &feature_elpm,
4925 &feature_addsubiw,
4926 &feature_des,
4927 &feature_xmega,
4928 },
4929};
4930
4931pub const cpu_atxmega8e5 = Cpu{
4932 .name = "atxmega8e5",
4933 .llvm_name = "atxmega8e5",
4934 .subfeatures = &[_]*const Feature {
4935 &feature_lpmx,
4936 &feature_jmpcall,
4937 &feature_ijmpcall,
4938 &feature_movw,
4939 &feature_sram,
4940 &feature_mul,
4941 &feature_avr0,
4942 &feature_spmx,
4943 &feature_lpm,
4944 &feature_eijmpcall,
4945 &feature_break,
4946 &feature_spm,
4947 &feature_elpmx,
4948 &feature_elpm,
4949 &feature_addsubiw,
4950 &feature_des,
4951 &feature_xmega,
4952 },
4953};
4954
4955pub const cpu_avr1 = Cpu{
4956 .name = "avr1",
4957 .llvm_name = "avr1",
4958 .subfeatures = &[_]*const Feature {
4959 &feature_avr0,
4960 &feature_lpm,
4961 &feature_avr1,
4962 },
4963};
4964
4965pub const cpu_avr2 = Cpu{
4966 .name = "avr2",
4967 .llvm_name = "avr2",
4968 .subfeatures = &[_]*const Feature {
4969 &feature_ijmpcall,
4970 &feature_sram,
4971 &feature_avr0,
4972 &feature_lpm,
4973 &feature_addsubiw,
4974 &feature_avr2,
4975 },
4976};
4977
4978pub const cpu_avr25 = Cpu{
4979 .name = "avr25",
4980 .llvm_name = "avr25",
4981 .subfeatures = &[_]*const Feature {
4982 &feature_lpmx,
4983 &feature_ijmpcall,
4984 &feature_movw,
4985 &feature_sram,
4986 &feature_avr0,
4987 &feature_lpm,
4988 &feature_break,
4989 &feature_spm,
4990 &feature_addsubiw,
4991 &feature_avr25,
4992 },
4993};
4994
4995pub const cpu_avr3 = Cpu{
4996 .name = "avr3",
4997 .llvm_name = "avr3",
4998 .subfeatures = &[_]*const Feature {
4999 &feature_ijmpcall,
5000 &feature_jmpcall,
5001 &feature_sram,
5002 &feature_avr0,
5003 &feature_lpm,
5004 &feature_addsubiw,
5005 &feature_avr3,
5006 },
5007};
5008
5009pub const cpu_avr31 = Cpu{
5010 .name = "avr31",
5011 .llvm_name = "avr31",
5012 .subfeatures = &[_]*const Feature {
5013 &feature_jmpcall,
5014 &feature_ijmpcall,
5015 &feature_sram,
5016 &feature_avr0,
5017 &feature_lpm,
5018 &feature_elpm,
5019 &feature_addsubiw,
5020 &feature_avr31,
5021 },
5022};
5023
5024pub const cpu_avr35 = Cpu{
5025 .name = "avr35",
5026 .llvm_name = "avr35",
5027 .subfeatures = &[_]*const Feature {
5028 &feature_lpmx,
5029 &feature_jmpcall,
5030 &feature_ijmpcall,
5031 &feature_movw,
5032 &feature_sram,
5033 &feature_avr0,
5034 &feature_lpm,
5035 &feature_break,
5036 &feature_spm,
5037 &feature_addsubiw,
5038 &feature_avr35,
5039 },
5040};
5041
5042pub const cpu_avr4 = Cpu{
5043 .name = "avr4",
5044 .llvm_name = "avr4",
5045 .subfeatures = &[_]*const Feature {
5046 &feature_lpmx,
5047 &feature_ijmpcall,
5048 &feature_movw,
5049 &feature_sram,
5050 &feature_mul,
5051 &feature_avr0,
5052 &feature_lpm,
5053 &feature_break,
5054 &feature_spm,
5055 &feature_addsubiw,
5056 &feature_avr4,
5057 },
5058};
5059
5060pub const cpu_avr5 = Cpu{
5061 .name = "avr5",
5062 .llvm_name = "avr5",
5063 .subfeatures = &[_]*const Feature {
5064 &feature_lpmx,
5065 &feature_jmpcall,
5066 &feature_ijmpcall,
5067 &feature_movw,
5068 &feature_sram,
5069 &feature_mul,
5070 &feature_avr0,
5071 &feature_lpm,
5072 &feature_break,
5073 &feature_spm,
5074 &feature_addsubiw,
5075 &feature_avr5,
5076 },
5077};
5078
5079pub const cpu_avr51 = Cpu{
5080 .name = "avr51",
5081 .llvm_name = "avr51",
5082 .subfeatures = &[_]*const Feature {
5083 &feature_lpmx,
5084 &feature_ijmpcall,
5085 &feature_jmpcall,
5086 &feature_movw,
5087 &feature_sram,
5088 &feature_mul,
5089 &feature_avr0,
5090 &feature_lpm,
5091 &feature_break,
5092 &feature_spm,
5093 &feature_elpmx,
5094 &feature_elpm,
5095 &feature_addsubiw,
5096 &feature_avr51,
5097 },
5098};
5099
5100pub const cpu_avr6 = Cpu{
5101 .name = "avr6",
5102 .llvm_name = "avr6",
5103 .subfeatures = &[_]*const Feature {
5104 &feature_lpmx,
5105 &feature_jmpcall,
5106 &feature_ijmpcall,
5107 &feature_movw,
5108 &feature_sram,
5109 &feature_mul,
5110 &feature_avr0,
5111 &feature_lpm,
5112 &feature_break,
5113 &feature_spm,
5114 &feature_elpmx,
5115 &feature_elpm,
5116 &feature_addsubiw,
5117 &feature_avr6,
5118 },
5119};
5120
5121pub const cpu_avrtiny = Cpu{
5122 .name = "avrtiny",
5123 .llvm_name = "avrtiny",
5124 .subfeatures = &[_]*const Feature {
5125 &feature_tinyencoding,
5126 &feature_sram,
5127 &feature_break,
5128 &feature_avr0,
5129 &feature_avrtiny,
5130 },
5131};
5132
5133pub const cpu_avrxmega1 = Cpu{
5134 .name = "avrxmega1",
5135 .llvm_name = "avrxmega1",
5136 .subfeatures = &[_]*const Feature {
5137 &feature_lpmx,
5138 &feature_jmpcall,
5139 &feature_ijmpcall,
5140 &feature_movw,
5141 &feature_sram,
5142 &feature_mul,
5143 &feature_avr0,
5144 &feature_spmx,
5145 &feature_lpm,
5146 &feature_eijmpcall,
5147 &feature_break,
5148 &feature_spm,
5149 &feature_elpmx,
5150 &feature_elpm,
5151 &feature_addsubiw,
5152 &feature_des,
5153 &feature_xmega,
5154 },
5155};
5156
5157pub const cpu_avrxmega2 = Cpu{
5158 .name = "avrxmega2",
5159 .llvm_name = "avrxmega2",
5160 .subfeatures = &[_]*const Feature {
5161 &feature_lpmx,
5162 &feature_jmpcall,
5163 &feature_ijmpcall,
5164 &feature_movw,
5165 &feature_sram,
5166 &feature_mul,
5167 &feature_avr0,
5168 &feature_spmx,
5169 &feature_lpm,
5170 &feature_eijmpcall,
5171 &feature_break,
5172 &feature_spm,
5173 &feature_elpmx,
5174 &feature_elpm,
5175 &feature_addsubiw,
5176 &feature_des,
5177 &feature_xmega,
5178 },
5179};
5180
5181pub const cpu_avrxmega3 = Cpu{
5182 .name = "avrxmega3",
5183 .llvm_name = "avrxmega3",
5184 .subfeatures = &[_]*const Feature {
5185 &feature_lpmx,
5186 &feature_jmpcall,
5187 &feature_ijmpcall,
5188 &feature_movw,
5189 &feature_sram,
5190 &feature_mul,
5191 &feature_avr0,
5192 &feature_spmx,
5193 &feature_lpm,
5194 &feature_eijmpcall,
5195 &feature_break,
5196 &feature_spm,
5197 &feature_elpmx,
5198 &feature_elpm,
5199 &feature_addsubiw,
5200 &feature_des,
5201 &feature_xmega,
5202 },
5203};
5204
5205pub const cpu_avrxmega4 = Cpu{
5206 .name = "avrxmega4",
5207 .llvm_name = "avrxmega4",
5208 .subfeatures = &[_]*const Feature {
5209 &feature_lpmx,
5210 &feature_jmpcall,
5211 &feature_ijmpcall,
5212 &feature_movw,
5213 &feature_sram,
5214 &feature_mul,
5215 &feature_avr0,
5216 &feature_spmx,
5217 &feature_lpm,
5218 &feature_eijmpcall,
5219 &feature_break,
5220 &feature_spm,
5221 &feature_elpmx,
5222 &feature_elpm,
5223 &feature_addsubiw,
5224 &feature_des,
5225 &feature_xmega,
5226 },
5227};
5228
5229pub const cpu_avrxmega5 = Cpu{
5230 .name = "avrxmega5",
5231 .llvm_name = "avrxmega5",
5232 .subfeatures = &[_]*const Feature {
5233 &feature_lpmx,
5234 &feature_jmpcall,
5235 &feature_ijmpcall,
5236 &feature_movw,
5237 &feature_sram,
5238 &feature_mul,
5239 &feature_avr0,
5240 &feature_spmx,
5241 &feature_lpm,
5242 &feature_eijmpcall,
5243 &feature_break,
5244 &feature_spm,
5245 &feature_elpmx,
5246 &feature_elpm,
5247 &feature_addsubiw,
5248 &feature_des,
5249 &feature_xmega,
5250 },
5251};
5252
5253pub const cpu_avrxmega6 = Cpu{
5254 .name = "avrxmega6",
5255 .llvm_name = "avrxmega6",
5256 .subfeatures = &[_]*const Feature {
5257 &feature_lpmx,
5258 &feature_jmpcall,
5259 &feature_ijmpcall,
5260 &feature_movw,
5261 &feature_sram,
5262 &feature_mul,
5263 &feature_avr0,
5264 &feature_spmx,
5265 &feature_lpm,
5266 &feature_eijmpcall,
5267 &feature_break,
5268 &feature_spm,
5269 &feature_elpmx,
5270 &feature_elpm,
5271 &feature_addsubiw,
5272 &feature_des,
5273 &feature_xmega,
5274 },
5275};
5276
5277pub const cpu_avrxmega7 = Cpu{
5278 .name = "avrxmega7",
5279 .llvm_name = "avrxmega7",
5280 .subfeatures = &[_]*const Feature {
5281 &feature_lpmx,
5282 &feature_jmpcall,
5283 &feature_ijmpcall,
5284 &feature_movw,
5285 &feature_sram,
5286 &feature_mul,
5287 &feature_avr0,
5288 &feature_spmx,
5289 &feature_lpm,
5290 &feature_eijmpcall,
5291 &feature_break,
5292 &feature_spm,
5293 &feature_elpmx,
5294 &feature_elpm,
5295 &feature_addsubiw,
5296 &feature_des,
5297 &feature_xmega,
5298 },
5299};
5300
5301pub const cpu_m3000 = Cpu{
5302 .name = "m3000",
5303 .llvm_name = "m3000",
5304 .subfeatures = &[_]*const Feature {
5305 &feature_lpmx,
5306 &feature_jmpcall,
5307 &feature_ijmpcall,
5308 &feature_movw,
5309 &feature_sram,
5310 &feature_mul,
5311 &feature_avr0,
5312 &feature_lpm,
5313 &feature_break,
5314 &feature_spm,
5315 &feature_addsubiw,
5316 &feature_avr5,
5317 },
5318};
5319
5320pub const cpus = &[_]*const Cpu {
5321 &cpu_at43usb320,
5322 &cpu_at43usb355,
5323 &cpu_at76c711,
5324 &cpu_at86rf401,
5325 &cpu_at90c8534,
5326 &cpu_at90can128,
5327 &cpu_at90can32,
5328 &cpu_at90can64,
5329 &cpu_at90pwm1,
5330 &cpu_at90pwm161,
5331 &cpu_at90pwm2,
5332 &cpu_at90pwm216,
5333 &cpu_at90pwm2b,
5334 &cpu_at90pwm3,
5335 &cpu_at90pwm316,
5336 &cpu_at90pwm3b,
5337 &cpu_at90pwm81,
5338 &cpu_at90s1200,
5339 &cpu_at90s2313,
5340 &cpu_at90s2323,
5341 &cpu_at90s2333,
5342 &cpu_at90s2343,
5343 &cpu_at90s4414,
5344 &cpu_at90s4433,
5345 &cpu_at90s4434,
5346 &cpu_at90s8515,
5347 &cpu_at90s8535,
5348 &cpu_at90scr100,
5349 &cpu_at90usb1286,
5350 &cpu_at90usb1287,
5351 &cpu_at90usb162,
5352 &cpu_at90usb646,
5353 &cpu_at90usb647,
5354 &cpu_at90usb82,
5355 &cpu_at94k,
5356 &cpu_ata5272,
5357 &cpu_ata5505,
5358 &cpu_ata5790,
5359 &cpu_ata5795,
5360 &cpu_ata6285,
5361 &cpu_ata6286,
5362 &cpu_ata6289,
5363 &cpu_atmega103,
5364 &cpu_atmega128,
5365 &cpu_atmega1280,
5366 &cpu_atmega1281,
5367 &cpu_atmega1284,
5368 &cpu_atmega1284p,
5369 &cpu_atmega1284rfr2,
5370 &cpu_atmega128a,
5371 &cpu_atmega128rfa1,
5372 &cpu_atmega128rfr2,
5373 &cpu_atmega16,
5374 &cpu_atmega161,
5375 &cpu_atmega162,
5376 &cpu_atmega163,
5377 &cpu_atmega164a,
5378 &cpu_atmega164p,
5379 &cpu_atmega164pa,
5380 &cpu_atmega165,
5381 &cpu_atmega165a,
5382 &cpu_atmega165p,
5383 &cpu_atmega165pa,
5384 &cpu_atmega168,
5385 &cpu_atmega168a,
5386 &cpu_atmega168p,
5387 &cpu_atmega168pa,
5388 &cpu_atmega169,
5389 &cpu_atmega169a,
5390 &cpu_atmega169p,
5391 &cpu_atmega169pa,
5392 &cpu_atmega16a,
5393 &cpu_atmega16hva,
5394 &cpu_atmega16hva2,
5395 &cpu_atmega16hvb,
5396 &cpu_atmega16hvbrevb,
5397 &cpu_atmega16m1,
5398 &cpu_atmega16u2,
5399 &cpu_atmega16u4,
5400 &cpu_atmega2560,
5401 &cpu_atmega2561,
5402 &cpu_atmega2564rfr2,
5403 &cpu_atmega256rfr2,
5404 &cpu_atmega32,
5405 &cpu_atmega323,
5406 &cpu_atmega324a,
5407 &cpu_atmega324p,
5408 &cpu_atmega324pa,
5409 &cpu_atmega325,
5410 &cpu_atmega3250,
5411 &cpu_atmega3250a,
5412 &cpu_atmega3250p,
5413 &cpu_atmega3250pa,
5414 &cpu_atmega325a,
5415 &cpu_atmega325p,
5416 &cpu_atmega325pa,
5417 &cpu_atmega328,
5418 &cpu_atmega328p,
5419 &cpu_atmega329,
5420 &cpu_atmega3290,
5421 &cpu_atmega3290a,
5422 &cpu_atmega3290p,
5423 &cpu_atmega3290pa,
5424 &cpu_atmega329a,
5425 &cpu_atmega329p,
5426 &cpu_atmega329pa,
5427 &cpu_atmega32a,
5428 &cpu_atmega32c1,
5429 &cpu_atmega32hvb,
5430 &cpu_atmega32hvbrevb,
5431 &cpu_atmega32m1,
5432 &cpu_atmega32u2,
5433 &cpu_atmega32u4,
5434 &cpu_atmega32u6,
5435 &cpu_atmega406,
5436 &cpu_atmega48,
5437 &cpu_atmega48a,
5438 &cpu_atmega48p,
5439 &cpu_atmega48pa,
5440 &cpu_atmega64,
5441 &cpu_atmega640,
5442 &cpu_atmega644,
5443 &cpu_atmega644a,
5444 &cpu_atmega644p,
5445 &cpu_atmega644pa,
5446 &cpu_atmega644rfr2,
5447 &cpu_atmega645,
5448 &cpu_atmega6450,
5449 &cpu_atmega6450a,
5450 &cpu_atmega6450p,
5451 &cpu_atmega645a,
5452 &cpu_atmega645p,
5453 &cpu_atmega649,
5454 &cpu_atmega6490,
5455 &cpu_atmega6490a,
5456 &cpu_atmega6490p,
5457 &cpu_atmega649a,
5458 &cpu_atmega649p,
5459 &cpu_atmega64a,
5460 &cpu_atmega64c1,
5461 &cpu_atmega64hve,
5462 &cpu_atmega64m1,
5463 &cpu_atmega64rfr2,
5464 &cpu_atmega8,
5465 &cpu_atmega8515,
5466 &cpu_atmega8535,
5467 &cpu_atmega88,
5468 &cpu_atmega88a,
5469 &cpu_atmega88p,
5470 &cpu_atmega88pa,
5471 &cpu_atmega8a,
5472 &cpu_atmega8hva,
5473 &cpu_atmega8u2,
5474 &cpu_attiny10,
5475 &cpu_attiny102,
5476 &cpu_attiny104,
5477 &cpu_attiny11,
5478 &cpu_attiny12,
5479 &cpu_attiny13,
5480 &cpu_attiny13a,
5481 &cpu_attiny15,
5482 &cpu_attiny1634,
5483 &cpu_attiny167,
5484 &cpu_attiny20,
5485 &cpu_attiny22,
5486 &cpu_attiny2313,
5487 &cpu_attiny2313a,
5488 &cpu_attiny24,
5489 &cpu_attiny24a,
5490 &cpu_attiny25,
5491 &cpu_attiny26,
5492 &cpu_attiny261,
5493 &cpu_attiny261a,
5494 &cpu_attiny28,
5495 &cpu_attiny4,
5496 &cpu_attiny40,
5497 &cpu_attiny4313,
5498 &cpu_attiny43u,
5499 &cpu_attiny44,
5500 &cpu_attiny44a,
5501 &cpu_attiny45,
5502 &cpu_attiny461,
5503 &cpu_attiny461a,
5504 &cpu_attiny48,
5505 &cpu_attiny5,
5506 &cpu_attiny828,
5507 &cpu_attiny84,
5508 &cpu_attiny84a,
5509 &cpu_attiny85,
5510 &cpu_attiny861,
5511 &cpu_attiny861a,
5512 &cpu_attiny87,
5513 &cpu_attiny88,
5514 &cpu_attiny9,
5515 &cpu_atxmega128a1,
5516 &cpu_atxmega128a1u,
5517 &cpu_atxmega128a3,
5518 &cpu_atxmega128a3u,
5519 &cpu_atxmega128a4u,
5520 &cpu_atxmega128b1,
5521 &cpu_atxmega128b3,
5522 &cpu_atxmega128c3,
5523 &cpu_atxmega128d3,
5524 &cpu_atxmega128d4,
5525 &cpu_atxmega16a4,
5526 &cpu_atxmega16a4u,
5527 &cpu_atxmega16c4,
5528 &cpu_atxmega16d4,
5529 &cpu_atxmega16e5,
5530 &cpu_atxmega192a3,
5531 &cpu_atxmega192a3u,
5532 &cpu_atxmega192c3,
5533 &cpu_atxmega192d3,
5534 &cpu_atxmega256a3,
5535 &cpu_atxmega256a3b,
5536 &cpu_atxmega256a3bu,
5537 &cpu_atxmega256a3u,
5538 &cpu_atxmega256c3,
5539 &cpu_atxmega256d3,
5540 &cpu_atxmega32a4,
5541 &cpu_atxmega32a4u,
5542 &cpu_atxmega32c4,
5543 &cpu_atxmega32d4,
5544 &cpu_atxmega32e5,
5545 &cpu_atxmega32x1,
5546 &cpu_atxmega384c3,
5547 &cpu_atxmega384d3,
5548 &cpu_atxmega64a1,
5549 &cpu_atxmega64a1u,
5550 &cpu_atxmega64a3,
5551 &cpu_atxmega64a3u,
5552 &cpu_atxmega64a4u,
5553 &cpu_atxmega64b1,
5554 &cpu_atxmega64b3,
5555 &cpu_atxmega64c3,
5556 &cpu_atxmega64d3,
5557 &cpu_atxmega64d4,
5558 &cpu_atxmega8e5,
5559 &cpu_avr1,
5560 &cpu_avr2,
5561 &cpu_avr25,
5562 &cpu_avr3,
5563 &cpu_avr31,
5564 &cpu_avr35,
5565 &cpu_avr4,
5566 &cpu_avr5,
5567 &cpu_avr51,
5568 &cpu_avr6,
5569 &cpu_avrtiny,
5570 &cpu_avrxmega1,
5571 &cpu_avrxmega2,
5572 &cpu_avrxmega3,
5573 &cpu_avrxmega4,
5574 &cpu_avrxmega5,
5575 &cpu_avrxmega6,
5576 &cpu_avrxmega7,
5577 &cpu_m3000,
5578};
lib/std/target/bpf.zig created+75
......@@ -0,0 +1,75 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_alu32 = Feature{
5 .name = "alu32",
6 .description = "Enable ALU32 instructions",
7 .llvm_name = "alu32",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_dummy = Feature{
13 .name = "dummy",
14 .description = "unused feature",
15 .llvm_name = "dummy",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_dwarfris = Feature{
21 .name = "dwarfris",
22 .description = "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections",
23 .llvm_name = "dwarfris",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const features = &[_]*const Feature {
29 &feature_alu32,
30 &feature_dummy,
31 &feature_dwarfris,
32};
33
34pub const cpu_generic = Cpu{
35 .name = "generic",
36 .llvm_name = "generic",
37 .subfeatures = &[_]*const Feature {
38 },
39};
40
41pub const cpu_probe = Cpu{
42 .name = "probe",
43 .llvm_name = "probe",
44 .subfeatures = &[_]*const Feature {
45 },
46};
47
48pub const cpu_v1 = Cpu{
49 .name = "v1",
50 .llvm_name = "v1",
51 .subfeatures = &[_]*const Feature {
52 },
53};
54
55pub const cpu_v2 = Cpu{
56 .name = "v2",
57 .llvm_name = "v2",
58 .subfeatures = &[_]*const Feature {
59 },
60};
61
62pub const cpu_v3 = Cpu{
63 .name = "v3",
64 .llvm_name = "v3",
65 .subfeatures = &[_]*const Feature {
66 },
67};
68
69pub const cpus = &[_]*const Cpu {
70 &cpu_generic,
71 &cpu_probe,
72 &cpu_v1,
73 &cpu_v2,
74 &cpu_v3,
75};
lib/std/target/cpu.zig deleted-67
......@@ -1,67 +0,0 @@
1const std = @import("std");
2
3const feature = @import("feature.zig");
4const Arch = std.Target.Arch;
5
6pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
7pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
8pub const ArmCpu = @import("cpu/ArmCpu.zig").ArmCpu;
9pub const AvrCpu = @import("cpu/AvrCpu.zig").AvrCpu;
10pub const BpfCpu = @import("cpu/BpfCpu.zig").BpfCpu;
11pub const HexagonCpu = @import("cpu/HexagonCpu.zig").HexagonCpu;
12pub const MipsCpu = @import("cpu/MipsCpu.zig").MipsCpu;
13pub const Msp430Cpu = @import("cpu/Msp430Cpu.zig").Msp430Cpu;
14pub const NvptxCpu = @import("cpu/NvptxCpu.zig").NvptxCpu;
15pub const PowerPcCpu = @import("cpu/PowerPcCpu.zig").PowerPcCpu;
16pub const RiscVCpu = @import("cpu/RiscVCpu.zig").RiscVCpu;
17pub const SparcCpu = @import("cpu/SparcCpu.zig").SparcCpu;
18pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
19pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
20pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
21
22pub const EmptyCpu = @import("cpu/empty.zig").EmptyCpu;
23
24pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
25 return switch (arch) {
26 .arm, .armeb, .thumb, .thumbeb => ArmCpu,
27 .aarch64, .aarch64_be, .aarch64_32 => AArch64Cpu,
28 .avr => AvrCpu,
29 .bpfel, .bpfeb => BpfCpu,
30 .hexagon => HexagonCpu,
31 .mips, .mipsel, .mips64, .mips64el => MipsCpu,
32 .msp430 => Msp430Cpu,
33 .powerpc, .powerpc64, .powerpc64le => PowerPcCpu,
34 .amdgcn => AmdGpuCpu,
35 .riscv32, .riscv64 => RiscVCpu,
36 .sparc, .sparcv9, .sparcel => SparcCpu,
37 .s390x => SystemZCpu,
38 .i386, .x86_64 => X86Cpu,
39 .nvptx, .nvptx64 => NvptxCpu,
40 .wasm32, .wasm64 => WebAssemblyCpu,
41
42 else => EmptyCpu,
43 };
44}
45
46pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
47 return CpuInfo(ArchCpu(arch), feature.ArchFeature(arch));
48}
49
50pub fn CpuInfo(comptime CpuType: type, comptime FeatureType: type) type {
51 return struct {
52 value: CpuType,
53 name: []const u8,
54
55 features: []const FeatureType,
56
57 const Self = @This();
58
59 pub fn create(value: CpuType, name: []const u8, features: []const FeatureType) Self {
60 return Self {
61 .value = value,
62 .name = name,
63 .features = features,
64 };
65 }
66 };
67}
lib/std/target/cpu/AArch64Cpu.zig deleted-480
......@@ -1,480 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const AArch64Cpu = enum {
5 AppleLatest,
6 CortexA35,
7 CortexA53,
8 CortexA55,
9 CortexA57,
10 CortexA65,
11 CortexA65ae,
12 CortexA72,
13 CortexA73,
14 CortexA75,
15 CortexA76,
16 CortexA76ae,
17 Cyclone,
18 ExynosM1,
19 ExynosM2,
20 ExynosM3,
21 ExynosM4,
22 ExynosM5,
23 Falkor,
24 Generic,
25 Kryo,
26 NeoverseE1,
27 NeoverseN1,
28 Saphira,
29 Thunderx,
30 Thunderx2t99,
31 Thunderxt81,
32 Thunderxt83,
33 Thunderxt88,
34 Tsv110,
35
36 const FeatureType = feature.AArch64Feature;
37
38 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
39 return cpu_infos[@enumToInt(self)];
40 }
41
42 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
43 CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
44 .ArithBccFusion,
45 .ArithCbzFusion,
46 .ZczFp,
47 .AlternateSextloadCvtF32Pattern,
48 .DisableLatencySchedHeuristic,
49 .Perfmon,
50 .ZczGp,
51 .ZczFpWorkaround,
52 .Zcm,
53 .FpArmv8,
54 .FuseCryptoEor,
55 .FuseAes,
56 .Cyclone,
57 }),
58 CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
59 .Perfmon,
60 .FpArmv8,
61 .Crc,
62 .A35,
63 }),
64 CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
65 .Perfmon,
66 .UsePostraScheduler,
67 .Crc,
68 .CustomCheapAsMove,
69 .BalanceFpOps,
70 .UseAa,
71 .FpArmv8,
72 .FuseAes,
73 .A53,
74 }),
75 CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
76 .Lse,
77 .Vh,
78 .Rdm,
79 .Perfmon,
80 .Pan,
81 .Dotprod,
82 .Crc,
83 .Lor,
84 .Uaops,
85 .Ras,
86 .Rcpc,
87 .Ccpp,
88 .FpArmv8,
89 .FuseAes,
90 .A55,
91 }),
92 CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
93 .Perfmon,
94 .UsePostraScheduler,
95 .Crc,
96 .PredictableSelectExpensive,
97 .CustomCheapAsMove,
98 .BalanceFpOps,
99 .FuseLiterals,
100 .FpArmv8,
101 .FuseAes,
102 .A57,
103 }),
104 CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
105 .Lse,
106 .Vh,
107 .Rdm,
108 .Pan,
109 .Dotprod,
110 .Crc,
111 .Ssbs,
112 .Lor,
113 .Uaops,
114 .Ras,
115 .Rcpc,
116 .Ccpp,
117 .FpArmv8,
118 .A65,
119 }),
120 CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
121 .Lse,
122 .Vh,
123 .Rdm,
124 .Pan,
125 .Dotprod,
126 .Crc,
127 .Ssbs,
128 .Lor,
129 .Uaops,
130 .Ras,
131 .Rcpc,
132 .Ccpp,
133 .FpArmv8,
134 .A65,
135 }),
136 CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
137 .Perfmon,
138 .FpArmv8,
139 .Crc,
140 .FuseAes,
141 .A72,
142 }),
143 CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
144 .Perfmon,
145 .FpArmv8,
146 .Crc,
147 .FuseAes,
148 .A73,
149 }),
150 CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
151 .Lse,
152 .Vh,
153 .Rdm,
154 .Perfmon,
155 .Pan,
156 .Dotprod,
157 .Crc,
158 .Lor,
159 .Uaops,
160 .Ras,
161 .Rcpc,
162 .Ccpp,
163 .FpArmv8,
164 .FuseAes,
165 .A75,
166 }),
167 CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
168 .Lse,
169 .Vh,
170 .Rdm,
171 .Pan,
172 .Dotprod,
173 .Crc,
174 .Ssbs,
175 .Lor,
176 .Uaops,
177 .Ras,
178 .Rcpc,
179 .Ccpp,
180 .FpArmv8,
181 .A76,
182 }),
183 CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
184 .Lse,
185 .Vh,
186 .Rdm,
187 .Pan,
188 .Dotprod,
189 .Crc,
190 .Ssbs,
191 .Lor,
192 .Uaops,
193 .Ras,
194 .Rcpc,
195 .Ccpp,
196 .FpArmv8,
197 .A76,
198 }),
199 CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
200 .ArithBccFusion,
201 .ArithCbzFusion,
202 .ZczFp,
203 .AlternateSextloadCvtF32Pattern,
204 .DisableLatencySchedHeuristic,
205 .Perfmon,
206 .ZczGp,
207 .ZczFpWorkaround,
208 .Zcm,
209 .FpArmv8,
210 .FuseCryptoEor,
211 .FuseAes,
212 .Cyclone,
213 }),
214 CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
215 .ZczFp,
216 .Perfmon,
217 .UsePostraScheduler,
218 .Crc,
219 .UseReciprocalSquareRoot,
220 .CustomCheapAsMove,
221 .Force32bitJumpTables,
222 .SlowMisaligned128store,
223 .FpArmv8,
224 .SlowPaired128,
225 .FuseAes,
226 .Exynosm1,
227 }),
228 CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
229 .ZczFp,
230 .Perfmon,
231 .UsePostraScheduler,
232 .Crc,
233 .CustomCheapAsMove,
234 .Force32bitJumpTables,
235 .SlowMisaligned128store,
236 .FpArmv8,
237 .SlowPaired128,
238 .FuseAes,
239 .Exynosm2,
240 }),
241 CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
242 .FuseCsel,
243 .ZczFp,
244 .Perfmon,
245 .UsePostraScheduler,
246 .Crc,
247 .PredictableSelectExpensive,
248 .CustomCheapAsMove,
249 .Force32bitJumpTables,
250 .FuseLiterals,
251 .FuseAddress,
252 .LslFast,
253 .FpArmv8,
254 .FuseAes,
255 .Exynosm3,
256 }),
257 CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
258 .ArithBccFusion,
259 .Vh,
260 .ArithCbzFusion,
261 .ZczFp,
262 .Rdm,
263 .UsePostraScheduler,
264 .Ras,
265 .Force32bitJumpTables,
266 .Ccpp,
267 .FuseCsel,
268 .Pan,
269 .Uaops,
270 .FuseLiterals,
271 .LslFast,
272 .Lse,
273 .Perfmon,
274 .Dotprod,
275 .Lor,
276 .FuseArithLogic,
277 .Crc,
278 .CustomCheapAsMove,
279 .FuseAddress,
280 .ZczGp,
281 .FpArmv8,
282 .FuseAes,
283 .Exynosm4,
284 }),
285 CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
286 .ArithBccFusion,
287 .Vh,
288 .ArithCbzFusion,
289 .ZczFp,
290 .Rdm,
291 .UsePostraScheduler,
292 .Ras,
293 .Force32bitJumpTables,
294 .Ccpp,
295 .FuseCsel,
296 .Pan,
297 .Uaops,
298 .FuseLiterals,
299 .LslFast,
300 .Lse,
301 .Perfmon,
302 .Dotprod,
303 .Lor,
304 .FuseArithLogic,
305 .Crc,
306 .CustomCheapAsMove,
307 .FuseAddress,
308 .ZczGp,
309 .FpArmv8,
310 .FuseAes,
311 .Exynosm4,
312 }),
313 CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
314 .ZczFp,
315 .Rdm,
316 .Perfmon,
317 .UsePostraScheduler,
318 .Crc,
319 .PredictableSelectExpensive,
320 .CustomCheapAsMove,
321 .ZczGp,
322 .FpArmv8,
323 .SlowStrqroStore,
324 .LslFast,
325 .Falkor,
326 }),
327 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
328 .Trbe,
329 .Ete,
330 .FpArmv8,
331 .FuseAes,
332 .Neon,
333 .Perfmon,
334 .UsePostraScheduler,
335 }),
336 CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
337 .ZczFp,
338 .Perfmon,
339 .UsePostraScheduler,
340 .Crc,
341 .PredictableSelectExpensive,
342 .CustomCheapAsMove,
343 .ZczGp,
344 .FpArmv8,
345 .LslFast,
346 .Kryo,
347 }),
348 CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
349 .Lse,
350 .Vh,
351 .Rdm,
352 .Pan,
353 .Dotprod,
354 .Crc,
355 .Ssbs,
356 .Lor,
357 .Uaops,
358 .Ras,
359 .Rcpc,
360 .Ccpp,
361 .FpArmv8,
362 .Neoversee1,
363 }),
364 CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
365 .Lse,
366 .Spe,
367 .Vh,
368 .Rdm,
369 .Pan,
370 .Dotprod,
371 .Crc,
372 .Ssbs,
373 .Lor,
374 .Uaops,
375 .Ras,
376 .Rcpc,
377 .Ccpp,
378 .FpArmv8,
379 .Neoversen1,
380 }),
381 CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
382 .Spe,
383 .Vh,
384 .ZczFp,
385 .Rdm,
386 .UsePostraScheduler,
387 .Dit,
388 .Am,
389 .Ras,
390 .Rcpc,
391 .Sel2,
392 .Ccpp,
393 .Pa,
394 .Pan,
395 .Uaops,
396 .Tracev84,
397 .Mpam,
398 .LslFast,
399 .Lse,
400 .Nv,
401 .Perfmon,
402 .Dotprod,
403 .TlbRmi,
404 .Lor,
405 .Ccidx,
406 .PredictableSelectExpensive,
407 .Crc,
408 .CustomCheapAsMove,
409 .Fmi,
410 .ZczGp,
411 .FpArmv8,
412 .Saphira,
413 }),
414 CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
415 .Perfmon,
416 .UsePostraScheduler,
417 .Crc,
418 .FpArmv8,
419 .PredictableSelectExpensive,
420 .Thunderx,
421 }),
422 CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
423 .Lse,
424 .ArithBccFusion,
425 .Vh,
426 .Rdm,
427 .UsePostraScheduler,
428 .Crc,
429 .Lor,
430 .Pan,
431 .AggressiveFma,
432 .FpArmv8,
433 .PredictableSelectExpensive,
434 .Thunderx2t99,
435 }),
436 CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
437 .Perfmon,
438 .UsePostraScheduler,
439 .Crc,
440 .FpArmv8,
441 .PredictableSelectExpensive,
442 .Thunderxt81,
443 }),
444 CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
445 .Perfmon,
446 .UsePostraScheduler,
447 .Crc,
448 .FpArmv8,
449 .PredictableSelectExpensive,
450 .Thunderxt83,
451 }),
452 CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
453 .Perfmon,
454 .UsePostraScheduler,
455 .Crc,
456 .FpArmv8,
457 .PredictableSelectExpensive,
458 .Thunderxt88,
459 }),
460 CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
461 .Lse,
462 .Spe,
463 .Vh,
464 .Rdm,
465 .Perfmon,
466 .UsePostraScheduler,
467 .Pan,
468 .Dotprod,
469 .Crc,
470 .Lor,
471 .Uaops,
472 .CustomCheapAsMove,
473 .Ras,
474 .Ccpp,
475 .FpArmv8,
476 .FuseAes,
477 .Tsv110,
478 }),
479 };
480};
lib/std/target/cpu/AmdGpuCpu.zig deleted-1060
......@@ -1,1060 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const AmdGpuCpu = enum {
5 Bonaire,
6 Carrizo,
7 Fiji,
8 Generic,
9 GenericHsa,
10 Gfx1010,
11 Gfx1011,
12 Gfx1012,
13 Gfx600,
14 Gfx601,
15 Gfx700,
16 Gfx701,
17 Gfx702,
18 Gfx703,
19 Gfx704,
20 Gfx801,
21 Gfx802,
22 Gfx803,
23 Gfx810,
24 Gfx900,
25 Gfx902,
26 Gfx904,
27 Gfx906,
28 Gfx908,
29 Gfx909,
30 Hainan,
31 Hawaii,
32 Iceland,
33 Kabini,
34 Kaveri,
35 Mullins,
36 Oland,
37 Pitcairn,
38 Polaris10,
39 Polaris11,
40 Stoney,
41 Tahiti,
42 Tonga,
43 Verde,
44
45 const FeatureType = feature.AmdGpuFeature;
46
47 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
48 return cpu_infos[@enumToInt(self)];
49 }
50
51 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
52 CpuInfo(@This(), FeatureType).create(.Bonaire, "bonaire", &[_]FeatureType {
53 .CodeObjectV3,
54 .NoXnackSupport,
55 .Ldsbankcount32,
56 .Movrel,
57 .Gfx7Gfx8Gfx9Insts,
58 .Fp64,
59 .TrigReducedRange,
60 .CiInsts,
61 .FlatAddressSpace,
62 .Localmemorysize65536,
63 .Wavefrontsize64,
64 .NoSramEccSupport,
65 .MimgR128,
66 .SeaIslands,
67 }),
68 CpuInfo(@This(), FeatureType).create(.Carrizo, "carrizo", &[_]FeatureType {
69 .CodeObjectV3,
70 .FastFmaf,
71 .Ldsbankcount32,
72 .UnpackedD16Vmem,
73 .IntClampInsts,
74 .SdwaMav,
75 .Movrel,
76 .SMemrealtime,
77 .Gcn3Encoding,
78 .TrigReducedRange,
79 .CiInsts,
80 .FlatAddressSpace,
81 .Sdwa,
82 .Wavefrontsize64,
83 .NoSramEccSupport,
84 .ScalarStores,
85 .Gfx7Gfx8Gfx9Insts,
86 .Dpp,
87 .Localmemorysize65536,
88 .BitInsts16,
89 .VgprIndexMode,
90 .Gfx8Insts,
91 .Inv2piInlineImm,
92 .MimgR128,
93 .SdwaOutModsVopc,
94 .Fp64,
95 .VolcanicIslands,
96 .Xnack,
97 .HalfRate64Ops,
98 }),
99 CpuInfo(@This(), FeatureType).create(.Fiji, "fiji", &[_]FeatureType {
100 .CodeObjectV3,
101 .NoXnackSupport,
102 .Ldsbankcount32,
103 .UnpackedD16Vmem,
104 .IntClampInsts,
105 .SdwaMav,
106 .Movrel,
107 .SMemrealtime,
108 .Gcn3Encoding,
109 .TrigReducedRange,
110 .CiInsts,
111 .FlatAddressSpace,
112 .Sdwa,
113 .Wavefrontsize64,
114 .NoSramEccSupport,
115 .ScalarStores,
116 .Gfx7Gfx8Gfx9Insts,
117 .Dpp,
118 .Localmemorysize65536,
119 .BitInsts16,
120 .VgprIndexMode,
121 .Gfx8Insts,
122 .Inv2piInlineImm,
123 .MimgR128,
124 .SdwaOutModsVopc,
125 .Fp64,
126 .VolcanicIslands,
127 }),
128 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
129 .Wavefrontsize64,
130 }),
131 CpuInfo(@This(), FeatureType).create(.GenericHsa, "generic-hsa", &[_]FeatureType {
132 .FlatAddressSpace,
133 .Wavefrontsize64,
134 }),
135 CpuInfo(@This(), FeatureType).create(.Gfx1010, "gfx1010", &[_]FeatureType {
136 .CodeObjectV3,
137 .DlInsts,
138 .NoXnackSupport,
139 .FlatSegmentOffsetBug,
140 .Vscnt,
141 .ApertureRegs,
142 .Gfx10Insts,
143 .IntClampInsts,
144 .PkFmacF16Inst,
145 .SdwaOmod,
146 .SdwaScalar,
147 .AddNoCarryInsts,
148 .Movrel,
149 .SMemrealtime,
150 .NoSdstCmpx,
151 .CiInsts,
152 .FlatAddressSpace,
153 .Sdwa,
154 .NoSramEccSupport,
155 .SdwaSdst,
156 .FlatInstOffsets,
157 .RegisterBanking,
158 .Dpp,
159 .Localmemorysize65536,
160 .Vop3p,
161 .BitInsts16,
162 .Dpp8,
163 .Gfx8Insts,
164 .Inv2piInlineImm,
165 .Gfx9Insts,
166 .FmaMixInsts,
167 .MimgR128,
168 .Vop3Literal,
169 .FlatGlobalInsts,
170 .FlatScratchInsts,
171 .Fp64,
172 .FastFmaf,
173 .NoDataDepHazard,
174 .Gfx10,
175 .InstFwdPrefetchBug,
176 .Ldsbankcount32,
177 .LdsBranchVmemWarHazard,
178 .LdsMisalignedBug,
179 .NsaEncoding,
180 .NsaToVmemBug,
181 .Offset3fBug,
182 .SmemToVectorWriteHazard,
183 .ScalarAtomics,
184 .ScalarFlatScratchInsts,
185 .ScalarStores,
186 .VmemToScalarWriteHazard,
187 .VcmpxExecWarHazard,
188 .VcmpxPermlaneHazard,
189 .Wavefrontsize32,
190 }),
191 CpuInfo(@This(), FeatureType).create(.Gfx1011, "gfx1011", &[_]FeatureType {
192 .CodeObjectV3,
193 .DlInsts,
194 .NoXnackSupport,
195 .Dot1Insts,
196 .Dot2Insts,
197 .Dot5Insts,
198 .Dot6Insts,
199 .FlatSegmentOffsetBug,
200 .Vscnt,
201 .ApertureRegs,
202 .Gfx10Insts,
203 .IntClampInsts,
204 .PkFmacF16Inst,
205 .SdwaOmod,
206 .SdwaScalar,
207 .AddNoCarryInsts,
208 .Movrel,
209 .SMemrealtime,
210 .NoSdstCmpx,
211 .CiInsts,
212 .FlatAddressSpace,
213 .Sdwa,
214 .NoSramEccSupport,
215 .SdwaSdst,
216 .FlatInstOffsets,
217 .RegisterBanking,
218 .Dpp,
219 .Localmemorysize65536,
220 .Vop3p,
221 .BitInsts16,
222 .Dpp8,
223 .Gfx8Insts,
224 .Inv2piInlineImm,
225 .Gfx9Insts,
226 .FmaMixInsts,
227 .MimgR128,
228 .Vop3Literal,
229 .FlatGlobalInsts,
230 .FlatScratchInsts,
231 .Fp64,
232 .FastFmaf,
233 .NoDataDepHazard,
234 .Gfx10,
235 .InstFwdPrefetchBug,
236 .Ldsbankcount32,
237 .LdsBranchVmemWarHazard,
238 .NsaEncoding,
239 .NsaToVmemBug,
240 .Offset3fBug,
241 .SmemToVectorWriteHazard,
242 .ScalarAtomics,
243 .ScalarFlatScratchInsts,
244 .ScalarStores,
245 .VmemToScalarWriteHazard,
246 .VcmpxExecWarHazard,
247 .VcmpxPermlaneHazard,
248 .Wavefrontsize32,
249 }),
250 CpuInfo(@This(), FeatureType).create(.Gfx1012, "gfx1012", &[_]FeatureType {
251 .CodeObjectV3,
252 .DlInsts,
253 .NoXnackSupport,
254 .Dot1Insts,
255 .Dot2Insts,
256 .Dot5Insts,
257 .Dot6Insts,
258 .FlatSegmentOffsetBug,
259 .Vscnt,
260 .ApertureRegs,
261 .Gfx10Insts,
262 .IntClampInsts,
263 .PkFmacF16Inst,
264 .SdwaOmod,
265 .SdwaScalar,
266 .AddNoCarryInsts,
267 .Movrel,
268 .SMemrealtime,
269 .NoSdstCmpx,
270 .CiInsts,
271 .FlatAddressSpace,
272 .Sdwa,
273 .NoSramEccSupport,
274 .SdwaSdst,
275 .FlatInstOffsets,
276 .RegisterBanking,
277 .Dpp,
278 .Localmemorysize65536,
279 .Vop3p,
280 .BitInsts16,
281 .Dpp8,
282 .Gfx8Insts,
283 .Inv2piInlineImm,
284 .Gfx9Insts,
285 .FmaMixInsts,
286 .MimgR128,
287 .Vop3Literal,
288 .FlatGlobalInsts,
289 .FlatScratchInsts,
290 .Fp64,
291 .FastFmaf,
292 .NoDataDepHazard,
293 .Gfx10,
294 .InstFwdPrefetchBug,
295 .Ldsbankcount32,
296 .LdsBranchVmemWarHazard,
297 .LdsMisalignedBug,
298 .NsaEncoding,
299 .NsaToVmemBug,
300 .Offset3fBug,
301 .SmemToVectorWriteHazard,
302 .ScalarAtomics,
303 .ScalarFlatScratchInsts,
304 .ScalarStores,
305 .VmemToScalarWriteHazard,
306 .VcmpxExecWarHazard,
307 .VcmpxPermlaneHazard,
308 .Wavefrontsize32,
309 }),
310 CpuInfo(@This(), FeatureType).create(.Gfx600, "gfx600", &[_]FeatureType {
311 .CodeObjectV3,
312 .NoXnackSupport,
313 .FastFmaf,
314 .Ldsbankcount32,
315 .Movrel,
316 .MimgR128,
317 .Fp64,
318 .TrigReducedRange,
319 .Wavefrontsize64,
320 .NoSramEccSupport,
321 .Localmemorysize32768,
322 .SouthernIslands,
323 .HalfRate64Ops,
324 }),
325 CpuInfo(@This(), FeatureType).create(.Gfx601, "gfx601", &[_]FeatureType {
326 .CodeObjectV3,
327 .NoXnackSupport,
328 .Ldsbankcount32,
329 .Movrel,
330 .MimgR128,
331 .Fp64,
332 .TrigReducedRange,
333 .Wavefrontsize64,
334 .NoSramEccSupport,
335 .Localmemorysize32768,
336 .SouthernIslands,
337 }),
338 CpuInfo(@This(), FeatureType).create(.Gfx700, "gfx700", &[_]FeatureType {
339 .CodeObjectV3,
340 .NoXnackSupport,
341 .Ldsbankcount32,
342 .Movrel,
343 .Gfx7Gfx8Gfx9Insts,
344 .Fp64,
345 .TrigReducedRange,
346 .CiInsts,
347 .FlatAddressSpace,
348 .Localmemorysize65536,
349 .Wavefrontsize64,
350 .NoSramEccSupport,
351 .MimgR128,
352 .SeaIslands,
353 }),
354 CpuInfo(@This(), FeatureType).create(.Gfx701, "gfx701", &[_]FeatureType {
355 .CodeObjectV3,
356 .NoXnackSupport,
357 .FastFmaf,
358 .Ldsbankcount32,
359 .Movrel,
360 .Gfx7Gfx8Gfx9Insts,
361 .Fp64,
362 .TrigReducedRange,
363 .CiInsts,
364 .FlatAddressSpace,
365 .Localmemorysize65536,
366 .Wavefrontsize64,
367 .NoSramEccSupport,
368 .MimgR128,
369 .SeaIslands,
370 .HalfRate64Ops,
371 }),
372 CpuInfo(@This(), FeatureType).create(.Gfx702, "gfx702", &[_]FeatureType {
373 .CodeObjectV3,
374 .NoXnackSupport,
375 .FastFmaf,
376 .Ldsbankcount16,
377 .Movrel,
378 .Gfx7Gfx8Gfx9Insts,
379 .Fp64,
380 .TrigReducedRange,
381 .CiInsts,
382 .FlatAddressSpace,
383 .Localmemorysize65536,
384 .Wavefrontsize64,
385 .NoSramEccSupport,
386 .MimgR128,
387 .SeaIslands,
388 }),
389 CpuInfo(@This(), FeatureType).create(.Gfx703, "gfx703", &[_]FeatureType {
390 .CodeObjectV3,
391 .NoXnackSupport,
392 .Ldsbankcount16,
393 .Movrel,
394 .Gfx7Gfx8Gfx9Insts,
395 .Fp64,
396 .TrigReducedRange,
397 .CiInsts,
398 .FlatAddressSpace,
399 .Localmemorysize65536,
400 .Wavefrontsize64,
401 .NoSramEccSupport,
402 .MimgR128,
403 .SeaIslands,
404 }),
405 CpuInfo(@This(), FeatureType).create(.Gfx704, "gfx704", &[_]FeatureType {
406 .CodeObjectV3,
407 .NoXnackSupport,
408 .Ldsbankcount32,
409 .Movrel,
410 .Gfx7Gfx8Gfx9Insts,
411 .Fp64,
412 .TrigReducedRange,
413 .CiInsts,
414 .FlatAddressSpace,
415 .Localmemorysize65536,
416 .Wavefrontsize64,
417 .NoSramEccSupport,
418 .MimgR128,
419 .SeaIslands,
420 }),
421 CpuInfo(@This(), FeatureType).create(.Gfx801, "gfx801", &[_]FeatureType {
422 .CodeObjectV3,
423 .FastFmaf,
424 .Ldsbankcount32,
425 .UnpackedD16Vmem,
426 .IntClampInsts,
427 .SdwaMav,
428 .Movrel,
429 .SMemrealtime,
430 .Gcn3Encoding,
431 .TrigReducedRange,
432 .CiInsts,
433 .FlatAddressSpace,
434 .Sdwa,
435 .Wavefrontsize64,
436 .NoSramEccSupport,
437 .ScalarStores,
438 .Gfx7Gfx8Gfx9Insts,
439 .Dpp,
440 .Localmemorysize65536,
441 .BitInsts16,
442 .VgprIndexMode,
443 .Gfx8Insts,
444 .Inv2piInlineImm,
445 .MimgR128,
446 .SdwaOutModsVopc,
447 .Fp64,
448 .VolcanicIslands,
449 .Xnack,
450 .HalfRate64Ops,
451 }),
452 CpuInfo(@This(), FeatureType).create(.Gfx802, "gfx802", &[_]FeatureType {
453 .CodeObjectV3,
454 .NoXnackSupport,
455 .Ldsbankcount32,
456 .SgprInitBug,
457 .UnpackedD16Vmem,
458 .IntClampInsts,
459 .SdwaMav,
460 .Movrel,
461 .SMemrealtime,
462 .Gcn3Encoding,
463 .TrigReducedRange,
464 .CiInsts,
465 .FlatAddressSpace,
466 .Sdwa,
467 .Wavefrontsize64,
468 .NoSramEccSupport,
469 .ScalarStores,
470 .Gfx7Gfx8Gfx9Insts,
471 .Dpp,
472 .Localmemorysize65536,
473 .BitInsts16,
474 .VgprIndexMode,
475 .Gfx8Insts,
476 .Inv2piInlineImm,
477 .MimgR128,
478 .SdwaOutModsVopc,
479 .Fp64,
480 .VolcanicIslands,
481 }),
482 CpuInfo(@This(), FeatureType).create(.Gfx803, "gfx803", &[_]FeatureType {
483 .CodeObjectV3,
484 .NoXnackSupport,
485 .Ldsbankcount32,
486 .UnpackedD16Vmem,
487 .IntClampInsts,
488 .SdwaMav,
489 .Movrel,
490 .SMemrealtime,
491 .Gcn3Encoding,
492 .TrigReducedRange,
493 .CiInsts,
494 .FlatAddressSpace,
495 .Sdwa,
496 .Wavefrontsize64,
497 .NoSramEccSupport,
498 .ScalarStores,
499 .Gfx7Gfx8Gfx9Insts,
500 .Dpp,
501 .Localmemorysize65536,
502 .BitInsts16,
503 .VgprIndexMode,
504 .Gfx8Insts,
505 .Inv2piInlineImm,
506 .MimgR128,
507 .SdwaOutModsVopc,
508 .Fp64,
509 .VolcanicIslands,
510 }),
511 CpuInfo(@This(), FeatureType).create(.Gfx810, "gfx810", &[_]FeatureType {
512 .CodeObjectV3,
513 .Ldsbankcount16,
514 .IntClampInsts,
515 .SdwaMav,
516 .Movrel,
517 .SMemrealtime,
518 .Gcn3Encoding,
519 .TrigReducedRange,
520 .CiInsts,
521 .FlatAddressSpace,
522 .Sdwa,
523 .Wavefrontsize64,
524 .NoSramEccSupport,
525 .ScalarStores,
526 .Gfx7Gfx8Gfx9Insts,
527 .Dpp,
528 .Localmemorysize65536,
529 .BitInsts16,
530 .VgprIndexMode,
531 .Gfx8Insts,
532 .Inv2piInlineImm,
533 .MimgR128,
534 .SdwaOutModsVopc,
535 .Fp64,
536 .VolcanicIslands,
537 .Xnack,
538 }),
539 CpuInfo(@This(), FeatureType).create(.Gfx900, "gfx900", &[_]FeatureType {
540 .CodeObjectV3,
541 .NoSramEccSupport,
542 .NoXnackSupport,
543 .ApertureRegs,
544 .IntClampInsts,
545 .SdwaOmod,
546 .SdwaScalar,
547 .AddNoCarryInsts,
548 .ScalarAtomics,
549 .SMemrealtime,
550 .Gcn3Encoding,
551 .CiInsts,
552 .FlatAddressSpace,
553 .Sdwa,
554 .Wavefrontsize64,
555 .SdwaSdst,
556 .FlatInstOffsets,
557 .ScalarStores,
558 .Gfx7Gfx8Gfx9Insts,
559 .R128A16,
560 .Dpp,
561 .Localmemorysize65536,
562 .Vop3p,
563 .BitInsts16,
564 .VgprIndexMode,
565 .Gfx8Insts,
566 .Inv2piInlineImm,
567 .Gfx9Insts,
568 .ScalarFlatScratchInsts,
569 .FlatGlobalInsts,
570 .FlatScratchInsts,
571 .Fp64,
572 .FastFmaf,
573 .Gfx9,
574 .Ldsbankcount32,
575 .MadMixInsts,
576 }),
577 CpuInfo(@This(), FeatureType).create(.Gfx902, "gfx902", &[_]FeatureType {
578 .CodeObjectV3,
579 .NoSramEccSupport,
580 .ApertureRegs,
581 .IntClampInsts,
582 .SdwaOmod,
583 .SdwaScalar,
584 .AddNoCarryInsts,
585 .ScalarAtomics,
586 .SMemrealtime,
587 .Gcn3Encoding,
588 .CiInsts,
589 .FlatAddressSpace,
590 .Sdwa,
591 .Wavefrontsize64,
592 .SdwaSdst,
593 .FlatInstOffsets,
594 .ScalarStores,
595 .Gfx7Gfx8Gfx9Insts,
596 .R128A16,
597 .Dpp,
598 .Localmemorysize65536,
599 .Vop3p,
600 .BitInsts16,
601 .VgprIndexMode,
602 .Gfx8Insts,
603 .Inv2piInlineImm,
604 .Gfx9Insts,
605 .ScalarFlatScratchInsts,
606 .FlatGlobalInsts,
607 .FlatScratchInsts,
608 .Fp64,
609 .FastFmaf,
610 .Gfx9,
611 .Ldsbankcount32,
612 .MadMixInsts,
613 .Xnack,
614 }),
615 CpuInfo(@This(), FeatureType).create(.Gfx904, "gfx904", &[_]FeatureType {
616 .CodeObjectV3,
617 .NoSramEccSupport,
618 .NoXnackSupport,
619 .FmaMixInsts,
620 .ApertureRegs,
621 .IntClampInsts,
622 .SdwaOmod,
623 .SdwaScalar,
624 .AddNoCarryInsts,
625 .ScalarAtomics,
626 .SMemrealtime,
627 .Gcn3Encoding,
628 .CiInsts,
629 .FlatAddressSpace,
630 .Sdwa,
631 .Wavefrontsize64,
632 .SdwaSdst,
633 .FlatInstOffsets,
634 .ScalarStores,
635 .Gfx7Gfx8Gfx9Insts,
636 .R128A16,
637 .Dpp,
638 .Localmemorysize65536,
639 .Vop3p,
640 .BitInsts16,
641 .VgprIndexMode,
642 .Gfx8Insts,
643 .Inv2piInlineImm,
644 .Gfx9Insts,
645 .ScalarFlatScratchInsts,
646 .FlatGlobalInsts,
647 .FlatScratchInsts,
648 .Fp64,
649 .FastFmaf,
650 .Gfx9,
651 .Ldsbankcount32,
652 }),
653 CpuInfo(@This(), FeatureType).create(.Gfx906, "gfx906", &[_]FeatureType {
654 .CodeObjectV3,
655 .DlInsts,
656 .NoXnackSupport,
657 .Dot1Insts,
658 .Dot2Insts,
659 .FmaMixInsts,
660 .ApertureRegs,
661 .IntClampInsts,
662 .SdwaOmod,
663 .SdwaScalar,
664 .AddNoCarryInsts,
665 .ScalarAtomics,
666 .SMemrealtime,
667 .Gcn3Encoding,
668 .CiInsts,
669 .FlatAddressSpace,
670 .Sdwa,
671 .Wavefrontsize64,
672 .SdwaSdst,
673 .FlatInstOffsets,
674 .ScalarStores,
675 .Gfx7Gfx8Gfx9Insts,
676 .R128A16,
677 .Dpp,
678 .Localmemorysize65536,
679 .Vop3p,
680 .BitInsts16,
681 .VgprIndexMode,
682 .Gfx8Insts,
683 .Inv2piInlineImm,
684 .Gfx9Insts,
685 .ScalarFlatScratchInsts,
686 .FlatGlobalInsts,
687 .FlatScratchInsts,
688 .Fp64,
689 .FastFmaf,
690 .Gfx9,
691 .Ldsbankcount32,
692 .HalfRate64Ops,
693 }),
694 CpuInfo(@This(), FeatureType).create(.Gfx908, "gfx908", &[_]FeatureType {
695 .AtomicFaddInsts,
696 .CodeObjectV3,
697 .DlInsts,
698 .Dot1Insts,
699 .Dot2Insts,
700 .Dot3Insts,
701 .Dot4Insts,
702 .Dot5Insts,
703 .Dot6Insts,
704 .FmaMixInsts,
705 .ApertureRegs,
706 .IntClampInsts,
707 .SdwaOmod,
708 .SdwaScalar,
709 .AddNoCarryInsts,
710 .ScalarAtomics,
711 .SMemrealtime,
712 .Gcn3Encoding,
713 .CiInsts,
714 .FlatAddressSpace,
715 .Sdwa,
716 .Wavefrontsize64,
717 .SdwaSdst,
718 .FlatInstOffsets,
719 .ScalarStores,
720 .Gfx7Gfx8Gfx9Insts,
721 .R128A16,
722 .Dpp,
723 .Localmemorysize65536,
724 .Vop3p,
725 .BitInsts16,
726 .VgprIndexMode,
727 .Gfx8Insts,
728 .Inv2piInlineImm,
729 .Gfx9Insts,
730 .ScalarFlatScratchInsts,
731 .FlatGlobalInsts,
732 .FlatScratchInsts,
733 .Fp64,
734 .FastFmaf,
735 .Gfx9,
736 .Ldsbankcount32,
737 .MaiInsts,
738 .MfmaInlineLiteralBug,
739 .PkFmacF16Inst,
740 .SramEcc,
741 .HalfRate64Ops,
742 }),
743 CpuInfo(@This(), FeatureType).create(.Gfx909, "gfx909", &[_]FeatureType {
744 .CodeObjectV3,
745 .ApertureRegs,
746 .IntClampInsts,
747 .SdwaOmod,
748 .SdwaScalar,
749 .AddNoCarryInsts,
750 .ScalarAtomics,
751 .SMemrealtime,
752 .Gcn3Encoding,
753 .CiInsts,
754 .FlatAddressSpace,
755 .Sdwa,
756 .Wavefrontsize64,
757 .SdwaSdst,
758 .FlatInstOffsets,
759 .ScalarStores,
760 .Gfx7Gfx8Gfx9Insts,
761 .R128A16,
762 .Dpp,
763 .Localmemorysize65536,
764 .Vop3p,
765 .BitInsts16,
766 .VgprIndexMode,
767 .Gfx8Insts,
768 .Inv2piInlineImm,
769 .Gfx9Insts,
770 .ScalarFlatScratchInsts,
771 .FlatGlobalInsts,
772 .FlatScratchInsts,
773 .Fp64,
774 .FastFmaf,
775 .Gfx9,
776 .Ldsbankcount32,
777 .MadMixInsts,
778 .Xnack,
779 }),
780 CpuInfo(@This(), FeatureType).create(.Hainan, "hainan", &[_]FeatureType {
781 .CodeObjectV3,
782 .NoXnackSupport,
783 .Ldsbankcount32,
784 .Movrel,
785 .MimgR128,
786 .Fp64,
787 .TrigReducedRange,
788 .Wavefrontsize64,
789 .NoSramEccSupport,
790 .Localmemorysize32768,
791 .SouthernIslands,
792 }),
793 CpuInfo(@This(), FeatureType).create(.Hawaii, "hawaii", &[_]FeatureType {
794 .CodeObjectV3,
795 .NoXnackSupport,
796 .FastFmaf,
797 .Ldsbankcount32,
798 .Movrel,
799 .Gfx7Gfx8Gfx9Insts,
800 .Fp64,
801 .TrigReducedRange,
802 .CiInsts,
803 .FlatAddressSpace,
804 .Localmemorysize65536,
805 .Wavefrontsize64,
806 .NoSramEccSupport,
807 .MimgR128,
808 .SeaIslands,
809 .HalfRate64Ops,
810 }),
811 CpuInfo(@This(), FeatureType).create(.Iceland, "iceland", &[_]FeatureType {
812 .CodeObjectV3,
813 .NoXnackSupport,
814 .Ldsbankcount32,
815 .SgprInitBug,
816 .UnpackedD16Vmem,
817 .IntClampInsts,
818 .SdwaMav,
819 .Movrel,
820 .SMemrealtime,
821 .Gcn3Encoding,
822 .TrigReducedRange,
823 .CiInsts,
824 .FlatAddressSpace,
825 .Sdwa,
826 .Wavefrontsize64,
827 .NoSramEccSupport,
828 .ScalarStores,
829 .Gfx7Gfx8Gfx9Insts,
830 .Dpp,
831 .Localmemorysize65536,
832 .BitInsts16,
833 .VgprIndexMode,
834 .Gfx8Insts,
835 .Inv2piInlineImm,
836 .MimgR128,
837 .SdwaOutModsVopc,
838 .Fp64,
839 .VolcanicIslands,
840 }),
841 CpuInfo(@This(), FeatureType).create(.Kabini, "kabini", &[_]FeatureType {
842 .CodeObjectV3,
843 .NoXnackSupport,
844 .Ldsbankcount16,
845 .Movrel,
846 .Gfx7Gfx8Gfx9Insts,
847 .Fp64,
848 .TrigReducedRange,
849 .CiInsts,
850 .FlatAddressSpace,
851 .Localmemorysize65536,
852 .Wavefrontsize64,
853 .NoSramEccSupport,
854 .MimgR128,
855 .SeaIslands,
856 }),
857 CpuInfo(@This(), FeatureType).create(.Kaveri, "kaveri", &[_]FeatureType {
858 .CodeObjectV3,
859 .NoXnackSupport,
860 .Ldsbankcount32,
861 .Movrel,
862 .Gfx7Gfx8Gfx9Insts,
863 .Fp64,
864 .TrigReducedRange,
865 .CiInsts,
866 .FlatAddressSpace,
867 .Localmemorysize65536,
868 .Wavefrontsize64,
869 .NoSramEccSupport,
870 .MimgR128,
871 .SeaIslands,
872 }),
873 CpuInfo(@This(), FeatureType).create(.Mullins, "mullins", &[_]FeatureType {
874 .CodeObjectV3,
875 .NoXnackSupport,
876 .Ldsbankcount16,
877 .Movrel,
878 .Gfx7Gfx8Gfx9Insts,
879 .Fp64,
880 .TrigReducedRange,
881 .CiInsts,
882 .FlatAddressSpace,
883 .Localmemorysize65536,
884 .Wavefrontsize64,
885 .NoSramEccSupport,
886 .MimgR128,
887 .SeaIslands,
888 }),
889 CpuInfo(@This(), FeatureType).create(.Oland, "oland", &[_]FeatureType {
890 .CodeObjectV3,
891 .NoXnackSupport,
892 .Ldsbankcount32,
893 .Movrel,
894 .MimgR128,
895 .Fp64,
896 .TrigReducedRange,
897 .Wavefrontsize64,
898 .NoSramEccSupport,
899 .Localmemorysize32768,
900 .SouthernIslands,
901 }),
902 CpuInfo(@This(), FeatureType).create(.Pitcairn, "pitcairn", &[_]FeatureType {
903 .CodeObjectV3,
904 .NoXnackSupport,
905 .Ldsbankcount32,
906 .Movrel,
907 .MimgR128,
908 .Fp64,
909 .TrigReducedRange,
910 .Wavefrontsize64,
911 .NoSramEccSupport,
912 .Localmemorysize32768,
913 .SouthernIslands,
914 }),
915 CpuInfo(@This(), FeatureType).create(.Polaris10, "polaris10", &[_]FeatureType {
916 .CodeObjectV3,
917 .NoXnackSupport,
918 .Ldsbankcount32,
919 .UnpackedD16Vmem,
920 .IntClampInsts,
921 .SdwaMav,
922 .Movrel,
923 .SMemrealtime,
924 .Gcn3Encoding,
925 .TrigReducedRange,
926 .CiInsts,
927 .FlatAddressSpace,
928 .Sdwa,
929 .Wavefrontsize64,
930 .NoSramEccSupport,
931 .ScalarStores,
932 .Gfx7Gfx8Gfx9Insts,
933 .Dpp,
934 .Localmemorysize65536,
935 .BitInsts16,
936 .VgprIndexMode,
937 .Gfx8Insts,
938 .Inv2piInlineImm,
939 .MimgR128,
940 .SdwaOutModsVopc,
941 .Fp64,
942 .VolcanicIslands,
943 }),
944 CpuInfo(@This(), FeatureType).create(.Polaris11, "polaris11", &[_]FeatureType {
945 .CodeObjectV3,
946 .NoXnackSupport,
947 .Ldsbankcount32,
948 .UnpackedD16Vmem,
949 .IntClampInsts,
950 .SdwaMav,
951 .Movrel,
952 .SMemrealtime,
953 .Gcn3Encoding,
954 .TrigReducedRange,
955 .CiInsts,
956 .FlatAddressSpace,
957 .Sdwa,
958 .Wavefrontsize64,
959 .NoSramEccSupport,
960 .ScalarStores,
961 .Gfx7Gfx8Gfx9Insts,
962 .Dpp,
963 .Localmemorysize65536,
964 .BitInsts16,
965 .VgprIndexMode,
966 .Gfx8Insts,
967 .Inv2piInlineImm,
968 .MimgR128,
969 .SdwaOutModsVopc,
970 .Fp64,
971 .VolcanicIslands,
972 }),
973 CpuInfo(@This(), FeatureType).create(.Stoney, "stoney", &[_]FeatureType {
974 .CodeObjectV3,
975 .Ldsbankcount16,
976 .IntClampInsts,
977 .SdwaMav,
978 .Movrel,
979 .SMemrealtime,
980 .Gcn3Encoding,
981 .TrigReducedRange,
982 .CiInsts,
983 .FlatAddressSpace,
984 .Sdwa,
985 .Wavefrontsize64,
986 .NoSramEccSupport,
987 .ScalarStores,
988 .Gfx7Gfx8Gfx9Insts,
989 .Dpp,
990 .Localmemorysize65536,
991 .BitInsts16,
992 .VgprIndexMode,
993 .Gfx8Insts,
994 .Inv2piInlineImm,
995 .MimgR128,
996 .SdwaOutModsVopc,
997 .Fp64,
998 .VolcanicIslands,
999 .Xnack,
1000 }),
1001 CpuInfo(@This(), FeatureType).create(.Tahiti, "tahiti", &[_]FeatureType {
1002 .CodeObjectV3,
1003 .NoXnackSupport,
1004 .FastFmaf,
1005 .Ldsbankcount32,
1006 .Movrel,
1007 .MimgR128,
1008 .Fp64,
1009 .TrigReducedRange,
1010 .Wavefrontsize64,
1011 .NoSramEccSupport,
1012 .Localmemorysize32768,
1013 .SouthernIslands,
1014 .HalfRate64Ops,
1015 }),
1016 CpuInfo(@This(), FeatureType).create(.Tonga, "tonga", &[_]FeatureType {
1017 .CodeObjectV3,
1018 .NoXnackSupport,
1019 .Ldsbankcount32,
1020 .SgprInitBug,
1021 .UnpackedD16Vmem,
1022 .IntClampInsts,
1023 .SdwaMav,
1024 .Movrel,
1025 .SMemrealtime,
1026 .Gcn3Encoding,
1027 .TrigReducedRange,
1028 .CiInsts,
1029 .FlatAddressSpace,
1030 .Sdwa,
1031 .Wavefrontsize64,
1032 .NoSramEccSupport,
1033 .ScalarStores,
1034 .Gfx7Gfx8Gfx9Insts,
1035 .Dpp,
1036 .Localmemorysize65536,
1037 .BitInsts16,
1038 .VgprIndexMode,
1039 .Gfx8Insts,
1040 .Inv2piInlineImm,
1041 .MimgR128,
1042 .SdwaOutModsVopc,
1043 .Fp64,
1044 .VolcanicIslands,
1045 }),
1046 CpuInfo(@This(), FeatureType).create(.Verde, "verde", &[_]FeatureType {
1047 .CodeObjectV3,
1048 .NoXnackSupport,
1049 .Ldsbankcount32,
1050 .Movrel,
1051 .MimgR128,
1052 .Fp64,
1053 .TrigReducedRange,
1054 .Wavefrontsize64,
1055 .NoSramEccSupport,
1056 .Localmemorysize32768,
1057 .SouthernIslands,
1058 }),
1059 };
1060};
lib/std/target/cpu/ArmCpu.zig deleted-1230
......@@ -1,1230 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const ArmCpu = enum {
5 Arm1020e,
6 Arm1020t,
7 Arm1022e,
8 Arm10e,
9 Arm10tdmi,
10 Arm1136jS,
11 Arm1136jfS,
12 Arm1156t2S,
13 Arm1156t2fS,
14 Arm1176jS,
15 Arm1176jzS,
16 Arm1176jzfS,
17 Arm710t,
18 Arm720t,
19 Arm7tdmi,
20 Arm7tdmiS,
21 Arm8,
22 Arm810,
23 Arm9,
24 Arm920,
25 Arm920t,
26 Arm922t,
27 Arm926ejS,
28 Arm940t,
29 Arm946eS,
30 Arm966eS,
31 Arm968eS,
32 Arm9e,
33 Arm9tdmi,
34 CortexA12,
35 CortexA15,
36 CortexA17,
37 CortexA32,
38 CortexA35,
39 CortexA5,
40 CortexA53,
41 CortexA55,
42 CortexA57,
43 CortexA7,
44 CortexA72,
45 CortexA73,
46 CortexA75,
47 CortexA76,
48 CortexA76ae,
49 CortexA8,
50 CortexA9,
51 CortexM0,
52 CortexM0plus,
53 CortexM1,
54 CortexM23,
55 CortexM3,
56 CortexM33,
57 CortexM35p,
58 CortexM4,
59 CortexM7,
60 CortexR4,
61 CortexR4f,
62 CortexR5,
63 CortexR52,
64 CortexR7,
65 CortexR8,
66 Cyclone,
67 Ep9312,
68 ExynosM1,
69 ExynosM2,
70 ExynosM3,
71 ExynosM4,
72 ExynosM5,
73 Generic,
74 Iwmmxt,
75 Krait,
76 Kryo,
77 Mpcore,
78 Mpcorenovfp,
79 NeoverseN1,
80 Sc000,
81 Sc300,
82 Strongarm,
83 Strongarm110,
84 Strongarm1100,
85 Strongarm1110,
86 Swift,
87 Xscale,
88
89 const FeatureType = feature.ArmFeature;
90
91 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
92 return cpu_infos[@enumToInt(self)];
93 }
94
95 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
96 CpuInfo(@This(), FeatureType).create(.Arm1020e, "arm1020e", &[_]FeatureType {
97 .V4t,
98 .Armv5te,
99 }),
100 CpuInfo(@This(), FeatureType).create(.Arm1020t, "arm1020t", &[_]FeatureType {
101 .V4t,
102 .Armv5t,
103 }),
104 CpuInfo(@This(), FeatureType).create(.Arm1022e, "arm1022e", &[_]FeatureType {
105 .V4t,
106 .Armv5te,
107 }),
108 CpuInfo(@This(), FeatureType).create(.Arm10e, "arm10e", &[_]FeatureType {
109 .V4t,
110 .Armv5te,
111 }),
112 CpuInfo(@This(), FeatureType).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
113 .V4t,
114 .Armv5t,
115 }),
116 CpuInfo(@This(), FeatureType).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
117 .V4t,
118 .Dsp,
119 .Armv6,
120 }),
121 CpuInfo(@This(), FeatureType).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
122 .V4t,
123 .Dsp,
124 .Armv6,
125 .Slowfpvmlx,
126 .Fpregs,
127 .Vfp2,
128 }),
129 CpuInfo(@This(), FeatureType).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
130 .V4t,
131 .Thumb2,
132 .Dsp,
133 .Armv6t2,
134 }),
135 CpuInfo(@This(), FeatureType).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
136 .V4t,
137 .Thumb2,
138 .Dsp,
139 .Armv6t2,
140 .Slowfpvmlx,
141 .Fpregs,
142 .Vfp2,
143 }),
144 CpuInfo(@This(), FeatureType).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
145 .V4t,
146 .Trustzone,
147 .Armv6kz,
148 }),
149 CpuInfo(@This(), FeatureType).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
150 .V4t,
151 .Trustzone,
152 .Armv6kz,
153 }),
154 CpuInfo(@This(), FeatureType).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
155 .V4t,
156 .Trustzone,
157 .Armv6kz,
158 .Slowfpvmlx,
159 .Fpregs,
160 .Vfp2,
161 }),
162 CpuInfo(@This(), FeatureType).create(.Arm710t, "arm710t", &[_]FeatureType {
163 .V4t,
164 .Armv4t,
165 }),
166 CpuInfo(@This(), FeatureType).create(.Arm720t, "arm720t", &[_]FeatureType {
167 .V4t,
168 .Armv4t,
169 }),
170 CpuInfo(@This(), FeatureType).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
171 .V4t,
172 .Armv4t,
173 }),
174 CpuInfo(@This(), FeatureType).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
175 .V4t,
176 .Armv4t,
177 }),
178 CpuInfo(@This(), FeatureType).create(.Arm8, "arm8", &[_]FeatureType {
179 .Armv4,
180 }),
181 CpuInfo(@This(), FeatureType).create(.Arm810, "arm810", &[_]FeatureType {
182 .Armv4,
183 }),
184 CpuInfo(@This(), FeatureType).create(.Arm9, "arm9", &[_]FeatureType {
185 .V4t,
186 .Armv4t,
187 }),
188 CpuInfo(@This(), FeatureType).create(.Arm920, "arm920", &[_]FeatureType {
189 .V4t,
190 .Armv4t,
191 }),
192 CpuInfo(@This(), FeatureType).create(.Arm920t, "arm920t", &[_]FeatureType {
193 .V4t,
194 .Armv4t,
195 }),
196 CpuInfo(@This(), FeatureType).create(.Arm922t, "arm922t", &[_]FeatureType {
197 .V4t,
198 .Armv4t,
199 }),
200 CpuInfo(@This(), FeatureType).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
201 .V4t,
202 .Armv5te,
203 }),
204 CpuInfo(@This(), FeatureType).create(.Arm940t, "arm940t", &[_]FeatureType {
205 .V4t,
206 .Armv4t,
207 }),
208 CpuInfo(@This(), FeatureType).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
209 .V4t,
210 .Armv5te,
211 }),
212 CpuInfo(@This(), FeatureType).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
213 .V4t,
214 .Armv5te,
215 }),
216 CpuInfo(@This(), FeatureType).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
217 .V4t,
218 .Armv5te,
219 }),
220 CpuInfo(@This(), FeatureType).create(.Arm9e, "arm9e", &[_]FeatureType {
221 .V4t,
222 .Armv5te,
223 }),
224 CpuInfo(@This(), FeatureType).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
225 .V4t,
226 .Armv4t,
227 }),
228 CpuInfo(@This(), FeatureType).create(.CortexA12, "cortex-a12", &[_]FeatureType {
229 .Perfmon,
230 .V4t,
231 .D32,
232 .Fpregs,
233 .V7clrex,
234 .Dsp,
235 .Thumb2,
236 .Db,
237 .Aclass,
238 .Armv7A,
239 .AvoidPartialCpsr,
240 .RetAddrStack,
241 .Mp,
242 .Trustzone,
243 .Fp16,
244 .Vfp4,
245 .VmlxForwarding,
246 .HwdivArm,
247 .Hwdiv,
248 .Virtualization,
249 .A12,
250 }),
251 CpuInfo(@This(), FeatureType).create(.CortexA15, "cortex-a15", &[_]FeatureType {
252 .Perfmon,
253 .V4t,
254 .D32,
255 .Fpregs,
256 .V7clrex,
257 .Dsp,
258 .Thumb2,
259 .Db,
260 .Aclass,
261 .Armv7A,
262 .AvoidPartialCpsr,
263 .VldnAlign,
264 .DontWidenVmovs,
265 .RetAddrStack,
266 .Mp,
267 .MuxedUnits,
268 .SplatVfpNeon,
269 .Trustzone,
270 .Fp16,
271 .Vfp4,
272 .HwdivArm,
273 .Hwdiv,
274 .Virtualization,
275 .A15,
276 }),
277 CpuInfo(@This(), FeatureType).create(.CortexA17, "cortex-a17", &[_]FeatureType {
278 .Perfmon,
279 .V4t,
280 .D32,
281 .Fpregs,
282 .V7clrex,
283 .Dsp,
284 .Thumb2,
285 .Db,
286 .Aclass,
287 .Armv7A,
288 .AvoidPartialCpsr,
289 .RetAddrStack,
290 .Mp,
291 .Trustzone,
292 .Fp16,
293 .Vfp4,
294 .VmlxForwarding,
295 .HwdivArm,
296 .Hwdiv,
297 .Virtualization,
298 .A17,
299 }),
300 CpuInfo(@This(), FeatureType).create(.CortexA32, "cortex-a32", &[_]FeatureType {
301 .HwdivArm,
302 .Perfmon,
303 .D32,
304 .Fpregs,
305 .Crc,
306 .Mp,
307 .Fp16,
308 .Dsp,
309 .V4t,
310 .V7clrex,
311 .Db,
312 .Aclass,
313 .Thumb2,
314 .AcquireRelease,
315 .Hwdiv,
316 .Trustzone,
317 .Armv8A,
318 .Crypto,
319 }),
320 CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
321 .HwdivArm,
322 .Perfmon,
323 .D32,
324 .Fpregs,
325 .Crc,
326 .Mp,
327 .Fp16,
328 .Dsp,
329 .V4t,
330 .V7clrex,
331 .Db,
332 .Aclass,
333 .Thumb2,
334 .AcquireRelease,
335 .Hwdiv,
336 .Trustzone,
337 .Armv8A,
338 .Crypto,
339 .A35,
340 }),
341 CpuInfo(@This(), FeatureType).create(.CortexA5, "cortex-a5", &[_]FeatureType {
342 .Perfmon,
343 .V4t,
344 .D32,
345 .Fpregs,
346 .V7clrex,
347 .Dsp,
348 .Thumb2,
349 .Db,
350 .Aclass,
351 .Armv7A,
352 .RetAddrStack,
353 .Slowfpvmlx,
354 .Mp,
355 .SlowFpBrcc,
356 .Trustzone,
357 .Fp16,
358 .Vfp4,
359 .VmlxForwarding,
360 .A5,
361 }),
362 CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
363 .HwdivArm,
364 .Perfmon,
365 .D32,
366 .Fpregs,
367 .Crc,
368 .Mp,
369 .Fp16,
370 .Dsp,
371 .V4t,
372 .V7clrex,
373 .Db,
374 .Aclass,
375 .Thumb2,
376 .AcquireRelease,
377 .Hwdiv,
378 .Trustzone,
379 .Armv8A,
380 .Crypto,
381 .Fpao,
382 .A53,
383 }),
384 CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
385 .HwdivArm,
386 .Perfmon,
387 .D32,
388 .Fpregs,
389 .Crc,
390 .Mp,
391 .Fp16,
392 .Dsp,
393 .V4t,
394 .V7clrex,
395 .Db,
396 .Aclass,
397 .Thumb2,
398 .Ras,
399 .AcquireRelease,
400 .Hwdiv,
401 .Trustzone,
402 .Armv82A,
403 .Dotprod,
404 .A55,
405 }),
406 CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
407 .HwdivArm,
408 .Perfmon,
409 .D32,
410 .Fpregs,
411 .Crc,
412 .Mp,
413 .Fp16,
414 .Dsp,
415 .V4t,
416 .V7clrex,
417 .Db,
418 .Aclass,
419 .Thumb2,
420 .AcquireRelease,
421 .Hwdiv,
422 .Trustzone,
423 .Armv8A,
424 .AvoidPartialCpsr,
425 .CheapPredicableCpsr,
426 .Crypto,
427 .Fpao,
428 .A57,
429 }),
430 CpuInfo(@This(), FeatureType).create(.CortexA7, "cortex-a7", &[_]FeatureType {
431 .Perfmon,
432 .V4t,
433 .D32,
434 .Fpregs,
435 .V7clrex,
436 .Dsp,
437 .Thumb2,
438 .Db,
439 .Aclass,
440 .Armv7A,
441 .RetAddrStack,
442 .Slowfpvmlx,
443 .VmlxHazards,
444 .Mp,
445 .SlowFpBrcc,
446 .Trustzone,
447 .Fp16,
448 .Vfp4,
449 .VmlxForwarding,
450 .HwdivArm,
451 .Hwdiv,
452 .Virtualization,
453 .A7,
454 }),
455 CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
456 .HwdivArm,
457 .Perfmon,
458 .D32,
459 .Fpregs,
460 .Crc,
461 .Mp,
462 .Fp16,
463 .Dsp,
464 .V4t,
465 .V7clrex,
466 .Db,
467 .Aclass,
468 .Thumb2,
469 .AcquireRelease,
470 .Hwdiv,
471 .Trustzone,
472 .Armv8A,
473 .Crypto,
474 .A72,
475 }),
476 CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
477 .HwdivArm,
478 .Perfmon,
479 .D32,
480 .Fpregs,
481 .Crc,
482 .Mp,
483 .Fp16,
484 .Dsp,
485 .V4t,
486 .V7clrex,
487 .Db,
488 .Aclass,
489 .Thumb2,
490 .AcquireRelease,
491 .Hwdiv,
492 .Trustzone,
493 .Armv8A,
494 .Crypto,
495 .A73,
496 }),
497 CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
498 .HwdivArm,
499 .Perfmon,
500 .D32,
501 .Fpregs,
502 .Crc,
503 .Mp,
504 .Fp16,
505 .Dsp,
506 .V4t,
507 .V7clrex,
508 .Db,
509 .Aclass,
510 .Thumb2,
511 .Ras,
512 .AcquireRelease,
513 .Hwdiv,
514 .Trustzone,
515 .Armv82A,
516 .Dotprod,
517 .A75,
518 }),
519 CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
520 .HwdivArm,
521 .Perfmon,
522 .D32,
523 .Fpregs,
524 .Crc,
525 .Mp,
526 .Fp16,
527 .Dsp,
528 .V4t,
529 .V7clrex,
530 .Db,
531 .Aclass,
532 .Thumb2,
533 .Ras,
534 .AcquireRelease,
535 .Hwdiv,
536 .Trustzone,
537 .Armv82A,
538 .Crypto,
539 .Dotprod,
540 .Fullfp16,
541 .A76,
542 }),
543 CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
544 .HwdivArm,
545 .Perfmon,
546 .D32,
547 .Fpregs,
548 .Crc,
549 .Mp,
550 .Fp16,
551 .Dsp,
552 .V4t,
553 .V7clrex,
554 .Db,
555 .Aclass,
556 .Thumb2,
557 .Ras,
558 .AcquireRelease,
559 .Hwdiv,
560 .Trustzone,
561 .Armv82A,
562 .Crypto,
563 .Dotprod,
564 .Fullfp16,
565 .A76,
566 }),
567 CpuInfo(@This(), FeatureType).create(.CortexA8, "cortex-a8", &[_]FeatureType {
568 .Perfmon,
569 .V4t,
570 .D32,
571 .Fpregs,
572 .V7clrex,
573 .Dsp,
574 .Thumb2,
575 .Db,
576 .Aclass,
577 .Armv7A,
578 .RetAddrStack,
579 .Slowfpvmlx,
580 .VmlxHazards,
581 .NonpipelinedVfp,
582 .SlowFpBrcc,
583 .Trustzone,
584 .VmlxForwarding,
585 .A8,
586 }),
587 CpuInfo(@This(), FeatureType).create(.CortexA9, "cortex-a9", &[_]FeatureType {
588 .Perfmon,
589 .V4t,
590 .D32,
591 .Fpregs,
592 .V7clrex,
593 .Dsp,
594 .Thumb2,
595 .Db,
596 .Aclass,
597 .Armv7A,
598 .AvoidPartialCpsr,
599 .VldnAlign,
600 .ExpandFpMlx,
601 .Fp16,
602 .RetAddrStack,
603 .VmlxHazards,
604 .Mp,
605 .MuxedUnits,
606 .NeonFpmovs,
607 .PreferVmovsr,
608 .Trustzone,
609 .VmlxForwarding,
610 .A9,
611 }),
612 CpuInfo(@This(), FeatureType).create(.CortexM0, "cortex-m0", &[_]FeatureType {
613 .V4t,
614 .ThumbMode,
615 .Db,
616 .StrictAlign,
617 .Mclass,
618 .Noarm,
619 .Armv6M,
620 }),
621 CpuInfo(@This(), FeatureType).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
622 .V4t,
623 .ThumbMode,
624 .Db,
625 .StrictAlign,
626 .Mclass,
627 .Noarm,
628 .Armv6M,
629 }),
630 CpuInfo(@This(), FeatureType).create(.CortexM1, "cortex-m1", &[_]FeatureType {
631 .V4t,
632 .ThumbMode,
633 .Db,
634 .StrictAlign,
635 .Mclass,
636 .Noarm,
637 .Armv6M,
638 }),
639 CpuInfo(@This(), FeatureType).create(.CortexM23, "cortex-m23", &[_]FeatureType {
640 .V4t,
641 .ThumbMode,
642 .Msecext8,
643 .V7clrex,
644 .Db,
645 .StrictAlign,
646 .Mclass,
647 .Noarm,
648 .AcquireRelease,
649 .Hwdiv,
650 .Armv8Mbase,
651 .NoMovt,
652 }),
653 CpuInfo(@This(), FeatureType).create(.CortexM3, "cortex-m3", &[_]FeatureType {
654 .Perfmon,
655 .V4t,
656 .ThumbMode,
657 .V7clrex,
658 .Thumb2,
659 .Db,
660 .Mclass,
661 .Noarm,
662 .Hwdiv,
663 .Armv7M,
664 .NoBranchPredictor,
665 .LoopAlign,
666 .UseAa,
667 .UseMisched,
668 .M3,
669 }),
670 CpuInfo(@This(), FeatureType).create(.CortexM33, "cortex-m33", &[_]FeatureType {
671 .Perfmon,
672 .V4t,
673 .ThumbMode,
674 .Msecext8,
675 .V7clrex,
676 .Thumb2,
677 .Db,
678 .Mclass,
679 .Noarm,
680 .AcquireRelease,
681 .Hwdiv,
682 .Armv8Mmain,
683 .Dsp,
684 .Fpregs,
685 .Fp16,
686 .FpArmv8d16sp,
687 .NoBranchPredictor,
688 .Slowfpvmlx,
689 .LoopAlign,
690 .UseAa,
691 .UseMisched,
692 }),
693 CpuInfo(@This(), FeatureType).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
694 .Perfmon,
695 .V4t,
696 .ThumbMode,
697 .Msecext8,
698 .V7clrex,
699 .Thumb2,
700 .Db,
701 .Mclass,
702 .Noarm,
703 .AcquireRelease,
704 .Hwdiv,
705 .Armv8Mmain,
706 .Dsp,
707 .Fpregs,
708 .Fp16,
709 .FpArmv8d16sp,
710 .NoBranchPredictor,
711 .Slowfpvmlx,
712 .LoopAlign,
713 .UseAa,
714 .UseMisched,
715 }),
716 CpuInfo(@This(), FeatureType).create(.CortexM4, "cortex-m4", &[_]FeatureType {
717 .Perfmon,
718 .V4t,
719 .ThumbMode,
720 .V7clrex,
721 .Dsp,
722 .Thumb2,
723 .Db,
724 .Mclass,
725 .Noarm,
726 .Hwdiv,
727 .Armv7eM,
728 .NoBranchPredictor,
729 .Slowfpvmlx,
730 .LoopAlign,
731 .UseAa,
732 .UseMisched,
733 .Fpregs,
734 .Fp16,
735 .Vfp4d16sp,
736 }),
737 CpuInfo(@This(), FeatureType).create(.CortexM7, "cortex-m7", &[_]FeatureType {
738 .Perfmon,
739 .V4t,
740 .ThumbMode,
741 .V7clrex,
742 .Dsp,
743 .Thumb2,
744 .Db,
745 .Mclass,
746 .Noarm,
747 .Hwdiv,
748 .Armv7eM,
749 .Fpregs,
750 .Fp16,
751 .FpArmv8d16,
752 }),
753 CpuInfo(@This(), FeatureType).create(.CortexR4, "cortex-r4", &[_]FeatureType {
754 .Perfmon,
755 .V4t,
756 .V7clrex,
757 .Dsp,
758 .Thumb2,
759 .Db,
760 .Hwdiv,
761 .Rclass,
762 .Armv7R,
763 .AvoidPartialCpsr,
764 .RetAddrStack,
765 .R4,
766 }),
767 CpuInfo(@This(), FeatureType).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
768 .Perfmon,
769 .V4t,
770 .V7clrex,
771 .Dsp,
772 .Thumb2,
773 .Db,
774 .Hwdiv,
775 .Rclass,
776 .Armv7R,
777 .AvoidPartialCpsr,
778 .RetAddrStack,
779 .Slowfpvmlx,
780 .SlowFpBrcc,
781 .Fpregs,
782 .Vfp3d16,
783 .R4,
784 }),
785 CpuInfo(@This(), FeatureType).create(.CortexR5, "cortex-r5", &[_]FeatureType {
786 .Perfmon,
787 .V4t,
788 .V7clrex,
789 .Dsp,
790 .Thumb2,
791 .Db,
792 .Hwdiv,
793 .Rclass,
794 .Armv7R,
795 .AvoidPartialCpsr,
796 .HwdivArm,
797 .RetAddrStack,
798 .Slowfpvmlx,
799 .SlowFpBrcc,
800 .Fpregs,
801 .Vfp3d16,
802 .R5,
803 }),
804 CpuInfo(@This(), FeatureType).create(.CortexR52, "cortex-r52", &[_]FeatureType {
805 .HwdivArm,
806 .Perfmon,
807 .D32,
808 .Crc,
809 .Fpregs,
810 .Mp,
811 .Dfb,
812 .Dsp,
813 .Fp16,
814 .V4t,
815 .Db,
816 .V7clrex,
817 .Thumb2,
818 .AcquireRelease,
819 .Hwdiv,
820 .Rclass,
821 .Armv8R,
822 .Fpao,
823 .UseAa,
824 .UseMisched,
825 .R52,
826 }),
827 CpuInfo(@This(), FeatureType).create(.CortexR7, "cortex-r7", &[_]FeatureType {
828 .Perfmon,
829 .V4t,
830 .V7clrex,
831 .Dsp,
832 .Thumb2,
833 .Db,
834 .Hwdiv,
835 .Rclass,
836 .Armv7R,
837 .AvoidPartialCpsr,
838 .Fp16,
839 .HwdivArm,
840 .RetAddrStack,
841 .Slowfpvmlx,
842 .Mp,
843 .SlowFpBrcc,
844 .Fpregs,
845 .Vfp3d16,
846 .R7,
847 }),
848 CpuInfo(@This(), FeatureType).create(.CortexR8, "cortex-r8", &[_]FeatureType {
849 .Perfmon,
850 .V4t,
851 .V7clrex,
852 .Dsp,
853 .Thumb2,
854 .Db,
855 .Hwdiv,
856 .Rclass,
857 .Armv7R,
858 .AvoidPartialCpsr,
859 .Fp16,
860 .HwdivArm,
861 .RetAddrStack,
862 .Slowfpvmlx,
863 .Mp,
864 .SlowFpBrcc,
865 .Fpregs,
866 .Vfp3d16,
867 }),
868 CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
869 .HwdivArm,
870 .Perfmon,
871 .D32,
872 .Fpregs,
873 .Crc,
874 .Mp,
875 .Fp16,
876 .Dsp,
877 .V4t,
878 .V7clrex,
879 .Db,
880 .Aclass,
881 .Thumb2,
882 .AcquireRelease,
883 .Hwdiv,
884 .Trustzone,
885 .Armv8A,
886 .AvoidMovsShop,
887 .AvoidPartialCpsr,
888 .Crypto,
889 .RetAddrStack,
890 .Slowfpvmlx,
891 .Neonfp,
892 .DisablePostraScheduler,
893 .UseMisched,
894 .Vfp4,
895 .Zcz,
896 .Swift,
897 }),
898 CpuInfo(@This(), FeatureType).create(.Ep9312, "ep9312", &[_]FeatureType {
899 .V4t,
900 .Armv4t,
901 }),
902 CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
903 .HwdivArm,
904 .Perfmon,
905 .D32,
906 .Fpregs,
907 .Crc,
908 .Mp,
909 .Fp16,
910 .Dsp,
911 .V4t,
912 .V7clrex,
913 .Db,
914 .Aclass,
915 .Thumb2,
916 .AcquireRelease,
917 .Hwdiv,
918 .Trustzone,
919 .Armv8A,
920 .RetAddrStack,
921 .SlowVgetlni32,
922 .WideStrideVfp,
923 .SlowVdup32,
924 .SlowFpBrcc,
925 .ProfUnpr,
926 .DontWidenVmovs,
927 .Zcz,
928 .FuseAes,
929 .Slowfpvmlx,
930 .UseAa,
931 .FuseLiterals,
932 .ExpandFpMlx,
933 .Exynos,
934 }),
935 CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
936 .HwdivArm,
937 .Perfmon,
938 .D32,
939 .Fpregs,
940 .Crc,
941 .Mp,
942 .Fp16,
943 .Dsp,
944 .V4t,
945 .V7clrex,
946 .Db,
947 .Aclass,
948 .Thumb2,
949 .AcquireRelease,
950 .Hwdiv,
951 .Trustzone,
952 .Armv8A,
953 .RetAddrStack,
954 .SlowVgetlni32,
955 .WideStrideVfp,
956 .SlowVdup32,
957 .SlowFpBrcc,
958 .ProfUnpr,
959 .DontWidenVmovs,
960 .Zcz,
961 .FuseAes,
962 .Slowfpvmlx,
963 .UseAa,
964 .FuseLiterals,
965 .ExpandFpMlx,
966 .Exynos,
967 }),
968 CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
969 .HwdivArm,
970 .Perfmon,
971 .D32,
972 .Fpregs,
973 .Crc,
974 .Mp,
975 .Fp16,
976 .Dsp,
977 .V4t,
978 .V7clrex,
979 .Db,
980 .Aclass,
981 .Thumb2,
982 .AcquireRelease,
983 .Hwdiv,
984 .Trustzone,
985 .Armv8A,
986 .RetAddrStack,
987 .SlowVgetlni32,
988 .WideStrideVfp,
989 .SlowVdup32,
990 .SlowFpBrcc,
991 .ProfUnpr,
992 .DontWidenVmovs,
993 .Zcz,
994 .FuseAes,
995 .Slowfpvmlx,
996 .UseAa,
997 .FuseLiterals,
998 .ExpandFpMlx,
999 .Exynos,
1000 }),
1001 CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
1002 .HwdivArm,
1003 .Perfmon,
1004 .D32,
1005 .Fpregs,
1006 .Crc,
1007 .Mp,
1008 .Fp16,
1009 .Dsp,
1010 .V4t,
1011 .V7clrex,
1012 .Db,
1013 .Aclass,
1014 .Thumb2,
1015 .Ras,
1016 .AcquireRelease,
1017 .Hwdiv,
1018 .Trustzone,
1019 .Armv82A,
1020 .Dotprod,
1021 .Fullfp16,
1022 .RetAddrStack,
1023 .SlowVgetlni32,
1024 .WideStrideVfp,
1025 .SlowVdup32,
1026 .SlowFpBrcc,
1027 .ProfUnpr,
1028 .DontWidenVmovs,
1029 .Zcz,
1030 .FuseAes,
1031 .Slowfpvmlx,
1032 .UseAa,
1033 .FuseLiterals,
1034 .ExpandFpMlx,
1035 .Exynos,
1036 }),
1037 CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
1038 .HwdivArm,
1039 .Perfmon,
1040 .D32,
1041 .Fpregs,
1042 .Crc,
1043 .Mp,
1044 .Fp16,
1045 .Dsp,
1046 .V4t,
1047 .V7clrex,
1048 .Db,
1049 .Aclass,
1050 .Thumb2,
1051 .Ras,
1052 .AcquireRelease,
1053 .Hwdiv,
1054 .Trustzone,
1055 .Armv82A,
1056 .Dotprod,
1057 .Fullfp16,
1058 .RetAddrStack,
1059 .SlowVgetlni32,
1060 .WideStrideVfp,
1061 .SlowVdup32,
1062 .SlowFpBrcc,
1063 .ProfUnpr,
1064 .DontWidenVmovs,
1065 .Zcz,
1066 .FuseAes,
1067 .Slowfpvmlx,
1068 .UseAa,
1069 .FuseLiterals,
1070 .ExpandFpMlx,
1071 .Exynos,
1072 }),
1073 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
1074 }),
1075 CpuInfo(@This(), FeatureType).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
1076 .V4t,
1077 .Armv5te,
1078 }),
1079 CpuInfo(@This(), FeatureType).create(.Krait, "krait", &[_]FeatureType {
1080 .Perfmon,
1081 .V4t,
1082 .D32,
1083 .Fpregs,
1084 .V7clrex,
1085 .Dsp,
1086 .Thumb2,
1087 .Db,
1088 .Aclass,
1089 .Armv7A,
1090 .AvoidPartialCpsr,
1091 .VldnAlign,
1092 .Fp16,
1093 .HwdivArm,
1094 .Hwdiv,
1095 .RetAddrStack,
1096 .MuxedUnits,
1097 .Vfp4,
1098 .VmlxForwarding,
1099 .Krait,
1100 }),
1101 CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
1102 .HwdivArm,
1103 .Perfmon,
1104 .D32,
1105 .Fpregs,
1106 .Crc,
1107 .Mp,
1108 .Fp16,
1109 .Dsp,
1110 .V4t,
1111 .V7clrex,
1112 .Db,
1113 .Aclass,
1114 .Thumb2,
1115 .AcquireRelease,
1116 .Hwdiv,
1117 .Trustzone,
1118 .Armv8A,
1119 .Crypto,
1120 .Kryo,
1121 }),
1122 CpuInfo(@This(), FeatureType).create(.Mpcore, "mpcore", &[_]FeatureType {
1123 .V4t,
1124 .Armv6k,
1125 .Slowfpvmlx,
1126 .Fpregs,
1127 .Vfp2,
1128 }),
1129 CpuInfo(@This(), FeatureType).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
1130 .V4t,
1131 .Armv6k,
1132 }),
1133 CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
1134 .HwdivArm,
1135 .Perfmon,
1136 .D32,
1137 .Fpregs,
1138 .Crc,
1139 .Mp,
1140 .Fp16,
1141 .Dsp,
1142 .V4t,
1143 .V7clrex,
1144 .Db,
1145 .Aclass,
1146 .Thumb2,
1147 .Ras,
1148 .AcquireRelease,
1149 .Hwdiv,
1150 .Trustzone,
1151 .Armv82A,
1152 .Crypto,
1153 .Dotprod,
1154 }),
1155 CpuInfo(@This(), FeatureType).create(.Sc000, "sc000", &[_]FeatureType {
1156 .V4t,
1157 .ThumbMode,
1158 .Db,
1159 .StrictAlign,
1160 .Mclass,
1161 .Noarm,
1162 .Armv6M,
1163 }),
1164 CpuInfo(@This(), FeatureType).create(.Sc300, "sc300", &[_]FeatureType {
1165 .Perfmon,
1166 .V4t,
1167 .ThumbMode,
1168 .V7clrex,
1169 .Thumb2,
1170 .Db,
1171 .Mclass,
1172 .Noarm,
1173 .Hwdiv,
1174 .Armv7M,
1175 .NoBranchPredictor,
1176 .UseAa,
1177 .UseMisched,
1178 .M3,
1179 }),
1180 CpuInfo(@This(), FeatureType).create(.Strongarm, "strongarm", &[_]FeatureType {
1181 .Armv4,
1182 }),
1183 CpuInfo(@This(), FeatureType).create(.Strongarm110, "strongarm110", &[_]FeatureType {
1184 .Armv4,
1185 }),
1186 CpuInfo(@This(), FeatureType).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
1187 .Armv4,
1188 }),
1189 CpuInfo(@This(), FeatureType).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
1190 .Armv4,
1191 }),
1192 CpuInfo(@This(), FeatureType).create(.Swift, "swift", &[_]FeatureType {
1193 .Perfmon,
1194 .V4t,
1195 .D32,
1196 .Fpregs,
1197 .V7clrex,
1198 .Dsp,
1199 .Thumb2,
1200 .Db,
1201 .Aclass,
1202 .Armv7A,
1203 .AvoidMovsShop,
1204 .AvoidPartialCpsr,
1205 .HwdivArm,
1206 .Hwdiv,
1207 .RetAddrStack,
1208 .Slowfpvmlx,
1209 .VmlxHazards,
1210 .Mp,
1211 .Neonfp,
1212 .DisablePostraScheduler,
1213 .PreferIshst,
1214 .ProfUnpr,
1215 .SlowLoadDSubreg,
1216 .SlowOddReg,
1217 .SlowVdup32,
1218 .SlowVgetlni32,
1219 .UseMisched,
1220 .WideStrideVfp,
1221 .Fp16,
1222 .Vfp4,
1223 .Swift,
1224 }),
1225 CpuInfo(@This(), FeatureType).create(.Xscale, "xscale", &[_]FeatureType {
1226 .V4t,
1227 .Armv5te,
1228 }),
1229 };
1230};
lib/std/target/cpu/AvrCpu.zig deleted-3863
......@@ -1,3863 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const AvrCpu = enum {
5 At43usb320,
6 At43usb355,
7 At76c711,
8 At86rf401,
9 At90c8534,
10 At90can128,
11 At90can32,
12 At90can64,
13 At90pwm1,
14 At90pwm161,
15 At90pwm2,
16 At90pwm216,
17 At90pwm2b,
18 At90pwm3,
19 At90pwm316,
20 At90pwm3b,
21 At90pwm81,
22 At90s1200,
23 At90s2313,
24 At90s2323,
25 At90s2333,
26 At90s2343,
27 At90s4414,
28 At90s4433,
29 At90s4434,
30 At90s8515,
31 At90s8535,
32 At90scr100,
33 At90usb1286,
34 At90usb1287,
35 At90usb162,
36 At90usb646,
37 At90usb647,
38 At90usb82,
39 At94k,
40 Ata5272,
41 Ata5505,
42 Ata5790,
43 Ata5795,
44 Ata6285,
45 Ata6286,
46 Ata6289,
47 Atmega103,
48 Atmega128,
49 Atmega1280,
50 Atmega1281,
51 Atmega1284,
52 Atmega1284p,
53 Atmega1284rfr2,
54 Atmega128a,
55 Atmega128rfa1,
56 Atmega128rfr2,
57 Atmega16,
58 Atmega161,
59 Atmega162,
60 Atmega163,
61 Atmega164a,
62 Atmega164p,
63 Atmega164pa,
64 Atmega165,
65 Atmega165a,
66 Atmega165p,
67 Atmega165pa,
68 Atmega168,
69 Atmega168a,
70 Atmega168p,
71 Atmega168pa,
72 Atmega169,
73 Atmega169a,
74 Atmega169p,
75 Atmega169pa,
76 Atmega16a,
77 Atmega16hva,
78 Atmega16hva2,
79 Atmega16hvb,
80 Atmega16hvbrevb,
81 Atmega16m1,
82 Atmega16u2,
83 Atmega16u4,
84 Atmega2560,
85 Atmega2561,
86 Atmega2564rfr2,
87 Atmega256rfr2,
88 Atmega32,
89 Atmega323,
90 Atmega324a,
91 Atmega324p,
92 Atmega324pa,
93 Atmega325,
94 Atmega3250,
95 Atmega3250a,
96 Atmega3250p,
97 Atmega3250pa,
98 Atmega325a,
99 Atmega325p,
100 Atmega325pa,
101 Atmega328,
102 Atmega328p,
103 Atmega329,
104 Atmega3290,
105 Atmega3290a,
106 Atmega3290p,
107 Atmega3290pa,
108 Atmega329a,
109 Atmega329p,
110 Atmega329pa,
111 Atmega32a,
112 Atmega32c1,
113 Atmega32hvb,
114 Atmega32hvbrevb,
115 Atmega32m1,
116 Atmega32u2,
117 Atmega32u4,
118 Atmega32u6,
119 Atmega406,
120 Atmega48,
121 Atmega48a,
122 Atmega48p,
123 Atmega48pa,
124 Atmega64,
125 Atmega640,
126 Atmega644,
127 Atmega644a,
128 Atmega644p,
129 Atmega644pa,
130 Atmega644rfr2,
131 Atmega645,
132 Atmega6450,
133 Atmega6450a,
134 Atmega6450p,
135 Atmega645a,
136 Atmega645p,
137 Atmega649,
138 Atmega6490,
139 Atmega6490a,
140 Atmega6490p,
141 Atmega649a,
142 Atmega649p,
143 Atmega64a,
144 Atmega64c1,
145 Atmega64hve,
146 Atmega64m1,
147 Atmega64rfr2,
148 Atmega8,
149 Atmega8515,
150 Atmega8535,
151 Atmega88,
152 Atmega88a,
153 Atmega88p,
154 Atmega88pa,
155 Atmega8a,
156 Atmega8hva,
157 Atmega8u2,
158 Attiny10,
159 Attiny102,
160 Attiny104,
161 Attiny11,
162 Attiny12,
163 Attiny13,
164 Attiny13a,
165 Attiny15,
166 Attiny1634,
167 Attiny167,
168 Attiny20,
169 Attiny22,
170 Attiny2313,
171 Attiny2313a,
172 Attiny24,
173 Attiny24a,
174 Attiny25,
175 Attiny26,
176 Attiny261,
177 Attiny261a,
178 Attiny28,
179 Attiny4,
180 Attiny40,
181 Attiny4313,
182 Attiny43u,
183 Attiny44,
184 Attiny44a,
185 Attiny45,
186 Attiny461,
187 Attiny461a,
188 Attiny48,
189 Attiny5,
190 Attiny828,
191 Attiny84,
192 Attiny84a,
193 Attiny85,
194 Attiny861,
195 Attiny861a,
196 Attiny87,
197 Attiny88,
198 Attiny9,
199 Atxmega128a1,
200 Atxmega128a1u,
201 Atxmega128a3,
202 Atxmega128a3u,
203 Atxmega128a4u,
204 Atxmega128b1,
205 Atxmega128b3,
206 Atxmega128c3,
207 Atxmega128d3,
208 Atxmega128d4,
209 Atxmega16a4,
210 Atxmega16a4u,
211 Atxmega16c4,
212 Atxmega16d4,
213 Atxmega16e5,
214 Atxmega192a3,
215 Atxmega192a3u,
216 Atxmega192c3,
217 Atxmega192d3,
218 Atxmega256a3,
219 Atxmega256a3b,
220 Atxmega256a3bu,
221 Atxmega256a3u,
222 Atxmega256c3,
223 Atxmega256d3,
224 Atxmega32a4,
225 Atxmega32a4u,
226 Atxmega32c4,
227 Atxmega32d4,
228 Atxmega32e5,
229 Atxmega32x1,
230 Atxmega384c3,
231 Atxmega384d3,
232 Atxmega64a1,
233 Atxmega64a1u,
234 Atxmega64a3,
235 Atxmega64a3u,
236 Atxmega64a4u,
237 Atxmega64b1,
238 Atxmega64b3,
239 Atxmega64c3,
240 Atxmega64d3,
241 Atxmega64d4,
242 Atxmega8e5,
243 Avr1,
244 Avr2,
245 Avr25,
246 Avr3,
247 Avr31,
248 Avr35,
249 Avr4,
250 Avr5,
251 Avr51,
252 Avr6,
253 Avrtiny,
254 Avrxmega1,
255 Avrxmega2,
256 Avrxmega3,
257 Avrxmega4,
258 Avrxmega5,
259 Avrxmega6,
260 Avrxmega7,
261 M3000,
262
263 const FeatureType = feature.AvrFeature;
264
265 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
266 return cpu_infos[@enumToInt(self)];
267 }
268
269 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
270 CpuInfo(@This(), FeatureType).create(.At43usb320, "at43usb320", &[_]FeatureType {
271 .Lpm,
272 .Elpm,
273 .Avr0,
274 .Sram,
275 .Jmpcall,
276 .Addsubiw,
277 .Ijmpcall,
278 .Avr31,
279 }),
280 CpuInfo(@This(), FeatureType).create(.At43usb355, "at43usb355", &[_]FeatureType {
281 .Lpm,
282 .Avr0,
283 .Sram,
284 .Jmpcall,
285 .Addsubiw,
286 .Ijmpcall,
287 .Avr3,
288 }),
289 CpuInfo(@This(), FeatureType).create(.At76c711, "at76c711", &[_]FeatureType {
290 .Lpm,
291 .Avr0,
292 .Sram,
293 .Jmpcall,
294 .Addsubiw,
295 .Ijmpcall,
296 .Avr3,
297 }),
298 CpuInfo(@This(), FeatureType).create(.At86rf401, "at86rf401", &[_]FeatureType {
299 .Lpm,
300 .Avr0,
301 .Sram,
302 .Addsubiw,
303 .Ijmpcall,
304 .Avr2,
305 .Lpmx,
306 .Movw,
307 }),
308 CpuInfo(@This(), FeatureType).create(.At90c8534, "at90c8534", &[_]FeatureType {
309 .Lpm,
310 .Avr0,
311 .Sram,
312 .Addsubiw,
313 .Ijmpcall,
314 .Avr2,
315 }),
316 CpuInfo(@This(), FeatureType).create(.At90can128, "at90can128", &[_]FeatureType {
317 .Lpm,
318 .Elpm,
319 .Movw,
320 .Elpmx,
321 .Spm,
322 .Avr0,
323 .Sram,
324 .Jmpcall,
325 .Addsubiw,
326 .Mul,
327 .Lpmx,
328 .Ijmpcall,
329 .Break,
330 .Avr51,
331 }),
332 CpuInfo(@This(), FeatureType).create(.At90can32, "at90can32", &[_]FeatureType {
333 .Lpm,
334 .Movw,
335 .Spm,
336 .Avr0,
337 .Sram,
338 .Jmpcall,
339 .Addsubiw,
340 .Mul,
341 .Lpmx,
342 .Ijmpcall,
343 .Break,
344 .Avr5,
345 }),
346 CpuInfo(@This(), FeatureType).create(.At90can64, "at90can64", &[_]FeatureType {
347 .Lpm,
348 .Movw,
349 .Spm,
350 .Avr0,
351 .Sram,
352 .Jmpcall,
353 .Addsubiw,
354 .Mul,
355 .Lpmx,
356 .Ijmpcall,
357 .Break,
358 .Avr5,
359 }),
360 CpuInfo(@This(), FeatureType).create(.At90pwm1, "at90pwm1", &[_]FeatureType {
361 .Lpm,
362 .Movw,
363 .Spm,
364 .Avr0,
365 .Sram,
366 .Addsubiw,
367 .Mul,
368 .Lpmx,
369 .Ijmpcall,
370 .Break,
371 .Avr4,
372 }),
373 CpuInfo(@This(), FeatureType).create(.At90pwm161, "at90pwm161", &[_]FeatureType {
374 .Lpm,
375 .Movw,
376 .Spm,
377 .Avr0,
378 .Sram,
379 .Jmpcall,
380 .Addsubiw,
381 .Mul,
382 .Lpmx,
383 .Ijmpcall,
384 .Break,
385 .Avr5,
386 }),
387 CpuInfo(@This(), FeatureType).create(.At90pwm2, "at90pwm2", &[_]FeatureType {
388 .Lpm,
389 .Movw,
390 .Spm,
391 .Avr0,
392 .Sram,
393 .Addsubiw,
394 .Mul,
395 .Lpmx,
396 .Ijmpcall,
397 .Break,
398 .Avr4,
399 }),
400 CpuInfo(@This(), FeatureType).create(.At90pwm216, "at90pwm216", &[_]FeatureType {
401 .Lpm,
402 .Movw,
403 .Spm,
404 .Avr0,
405 .Sram,
406 .Jmpcall,
407 .Addsubiw,
408 .Mul,
409 .Lpmx,
410 .Ijmpcall,
411 .Break,
412 .Avr5,
413 }),
414 CpuInfo(@This(), FeatureType).create(.At90pwm2b, "at90pwm2b", &[_]FeatureType {
415 .Lpm,
416 .Movw,
417 .Spm,
418 .Avr0,
419 .Sram,
420 .Addsubiw,
421 .Mul,
422 .Lpmx,
423 .Ijmpcall,
424 .Break,
425 .Avr4,
426 }),
427 CpuInfo(@This(), FeatureType).create(.At90pwm3, "at90pwm3", &[_]FeatureType {
428 .Lpm,
429 .Movw,
430 .Spm,
431 .Avr0,
432 .Sram,
433 .Addsubiw,
434 .Mul,
435 .Lpmx,
436 .Ijmpcall,
437 .Break,
438 .Avr4,
439 }),
440 CpuInfo(@This(), FeatureType).create(.At90pwm316, "at90pwm316", &[_]FeatureType {
441 .Lpm,
442 .Movw,
443 .Spm,
444 .Avr0,
445 .Sram,
446 .Jmpcall,
447 .Addsubiw,
448 .Mul,
449 .Lpmx,
450 .Ijmpcall,
451 .Break,
452 .Avr5,
453 }),
454 CpuInfo(@This(), FeatureType).create(.At90pwm3b, "at90pwm3b", &[_]FeatureType {
455 .Lpm,
456 .Movw,
457 .Spm,
458 .Avr0,
459 .Sram,
460 .Addsubiw,
461 .Mul,
462 .Lpmx,
463 .Ijmpcall,
464 .Break,
465 .Avr4,
466 }),
467 CpuInfo(@This(), FeatureType).create(.At90pwm81, "at90pwm81", &[_]FeatureType {
468 .Lpm,
469 .Movw,
470 .Spm,
471 .Avr0,
472 .Sram,
473 .Addsubiw,
474 .Mul,
475 .Lpmx,
476 .Ijmpcall,
477 .Break,
478 .Avr4,
479 }),
480 CpuInfo(@This(), FeatureType).create(.At90s1200, "at90s1200", &[_]FeatureType {
481 .Avr0,
482 }),
483 CpuInfo(@This(), FeatureType).create(.At90s2313, "at90s2313", &[_]FeatureType {
484 .Lpm,
485 .Avr0,
486 .Sram,
487 .Addsubiw,
488 .Ijmpcall,
489 .Avr2,
490 }),
491 CpuInfo(@This(), FeatureType).create(.At90s2323, "at90s2323", &[_]FeatureType {
492 .Lpm,
493 .Avr0,
494 .Sram,
495 .Addsubiw,
496 .Ijmpcall,
497 .Avr2,
498 }),
499 CpuInfo(@This(), FeatureType).create(.At90s2333, "at90s2333", &[_]FeatureType {
500 .Lpm,
501 .Avr0,
502 .Sram,
503 .Addsubiw,
504 .Ijmpcall,
505 .Avr2,
506 }),
507 CpuInfo(@This(), FeatureType).create(.At90s2343, "at90s2343", &[_]FeatureType {
508 .Lpm,
509 .Avr0,
510 .Sram,
511 .Addsubiw,
512 .Ijmpcall,
513 .Avr2,
514 }),
515 CpuInfo(@This(), FeatureType).create(.At90s4414, "at90s4414", &[_]FeatureType {
516 .Lpm,
517 .Avr0,
518 .Sram,
519 .Addsubiw,
520 .Ijmpcall,
521 .Avr2,
522 }),
523 CpuInfo(@This(), FeatureType).create(.At90s4433, "at90s4433", &[_]FeatureType {
524 .Lpm,
525 .Avr0,
526 .Sram,
527 .Addsubiw,
528 .Ijmpcall,
529 .Avr2,
530 }),
531 CpuInfo(@This(), FeatureType).create(.At90s4434, "at90s4434", &[_]FeatureType {
532 .Lpm,
533 .Avr0,
534 .Sram,
535 .Addsubiw,
536 .Ijmpcall,
537 .Avr2,
538 }),
539 CpuInfo(@This(), FeatureType).create(.At90s8515, "at90s8515", &[_]FeatureType {
540 .Lpm,
541 .Avr0,
542 .Sram,
543 .Addsubiw,
544 .Ijmpcall,
545 .Avr2,
546 }),
547 CpuInfo(@This(), FeatureType).create(.At90s8535, "at90s8535", &[_]FeatureType {
548 .Lpm,
549 .Avr0,
550 .Sram,
551 .Addsubiw,
552 .Ijmpcall,
553 .Avr2,
554 }),
555 CpuInfo(@This(), FeatureType).create(.At90scr100, "at90scr100", &[_]FeatureType {
556 .Lpm,
557 .Movw,
558 .Spm,
559 .Avr0,
560 .Sram,
561 .Jmpcall,
562 .Addsubiw,
563 .Mul,
564 .Lpmx,
565 .Ijmpcall,
566 .Break,
567 .Avr5,
568 }),
569 CpuInfo(@This(), FeatureType).create(.At90usb1286, "at90usb1286", &[_]FeatureType {
570 .Lpm,
571 .Elpm,
572 .Movw,
573 .Elpmx,
574 .Spm,
575 .Avr0,
576 .Sram,
577 .Jmpcall,
578 .Addsubiw,
579 .Mul,
580 .Lpmx,
581 .Ijmpcall,
582 .Break,
583 .Avr51,
584 }),
585 CpuInfo(@This(), FeatureType).create(.At90usb1287, "at90usb1287", &[_]FeatureType {
586 .Lpm,
587 .Elpm,
588 .Movw,
589 .Elpmx,
590 .Spm,
591 .Avr0,
592 .Sram,
593 .Jmpcall,
594 .Addsubiw,
595 .Mul,
596 .Lpmx,
597 .Ijmpcall,
598 .Break,
599 .Avr51,
600 }),
601 CpuInfo(@This(), FeatureType).create(.At90usb162, "at90usb162", &[_]FeatureType {
602 .Lpm,
603 .Movw,
604 .Spm,
605 .Avr0,
606 .Sram,
607 .Jmpcall,
608 .Addsubiw,
609 .Lpmx,
610 .Ijmpcall,
611 .Break,
612 .Avr35,
613 }),
614 CpuInfo(@This(), FeatureType).create(.At90usb646, "at90usb646", &[_]FeatureType {
615 .Lpm,
616 .Movw,
617 .Spm,
618 .Avr0,
619 .Sram,
620 .Jmpcall,
621 .Addsubiw,
622 .Mul,
623 .Lpmx,
624 .Ijmpcall,
625 .Break,
626 .Avr5,
627 }),
628 CpuInfo(@This(), FeatureType).create(.At90usb647, "at90usb647", &[_]FeatureType {
629 .Lpm,
630 .Movw,
631 .Spm,
632 .Avr0,
633 .Sram,
634 .Jmpcall,
635 .Addsubiw,
636 .Mul,
637 .Lpmx,
638 .Ijmpcall,
639 .Break,
640 .Avr5,
641 }),
642 CpuInfo(@This(), FeatureType).create(.At90usb82, "at90usb82", &[_]FeatureType {
643 .Lpm,
644 .Movw,
645 .Spm,
646 .Avr0,
647 .Sram,
648 .Jmpcall,
649 .Addsubiw,
650 .Lpmx,
651 .Ijmpcall,
652 .Break,
653 .Avr35,
654 }),
655 CpuInfo(@This(), FeatureType).create(.At94k, "at94k", &[_]FeatureType {
656 .Lpm,
657 .Avr0,
658 .Sram,
659 .Jmpcall,
660 .Addsubiw,
661 .Ijmpcall,
662 .Avr3,
663 .Lpmx,
664 .Movw,
665 .Mul,
666 }),
667 CpuInfo(@This(), FeatureType).create(.Ata5272, "ata5272", &[_]FeatureType {
668 .Lpm,
669 .Movw,
670 .Spm,
671 .Avr0,
672 .Sram,
673 .Addsubiw,
674 .Lpmx,
675 .Ijmpcall,
676 .Break,
677 .Avr25,
678 }),
679 CpuInfo(@This(), FeatureType).create(.Ata5505, "ata5505", &[_]FeatureType {
680 .Lpm,
681 .Movw,
682 .Spm,
683 .Avr0,
684 .Sram,
685 .Jmpcall,
686 .Addsubiw,
687 .Lpmx,
688 .Ijmpcall,
689 .Break,
690 .Avr35,
691 }),
692 CpuInfo(@This(), FeatureType).create(.Ata5790, "ata5790", &[_]FeatureType {
693 .Lpm,
694 .Movw,
695 .Spm,
696 .Avr0,
697 .Sram,
698 .Jmpcall,
699 .Addsubiw,
700 .Mul,
701 .Lpmx,
702 .Ijmpcall,
703 .Break,
704 .Avr5,
705 }),
706 CpuInfo(@This(), FeatureType).create(.Ata5795, "ata5795", &[_]FeatureType {
707 .Lpm,
708 .Movw,
709 .Spm,
710 .Avr0,
711 .Sram,
712 .Jmpcall,
713 .Addsubiw,
714 .Mul,
715 .Lpmx,
716 .Ijmpcall,
717 .Break,
718 .Avr5,
719 }),
720 CpuInfo(@This(), FeatureType).create(.Ata6285, "ata6285", &[_]FeatureType {
721 .Lpm,
722 .Movw,
723 .Spm,
724 .Avr0,
725 .Sram,
726 .Addsubiw,
727 .Mul,
728 .Lpmx,
729 .Ijmpcall,
730 .Break,
731 .Avr4,
732 }),
733 CpuInfo(@This(), FeatureType).create(.Ata6286, "ata6286", &[_]FeatureType {
734 .Lpm,
735 .Movw,
736 .Spm,
737 .Avr0,
738 .Sram,
739 .Addsubiw,
740 .Mul,
741 .Lpmx,
742 .Ijmpcall,
743 .Break,
744 .Avr4,
745 }),
746 CpuInfo(@This(), FeatureType).create(.Ata6289, "ata6289", &[_]FeatureType {
747 .Lpm,
748 .Movw,
749 .Spm,
750 .Avr0,
751 .Sram,
752 .Addsubiw,
753 .Mul,
754 .Lpmx,
755 .Ijmpcall,
756 .Break,
757 .Avr4,
758 }),
759 CpuInfo(@This(), FeatureType).create(.Atmega103, "atmega103", &[_]FeatureType {
760 .Lpm,
761 .Elpm,
762 .Avr0,
763 .Sram,
764 .Jmpcall,
765 .Addsubiw,
766 .Ijmpcall,
767 .Avr31,
768 }),
769 CpuInfo(@This(), FeatureType).create(.Atmega128, "atmega128", &[_]FeatureType {
770 .Lpm,
771 .Elpm,
772 .Movw,
773 .Elpmx,
774 .Spm,
775 .Avr0,
776 .Sram,
777 .Jmpcall,
778 .Addsubiw,
779 .Mul,
780 .Lpmx,
781 .Ijmpcall,
782 .Break,
783 .Avr51,
784 }),
785 CpuInfo(@This(), FeatureType).create(.Atmega1280, "atmega1280", &[_]FeatureType {
786 .Lpm,
787 .Elpm,
788 .Movw,
789 .Elpmx,
790 .Spm,
791 .Avr0,
792 .Sram,
793 .Jmpcall,
794 .Addsubiw,
795 .Mul,
796 .Lpmx,
797 .Ijmpcall,
798 .Break,
799 .Avr51,
800 }),
801 CpuInfo(@This(), FeatureType).create(.Atmega1281, "atmega1281", &[_]FeatureType {
802 .Lpm,
803 .Elpm,
804 .Movw,
805 .Elpmx,
806 .Spm,
807 .Avr0,
808 .Sram,
809 .Jmpcall,
810 .Addsubiw,
811 .Mul,
812 .Lpmx,
813 .Ijmpcall,
814 .Break,
815 .Avr51,
816 }),
817 CpuInfo(@This(), FeatureType).create(.Atmega1284, "atmega1284", &[_]FeatureType {
818 .Lpm,
819 .Elpm,
820 .Movw,
821 .Elpmx,
822 .Spm,
823 .Avr0,
824 .Sram,
825 .Jmpcall,
826 .Addsubiw,
827 .Mul,
828 .Lpmx,
829 .Ijmpcall,
830 .Break,
831 .Avr51,
832 }),
833 CpuInfo(@This(), FeatureType).create(.Atmega1284p, "atmega1284p", &[_]FeatureType {
834 .Lpm,
835 .Elpm,
836 .Movw,
837 .Elpmx,
838 .Spm,
839 .Avr0,
840 .Sram,
841 .Jmpcall,
842 .Addsubiw,
843 .Mul,
844 .Lpmx,
845 .Ijmpcall,
846 .Break,
847 .Avr51,
848 }),
849 CpuInfo(@This(), FeatureType).create(.Atmega1284rfr2, "atmega1284rfr2", &[_]FeatureType {
850 .Lpm,
851 .Elpm,
852 .Movw,
853 .Elpmx,
854 .Spm,
855 .Avr0,
856 .Sram,
857 .Jmpcall,
858 .Addsubiw,
859 .Mul,
860 .Lpmx,
861 .Ijmpcall,
862 .Break,
863 .Avr51,
864 }),
865 CpuInfo(@This(), FeatureType).create(.Atmega128a, "atmega128a", &[_]FeatureType {
866 .Lpm,
867 .Elpm,
868 .Movw,
869 .Elpmx,
870 .Spm,
871 .Avr0,
872 .Sram,
873 .Jmpcall,
874 .Addsubiw,
875 .Mul,
876 .Lpmx,
877 .Ijmpcall,
878 .Break,
879 .Avr51,
880 }),
881 CpuInfo(@This(), FeatureType).create(.Atmega128rfa1, "atmega128rfa1", &[_]FeatureType {
882 .Lpm,
883 .Elpm,
884 .Movw,
885 .Elpmx,
886 .Spm,
887 .Avr0,
888 .Sram,
889 .Jmpcall,
890 .Addsubiw,
891 .Mul,
892 .Lpmx,
893 .Ijmpcall,
894 .Break,
895 .Avr51,
896 }),
897 CpuInfo(@This(), FeatureType).create(.Atmega128rfr2, "atmega128rfr2", &[_]FeatureType {
898 .Lpm,
899 .Elpm,
900 .Movw,
901 .Elpmx,
902 .Spm,
903 .Avr0,
904 .Sram,
905 .Jmpcall,
906 .Addsubiw,
907 .Mul,
908 .Lpmx,
909 .Ijmpcall,
910 .Break,
911 .Avr51,
912 }),
913 CpuInfo(@This(), FeatureType).create(.Atmega16, "atmega16", &[_]FeatureType {
914 .Lpm,
915 .Movw,
916 .Spm,
917 .Avr0,
918 .Sram,
919 .Jmpcall,
920 .Addsubiw,
921 .Mul,
922 .Lpmx,
923 .Ijmpcall,
924 .Break,
925 .Avr5,
926 }),
927 CpuInfo(@This(), FeatureType).create(.Atmega161, "atmega161", &[_]FeatureType {
928 .Lpm,
929 .Avr0,
930 .Sram,
931 .Jmpcall,
932 .Addsubiw,
933 .Ijmpcall,
934 .Avr3,
935 .Lpmx,
936 .Movw,
937 .Mul,
938 .Spm,
939 }),
940 CpuInfo(@This(), FeatureType).create(.Atmega162, "atmega162", &[_]FeatureType {
941 .Lpm,
942 .Movw,
943 .Spm,
944 .Avr0,
945 .Sram,
946 .Jmpcall,
947 .Addsubiw,
948 .Mul,
949 .Lpmx,
950 .Ijmpcall,
951 .Break,
952 .Avr5,
953 }),
954 CpuInfo(@This(), FeatureType).create(.Atmega163, "atmega163", &[_]FeatureType {
955 .Lpm,
956 .Avr0,
957 .Sram,
958 .Jmpcall,
959 .Addsubiw,
960 .Ijmpcall,
961 .Avr3,
962 .Lpmx,
963 .Movw,
964 .Mul,
965 .Spm,
966 }),
967 CpuInfo(@This(), FeatureType).create(.Atmega164a, "atmega164a", &[_]FeatureType {
968 .Lpm,
969 .Movw,
970 .Spm,
971 .Avr0,
972 .Sram,
973 .Jmpcall,
974 .Addsubiw,
975 .Mul,
976 .Lpmx,
977 .Ijmpcall,
978 .Break,
979 .Avr5,
980 }),
981 CpuInfo(@This(), FeatureType).create(.Atmega164p, "atmega164p", &[_]FeatureType {
982 .Lpm,
983 .Movw,
984 .Spm,
985 .Avr0,
986 .Sram,
987 .Jmpcall,
988 .Addsubiw,
989 .Mul,
990 .Lpmx,
991 .Ijmpcall,
992 .Break,
993 .Avr5,
994 }),
995 CpuInfo(@This(), FeatureType).create(.Atmega164pa, "atmega164pa", &[_]FeatureType {
996 .Lpm,
997 .Movw,
998 .Spm,
999 .Avr0,
1000 .Sram,
1001 .Jmpcall,
1002 .Addsubiw,
1003 .Mul,
1004 .Lpmx,
1005 .Ijmpcall,
1006 .Break,
1007 .Avr5,
1008 }),
1009 CpuInfo(@This(), FeatureType).create(.Atmega165, "atmega165", &[_]FeatureType {
1010 .Lpm,
1011 .Movw,
1012 .Spm,
1013 .Avr0,
1014 .Sram,
1015 .Jmpcall,
1016 .Addsubiw,
1017 .Mul,
1018 .Lpmx,
1019 .Ijmpcall,
1020 .Break,
1021 .Avr5,
1022 }),
1023 CpuInfo(@This(), FeatureType).create(.Atmega165a, "atmega165a", &[_]FeatureType {
1024 .Lpm,
1025 .Movw,
1026 .Spm,
1027 .Avr0,
1028 .Sram,
1029 .Jmpcall,
1030 .Addsubiw,
1031 .Mul,
1032 .Lpmx,
1033 .Ijmpcall,
1034 .Break,
1035 .Avr5,
1036 }),
1037 CpuInfo(@This(), FeatureType).create(.Atmega165p, "atmega165p", &[_]FeatureType {
1038 .Lpm,
1039 .Movw,
1040 .Spm,
1041 .Avr0,
1042 .Sram,
1043 .Jmpcall,
1044 .Addsubiw,
1045 .Mul,
1046 .Lpmx,
1047 .Ijmpcall,
1048 .Break,
1049 .Avr5,
1050 }),
1051 CpuInfo(@This(), FeatureType).create(.Atmega165pa, "atmega165pa", &[_]FeatureType {
1052 .Lpm,
1053 .Movw,
1054 .Spm,
1055 .Avr0,
1056 .Sram,
1057 .Jmpcall,
1058 .Addsubiw,
1059 .Mul,
1060 .Lpmx,
1061 .Ijmpcall,
1062 .Break,
1063 .Avr5,
1064 }),
1065 CpuInfo(@This(), FeatureType).create(.Atmega168, "atmega168", &[_]FeatureType {
1066 .Lpm,
1067 .Movw,
1068 .Spm,
1069 .Avr0,
1070 .Sram,
1071 .Jmpcall,
1072 .Addsubiw,
1073 .Mul,
1074 .Lpmx,
1075 .Ijmpcall,
1076 .Break,
1077 .Avr5,
1078 }),
1079 CpuInfo(@This(), FeatureType).create(.Atmega168a, "atmega168a", &[_]FeatureType {
1080 .Lpm,
1081 .Movw,
1082 .Spm,
1083 .Avr0,
1084 .Sram,
1085 .Jmpcall,
1086 .Addsubiw,
1087 .Mul,
1088 .Lpmx,
1089 .Ijmpcall,
1090 .Break,
1091 .Avr5,
1092 }),
1093 CpuInfo(@This(), FeatureType).create(.Atmega168p, "atmega168p", &[_]FeatureType {
1094 .Lpm,
1095 .Movw,
1096 .Spm,
1097 .Avr0,
1098 .Sram,
1099 .Jmpcall,
1100 .Addsubiw,
1101 .Mul,
1102 .Lpmx,
1103 .Ijmpcall,
1104 .Break,
1105 .Avr5,
1106 }),
1107 CpuInfo(@This(), FeatureType).create(.Atmega168pa, "atmega168pa", &[_]FeatureType {
1108 .Lpm,
1109 .Movw,
1110 .Spm,
1111 .Avr0,
1112 .Sram,
1113 .Jmpcall,
1114 .Addsubiw,
1115 .Mul,
1116 .Lpmx,
1117 .Ijmpcall,
1118 .Break,
1119 .Avr5,
1120 }),
1121 CpuInfo(@This(), FeatureType).create(.Atmega169, "atmega169", &[_]FeatureType {
1122 .Lpm,
1123 .Movw,
1124 .Spm,
1125 .Avr0,
1126 .Sram,
1127 .Jmpcall,
1128 .Addsubiw,
1129 .Mul,
1130 .Lpmx,
1131 .Ijmpcall,
1132 .Break,
1133 .Avr5,
1134 }),
1135 CpuInfo(@This(), FeatureType).create(.Atmega169a, "atmega169a", &[_]FeatureType {
1136 .Lpm,
1137 .Movw,
1138 .Spm,
1139 .Avr0,
1140 .Sram,
1141 .Jmpcall,
1142 .Addsubiw,
1143 .Mul,
1144 .Lpmx,
1145 .Ijmpcall,
1146 .Break,
1147 .Avr5,
1148 }),
1149 CpuInfo(@This(), FeatureType).create(.Atmega169p, "atmega169p", &[_]FeatureType {
1150 .Lpm,
1151 .Movw,
1152 .Spm,
1153 .Avr0,
1154 .Sram,
1155 .Jmpcall,
1156 .Addsubiw,
1157 .Mul,
1158 .Lpmx,
1159 .Ijmpcall,
1160 .Break,
1161 .Avr5,
1162 }),
1163 CpuInfo(@This(), FeatureType).create(.Atmega169pa, "atmega169pa", &[_]FeatureType {
1164 .Lpm,
1165 .Movw,
1166 .Spm,
1167 .Avr0,
1168 .Sram,
1169 .Jmpcall,
1170 .Addsubiw,
1171 .Mul,
1172 .Lpmx,
1173 .Ijmpcall,
1174 .Break,
1175 .Avr5,
1176 }),
1177 CpuInfo(@This(), FeatureType).create(.Atmega16a, "atmega16a", &[_]FeatureType {
1178 .Lpm,
1179 .Movw,
1180 .Spm,
1181 .Avr0,
1182 .Sram,
1183 .Jmpcall,
1184 .Addsubiw,
1185 .Mul,
1186 .Lpmx,
1187 .Ijmpcall,
1188 .Break,
1189 .Avr5,
1190 }),
1191 CpuInfo(@This(), FeatureType).create(.Atmega16hva, "atmega16hva", &[_]FeatureType {
1192 .Lpm,
1193 .Movw,
1194 .Spm,
1195 .Avr0,
1196 .Sram,
1197 .Jmpcall,
1198 .Addsubiw,
1199 .Mul,
1200 .Lpmx,
1201 .Ijmpcall,
1202 .Break,
1203 .Avr5,
1204 }),
1205 CpuInfo(@This(), FeatureType).create(.Atmega16hva2, "atmega16hva2", &[_]FeatureType {
1206 .Lpm,
1207 .Movw,
1208 .Spm,
1209 .Avr0,
1210 .Sram,
1211 .Jmpcall,
1212 .Addsubiw,
1213 .Mul,
1214 .Lpmx,
1215 .Ijmpcall,
1216 .Break,
1217 .Avr5,
1218 }),
1219 CpuInfo(@This(), FeatureType).create(.Atmega16hvb, "atmega16hvb", &[_]FeatureType {
1220 .Lpm,
1221 .Movw,
1222 .Spm,
1223 .Avr0,
1224 .Sram,
1225 .Jmpcall,
1226 .Addsubiw,
1227 .Mul,
1228 .Lpmx,
1229 .Ijmpcall,
1230 .Break,
1231 .Avr5,
1232 }),
1233 CpuInfo(@This(), FeatureType).create(.Atmega16hvbrevb, "atmega16hvbrevb", &[_]FeatureType {
1234 .Lpm,
1235 .Movw,
1236 .Spm,
1237 .Avr0,
1238 .Sram,
1239 .Jmpcall,
1240 .Addsubiw,
1241 .Mul,
1242 .Lpmx,
1243 .Ijmpcall,
1244 .Break,
1245 .Avr5,
1246 }),
1247 CpuInfo(@This(), FeatureType).create(.Atmega16m1, "atmega16m1", &[_]FeatureType {
1248 .Lpm,
1249 .Movw,
1250 .Spm,
1251 .Avr0,
1252 .Sram,
1253 .Jmpcall,
1254 .Addsubiw,
1255 .Mul,
1256 .Lpmx,
1257 .Ijmpcall,
1258 .Break,
1259 .Avr5,
1260 }),
1261 CpuInfo(@This(), FeatureType).create(.Atmega16u2, "atmega16u2", &[_]FeatureType {
1262 .Lpm,
1263 .Movw,
1264 .Spm,
1265 .Avr0,
1266 .Sram,
1267 .Jmpcall,
1268 .Addsubiw,
1269 .Lpmx,
1270 .Ijmpcall,
1271 .Break,
1272 .Avr35,
1273 }),
1274 CpuInfo(@This(), FeatureType).create(.Atmega16u4, "atmega16u4", &[_]FeatureType {
1275 .Lpm,
1276 .Movw,
1277 .Spm,
1278 .Avr0,
1279 .Sram,
1280 .Jmpcall,
1281 .Addsubiw,
1282 .Mul,
1283 .Lpmx,
1284 .Ijmpcall,
1285 .Break,
1286 .Avr5,
1287 }),
1288 CpuInfo(@This(), FeatureType).create(.Atmega2560, "atmega2560", &[_]FeatureType {
1289 .Lpm,
1290 .Elpm,
1291 .Movw,
1292 .Elpmx,
1293 .Spm,
1294 .Avr0,
1295 .Sram,
1296 .Jmpcall,
1297 .Addsubiw,
1298 .Mul,
1299 .Lpmx,
1300 .Ijmpcall,
1301 .Break,
1302 .Avr6,
1303 }),
1304 CpuInfo(@This(), FeatureType).create(.Atmega2561, "atmega2561", &[_]FeatureType {
1305 .Lpm,
1306 .Elpm,
1307 .Movw,
1308 .Elpmx,
1309 .Spm,
1310 .Avr0,
1311 .Sram,
1312 .Jmpcall,
1313 .Addsubiw,
1314 .Mul,
1315 .Lpmx,
1316 .Ijmpcall,
1317 .Break,
1318 .Avr6,
1319 }),
1320 CpuInfo(@This(), FeatureType).create(.Atmega2564rfr2, "atmega2564rfr2", &[_]FeatureType {
1321 .Lpm,
1322 .Elpm,
1323 .Movw,
1324 .Elpmx,
1325 .Spm,
1326 .Avr0,
1327 .Sram,
1328 .Jmpcall,
1329 .Addsubiw,
1330 .Mul,
1331 .Lpmx,
1332 .Ijmpcall,
1333 .Break,
1334 .Avr6,
1335 }),
1336 CpuInfo(@This(), FeatureType).create(.Atmega256rfr2, "atmega256rfr2", &[_]FeatureType {
1337 .Lpm,
1338 .Elpm,
1339 .Movw,
1340 .Elpmx,
1341 .Spm,
1342 .Avr0,
1343 .Sram,
1344 .Jmpcall,
1345 .Addsubiw,
1346 .Mul,
1347 .Lpmx,
1348 .Ijmpcall,
1349 .Break,
1350 .Avr6,
1351 }),
1352 CpuInfo(@This(), FeatureType).create(.Atmega32, "atmega32", &[_]FeatureType {
1353 .Lpm,
1354 .Movw,
1355 .Spm,
1356 .Avr0,
1357 .Sram,
1358 .Jmpcall,
1359 .Addsubiw,
1360 .Mul,
1361 .Lpmx,
1362 .Ijmpcall,
1363 .Break,
1364 .Avr5,
1365 }),
1366 CpuInfo(@This(), FeatureType).create(.Atmega323, "atmega323", &[_]FeatureType {
1367 .Lpm,
1368 .Movw,
1369 .Spm,
1370 .Avr0,
1371 .Sram,
1372 .Jmpcall,
1373 .Addsubiw,
1374 .Mul,
1375 .Lpmx,
1376 .Ijmpcall,
1377 .Break,
1378 .Avr5,
1379 }),
1380 CpuInfo(@This(), FeatureType).create(.Atmega324a, "atmega324a", &[_]FeatureType {
1381 .Lpm,
1382 .Movw,
1383 .Spm,
1384 .Avr0,
1385 .Sram,
1386 .Jmpcall,
1387 .Addsubiw,
1388 .Mul,
1389 .Lpmx,
1390 .Ijmpcall,
1391 .Break,
1392 .Avr5,
1393 }),
1394 CpuInfo(@This(), FeatureType).create(.Atmega324p, "atmega324p", &[_]FeatureType {
1395 .Lpm,
1396 .Movw,
1397 .Spm,
1398 .Avr0,
1399 .Sram,
1400 .Jmpcall,
1401 .Addsubiw,
1402 .Mul,
1403 .Lpmx,
1404 .Ijmpcall,
1405 .Break,
1406 .Avr5,
1407 }),
1408 CpuInfo(@This(), FeatureType).create(.Atmega324pa, "atmega324pa", &[_]FeatureType {
1409 .Lpm,
1410 .Movw,
1411 .Spm,
1412 .Avr0,
1413 .Sram,
1414 .Jmpcall,
1415 .Addsubiw,
1416 .Mul,
1417 .Lpmx,
1418 .Ijmpcall,
1419 .Break,
1420 .Avr5,
1421 }),
1422 CpuInfo(@This(), FeatureType).create(.Atmega325, "atmega325", &[_]FeatureType {
1423 .Lpm,
1424 .Movw,
1425 .Spm,
1426 .Avr0,
1427 .Sram,
1428 .Jmpcall,
1429 .Addsubiw,
1430 .Mul,
1431 .Lpmx,
1432 .Ijmpcall,
1433 .Break,
1434 .Avr5,
1435 }),
1436 CpuInfo(@This(), FeatureType).create(.Atmega3250, "atmega3250", &[_]FeatureType {
1437 .Lpm,
1438 .Movw,
1439 .Spm,
1440 .Avr0,
1441 .Sram,
1442 .Jmpcall,
1443 .Addsubiw,
1444 .Mul,
1445 .Lpmx,
1446 .Ijmpcall,
1447 .Break,
1448 .Avr5,
1449 }),
1450 CpuInfo(@This(), FeatureType).create(.Atmega3250a, "atmega3250a", &[_]FeatureType {
1451 .Lpm,
1452 .Movw,
1453 .Spm,
1454 .Avr0,
1455 .Sram,
1456 .Jmpcall,
1457 .Addsubiw,
1458 .Mul,
1459 .Lpmx,
1460 .Ijmpcall,
1461 .Break,
1462 .Avr5,
1463 }),
1464 CpuInfo(@This(), FeatureType).create(.Atmega3250p, "atmega3250p", &[_]FeatureType {
1465 .Lpm,
1466 .Movw,
1467 .Spm,
1468 .Avr0,
1469 .Sram,
1470 .Jmpcall,
1471 .Addsubiw,
1472 .Mul,
1473 .Lpmx,
1474 .Ijmpcall,
1475 .Break,
1476 .Avr5,
1477 }),
1478 CpuInfo(@This(), FeatureType).create(.Atmega3250pa, "atmega3250pa", &[_]FeatureType {
1479 .Lpm,
1480 .Movw,
1481 .Spm,
1482 .Avr0,
1483 .Sram,
1484 .Jmpcall,
1485 .Addsubiw,
1486 .Mul,
1487 .Lpmx,
1488 .Ijmpcall,
1489 .Break,
1490 .Avr5,
1491 }),
1492 CpuInfo(@This(), FeatureType).create(.Atmega325a, "atmega325a", &[_]FeatureType {
1493 .Lpm,
1494 .Movw,
1495 .Spm,
1496 .Avr0,
1497 .Sram,
1498 .Jmpcall,
1499 .Addsubiw,
1500 .Mul,
1501 .Lpmx,
1502 .Ijmpcall,
1503 .Break,
1504 .Avr5,
1505 }),
1506 CpuInfo(@This(), FeatureType).create(.Atmega325p, "atmega325p", &[_]FeatureType {
1507 .Lpm,
1508 .Movw,
1509 .Spm,
1510 .Avr0,
1511 .Sram,
1512 .Jmpcall,
1513 .Addsubiw,
1514 .Mul,
1515 .Lpmx,
1516 .Ijmpcall,
1517 .Break,
1518 .Avr5,
1519 }),
1520 CpuInfo(@This(), FeatureType).create(.Atmega325pa, "atmega325pa", &[_]FeatureType {
1521 .Lpm,
1522 .Movw,
1523 .Spm,
1524 .Avr0,
1525 .Sram,
1526 .Jmpcall,
1527 .Addsubiw,
1528 .Mul,
1529 .Lpmx,
1530 .Ijmpcall,
1531 .Break,
1532 .Avr5,
1533 }),
1534 CpuInfo(@This(), FeatureType).create(.Atmega328, "atmega328", &[_]FeatureType {
1535 .Lpm,
1536 .Movw,
1537 .Spm,
1538 .Avr0,
1539 .Sram,
1540 .Jmpcall,
1541 .Addsubiw,
1542 .Mul,
1543 .Lpmx,
1544 .Ijmpcall,
1545 .Break,
1546 .Avr5,
1547 }),
1548 CpuInfo(@This(), FeatureType).create(.Atmega328p, "atmega328p", &[_]FeatureType {
1549 .Lpm,
1550 .Movw,
1551 .Spm,
1552 .Avr0,
1553 .Sram,
1554 .Jmpcall,
1555 .Addsubiw,
1556 .Mul,
1557 .Lpmx,
1558 .Ijmpcall,
1559 .Break,
1560 .Avr5,
1561 }),
1562 CpuInfo(@This(), FeatureType).create(.Atmega329, "atmega329", &[_]FeatureType {
1563 .Lpm,
1564 .Movw,
1565 .Spm,
1566 .Avr0,
1567 .Sram,
1568 .Jmpcall,
1569 .Addsubiw,
1570 .Mul,
1571 .Lpmx,
1572 .Ijmpcall,
1573 .Break,
1574 .Avr5,
1575 }),
1576 CpuInfo(@This(), FeatureType).create(.Atmega3290, "atmega3290", &[_]FeatureType {
1577 .Lpm,
1578 .Movw,
1579 .Spm,
1580 .Avr0,
1581 .Sram,
1582 .Jmpcall,
1583 .Addsubiw,
1584 .Mul,
1585 .Lpmx,
1586 .Ijmpcall,
1587 .Break,
1588 .Avr5,
1589 }),
1590 CpuInfo(@This(), FeatureType).create(.Atmega3290a, "atmega3290a", &[_]FeatureType {
1591 .Lpm,
1592 .Movw,
1593 .Spm,
1594 .Avr0,
1595 .Sram,
1596 .Jmpcall,
1597 .Addsubiw,
1598 .Mul,
1599 .Lpmx,
1600 .Ijmpcall,
1601 .Break,
1602 .Avr5,
1603 }),
1604 CpuInfo(@This(), FeatureType).create(.Atmega3290p, "atmega3290p", &[_]FeatureType {
1605 .Lpm,
1606 .Movw,
1607 .Spm,
1608 .Avr0,
1609 .Sram,
1610 .Jmpcall,
1611 .Addsubiw,
1612 .Mul,
1613 .Lpmx,
1614 .Ijmpcall,
1615 .Break,
1616 .Avr5,
1617 }),
1618 CpuInfo(@This(), FeatureType).create(.Atmega3290pa, "atmega3290pa", &[_]FeatureType {
1619 .Lpm,
1620 .Movw,
1621 .Spm,
1622 .Avr0,
1623 .Sram,
1624 .Jmpcall,
1625 .Addsubiw,
1626 .Mul,
1627 .Lpmx,
1628 .Ijmpcall,
1629 .Break,
1630 .Avr5,
1631 }),
1632 CpuInfo(@This(), FeatureType).create(.Atmega329a, "atmega329a", &[_]FeatureType {
1633 .Lpm,
1634 .Movw,
1635 .Spm,
1636 .Avr0,
1637 .Sram,
1638 .Jmpcall,
1639 .Addsubiw,
1640 .Mul,
1641 .Lpmx,
1642 .Ijmpcall,
1643 .Break,
1644 .Avr5,
1645 }),
1646 CpuInfo(@This(), FeatureType).create(.Atmega329p, "atmega329p", &[_]FeatureType {
1647 .Lpm,
1648 .Movw,
1649 .Spm,
1650 .Avr0,
1651 .Sram,
1652 .Jmpcall,
1653 .Addsubiw,
1654 .Mul,
1655 .Lpmx,
1656 .Ijmpcall,
1657 .Break,
1658 .Avr5,
1659 }),
1660 CpuInfo(@This(), FeatureType).create(.Atmega329pa, "atmega329pa", &[_]FeatureType {
1661 .Lpm,
1662 .Movw,
1663 .Spm,
1664 .Avr0,
1665 .Sram,
1666 .Jmpcall,
1667 .Addsubiw,
1668 .Mul,
1669 .Lpmx,
1670 .Ijmpcall,
1671 .Break,
1672 .Avr5,
1673 }),
1674 CpuInfo(@This(), FeatureType).create(.Atmega32a, "atmega32a", &[_]FeatureType {
1675 .Lpm,
1676 .Movw,
1677 .Spm,
1678 .Avr0,
1679 .Sram,
1680 .Jmpcall,
1681 .Addsubiw,
1682 .Mul,
1683 .Lpmx,
1684 .Ijmpcall,
1685 .Break,
1686 .Avr5,
1687 }),
1688 CpuInfo(@This(), FeatureType).create(.Atmega32c1, "atmega32c1", &[_]FeatureType {
1689 .Lpm,
1690 .Movw,
1691 .Spm,
1692 .Avr0,
1693 .Sram,
1694 .Jmpcall,
1695 .Addsubiw,
1696 .Mul,
1697 .Lpmx,
1698 .Ijmpcall,
1699 .Break,
1700 .Avr5,
1701 }),
1702 CpuInfo(@This(), FeatureType).create(.Atmega32hvb, "atmega32hvb", &[_]FeatureType {
1703 .Lpm,
1704 .Movw,
1705 .Spm,
1706 .Avr0,
1707 .Sram,
1708 .Jmpcall,
1709 .Addsubiw,
1710 .Mul,
1711 .Lpmx,
1712 .Ijmpcall,
1713 .Break,
1714 .Avr5,
1715 }),
1716 CpuInfo(@This(), FeatureType).create(.Atmega32hvbrevb, "atmega32hvbrevb", &[_]FeatureType {
1717 .Lpm,
1718 .Movw,
1719 .Spm,
1720 .Avr0,
1721 .Sram,
1722 .Jmpcall,
1723 .Addsubiw,
1724 .Mul,
1725 .Lpmx,
1726 .Ijmpcall,
1727 .Break,
1728 .Avr5,
1729 }),
1730 CpuInfo(@This(), FeatureType).create(.Atmega32m1, "atmega32m1", &[_]FeatureType {
1731 .Lpm,
1732 .Movw,
1733 .Spm,
1734 .Avr0,
1735 .Sram,
1736 .Jmpcall,
1737 .Addsubiw,
1738 .Mul,
1739 .Lpmx,
1740 .Ijmpcall,
1741 .Break,
1742 .Avr5,
1743 }),
1744 CpuInfo(@This(), FeatureType).create(.Atmega32u2, "atmega32u2", &[_]FeatureType {
1745 .Lpm,
1746 .Movw,
1747 .Spm,
1748 .Avr0,
1749 .Sram,
1750 .Jmpcall,
1751 .Addsubiw,
1752 .Lpmx,
1753 .Ijmpcall,
1754 .Break,
1755 .Avr35,
1756 }),
1757 CpuInfo(@This(), FeatureType).create(.Atmega32u4, "atmega32u4", &[_]FeatureType {
1758 .Lpm,
1759 .Movw,
1760 .Spm,
1761 .Avr0,
1762 .Sram,
1763 .Jmpcall,
1764 .Addsubiw,
1765 .Mul,
1766 .Lpmx,
1767 .Ijmpcall,
1768 .Break,
1769 .Avr5,
1770 }),
1771 CpuInfo(@This(), FeatureType).create(.Atmega32u6, "atmega32u6", &[_]FeatureType {
1772 .Lpm,
1773 .Movw,
1774 .Spm,
1775 .Avr0,
1776 .Sram,
1777 .Jmpcall,
1778 .Addsubiw,
1779 .Mul,
1780 .Lpmx,
1781 .Ijmpcall,
1782 .Break,
1783 .Avr5,
1784 }),
1785 CpuInfo(@This(), FeatureType).create(.Atmega406, "atmega406", &[_]FeatureType {
1786 .Lpm,
1787 .Movw,
1788 .Spm,
1789 .Avr0,
1790 .Sram,
1791 .Jmpcall,
1792 .Addsubiw,
1793 .Mul,
1794 .Lpmx,
1795 .Ijmpcall,
1796 .Break,
1797 .Avr5,
1798 }),
1799 CpuInfo(@This(), FeatureType).create(.Atmega48, "atmega48", &[_]FeatureType {
1800 .Lpm,
1801 .Movw,
1802 .Spm,
1803 .Avr0,
1804 .Sram,
1805 .Addsubiw,
1806 .Mul,
1807 .Lpmx,
1808 .Ijmpcall,
1809 .Break,
1810 .Avr4,
1811 }),
1812 CpuInfo(@This(), FeatureType).create(.Atmega48a, "atmega48a", &[_]FeatureType {
1813 .Lpm,
1814 .Movw,
1815 .Spm,
1816 .Avr0,
1817 .Sram,
1818 .Addsubiw,
1819 .Mul,
1820 .Lpmx,
1821 .Ijmpcall,
1822 .Break,
1823 .Avr4,
1824 }),
1825 CpuInfo(@This(), FeatureType).create(.Atmega48p, "atmega48p", &[_]FeatureType {
1826 .Lpm,
1827 .Movw,
1828 .Spm,
1829 .Avr0,
1830 .Sram,
1831 .Addsubiw,
1832 .Mul,
1833 .Lpmx,
1834 .Ijmpcall,
1835 .Break,
1836 .Avr4,
1837 }),
1838 CpuInfo(@This(), FeatureType).create(.Atmega48pa, "atmega48pa", &[_]FeatureType {
1839 .Lpm,
1840 .Movw,
1841 .Spm,
1842 .Avr0,
1843 .Sram,
1844 .Addsubiw,
1845 .Mul,
1846 .Lpmx,
1847 .Ijmpcall,
1848 .Break,
1849 .Avr4,
1850 }),
1851 CpuInfo(@This(), FeatureType).create(.Atmega64, "atmega64", &[_]FeatureType {
1852 .Lpm,
1853 .Movw,
1854 .Spm,
1855 .Avr0,
1856 .Sram,
1857 .Jmpcall,
1858 .Addsubiw,
1859 .Mul,
1860 .Lpmx,
1861 .Ijmpcall,
1862 .Break,
1863 .Avr5,
1864 }),
1865 CpuInfo(@This(), FeatureType).create(.Atmega640, "atmega640", &[_]FeatureType {
1866 .Lpm,
1867 .Movw,
1868 .Spm,
1869 .Avr0,
1870 .Sram,
1871 .Jmpcall,
1872 .Addsubiw,
1873 .Mul,
1874 .Lpmx,
1875 .Ijmpcall,
1876 .Break,
1877 .Avr5,
1878 }),
1879 CpuInfo(@This(), FeatureType).create(.Atmega644, "atmega644", &[_]FeatureType {
1880 .Lpm,
1881 .Movw,
1882 .Spm,
1883 .Avr0,
1884 .Sram,
1885 .Jmpcall,
1886 .Addsubiw,
1887 .Mul,
1888 .Lpmx,
1889 .Ijmpcall,
1890 .Break,
1891 .Avr5,
1892 }),
1893 CpuInfo(@This(), FeatureType).create(.Atmega644a, "atmega644a", &[_]FeatureType {
1894 .Lpm,
1895 .Movw,
1896 .Spm,
1897 .Avr0,
1898 .Sram,
1899 .Jmpcall,
1900 .Addsubiw,
1901 .Mul,
1902 .Lpmx,
1903 .Ijmpcall,
1904 .Break,
1905 .Avr5,
1906 }),
1907 CpuInfo(@This(), FeatureType).create(.Atmega644p, "atmega644p", &[_]FeatureType {
1908 .Lpm,
1909 .Movw,
1910 .Spm,
1911 .Avr0,
1912 .Sram,
1913 .Jmpcall,
1914 .Addsubiw,
1915 .Mul,
1916 .Lpmx,
1917 .Ijmpcall,
1918 .Break,
1919 .Avr5,
1920 }),
1921 CpuInfo(@This(), FeatureType).create(.Atmega644pa, "atmega644pa", &[_]FeatureType {
1922 .Lpm,
1923 .Movw,
1924 .Spm,
1925 .Avr0,
1926 .Sram,
1927 .Jmpcall,
1928 .Addsubiw,
1929 .Mul,
1930 .Lpmx,
1931 .Ijmpcall,
1932 .Break,
1933 .Avr5,
1934 }),
1935 CpuInfo(@This(), FeatureType).create(.Atmega644rfr2, "atmega644rfr2", &[_]FeatureType {
1936 .Lpm,
1937 .Movw,
1938 .Spm,
1939 .Avr0,
1940 .Sram,
1941 .Jmpcall,
1942 .Addsubiw,
1943 .Mul,
1944 .Lpmx,
1945 .Ijmpcall,
1946 .Break,
1947 .Avr5,
1948 }),
1949 CpuInfo(@This(), FeatureType).create(.Atmega645, "atmega645", &[_]FeatureType {
1950 .Lpm,
1951 .Movw,
1952 .Spm,
1953 .Avr0,
1954 .Sram,
1955 .Jmpcall,
1956 .Addsubiw,
1957 .Mul,
1958 .Lpmx,
1959 .Ijmpcall,
1960 .Break,
1961 .Avr5,
1962 }),
1963 CpuInfo(@This(), FeatureType).create(.Atmega6450, "atmega6450", &[_]FeatureType {
1964 .Lpm,
1965 .Movw,
1966 .Spm,
1967 .Avr0,
1968 .Sram,
1969 .Jmpcall,
1970 .Addsubiw,
1971 .Mul,
1972 .Lpmx,
1973 .Ijmpcall,
1974 .Break,
1975 .Avr5,
1976 }),
1977 CpuInfo(@This(), FeatureType).create(.Atmega6450a, "atmega6450a", &[_]FeatureType {
1978 .Lpm,
1979 .Movw,
1980 .Spm,
1981 .Avr0,
1982 .Sram,
1983 .Jmpcall,
1984 .Addsubiw,
1985 .Mul,
1986 .Lpmx,
1987 .Ijmpcall,
1988 .Break,
1989 .Avr5,
1990 }),
1991 CpuInfo(@This(), FeatureType).create(.Atmega6450p, "atmega6450p", &[_]FeatureType {
1992 .Lpm,
1993 .Movw,
1994 .Spm,
1995 .Avr0,
1996 .Sram,
1997 .Jmpcall,
1998 .Addsubiw,
1999 .Mul,
2000 .Lpmx,
2001 .Ijmpcall,
2002 .Break,
2003 .Avr5,
2004 }),
2005 CpuInfo(@This(), FeatureType).create(.Atmega645a, "atmega645a", &[_]FeatureType {
2006 .Lpm,
2007 .Movw,
2008 .Spm,
2009 .Avr0,
2010 .Sram,
2011 .Jmpcall,
2012 .Addsubiw,
2013 .Mul,
2014 .Lpmx,
2015 .Ijmpcall,
2016 .Break,
2017 .Avr5,
2018 }),
2019 CpuInfo(@This(), FeatureType).create(.Atmega645p, "atmega645p", &[_]FeatureType {
2020 .Lpm,
2021 .Movw,
2022 .Spm,
2023 .Avr0,
2024 .Sram,
2025 .Jmpcall,
2026 .Addsubiw,
2027 .Mul,
2028 .Lpmx,
2029 .Ijmpcall,
2030 .Break,
2031 .Avr5,
2032 }),
2033 CpuInfo(@This(), FeatureType).create(.Atmega649, "atmega649", &[_]FeatureType {
2034 .Lpm,
2035 .Movw,
2036 .Spm,
2037 .Avr0,
2038 .Sram,
2039 .Jmpcall,
2040 .Addsubiw,
2041 .Mul,
2042 .Lpmx,
2043 .Ijmpcall,
2044 .Break,
2045 .Avr5,
2046 }),
2047 CpuInfo(@This(), FeatureType).create(.Atmega6490, "atmega6490", &[_]FeatureType {
2048 .Lpm,
2049 .Movw,
2050 .Spm,
2051 .Avr0,
2052 .Sram,
2053 .Jmpcall,
2054 .Addsubiw,
2055 .Mul,
2056 .Lpmx,
2057 .Ijmpcall,
2058 .Break,
2059 .Avr5,
2060 }),
2061 CpuInfo(@This(), FeatureType).create(.Atmega6490a, "atmega6490a", &[_]FeatureType {
2062 .Lpm,
2063 .Movw,
2064 .Spm,
2065 .Avr0,
2066 .Sram,
2067 .Jmpcall,
2068 .Addsubiw,
2069 .Mul,
2070 .Lpmx,
2071 .Ijmpcall,
2072 .Break,
2073 .Avr5,
2074 }),
2075 CpuInfo(@This(), FeatureType).create(.Atmega6490p, "atmega6490p", &[_]FeatureType {
2076 .Lpm,
2077 .Movw,
2078 .Spm,
2079 .Avr0,
2080 .Sram,
2081 .Jmpcall,
2082 .Addsubiw,
2083 .Mul,
2084 .Lpmx,
2085 .Ijmpcall,
2086 .Break,
2087 .Avr5,
2088 }),
2089 CpuInfo(@This(), FeatureType).create(.Atmega649a, "atmega649a", &[_]FeatureType {
2090 .Lpm,
2091 .Movw,
2092 .Spm,
2093 .Avr0,
2094 .Sram,
2095 .Jmpcall,
2096 .Addsubiw,
2097 .Mul,
2098 .Lpmx,
2099 .Ijmpcall,
2100 .Break,
2101 .Avr5,
2102 }),
2103 CpuInfo(@This(), FeatureType).create(.Atmega649p, "atmega649p", &[_]FeatureType {
2104 .Lpm,
2105 .Movw,
2106 .Spm,
2107 .Avr0,
2108 .Sram,
2109 .Jmpcall,
2110 .Addsubiw,
2111 .Mul,
2112 .Lpmx,
2113 .Ijmpcall,
2114 .Break,
2115 .Avr5,
2116 }),
2117 CpuInfo(@This(), FeatureType).create(.Atmega64a, "atmega64a", &[_]FeatureType {
2118 .Lpm,
2119 .Movw,
2120 .Spm,
2121 .Avr0,
2122 .Sram,
2123 .Jmpcall,
2124 .Addsubiw,
2125 .Mul,
2126 .Lpmx,
2127 .Ijmpcall,
2128 .Break,
2129 .Avr5,
2130 }),
2131 CpuInfo(@This(), FeatureType).create(.Atmega64c1, "atmega64c1", &[_]FeatureType {
2132 .Lpm,
2133 .Movw,
2134 .Spm,
2135 .Avr0,
2136 .Sram,
2137 .Jmpcall,
2138 .Addsubiw,
2139 .Mul,
2140 .Lpmx,
2141 .Ijmpcall,
2142 .Break,
2143 .Avr5,
2144 }),
2145 CpuInfo(@This(), FeatureType).create(.Atmega64hve, "atmega64hve", &[_]FeatureType {
2146 .Lpm,
2147 .Movw,
2148 .Spm,
2149 .Avr0,
2150 .Sram,
2151 .Jmpcall,
2152 .Addsubiw,
2153 .Mul,
2154 .Lpmx,
2155 .Ijmpcall,
2156 .Break,
2157 .Avr5,
2158 }),
2159 CpuInfo(@This(), FeatureType).create(.Atmega64m1, "atmega64m1", &[_]FeatureType {
2160 .Lpm,
2161 .Movw,
2162 .Spm,
2163 .Avr0,
2164 .Sram,
2165 .Jmpcall,
2166 .Addsubiw,
2167 .Mul,
2168 .Lpmx,
2169 .Ijmpcall,
2170 .Break,
2171 .Avr5,
2172 }),
2173 CpuInfo(@This(), FeatureType).create(.Atmega64rfr2, "atmega64rfr2", &[_]FeatureType {
2174 .Lpm,
2175 .Movw,
2176 .Spm,
2177 .Avr0,
2178 .Sram,
2179 .Jmpcall,
2180 .Addsubiw,
2181 .Mul,
2182 .Lpmx,
2183 .Ijmpcall,
2184 .Break,
2185 .Avr5,
2186 }),
2187 CpuInfo(@This(), FeatureType).create(.Atmega8, "atmega8", &[_]FeatureType {
2188 .Lpm,
2189 .Movw,
2190 .Spm,
2191 .Avr0,
2192 .Sram,
2193 .Addsubiw,
2194 .Mul,
2195 .Lpmx,
2196 .Ijmpcall,
2197 .Break,
2198 .Avr4,
2199 }),
2200 CpuInfo(@This(), FeatureType).create(.Atmega8515, "atmega8515", &[_]FeatureType {
2201 .Lpm,
2202 .Avr0,
2203 .Sram,
2204 .Addsubiw,
2205 .Ijmpcall,
2206 .Avr2,
2207 .Lpmx,
2208 .Movw,
2209 .Mul,
2210 .Spm,
2211 }),
2212 CpuInfo(@This(), FeatureType).create(.Atmega8535, "atmega8535", &[_]FeatureType {
2213 .Lpm,
2214 .Avr0,
2215 .Sram,
2216 .Addsubiw,
2217 .Ijmpcall,
2218 .Avr2,
2219 .Lpmx,
2220 .Movw,
2221 .Mul,
2222 .Spm,
2223 }),
2224 CpuInfo(@This(), FeatureType).create(.Atmega88, "atmega88", &[_]FeatureType {
2225 .Lpm,
2226 .Movw,
2227 .Spm,
2228 .Avr0,
2229 .Sram,
2230 .Addsubiw,
2231 .Mul,
2232 .Lpmx,
2233 .Ijmpcall,
2234 .Break,
2235 .Avr4,
2236 }),
2237 CpuInfo(@This(), FeatureType).create(.Atmega88a, "atmega88a", &[_]FeatureType {
2238 .Lpm,
2239 .Movw,
2240 .Spm,
2241 .Avr0,
2242 .Sram,
2243 .Addsubiw,
2244 .Mul,
2245 .Lpmx,
2246 .Ijmpcall,
2247 .Break,
2248 .Avr4,
2249 }),
2250 CpuInfo(@This(), FeatureType).create(.Atmega88p, "atmega88p", &[_]FeatureType {
2251 .Lpm,
2252 .Movw,
2253 .Spm,
2254 .Avr0,
2255 .Sram,
2256 .Addsubiw,
2257 .Mul,
2258 .Lpmx,
2259 .Ijmpcall,
2260 .Break,
2261 .Avr4,
2262 }),
2263 CpuInfo(@This(), FeatureType).create(.Atmega88pa, "atmega88pa", &[_]FeatureType {
2264 .Lpm,
2265 .Movw,
2266 .Spm,
2267 .Avr0,
2268 .Sram,
2269 .Addsubiw,
2270 .Mul,
2271 .Lpmx,
2272 .Ijmpcall,
2273 .Break,
2274 .Avr4,
2275 }),
2276 CpuInfo(@This(), FeatureType).create(.Atmega8a, "atmega8a", &[_]FeatureType {
2277 .Lpm,
2278 .Movw,
2279 .Spm,
2280 .Avr0,
2281 .Sram,
2282 .Addsubiw,
2283 .Mul,
2284 .Lpmx,
2285 .Ijmpcall,
2286 .Break,
2287 .Avr4,
2288 }),
2289 CpuInfo(@This(), FeatureType).create(.Atmega8hva, "atmega8hva", &[_]FeatureType {
2290 .Lpm,
2291 .Movw,
2292 .Spm,
2293 .Avr0,
2294 .Sram,
2295 .Addsubiw,
2296 .Mul,
2297 .Lpmx,
2298 .Ijmpcall,
2299 .Break,
2300 .Avr4,
2301 }),
2302 CpuInfo(@This(), FeatureType).create(.Atmega8u2, "atmega8u2", &[_]FeatureType {
2303 .Lpm,
2304 .Movw,
2305 .Spm,
2306 .Avr0,
2307 .Sram,
2308 .Jmpcall,
2309 .Addsubiw,
2310 .Lpmx,
2311 .Ijmpcall,
2312 .Break,
2313 .Avr35,
2314 }),
2315 CpuInfo(@This(), FeatureType).create(.Attiny10, "attiny10", &[_]FeatureType {
2316 .Avr0,
2317 .Sram,
2318 .Break,
2319 .Tinyencoding,
2320 .Avrtiny,
2321 }),
2322 CpuInfo(@This(), FeatureType).create(.Attiny102, "attiny102", &[_]FeatureType {
2323 .Avr0,
2324 .Sram,
2325 .Break,
2326 .Tinyencoding,
2327 .Avrtiny,
2328 }),
2329 CpuInfo(@This(), FeatureType).create(.Attiny104, "attiny104", &[_]FeatureType {
2330 .Avr0,
2331 .Sram,
2332 .Break,
2333 .Tinyencoding,
2334 .Avrtiny,
2335 }),
2336 CpuInfo(@This(), FeatureType).create(.Attiny11, "attiny11", &[_]FeatureType {
2337 .Avr0,
2338 .Lpm,
2339 .Avr1,
2340 }),
2341 CpuInfo(@This(), FeatureType).create(.Attiny12, "attiny12", &[_]FeatureType {
2342 .Avr0,
2343 .Lpm,
2344 .Avr1,
2345 }),
2346 CpuInfo(@This(), FeatureType).create(.Attiny13, "attiny13", &[_]FeatureType {
2347 .Lpm,
2348 .Movw,
2349 .Spm,
2350 .Avr0,
2351 .Sram,
2352 .Addsubiw,
2353 .Lpmx,
2354 .Ijmpcall,
2355 .Break,
2356 .Avr25,
2357 }),
2358 CpuInfo(@This(), FeatureType).create(.Attiny13a, "attiny13a", &[_]FeatureType {
2359 .Lpm,
2360 .Movw,
2361 .Spm,
2362 .Avr0,
2363 .Sram,
2364 .Addsubiw,
2365 .Lpmx,
2366 .Ijmpcall,
2367 .Break,
2368 .Avr25,
2369 }),
2370 CpuInfo(@This(), FeatureType).create(.Attiny15, "attiny15", &[_]FeatureType {
2371 .Avr0,
2372 .Lpm,
2373 .Avr1,
2374 }),
2375 CpuInfo(@This(), FeatureType).create(.Attiny1634, "attiny1634", &[_]FeatureType {
2376 .Lpm,
2377 .Movw,
2378 .Spm,
2379 .Avr0,
2380 .Sram,
2381 .Jmpcall,
2382 .Addsubiw,
2383 .Lpmx,
2384 .Ijmpcall,
2385 .Break,
2386 .Avr35,
2387 }),
2388 CpuInfo(@This(), FeatureType).create(.Attiny167, "attiny167", &[_]FeatureType {
2389 .Lpm,
2390 .Movw,
2391 .Spm,
2392 .Avr0,
2393 .Sram,
2394 .Jmpcall,
2395 .Addsubiw,
2396 .Lpmx,
2397 .Ijmpcall,
2398 .Break,
2399 .Avr35,
2400 }),
2401 CpuInfo(@This(), FeatureType).create(.Attiny20, "attiny20", &[_]FeatureType {
2402 .Avr0,
2403 .Sram,
2404 .Break,
2405 .Tinyencoding,
2406 .Avrtiny,
2407 }),
2408 CpuInfo(@This(), FeatureType).create(.Attiny22, "attiny22", &[_]FeatureType {
2409 .Lpm,
2410 .Avr0,
2411 .Sram,
2412 .Addsubiw,
2413 .Ijmpcall,
2414 .Avr2,
2415 }),
2416 CpuInfo(@This(), FeatureType).create(.Attiny2313, "attiny2313", &[_]FeatureType {
2417 .Lpm,
2418 .Movw,
2419 .Spm,
2420 .Avr0,
2421 .Sram,
2422 .Addsubiw,
2423 .Lpmx,
2424 .Ijmpcall,
2425 .Break,
2426 .Avr25,
2427 }),
2428 CpuInfo(@This(), FeatureType).create(.Attiny2313a, "attiny2313a", &[_]FeatureType {
2429 .Lpm,
2430 .Movw,
2431 .Spm,
2432 .Avr0,
2433 .Sram,
2434 .Addsubiw,
2435 .Lpmx,
2436 .Ijmpcall,
2437 .Break,
2438 .Avr25,
2439 }),
2440 CpuInfo(@This(), FeatureType).create(.Attiny24, "attiny24", &[_]FeatureType {
2441 .Lpm,
2442 .Movw,
2443 .Spm,
2444 .Avr0,
2445 .Sram,
2446 .Addsubiw,
2447 .Lpmx,
2448 .Ijmpcall,
2449 .Break,
2450 .Avr25,
2451 }),
2452 CpuInfo(@This(), FeatureType).create(.Attiny24a, "attiny24a", &[_]FeatureType {
2453 .Lpm,
2454 .Movw,
2455 .Spm,
2456 .Avr0,
2457 .Sram,
2458 .Addsubiw,
2459 .Lpmx,
2460 .Ijmpcall,
2461 .Break,
2462 .Avr25,
2463 }),
2464 CpuInfo(@This(), FeatureType).create(.Attiny25, "attiny25", &[_]FeatureType {
2465 .Lpm,
2466 .Movw,
2467 .Spm,
2468 .Avr0,
2469 .Sram,
2470 .Addsubiw,
2471 .Lpmx,
2472 .Ijmpcall,
2473 .Break,
2474 .Avr25,
2475 }),
2476 CpuInfo(@This(), FeatureType).create(.Attiny26, "attiny26", &[_]FeatureType {
2477 .Lpm,
2478 .Avr0,
2479 .Sram,
2480 .Addsubiw,
2481 .Ijmpcall,
2482 .Avr2,
2483 .Lpmx,
2484 }),
2485 CpuInfo(@This(), FeatureType).create(.Attiny261, "attiny261", &[_]FeatureType {
2486 .Lpm,
2487 .Movw,
2488 .Spm,
2489 .Avr0,
2490 .Sram,
2491 .Addsubiw,
2492 .Lpmx,
2493 .Ijmpcall,
2494 .Break,
2495 .Avr25,
2496 }),
2497 CpuInfo(@This(), FeatureType).create(.Attiny261a, "attiny261a", &[_]FeatureType {
2498 .Lpm,
2499 .Movw,
2500 .Spm,
2501 .Avr0,
2502 .Sram,
2503 .Addsubiw,
2504 .Lpmx,
2505 .Ijmpcall,
2506 .Break,
2507 .Avr25,
2508 }),
2509 CpuInfo(@This(), FeatureType).create(.Attiny28, "attiny28", &[_]FeatureType {
2510 .Avr0,
2511 .Lpm,
2512 .Avr1,
2513 }),
2514 CpuInfo(@This(), FeatureType).create(.Attiny4, "attiny4", &[_]FeatureType {
2515 .Avr0,
2516 .Sram,
2517 .Break,
2518 .Tinyencoding,
2519 .Avrtiny,
2520 }),
2521 CpuInfo(@This(), FeatureType).create(.Attiny40, "attiny40", &[_]FeatureType {
2522 .Avr0,
2523 .Sram,
2524 .Break,
2525 .Tinyencoding,
2526 .Avrtiny,
2527 }),
2528 CpuInfo(@This(), FeatureType).create(.Attiny4313, "attiny4313", &[_]FeatureType {
2529 .Lpm,
2530 .Movw,
2531 .Spm,
2532 .Avr0,
2533 .Sram,
2534 .Addsubiw,
2535 .Lpmx,
2536 .Ijmpcall,
2537 .Break,
2538 .Avr25,
2539 }),
2540 CpuInfo(@This(), FeatureType).create(.Attiny43u, "attiny43u", &[_]FeatureType {
2541 .Lpm,
2542 .Movw,
2543 .Spm,
2544 .Avr0,
2545 .Sram,
2546 .Addsubiw,
2547 .Lpmx,
2548 .Ijmpcall,
2549 .Break,
2550 .Avr25,
2551 }),
2552 CpuInfo(@This(), FeatureType).create(.Attiny44, "attiny44", &[_]FeatureType {
2553 .Lpm,
2554 .Movw,
2555 .Spm,
2556 .Avr0,
2557 .Sram,
2558 .Addsubiw,
2559 .Lpmx,
2560 .Ijmpcall,
2561 .Break,
2562 .Avr25,
2563 }),
2564 CpuInfo(@This(), FeatureType).create(.Attiny44a, "attiny44a", &[_]FeatureType {
2565 .Lpm,
2566 .Movw,
2567 .Spm,
2568 .Avr0,
2569 .Sram,
2570 .Addsubiw,
2571 .Lpmx,
2572 .Ijmpcall,
2573 .Break,
2574 .Avr25,
2575 }),
2576 CpuInfo(@This(), FeatureType).create(.Attiny45, "attiny45", &[_]FeatureType {
2577 .Lpm,
2578 .Movw,
2579 .Spm,
2580 .Avr0,
2581 .Sram,
2582 .Addsubiw,
2583 .Lpmx,
2584 .Ijmpcall,
2585 .Break,
2586 .Avr25,
2587 }),
2588 CpuInfo(@This(), FeatureType).create(.Attiny461, "attiny461", &[_]FeatureType {
2589 .Lpm,
2590 .Movw,
2591 .Spm,
2592 .Avr0,
2593 .Sram,
2594 .Addsubiw,
2595 .Lpmx,
2596 .Ijmpcall,
2597 .Break,
2598 .Avr25,
2599 }),
2600 CpuInfo(@This(), FeatureType).create(.Attiny461a, "attiny461a", &[_]FeatureType {
2601 .Lpm,
2602 .Movw,
2603 .Spm,
2604 .Avr0,
2605 .Sram,
2606 .Addsubiw,
2607 .Lpmx,
2608 .Ijmpcall,
2609 .Break,
2610 .Avr25,
2611 }),
2612 CpuInfo(@This(), FeatureType).create(.Attiny48, "attiny48", &[_]FeatureType {
2613 .Lpm,
2614 .Movw,
2615 .Spm,
2616 .Avr0,
2617 .Sram,
2618 .Addsubiw,
2619 .Lpmx,
2620 .Ijmpcall,
2621 .Break,
2622 .Avr25,
2623 }),
2624 CpuInfo(@This(), FeatureType).create(.Attiny5, "attiny5", &[_]FeatureType {
2625 .Avr0,
2626 .Sram,
2627 .Break,
2628 .Tinyencoding,
2629 .Avrtiny,
2630 }),
2631 CpuInfo(@This(), FeatureType).create(.Attiny828, "attiny828", &[_]FeatureType {
2632 .Lpm,
2633 .Movw,
2634 .Spm,
2635 .Avr0,
2636 .Sram,
2637 .Addsubiw,
2638 .Lpmx,
2639 .Ijmpcall,
2640 .Break,
2641 .Avr25,
2642 }),
2643 CpuInfo(@This(), FeatureType).create(.Attiny84, "attiny84", &[_]FeatureType {
2644 .Lpm,
2645 .Movw,
2646 .Spm,
2647 .Avr0,
2648 .Sram,
2649 .Addsubiw,
2650 .Lpmx,
2651 .Ijmpcall,
2652 .Break,
2653 .Avr25,
2654 }),
2655 CpuInfo(@This(), FeatureType).create(.Attiny84a, "attiny84a", &[_]FeatureType {
2656 .Lpm,
2657 .Movw,
2658 .Spm,
2659 .Avr0,
2660 .Sram,
2661 .Addsubiw,
2662 .Lpmx,
2663 .Ijmpcall,
2664 .Break,
2665 .Avr25,
2666 }),
2667 CpuInfo(@This(), FeatureType).create(.Attiny85, "attiny85", &[_]FeatureType {
2668 .Lpm,
2669 .Movw,
2670 .Spm,
2671 .Avr0,
2672 .Sram,
2673 .Addsubiw,
2674 .Lpmx,
2675 .Ijmpcall,
2676 .Break,
2677 .Avr25,
2678 }),
2679 CpuInfo(@This(), FeatureType).create(.Attiny861, "attiny861", &[_]FeatureType {
2680 .Lpm,
2681 .Movw,
2682 .Spm,
2683 .Avr0,
2684 .Sram,
2685 .Addsubiw,
2686 .Lpmx,
2687 .Ijmpcall,
2688 .Break,
2689 .Avr25,
2690 }),
2691 CpuInfo(@This(), FeatureType).create(.Attiny861a, "attiny861a", &[_]FeatureType {
2692 .Lpm,
2693 .Movw,
2694 .Spm,
2695 .Avr0,
2696 .Sram,
2697 .Addsubiw,
2698 .Lpmx,
2699 .Ijmpcall,
2700 .Break,
2701 .Avr25,
2702 }),
2703 CpuInfo(@This(), FeatureType).create(.Attiny87, "attiny87", &[_]FeatureType {
2704 .Lpm,
2705 .Movw,
2706 .Spm,
2707 .Avr0,
2708 .Sram,
2709 .Addsubiw,
2710 .Lpmx,
2711 .Ijmpcall,
2712 .Break,
2713 .Avr25,
2714 }),
2715 CpuInfo(@This(), FeatureType).create(.Attiny88, "attiny88", &[_]FeatureType {
2716 .Lpm,
2717 .Movw,
2718 .Spm,
2719 .Avr0,
2720 .Sram,
2721 .Addsubiw,
2722 .Lpmx,
2723 .Ijmpcall,
2724 .Break,
2725 .Avr25,
2726 }),
2727 CpuInfo(@This(), FeatureType).create(.Attiny9, "attiny9", &[_]FeatureType {
2728 .Avr0,
2729 .Sram,
2730 .Break,
2731 .Tinyencoding,
2732 .Avrtiny,
2733 }),
2734 CpuInfo(@This(), FeatureType).create(.Atxmega128a1, "atxmega128a1", &[_]FeatureType {
2735 .Lpm,
2736 .Elpm,
2737 .Movw,
2738 .Elpmx,
2739 .Spm,
2740 .Avr0,
2741 .Sram,
2742 .Jmpcall,
2743 .Eijmpcall,
2744 .Spmx,
2745 .Addsubiw,
2746 .Mul,
2747 .Lpmx,
2748 .Des,
2749 .Ijmpcall,
2750 .Break,
2751 .Xmega,
2752 }),
2753 CpuInfo(@This(), FeatureType).create(.Atxmega128a1u, "atxmega128a1u", &[_]FeatureType {
2754 .Lpm,
2755 .Elpm,
2756 .Movw,
2757 .Elpmx,
2758 .Spm,
2759 .Avr0,
2760 .Sram,
2761 .Jmpcall,
2762 .Eijmpcall,
2763 .Spmx,
2764 .Addsubiw,
2765 .Mul,
2766 .Lpmx,
2767 .Rmw,
2768 .Des,
2769 .Ijmpcall,
2770 .Break,
2771 .Xmegau,
2772 }),
2773 CpuInfo(@This(), FeatureType).create(.Atxmega128a3, "atxmega128a3", &[_]FeatureType {
2774 .Lpm,
2775 .Elpm,
2776 .Movw,
2777 .Elpmx,
2778 .Spm,
2779 .Avr0,
2780 .Sram,
2781 .Jmpcall,
2782 .Eijmpcall,
2783 .Spmx,
2784 .Addsubiw,
2785 .Mul,
2786 .Lpmx,
2787 .Des,
2788 .Ijmpcall,
2789 .Break,
2790 .Xmega,
2791 }),
2792 CpuInfo(@This(), FeatureType).create(.Atxmega128a3u, "atxmega128a3u", &[_]FeatureType {
2793 .Lpm,
2794 .Elpm,
2795 .Movw,
2796 .Elpmx,
2797 .Spm,
2798 .Avr0,
2799 .Sram,
2800 .Jmpcall,
2801 .Eijmpcall,
2802 .Spmx,
2803 .Addsubiw,
2804 .Mul,
2805 .Lpmx,
2806 .Rmw,
2807 .Des,
2808 .Ijmpcall,
2809 .Break,
2810 .Xmegau,
2811 }),
2812 CpuInfo(@This(), FeatureType).create(.Atxmega128a4u, "atxmega128a4u", &[_]FeatureType {
2813 .Lpm,
2814 .Elpm,
2815 .Movw,
2816 .Elpmx,
2817 .Spm,
2818 .Avr0,
2819 .Sram,
2820 .Jmpcall,
2821 .Eijmpcall,
2822 .Spmx,
2823 .Addsubiw,
2824 .Mul,
2825 .Lpmx,
2826 .Rmw,
2827 .Des,
2828 .Ijmpcall,
2829 .Break,
2830 .Xmegau,
2831 }),
2832 CpuInfo(@This(), FeatureType).create(.Atxmega128b1, "atxmega128b1", &[_]FeatureType {
2833 .Lpm,
2834 .Elpm,
2835 .Movw,
2836 .Elpmx,
2837 .Spm,
2838 .Avr0,
2839 .Sram,
2840 .Jmpcall,
2841 .Eijmpcall,
2842 .Spmx,
2843 .Addsubiw,
2844 .Mul,
2845 .Lpmx,
2846 .Rmw,
2847 .Des,
2848 .Ijmpcall,
2849 .Break,
2850 .Xmegau,
2851 }),
2852 CpuInfo(@This(), FeatureType).create(.Atxmega128b3, "atxmega128b3", &[_]FeatureType {
2853 .Lpm,
2854 .Elpm,
2855 .Movw,
2856 .Elpmx,
2857 .Spm,
2858 .Avr0,
2859 .Sram,
2860 .Jmpcall,
2861 .Eijmpcall,
2862 .Spmx,
2863 .Addsubiw,
2864 .Mul,
2865 .Lpmx,
2866 .Rmw,
2867 .Des,
2868 .Ijmpcall,
2869 .Break,
2870 .Xmegau,
2871 }),
2872 CpuInfo(@This(), FeatureType).create(.Atxmega128c3, "atxmega128c3", &[_]FeatureType {
2873 .Lpm,
2874 .Elpm,
2875 .Movw,
2876 .Elpmx,
2877 .Spm,
2878 .Avr0,
2879 .Sram,
2880 .Jmpcall,
2881 .Eijmpcall,
2882 .Spmx,
2883 .Addsubiw,
2884 .Mul,
2885 .Lpmx,
2886 .Rmw,
2887 .Des,
2888 .Ijmpcall,
2889 .Break,
2890 .Xmegau,
2891 }),
2892 CpuInfo(@This(), FeatureType).create(.Atxmega128d3, "atxmega128d3", &[_]FeatureType {
2893 .Lpm,
2894 .Elpm,
2895 .Movw,
2896 .Elpmx,
2897 .Spm,
2898 .Avr0,
2899 .Sram,
2900 .Jmpcall,
2901 .Eijmpcall,
2902 .Spmx,
2903 .Addsubiw,
2904 .Mul,
2905 .Lpmx,
2906 .Des,
2907 .Ijmpcall,
2908 .Break,
2909 .Xmega,
2910 }),
2911 CpuInfo(@This(), FeatureType).create(.Atxmega128d4, "atxmega128d4", &[_]FeatureType {
2912 .Lpm,
2913 .Elpm,
2914 .Movw,
2915 .Elpmx,
2916 .Spm,
2917 .Avr0,
2918 .Sram,
2919 .Jmpcall,
2920 .Eijmpcall,
2921 .Spmx,
2922 .Addsubiw,
2923 .Mul,
2924 .Lpmx,
2925 .Des,
2926 .Ijmpcall,
2927 .Break,
2928 .Xmega,
2929 }),
2930 CpuInfo(@This(), FeatureType).create(.Atxmega16a4, "atxmega16a4", &[_]FeatureType {
2931 .Lpm,
2932 .Elpm,
2933 .Movw,
2934 .Elpmx,
2935 .Spm,
2936 .Avr0,
2937 .Sram,
2938 .Jmpcall,
2939 .Eijmpcall,
2940 .Spmx,
2941 .Addsubiw,
2942 .Mul,
2943 .Lpmx,
2944 .Des,
2945 .Ijmpcall,
2946 .Break,
2947 .Xmega,
2948 }),
2949 CpuInfo(@This(), FeatureType).create(.Atxmega16a4u, "atxmega16a4u", &[_]FeatureType {
2950 .Lpm,
2951 .Elpm,
2952 .Movw,
2953 .Elpmx,
2954 .Spm,
2955 .Avr0,
2956 .Sram,
2957 .Jmpcall,
2958 .Eijmpcall,
2959 .Spmx,
2960 .Addsubiw,
2961 .Mul,
2962 .Lpmx,
2963 .Rmw,
2964 .Des,
2965 .Ijmpcall,
2966 .Break,
2967 .Xmegau,
2968 }),
2969 CpuInfo(@This(), FeatureType).create(.Atxmega16c4, "atxmega16c4", &[_]FeatureType {
2970 .Lpm,
2971 .Elpm,
2972 .Movw,
2973 .Elpmx,
2974 .Spm,
2975 .Avr0,
2976 .Sram,
2977 .Jmpcall,
2978 .Eijmpcall,
2979 .Spmx,
2980 .Addsubiw,
2981 .Mul,
2982 .Lpmx,
2983 .Rmw,
2984 .Des,
2985 .Ijmpcall,
2986 .Break,
2987 .Xmegau,
2988 }),
2989 CpuInfo(@This(), FeatureType).create(.Atxmega16d4, "atxmega16d4", &[_]FeatureType {
2990 .Lpm,
2991 .Elpm,
2992 .Movw,
2993 .Elpmx,
2994 .Spm,
2995 .Avr0,
2996 .Sram,
2997 .Jmpcall,
2998 .Eijmpcall,
2999 .Spmx,
3000 .Addsubiw,
3001 .Mul,
3002 .Lpmx,
3003 .Des,
3004 .Ijmpcall,
3005 .Break,
3006 .Xmega,
3007 }),
3008 CpuInfo(@This(), FeatureType).create(.Atxmega16e5, "atxmega16e5", &[_]FeatureType {
3009 .Lpm,
3010 .Elpm,
3011 .Movw,
3012 .Elpmx,
3013 .Spm,
3014 .Avr0,
3015 .Sram,
3016 .Jmpcall,
3017 .Eijmpcall,
3018 .Spmx,
3019 .Addsubiw,
3020 .Mul,
3021 .Lpmx,
3022 .Des,
3023 .Ijmpcall,
3024 .Break,
3025 .Xmega,
3026 }),
3027 CpuInfo(@This(), FeatureType).create(.Atxmega192a3, "atxmega192a3", &[_]FeatureType {
3028 .Lpm,
3029 .Elpm,
3030 .Movw,
3031 .Elpmx,
3032 .Spm,
3033 .Avr0,
3034 .Sram,
3035 .Jmpcall,
3036 .Eijmpcall,
3037 .Spmx,
3038 .Addsubiw,
3039 .Mul,
3040 .Lpmx,
3041 .Des,
3042 .Ijmpcall,
3043 .Break,
3044 .Xmega,
3045 }),
3046 CpuInfo(@This(), FeatureType).create(.Atxmega192a3u, "atxmega192a3u", &[_]FeatureType {
3047 .Lpm,
3048 .Elpm,
3049 .Movw,
3050 .Elpmx,
3051 .Spm,
3052 .Avr0,
3053 .Sram,
3054 .Jmpcall,
3055 .Eijmpcall,
3056 .Spmx,
3057 .Addsubiw,
3058 .Mul,
3059 .Lpmx,
3060 .Rmw,
3061 .Des,
3062 .Ijmpcall,
3063 .Break,
3064 .Xmegau,
3065 }),
3066 CpuInfo(@This(), FeatureType).create(.Atxmega192c3, "atxmega192c3", &[_]FeatureType {
3067 .Lpm,
3068 .Elpm,
3069 .Movw,
3070 .Elpmx,
3071 .Spm,
3072 .Avr0,
3073 .Sram,
3074 .Jmpcall,
3075 .Eijmpcall,
3076 .Spmx,
3077 .Addsubiw,
3078 .Mul,
3079 .Lpmx,
3080 .Rmw,
3081 .Des,
3082 .Ijmpcall,
3083 .Break,
3084 .Xmegau,
3085 }),
3086 CpuInfo(@This(), FeatureType).create(.Atxmega192d3, "atxmega192d3", &[_]FeatureType {
3087 .Lpm,
3088 .Elpm,
3089 .Movw,
3090 .Elpmx,
3091 .Spm,
3092 .Avr0,
3093 .Sram,
3094 .Jmpcall,
3095 .Eijmpcall,
3096 .Spmx,
3097 .Addsubiw,
3098 .Mul,
3099 .Lpmx,
3100 .Des,
3101 .Ijmpcall,
3102 .Break,
3103 .Xmega,
3104 }),
3105 CpuInfo(@This(), FeatureType).create(.Atxmega256a3, "atxmega256a3", &[_]FeatureType {
3106 .Lpm,
3107 .Elpm,
3108 .Movw,
3109 .Elpmx,
3110 .Spm,
3111 .Avr0,
3112 .Sram,
3113 .Jmpcall,
3114 .Eijmpcall,
3115 .Spmx,
3116 .Addsubiw,
3117 .Mul,
3118 .Lpmx,
3119 .Des,
3120 .Ijmpcall,
3121 .Break,
3122 .Xmega,
3123 }),
3124 CpuInfo(@This(), FeatureType).create(.Atxmega256a3b, "atxmega256a3b", &[_]FeatureType {
3125 .Lpm,
3126 .Elpm,
3127 .Movw,
3128 .Elpmx,
3129 .Spm,
3130 .Avr0,
3131 .Sram,
3132 .Jmpcall,
3133 .Eijmpcall,
3134 .Spmx,
3135 .Addsubiw,
3136 .Mul,
3137 .Lpmx,
3138 .Des,
3139 .Ijmpcall,
3140 .Break,
3141 .Xmega,
3142 }),
3143 CpuInfo(@This(), FeatureType).create(.Atxmega256a3bu, "atxmega256a3bu", &[_]FeatureType {
3144 .Lpm,
3145 .Elpm,
3146 .Movw,
3147 .Elpmx,
3148 .Spm,
3149 .Avr0,
3150 .Sram,
3151 .Jmpcall,
3152 .Eijmpcall,
3153 .Spmx,
3154 .Addsubiw,
3155 .Mul,
3156 .Lpmx,
3157 .Rmw,
3158 .Des,
3159 .Ijmpcall,
3160 .Break,
3161 .Xmegau,
3162 }),
3163 CpuInfo(@This(), FeatureType).create(.Atxmega256a3u, "atxmega256a3u", &[_]FeatureType {
3164 .Lpm,
3165 .Elpm,
3166 .Movw,
3167 .Elpmx,
3168 .Spm,
3169 .Avr0,
3170 .Sram,
3171 .Jmpcall,
3172 .Eijmpcall,
3173 .Spmx,
3174 .Addsubiw,
3175 .Mul,
3176 .Lpmx,
3177 .Rmw,
3178 .Des,
3179 .Ijmpcall,
3180 .Break,
3181 .Xmegau,
3182 }),
3183 CpuInfo(@This(), FeatureType).create(.Atxmega256c3, "atxmega256c3", &[_]FeatureType {
3184 .Lpm,
3185 .Elpm,
3186 .Movw,
3187 .Elpmx,
3188 .Spm,
3189 .Avr0,
3190 .Sram,
3191 .Jmpcall,
3192 .Eijmpcall,
3193 .Spmx,
3194 .Addsubiw,
3195 .Mul,
3196 .Lpmx,
3197 .Rmw,
3198 .Des,
3199 .Ijmpcall,
3200 .Break,
3201 .Xmegau,
3202 }),
3203 CpuInfo(@This(), FeatureType).create(.Atxmega256d3, "atxmega256d3", &[_]FeatureType {
3204 .Lpm,
3205 .Elpm,
3206 .Movw,
3207 .Elpmx,
3208 .Spm,
3209 .Avr0,
3210 .Sram,
3211 .Jmpcall,
3212 .Eijmpcall,
3213 .Spmx,
3214 .Addsubiw,
3215 .Mul,
3216 .Lpmx,
3217 .Des,
3218 .Ijmpcall,
3219 .Break,
3220 .Xmega,
3221 }),
3222 CpuInfo(@This(), FeatureType).create(.Atxmega32a4, "atxmega32a4", &[_]FeatureType {
3223 .Lpm,
3224 .Elpm,
3225 .Movw,
3226 .Elpmx,
3227 .Spm,
3228 .Avr0,
3229 .Sram,
3230 .Jmpcall,
3231 .Eijmpcall,
3232 .Spmx,
3233 .Addsubiw,
3234 .Mul,
3235 .Lpmx,
3236 .Des,
3237 .Ijmpcall,
3238 .Break,
3239 .Xmega,
3240 }),
3241 CpuInfo(@This(), FeatureType).create(.Atxmega32a4u, "atxmega32a4u", &[_]FeatureType {
3242 .Lpm,
3243 .Elpm,
3244 .Movw,
3245 .Elpmx,
3246 .Spm,
3247 .Avr0,
3248 .Sram,
3249 .Jmpcall,
3250 .Eijmpcall,
3251 .Spmx,
3252 .Addsubiw,
3253 .Mul,
3254 .Lpmx,
3255 .Rmw,
3256 .Des,
3257 .Ijmpcall,
3258 .Break,
3259 .Xmegau,
3260 }),
3261 CpuInfo(@This(), FeatureType).create(.Atxmega32c4, "atxmega32c4", &[_]FeatureType {
3262 .Lpm,
3263 .Elpm,
3264 .Movw,
3265 .Elpmx,
3266 .Spm,
3267 .Avr0,
3268 .Sram,
3269 .Jmpcall,
3270 .Eijmpcall,
3271 .Spmx,
3272 .Addsubiw,
3273 .Mul,
3274 .Lpmx,
3275 .Rmw,
3276 .Des,
3277 .Ijmpcall,
3278 .Break,
3279 .Xmegau,
3280 }),
3281 CpuInfo(@This(), FeatureType).create(.Atxmega32d4, "atxmega32d4", &[_]FeatureType {
3282 .Lpm,
3283 .Elpm,
3284 .Movw,
3285 .Elpmx,
3286 .Spm,
3287 .Avr0,
3288 .Sram,
3289 .Jmpcall,
3290 .Eijmpcall,
3291 .Spmx,
3292 .Addsubiw,
3293 .Mul,
3294 .Lpmx,
3295 .Des,
3296 .Ijmpcall,
3297 .Break,
3298 .Xmega,
3299 }),
3300 CpuInfo(@This(), FeatureType).create(.Atxmega32e5, "atxmega32e5", &[_]FeatureType {
3301 .Lpm,
3302 .Elpm,
3303 .Movw,
3304 .Elpmx,
3305 .Spm,
3306 .Avr0,
3307 .Sram,
3308 .Jmpcall,
3309 .Eijmpcall,
3310 .Spmx,
3311 .Addsubiw,
3312 .Mul,
3313 .Lpmx,
3314 .Des,
3315 .Ijmpcall,
3316 .Break,
3317 .Xmega,
3318 }),
3319 CpuInfo(@This(), FeatureType).create(.Atxmega32x1, "atxmega32x1", &[_]FeatureType {
3320 .Lpm,
3321 .Elpm,
3322 .Movw,
3323 .Elpmx,
3324 .Spm,
3325 .Avr0,
3326 .Sram,
3327 .Jmpcall,
3328 .Eijmpcall,
3329 .Spmx,
3330 .Addsubiw,
3331 .Mul,
3332 .Lpmx,
3333 .Des,
3334 .Ijmpcall,
3335 .Break,
3336 .Xmega,
3337 }),
3338 CpuInfo(@This(), FeatureType).create(.Atxmega384c3, "atxmega384c3", &[_]FeatureType {
3339 .Lpm,
3340 .Elpm,
3341 .Movw,
3342 .Elpmx,
3343 .Spm,
3344 .Avr0,
3345 .Sram,
3346 .Jmpcall,
3347 .Eijmpcall,
3348 .Spmx,
3349 .Addsubiw,
3350 .Mul,
3351 .Lpmx,
3352 .Rmw,
3353 .Des,
3354 .Ijmpcall,
3355 .Break,
3356 .Xmegau,
3357 }),
3358 CpuInfo(@This(), FeatureType).create(.Atxmega384d3, "atxmega384d3", &[_]FeatureType {
3359 .Lpm,
3360 .Elpm,
3361 .Movw,
3362 .Elpmx,
3363 .Spm,
3364 .Avr0,
3365 .Sram,
3366 .Jmpcall,
3367 .Eijmpcall,
3368 .Spmx,
3369 .Addsubiw,
3370 .Mul,
3371 .Lpmx,
3372 .Des,
3373 .Ijmpcall,
3374 .Break,
3375 .Xmega,
3376 }),
3377 CpuInfo(@This(), FeatureType).create(.Atxmega64a1, "atxmega64a1", &[_]FeatureType {
3378 .Lpm,
3379 .Elpm,
3380 .Movw,
3381 .Elpmx,
3382 .Spm,
3383 .Avr0,
3384 .Sram,
3385 .Jmpcall,
3386 .Eijmpcall,
3387 .Spmx,
3388 .Addsubiw,
3389 .Mul,
3390 .Lpmx,
3391 .Des,
3392 .Ijmpcall,
3393 .Break,
3394 .Xmega,
3395 }),
3396 CpuInfo(@This(), FeatureType).create(.Atxmega64a1u, "atxmega64a1u", &[_]FeatureType {
3397 .Lpm,
3398 .Elpm,
3399 .Movw,
3400 .Elpmx,
3401 .Spm,
3402 .Avr0,
3403 .Sram,
3404 .Jmpcall,
3405 .Eijmpcall,
3406 .Spmx,
3407 .Addsubiw,
3408 .Mul,
3409 .Lpmx,
3410 .Rmw,
3411 .Des,
3412 .Ijmpcall,
3413 .Break,
3414 .Xmegau,
3415 }),
3416 CpuInfo(@This(), FeatureType).create(.Atxmega64a3, "atxmega64a3", &[_]FeatureType {
3417 .Lpm,
3418 .Elpm,
3419 .Movw,
3420 .Elpmx,
3421 .Spm,
3422 .Avr0,
3423 .Sram,
3424 .Jmpcall,
3425 .Eijmpcall,
3426 .Spmx,
3427 .Addsubiw,
3428 .Mul,
3429 .Lpmx,
3430 .Des,
3431 .Ijmpcall,
3432 .Break,
3433 .Xmega,
3434 }),
3435 CpuInfo(@This(), FeatureType).create(.Atxmega64a3u, "atxmega64a3u", &[_]FeatureType {
3436 .Lpm,
3437 .Elpm,
3438 .Movw,
3439 .Elpmx,
3440 .Spm,
3441 .Avr0,
3442 .Sram,
3443 .Jmpcall,
3444 .Eijmpcall,
3445 .Spmx,
3446 .Addsubiw,
3447 .Mul,
3448 .Lpmx,
3449 .Rmw,
3450 .Des,
3451 .Ijmpcall,
3452 .Break,
3453 .Xmegau,
3454 }),
3455 CpuInfo(@This(), FeatureType).create(.Atxmega64a4u, "atxmega64a4u", &[_]FeatureType {
3456 .Lpm,
3457 .Elpm,
3458 .Movw,
3459 .Elpmx,
3460 .Spm,
3461 .Avr0,
3462 .Sram,
3463 .Jmpcall,
3464 .Eijmpcall,
3465 .Spmx,
3466 .Addsubiw,
3467 .Mul,
3468 .Lpmx,
3469 .Rmw,
3470 .Des,
3471 .Ijmpcall,
3472 .Break,
3473 .Xmegau,
3474 }),
3475 CpuInfo(@This(), FeatureType).create(.Atxmega64b1, "atxmega64b1", &[_]FeatureType {
3476 .Lpm,
3477 .Elpm,
3478 .Movw,
3479 .Elpmx,
3480 .Spm,
3481 .Avr0,
3482 .Sram,
3483 .Jmpcall,
3484 .Eijmpcall,
3485 .Spmx,
3486 .Addsubiw,
3487 .Mul,
3488 .Lpmx,
3489 .Rmw,
3490 .Des,
3491 .Ijmpcall,
3492 .Break,
3493 .Xmegau,
3494 }),
3495 CpuInfo(@This(), FeatureType).create(.Atxmega64b3, "atxmega64b3", &[_]FeatureType {
3496 .Lpm,
3497 .Elpm,
3498 .Movw,
3499 .Elpmx,
3500 .Spm,
3501 .Avr0,
3502 .Sram,
3503 .Jmpcall,
3504 .Eijmpcall,
3505 .Spmx,
3506 .Addsubiw,
3507 .Mul,
3508 .Lpmx,
3509 .Rmw,
3510 .Des,
3511 .Ijmpcall,
3512 .Break,
3513 .Xmegau,
3514 }),
3515 CpuInfo(@This(), FeatureType).create(.Atxmega64c3, "atxmega64c3", &[_]FeatureType {
3516 .Lpm,
3517 .Elpm,
3518 .Movw,
3519 .Elpmx,
3520 .Spm,
3521 .Avr0,
3522 .Sram,
3523 .Jmpcall,
3524 .Eijmpcall,
3525 .Spmx,
3526 .Addsubiw,
3527 .Mul,
3528 .Lpmx,
3529 .Rmw,
3530 .Des,
3531 .Ijmpcall,
3532 .Break,
3533 .Xmegau,
3534 }),
3535 CpuInfo(@This(), FeatureType).create(.Atxmega64d3, "atxmega64d3", &[_]FeatureType {
3536 .Lpm,
3537 .Elpm,
3538 .Movw,
3539 .Elpmx,
3540 .Spm,
3541 .Avr0,
3542 .Sram,
3543 .Jmpcall,
3544 .Eijmpcall,
3545 .Spmx,
3546 .Addsubiw,
3547 .Mul,
3548 .Lpmx,
3549 .Des,
3550 .Ijmpcall,
3551 .Break,
3552 .Xmega,
3553 }),
3554 CpuInfo(@This(), FeatureType).create(.Atxmega64d4, "atxmega64d4", &[_]FeatureType {
3555 .Lpm,
3556 .Elpm,
3557 .Movw,
3558 .Elpmx,
3559 .Spm,
3560 .Avr0,
3561 .Sram,
3562 .Jmpcall,
3563 .Eijmpcall,
3564 .Spmx,
3565 .Addsubiw,
3566 .Mul,
3567 .Lpmx,
3568 .Des,
3569 .Ijmpcall,
3570 .Break,
3571 .Xmega,
3572 }),
3573 CpuInfo(@This(), FeatureType).create(.Atxmega8e5, "atxmega8e5", &[_]FeatureType {
3574 .Lpm,
3575 .Elpm,
3576 .Movw,
3577 .Elpmx,
3578 .Spm,
3579 .Avr0,
3580 .Sram,
3581 .Jmpcall,
3582 .Eijmpcall,
3583 .Spmx,
3584 .Addsubiw,
3585 .Mul,
3586 .Lpmx,
3587 .Des,
3588 .Ijmpcall,
3589 .Break,
3590 .Xmega,
3591 }),
3592 CpuInfo(@This(), FeatureType).create(.Avr1, "avr1", &[_]FeatureType {
3593 .Avr0,
3594 .Lpm,
3595 .Avr1,
3596 }),
3597 CpuInfo(@This(), FeatureType).create(.Avr2, "avr2", &[_]FeatureType {
3598 .Lpm,
3599 .Avr0,
3600 .Sram,
3601 .Addsubiw,
3602 .Ijmpcall,
3603 .Avr2,
3604 }),
3605 CpuInfo(@This(), FeatureType).create(.Avr25, "avr25", &[_]FeatureType {
3606 .Lpm,
3607 .Movw,
3608 .Spm,
3609 .Avr0,
3610 .Sram,
3611 .Addsubiw,
3612 .Lpmx,
3613 .Ijmpcall,
3614 .Break,
3615 .Avr25,
3616 }),
3617 CpuInfo(@This(), FeatureType).create(.Avr3, "avr3", &[_]FeatureType {
3618 .Lpm,
3619 .Avr0,
3620 .Sram,
3621 .Jmpcall,
3622 .Addsubiw,
3623 .Ijmpcall,
3624 .Avr3,
3625 }),
3626 CpuInfo(@This(), FeatureType).create(.Avr31, "avr31", &[_]FeatureType {
3627 .Lpm,
3628 .Elpm,
3629 .Avr0,
3630 .Sram,
3631 .Jmpcall,
3632 .Addsubiw,
3633 .Ijmpcall,
3634 .Avr31,
3635 }),
3636 CpuInfo(@This(), FeatureType).create(.Avr35, "avr35", &[_]FeatureType {
3637 .Lpm,
3638 .Movw,
3639 .Spm,
3640 .Avr0,
3641 .Sram,
3642 .Jmpcall,
3643 .Addsubiw,
3644 .Lpmx,
3645 .Ijmpcall,
3646 .Break,
3647 .Avr35,
3648 }),
3649 CpuInfo(@This(), FeatureType).create(.Avr4, "avr4", &[_]FeatureType {
3650 .Lpm,
3651 .Movw,
3652 .Spm,
3653 .Avr0,
3654 .Sram,
3655 .Addsubiw,
3656 .Mul,
3657 .Lpmx,
3658 .Ijmpcall,
3659 .Break,
3660 .Avr4,
3661 }),
3662 CpuInfo(@This(), FeatureType).create(.Avr5, "avr5", &[_]FeatureType {
3663 .Lpm,
3664 .Movw,
3665 .Spm,
3666 .Avr0,
3667 .Sram,
3668 .Jmpcall,
3669 .Addsubiw,
3670 .Mul,
3671 .Lpmx,
3672 .Ijmpcall,
3673 .Break,
3674 .Avr5,
3675 }),
3676 CpuInfo(@This(), FeatureType).create(.Avr51, "avr51", &[_]FeatureType {
3677 .Lpm,
3678 .Elpm,
3679 .Movw,
3680 .Elpmx,
3681 .Spm,
3682 .Avr0,
3683 .Sram,
3684 .Jmpcall,
3685 .Addsubiw,
3686 .Mul,
3687 .Lpmx,
3688 .Ijmpcall,
3689 .Break,
3690 .Avr51,
3691 }),
3692 CpuInfo(@This(), FeatureType).create(.Avr6, "avr6", &[_]FeatureType {
3693 .Lpm,
3694 .Elpm,
3695 .Movw,
3696 .Elpmx,
3697 .Spm,
3698 .Avr0,
3699 .Sram,
3700 .Jmpcall,
3701 .Addsubiw,
3702 .Mul,
3703 .Lpmx,
3704 .Ijmpcall,
3705 .Break,
3706 .Avr6,
3707 }),
3708 CpuInfo(@This(), FeatureType).create(.Avrtiny, "avrtiny", &[_]FeatureType {
3709 .Avr0,
3710 .Sram,
3711 .Break,
3712 .Tinyencoding,
3713 .Avrtiny,
3714 }),
3715 CpuInfo(@This(), FeatureType).create(.Avrxmega1, "avrxmega1", &[_]FeatureType {
3716 .Lpm,
3717 .Elpm,
3718 .Movw,
3719 .Elpmx,
3720 .Spm,
3721 .Avr0,
3722 .Sram,
3723 .Jmpcall,
3724 .Eijmpcall,
3725 .Spmx,
3726 .Addsubiw,
3727 .Mul,
3728 .Lpmx,
3729 .Des,
3730 .Ijmpcall,
3731 .Break,
3732 .Xmega,
3733 }),
3734 CpuInfo(@This(), FeatureType).create(.Avrxmega2, "avrxmega2", &[_]FeatureType {
3735 .Lpm,
3736 .Elpm,
3737 .Movw,
3738 .Elpmx,
3739 .Spm,
3740 .Avr0,
3741 .Sram,
3742 .Jmpcall,
3743 .Eijmpcall,
3744 .Spmx,
3745 .Addsubiw,
3746 .Mul,
3747 .Lpmx,
3748 .Des,
3749 .Ijmpcall,
3750 .Break,
3751 .Xmega,
3752 }),
3753 CpuInfo(@This(), FeatureType).create(.Avrxmega3, "avrxmega3", &[_]FeatureType {
3754 .Lpm,
3755 .Elpm,
3756 .Movw,
3757 .Elpmx,
3758 .Spm,
3759 .Avr0,
3760 .Sram,
3761 .Jmpcall,
3762 .Eijmpcall,
3763 .Spmx,
3764 .Addsubiw,
3765 .Mul,
3766 .Lpmx,
3767 .Des,
3768 .Ijmpcall,
3769 .Break,
3770 .Xmega,
3771 }),
3772 CpuInfo(@This(), FeatureType).create(.Avrxmega4, "avrxmega4", &[_]FeatureType {
3773 .Lpm,
3774 .Elpm,
3775 .Movw,
3776 .Elpmx,
3777 .Spm,
3778 .Avr0,
3779 .Sram,
3780 .Jmpcall,
3781 .Eijmpcall,
3782 .Spmx,
3783 .Addsubiw,
3784 .Mul,
3785 .Lpmx,
3786 .Des,
3787 .Ijmpcall,
3788 .Break,
3789 .Xmega,
3790 }),
3791 CpuInfo(@This(), FeatureType).create(.Avrxmega5, "avrxmega5", &[_]FeatureType {
3792 .Lpm,
3793 .Elpm,
3794 .Movw,
3795 .Elpmx,
3796 .Spm,
3797 .Avr0,
3798 .Sram,
3799 .Jmpcall,
3800 .Eijmpcall,
3801 .Spmx,
3802 .Addsubiw,
3803 .Mul,
3804 .Lpmx,
3805 .Des,
3806 .Ijmpcall,
3807 .Break,
3808 .Xmega,
3809 }),
3810 CpuInfo(@This(), FeatureType).create(.Avrxmega6, "avrxmega6", &[_]FeatureType {
3811 .Lpm,
3812 .Elpm,
3813 .Movw,
3814 .Elpmx,
3815 .Spm,
3816 .Avr0,
3817 .Sram,
3818 .Jmpcall,
3819 .Eijmpcall,
3820 .Spmx,
3821 .Addsubiw,
3822 .Mul,
3823 .Lpmx,
3824 .Des,
3825 .Ijmpcall,
3826 .Break,
3827 .Xmega,
3828 }),
3829 CpuInfo(@This(), FeatureType).create(.Avrxmega7, "avrxmega7", &[_]FeatureType {
3830 .Lpm,
3831 .Elpm,
3832 .Movw,
3833 .Elpmx,
3834 .Spm,
3835 .Avr0,
3836 .Sram,
3837 .Jmpcall,
3838 .Eijmpcall,
3839 .Spmx,
3840 .Addsubiw,
3841 .Mul,
3842 .Lpmx,
3843 .Des,
3844 .Ijmpcall,
3845 .Break,
3846 .Xmega,
3847 }),
3848 CpuInfo(@This(), FeatureType).create(.M3000, "m3000", &[_]FeatureType {
3849 .Lpm,
3850 .Movw,
3851 .Spm,
3852 .Avr0,
3853 .Sram,
3854 .Jmpcall,
3855 .Addsubiw,
3856 .Mul,
3857 .Lpmx,
3858 .Ijmpcall,
3859 .Break,
3860 .Avr5,
3861 }),
3862 };
3863};
lib/std/target/cpu/BpfCpu.zig deleted-29
......@@ -1,29 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const BpfCpu = enum {
5 Generic,
6 Probe,
7 V1,
8 V2,
9 V3,
10
11 const FeatureType = feature.BpfFeature;
12
13 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
14 return cpu_infos[@enumToInt(self)];
15 }
16
17 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
18 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
19 }),
20 CpuInfo(@This(), FeatureType).create(.Probe, "probe", &[_]FeatureType {
21 }),
22 CpuInfo(@This(), FeatureType).create(.V1, "v1", &[_]FeatureType {
23 }),
24 CpuInfo(@This(), FeatureType).create(.V2, "v2", &[_]FeatureType {
25 }),
26 CpuInfo(@This(), FeatureType).create(.V3, "v3", &[_]FeatureType {
27 }),
28 };
29};
lib/std/target/cpu/HexagonCpu.zig deleted-103
......@@ -1,103 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const HexagonCpu = enum {
5 Generic,
6 Hexagonv5,
7 Hexagonv55,
8 Hexagonv60,
9 Hexagonv62,
10 Hexagonv65,
11 Hexagonv66,
12
13 const FeatureType = feature.HexagonFeature;
14
15 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
16 return cpu_infos[@enumToInt(self)];
17 }
18
19 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
20 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
21 .V5,
22 .V55,
23 .V60,
24 .Duplex,
25 .Memops,
26 .Packets,
27 .Nvj,
28 .Nvs,
29 .SmallData,
30 }),
31 CpuInfo(@This(), FeatureType).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
32 .V5,
33 .Duplex,
34 .Memops,
35 .Packets,
36 .Nvj,
37 .Nvs,
38 .SmallData,
39 }),
40 CpuInfo(@This(), FeatureType).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
41 .V5,
42 .V55,
43 .Duplex,
44 .Memops,
45 .Packets,
46 .Nvj,
47 .Nvs,
48 .SmallData,
49 }),
50 CpuInfo(@This(), FeatureType).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
51 .V5,
52 .V55,
53 .V60,
54 .Duplex,
55 .Memops,
56 .Packets,
57 .Nvj,
58 .Nvs,
59 .SmallData,
60 }),
61 CpuInfo(@This(), FeatureType).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
62 .V5,
63 .V55,
64 .V60,
65 .V62,
66 .Duplex,
67 .Memops,
68 .Packets,
69 .Nvj,
70 .Nvs,
71 .SmallData,
72 }),
73 CpuInfo(@This(), FeatureType).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
74 .V5,
75 .V55,
76 .V60,
77 .V62,
78 .V65,
79 .Duplex,
80 .Mem_noshuf,
81 .Memops,
82 .Packets,
83 .Nvj,
84 .Nvs,
85 .SmallData,
86 }),
87 CpuInfo(@This(), FeatureType).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
88 .V5,
89 .V55,
90 .V60,
91 .V62,
92 .V65,
93 .V66,
94 .Duplex,
95 .Mem_noshuf,
96 .Memops,
97 .Packets,
98 .Nvj,
99 .Nvs,
100 .SmallData,
101 }),
102 };
103};
lib/std/target/cpu/MipsCpu.zig deleted-190
......@@ -1,190 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const MipsCpu = enum {
5 Mips1,
6 Mips2,
7 Mips3,
8 Mips32,
9 Mips32r2,
10 Mips32r3,
11 Mips32r5,
12 Mips32r6,
13 Mips4,
14 Mips5,
15 Mips64,
16 Mips64r2,
17 Mips64r3,
18 Mips64r5,
19 Mips64r6,
20 Octeon,
21 P5600,
22
23 const FeatureType = feature.MipsFeature;
24
25 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
26 return cpu_infos[@enumToInt(self)];
27 }
28
29 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
30 CpuInfo(@This(), FeatureType).create(.Mips1, "mips1", &[_]FeatureType {
31 .Mips1,
32 }),
33 CpuInfo(@This(), FeatureType).create(.Mips2, "mips2", &[_]FeatureType {
34 .Mips1,
35 .Mips2,
36 }),
37 CpuInfo(@This(), FeatureType).create(.Mips3, "mips3", &[_]FeatureType {
38 .Mips3_32r2,
39 .Fp64,
40 .Gp64,
41 .Mips1,
42 .Mips3_32,
43 .Mips3,
44 }),
45 CpuInfo(@This(), FeatureType).create(.Mips32, "mips32", &[_]FeatureType {
46 .Mips4_32,
47 .Mips1,
48 .Mips3_32,
49 .Mips32,
50 }),
51 CpuInfo(@This(), FeatureType).create(.Mips32r2, "mips32r2", &[_]FeatureType {
52 .Mips5_32r2,
53 .Mips4_32r2,
54 .Mips3_32r2,
55 .Mips4_32,
56 .Mips1,
57 .Mips3_32,
58 .Mips32r2,
59 }),
60 CpuInfo(@This(), FeatureType).create(.Mips32r3, "mips32r3", &[_]FeatureType {
61 .Mips5_32r2,
62 .Mips3_32r2,
63 .Mips4_32r2,
64 .Mips4_32,
65 .Mips1,
66 .Mips3_32,
67 .Mips32r3,
68 }),
69 CpuInfo(@This(), FeatureType).create(.Mips32r5, "mips32r5", &[_]FeatureType {
70 .Mips5_32r2,
71 .Mips3_32r2,
72 .Mips4_32r2,
73 .Mips4_32,
74 .Mips1,
75 .Mips3_32,
76 .Mips32r5,
77 }),
78 CpuInfo(@This(), FeatureType).create(.Mips32r6, "mips32r6", &[_]FeatureType {
79 .Mips5_32r2,
80 .Mips3_32r2,
81 .Mips4_32r2,
82 .Abs2008,
83 .Nan2008,
84 .Fp64,
85 .Mips4_32,
86 .Mips1,
87 .Mips3_32,
88 .Mips32r6,
89 }),
90 CpuInfo(@This(), FeatureType).create(.Mips4, "mips4", &[_]FeatureType {
91 .Mips3_32r2,
92 .Mips4_32r2,
93 .Fp64,
94 .Gp64,
95 .Mips4_32,
96 .Mips1,
97 .Mips3_32,
98 .Mips4,
99 }),
100 CpuInfo(@This(), FeatureType).create(.Mips5, "mips5", &[_]FeatureType {
101 .Mips5_32r2,
102 .Mips4_32r2,
103 .Mips3_32r2,
104 .Gp64,
105 .Fp64,
106 .Mips4_32,
107 .Mips1,
108 .Mips3_32,
109 .Mips5,
110 }),
111 CpuInfo(@This(), FeatureType).create(.Mips64, "mips64", &[_]FeatureType {
112 .Mips5_32r2,
113 .Mips3_32r2,
114 .Mips4_32r2,
115 .Gp64,
116 .Fp64,
117 .Mips4_32,
118 .Mips1,
119 .Mips3_32,
120 .Mips64,
121 }),
122 CpuInfo(@This(), FeatureType).create(.Mips64r2, "mips64r2", &[_]FeatureType {
123 .Mips5_32r2,
124 .Mips3_32r2,
125 .Mips4_32r2,
126 .Gp64,
127 .Fp64,
128 .Mips4_32,
129 .Mips1,
130 .Mips3_32,
131 .Mips64r2,
132 }),
133 CpuInfo(@This(), FeatureType).create(.Mips64r3, "mips64r3", &[_]FeatureType {
134 .Mips5_32r2,
135 .Mips3_32r2,
136 .Mips4_32r2,
137 .Gp64,
138 .Fp64,
139 .Mips4_32,
140 .Mips1,
141 .Mips3_32,
142 .Mips64r3,
143 }),
144 CpuInfo(@This(), FeatureType).create(.Mips64r5, "mips64r5", &[_]FeatureType {
145 .Mips5_32r2,
146 .Mips3_32r2,
147 .Mips4_32r2,
148 .Gp64,
149 .Fp64,
150 .Mips4_32,
151 .Mips1,
152 .Mips3_32,
153 .Mips64r5,
154 }),
155 CpuInfo(@This(), FeatureType).create(.Mips64r6, "mips64r6", &[_]FeatureType {
156 .Mips5_32r2,
157 .Mips3_32r2,
158 .Nan2008,
159 .Abs2008,
160 .Mips4_32r2,
161 .Fp64,
162 .Gp64,
163 .Mips4_32,
164 .Mips1,
165 .Mips3_32,
166 .Mips64r6,
167 }),
168 CpuInfo(@This(), FeatureType).create(.Octeon, "octeon", &[_]FeatureType {
169 .Mips5_32r2,
170 .Mips3_32r2,
171 .Mips4_32r2,
172 .Gp64,
173 .Fp64,
174 .Mips4_32,
175 .Mips1,
176 .Mips3_32,
177 .Cnmips,
178 .Mips64r2,
179 }),
180 CpuInfo(@This(), FeatureType).create(.P5600, "p5600", &[_]FeatureType {
181 .Mips5_32r2,
182 .Mips3_32r2,
183 .Mips4_32r2,
184 .Mips4_32,
185 .Mips1,
186 .Mips3_32,
187 .P5600,
188 }),
189 };
190};
lib/std/target/cpu/Msp430Cpu.zig deleted-24
......@@ -1,24 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const Msp430Cpu = enum {
5 Generic,
6 Msp430,
7 Msp430x,
8
9 const FeatureType = feature.Msp430Feature;
10
11 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
12 return cpu_infos[@enumToInt(self)];
13 }
14
15 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
16 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
17 }),
18 CpuInfo(@This(), FeatureType).create(.Msp430, "msp430", &[_]FeatureType {
19 }),
20 CpuInfo(@This(), FeatureType).create(.Msp430x, "msp430x", &[_]FeatureType {
21 .Ext,
22 }),
23 };
24};
lib/std/target/cpu/NvptxCpu.zig deleted-85
......@@ -1,85 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const NvptxCpu = enum {
5 Sm_20,
6 Sm_21,
7 Sm_30,
8 Sm_32,
9 Sm_35,
10 Sm_37,
11 Sm_50,
12 Sm_52,
13 Sm_53,
14 Sm_60,
15 Sm_61,
16 Sm_62,
17 Sm_70,
18 Sm_72,
19 Sm_75,
20
21 const FeatureType = feature.NvptxFeature;
22
23 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
24 return cpu_infos[@enumToInt(self)];
25 }
26
27 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
28 CpuInfo(@This(), FeatureType).create(.Sm_20, "sm_20", &[_]FeatureType {
29 .Sm_20,
30 }),
31 CpuInfo(@This(), FeatureType).create(.Sm_21, "sm_21", &[_]FeatureType {
32 .Sm_21,
33 }),
34 CpuInfo(@This(), FeatureType).create(.Sm_30, "sm_30", &[_]FeatureType {
35 .Sm_30,
36 }),
37 CpuInfo(@This(), FeatureType).create(.Sm_32, "sm_32", &[_]FeatureType {
38 .Ptx40,
39 .Sm_32,
40 }),
41 CpuInfo(@This(), FeatureType).create(.Sm_35, "sm_35", &[_]FeatureType {
42 .Sm_35,
43 }),
44 CpuInfo(@This(), FeatureType).create(.Sm_37, "sm_37", &[_]FeatureType {
45 .Ptx41,
46 .Sm_37,
47 }),
48 CpuInfo(@This(), FeatureType).create(.Sm_50, "sm_50", &[_]FeatureType {
49 .Ptx40,
50 .Sm_50,
51 }),
52 CpuInfo(@This(), FeatureType).create(.Sm_52, "sm_52", &[_]FeatureType {
53 .Ptx41,
54 .Sm_52,
55 }),
56 CpuInfo(@This(), FeatureType).create(.Sm_53, "sm_53", &[_]FeatureType {
57 .Ptx42,
58 .Sm_53,
59 }),
60 CpuInfo(@This(), FeatureType).create(.Sm_60, "sm_60", &[_]FeatureType {
61 .Ptx50,
62 .Sm_60,
63 }),
64 CpuInfo(@This(), FeatureType).create(.Sm_61, "sm_61", &[_]FeatureType {
65 .Ptx50,
66 .Sm_61,
67 }),
68 CpuInfo(@This(), FeatureType).create(.Sm_62, "sm_62", &[_]FeatureType {
69 .Ptx50,
70 .Sm_62,
71 }),
72 CpuInfo(@This(), FeatureType).create(.Sm_70, "sm_70", &[_]FeatureType {
73 .Ptx60,
74 .Sm_70,
75 }),
76 CpuInfo(@This(), FeatureType).create(.Sm_72, "sm_72", &[_]FeatureType {
77 .Ptx61,
78 .Sm_72,
79 }),
80 CpuInfo(@This(), FeatureType).create(.Sm_75, "sm_75", &[_]FeatureType {
81 .Ptx63,
82 .Sm_75,
83 }),
84 };
85};
lib/std/target/cpu/PowerPcCpu.zig deleted-451
......@@ -1,451 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const PowerPcCpu = enum {
5 Cpu440,
6 Cpu450,
7 Cpu601,
8 Cpu602,
9 Cpu603,
10 E603,
11 Ev603,
12 Cpu604,
13 E604,
14 Cpu620,
15 Cpu7400,
16 Cpu7450,
17 Cpu750,
18 Cpu970,
19 A2,
20 A2q,
21 E500,
22 E500mc,
23 E5500,
24 G3,
25 G4,
26 G4plus,
27 G5,
28 Generic,
29 Ppc,
30 Ppc32,
31 Ppc64,
32 Ppc64le,
33 Pwr3,
34 Pwr4,
35 Pwr5,
36 Pwr5x,
37 Pwr6,
38 Pwr6x,
39 Pwr7,
40 Pwr8,
41 Pwr9,
42
43 const FeatureType = feature.PowerPcFeature;
44
45 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
46 return cpu_infos[@enumToInt(self)];
47 }
48
49 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
50 CpuInfo(@This(), FeatureType).create(.Cpu440, "440", &[_]FeatureType {
51 .Icbt,
52 .Booke,
53 .HardFloat,
54 .Fres,
55 .Frsqrte,
56 .Isel,
57 .Msync,
58 }),
59 CpuInfo(@This(), FeatureType).create(.Cpu450, "450", &[_]FeatureType {
60 .Icbt,
61 .Booke,
62 .HardFloat,
63 .Fres,
64 .Frsqrte,
65 .Isel,
66 .Msync,
67 }),
68 CpuInfo(@This(), FeatureType).create(.Cpu601, "601", &[_]FeatureType {
69 .HardFloat,
70 .Fpu,
71 }),
72 CpuInfo(@This(), FeatureType).create(.Cpu602, "602", &[_]FeatureType {
73 .HardFloat,
74 .Fpu,
75 }),
76 CpuInfo(@This(), FeatureType).create(.Cpu603, "603", &[_]FeatureType {
77 .HardFloat,
78 .Fres,
79 .Frsqrte,
80 }),
81 CpuInfo(@This(), FeatureType).create(.E603, "603e", &[_]FeatureType {
82 .HardFloat,
83 .Fres,
84 .Frsqrte,
85 }),
86 CpuInfo(@This(), FeatureType).create(.Ev603, "603ev", &[_]FeatureType {
87 .HardFloat,
88 .Fres,
89 .Frsqrte,
90 }),
91 CpuInfo(@This(), FeatureType).create(.Cpu604, "604", &[_]FeatureType {
92 .HardFloat,
93 .Fres,
94 .Frsqrte,
95 }),
96 CpuInfo(@This(), FeatureType).create(.E604, "604e", &[_]FeatureType {
97 .HardFloat,
98 .Fres,
99 .Frsqrte,
100 }),
101 CpuInfo(@This(), FeatureType).create(.Cpu620, "620", &[_]FeatureType {
102 .HardFloat,
103 .Fres,
104 .Frsqrte,
105 }),
106 CpuInfo(@This(), FeatureType).create(.Cpu7400, "7400", &[_]FeatureType {
107 .HardFloat,
108 .Altivec,
109 .Fres,
110 .Frsqrte,
111 }),
112 CpuInfo(@This(), FeatureType).create(.Cpu7450, "7450", &[_]FeatureType {
113 .HardFloat,
114 .Altivec,
115 .Fres,
116 .Frsqrte,
117 }),
118 CpuInfo(@This(), FeatureType).create(.Cpu750, "750", &[_]FeatureType {
119 .HardFloat,
120 .Fres,
121 .Frsqrte,
122 }),
123 CpuInfo(@This(), FeatureType).create(.Cpu970, "970", &[_]FeatureType {
124 .Bit64,
125 .HardFloat,
126 .Altivec,
127 .Fres,
128 .Frsqrte,
129 .Fsqrt,
130 .Mfocrf,
131 .Stfiwx,
132 }),
133 CpuInfo(@This(), FeatureType).create(.A2, "a2", &[_]FeatureType {
134 .Bit64,
135 .Icbt,
136 .Booke,
137 .Cmpb,
138 .HardFloat,
139 .Fcpsgn,
140 .Fpcvt,
141 .Fprnd,
142 .Fre,
143 .Fres,
144 .Frsqrte,
145 .Frsqrtes,
146 .Fsqrt,
147 .Isel,
148 .Ldbrx,
149 .Lfiwax,
150 .Mfocrf,
151 .Recipprec,
152 .Stfiwx,
153 .SlowPopcntd,
154 }),
155 CpuInfo(@This(), FeatureType).create(.A2q, "a2q", &[_]FeatureType {
156 .Bit64,
157 .Icbt,
158 .Booke,
159 .Cmpb,
160 .HardFloat,
161 .Fcpsgn,
162 .Fpcvt,
163 .Fprnd,
164 .Fre,
165 .Fres,
166 .Frsqrte,
167 .Frsqrtes,
168 .Fsqrt,
169 .Isel,
170 .Ldbrx,
171 .Lfiwax,
172 .Mfocrf,
173 .Qpx,
174 .Recipprec,
175 .Stfiwx,
176 .SlowPopcntd,
177 }),
178 CpuInfo(@This(), FeatureType).create(.E500, "e500", &[_]FeatureType {
179 .Icbt,
180 .Booke,
181 .Isel,
182 }),
183 CpuInfo(@This(), FeatureType).create(.E500mc, "e500mc", &[_]FeatureType {
184 .Icbt,
185 .Booke,
186 .Isel,
187 .HardFloat,
188 .Stfiwx,
189 }),
190 CpuInfo(@This(), FeatureType).create(.E5500, "e5500", &[_]FeatureType {
191 .Bit64,
192 .Icbt,
193 .Booke,
194 .Isel,
195 .Mfocrf,
196 .HardFloat,
197 .Stfiwx,
198 }),
199 CpuInfo(@This(), FeatureType).create(.G3, "g3", &[_]FeatureType {
200 .HardFloat,
201 .Fres,
202 .Frsqrte,
203 }),
204 CpuInfo(@This(), FeatureType).create(.G4, "g4", &[_]FeatureType {
205 .HardFloat,
206 .Altivec,
207 .Fres,
208 .Frsqrte,
209 }),
210 CpuInfo(@This(), FeatureType).create(.G4plus, "g4+", &[_]FeatureType {
211 .HardFloat,
212 .Altivec,
213 .Fres,
214 .Frsqrte,
215 }),
216 CpuInfo(@This(), FeatureType).create(.G5, "g5", &[_]FeatureType {
217 .Bit64,
218 .HardFloat,
219 .Altivec,
220 .Fres,
221 .Frsqrte,
222 .Fsqrt,
223 .Mfocrf,
224 .Stfiwx,
225 }),
226 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
227 .HardFloat,
228 }),
229 CpuInfo(@This(), FeatureType).create(.Ppc, "ppc", &[_]FeatureType {
230 .HardFloat,
231 }),
232 CpuInfo(@This(), FeatureType).create(.Ppc32, "ppc32", &[_]FeatureType {
233 .HardFloat,
234 }),
235 CpuInfo(@This(), FeatureType).create(.Ppc64, "ppc64", &[_]FeatureType {
236 .Bit64,
237 .HardFloat,
238 .Altivec,
239 .Fres,
240 .Frsqrte,
241 .Fsqrt,
242 .Mfocrf,
243 .Stfiwx,
244 }),
245 CpuInfo(@This(), FeatureType).create(.Ppc64le, "ppc64le", &[_]FeatureType {
246 .Bit64,
247 .HardFloat,
248 .Altivec,
249 .Bpermd,
250 .Cmpb,
251 .DirectMove,
252 .Extdiv,
253 .Fcpsgn,
254 .Fpcvt,
255 .Fprnd,
256 .Fre,
257 .Fres,
258 .Frsqrte,
259 .Frsqrtes,
260 .Fsqrt,
261 .Htm,
262 .Icbt,
263 .Isel,
264 .Ldbrx,
265 .Lfiwax,
266 .Mfocrf,
267 .Power8Altivec,
268 .Crypto,
269 .Power8Vector,
270 .Popcntd,
271 .PartwordAtomics,
272 .Recipprec,
273 .Stfiwx,
274 .TwoConstNr,
275 .Vsx,
276 }),
277 CpuInfo(@This(), FeatureType).create(.Pwr3, "pwr3", &[_]FeatureType {
278 .Bit64,
279 .HardFloat,
280 .Altivec,
281 .Fres,
282 .Frsqrte,
283 .Mfocrf,
284 .Stfiwx,
285 }),
286 CpuInfo(@This(), FeatureType).create(.Pwr4, "pwr4", &[_]FeatureType {
287 .Bit64,
288 .HardFloat,
289 .Altivec,
290 .Fres,
291 .Frsqrte,
292 .Fsqrt,
293 .Mfocrf,
294 .Stfiwx,
295 }),
296 CpuInfo(@This(), FeatureType).create(.Pwr5, "pwr5", &[_]FeatureType {
297 .Bit64,
298 .HardFloat,
299 .Altivec,
300 .Fre,
301 .Fres,
302 .Frsqrte,
303 .Frsqrtes,
304 .Fsqrt,
305 .Mfocrf,
306 .Stfiwx,
307 }),
308 CpuInfo(@This(), FeatureType).create(.Pwr5x, "pwr5x", &[_]FeatureType {
309 .Bit64,
310 .HardFloat,
311 .Altivec,
312 .Fprnd,
313 .Fre,
314 .Fres,
315 .Frsqrte,
316 .Frsqrtes,
317 .Fsqrt,
318 .Mfocrf,
319 .Stfiwx,
320 }),
321 CpuInfo(@This(), FeatureType).create(.Pwr6, "pwr6", &[_]FeatureType {
322 .Bit64,
323 .HardFloat,
324 .Altivec,
325 .Cmpb,
326 .Fcpsgn,
327 .Fprnd,
328 .Fre,
329 .Fres,
330 .Frsqrte,
331 .Frsqrtes,
332 .Fsqrt,
333 .Lfiwax,
334 .Mfocrf,
335 .Recipprec,
336 .Stfiwx,
337 }),
338 CpuInfo(@This(), FeatureType).create(.Pwr6x, "pwr6x", &[_]FeatureType {
339 .Bit64,
340 .HardFloat,
341 .Altivec,
342 .Cmpb,
343 .Fcpsgn,
344 .Fprnd,
345 .Fre,
346 .Fres,
347 .Frsqrte,
348 .Frsqrtes,
349 .Fsqrt,
350 .Lfiwax,
351 .Mfocrf,
352 .Recipprec,
353 .Stfiwx,
354 }),
355 CpuInfo(@This(), FeatureType).create(.Pwr7, "pwr7", &[_]FeatureType {
356 .Bit64,
357 .HardFloat,
358 .Altivec,
359 .Bpermd,
360 .Cmpb,
361 .Extdiv,
362 .Fcpsgn,
363 .Fpcvt,
364 .Fprnd,
365 .Fre,
366 .Fres,
367 .Frsqrte,
368 .Frsqrtes,
369 .Fsqrt,
370 .Isel,
371 .Ldbrx,
372 .Lfiwax,
373 .Mfocrf,
374 .Popcntd,
375 .Recipprec,
376 .Stfiwx,
377 .TwoConstNr,
378 .Vsx,
379 }),
380 CpuInfo(@This(), FeatureType).create(.Pwr8, "pwr8", &[_]FeatureType {
381 .Bit64,
382 .HardFloat,
383 .Altivec,
384 .Bpermd,
385 .Cmpb,
386 .DirectMove,
387 .Extdiv,
388 .Fcpsgn,
389 .Fpcvt,
390 .Fprnd,
391 .Fre,
392 .Fres,
393 .Frsqrte,
394 .Frsqrtes,
395 .Fsqrt,
396 .Htm,
397 .Icbt,
398 .Isel,
399 .Ldbrx,
400 .Lfiwax,
401 .Mfocrf,
402 .Power8Altivec,
403 .Crypto,
404 .Power8Vector,
405 .Popcntd,
406 .PartwordAtomics,
407 .Recipprec,
408 .Stfiwx,
409 .TwoConstNr,
410 .Vsx,
411 }),
412 CpuInfo(@This(), FeatureType).create(.Pwr9, "pwr9", &[_]FeatureType {
413 .Bit64,
414 .HardFloat,
415 .Altivec,
416 .Bpermd,
417 .Cmpb,
418 .DirectMove,
419 .Extdiv,
420 .Fcpsgn,
421 .Fpcvt,
422 .Fprnd,
423 .Fre,
424 .Fres,
425 .Frsqrte,
426 .Frsqrtes,
427 .Fsqrt,
428 .Htm,
429 .Icbt,
430 .IsaV30Instructions,
431 .Isel,
432 .Ldbrx,
433 .Lfiwax,
434 .Mfocrf,
435 .Power8Altivec,
436 .Crypto,
437 .Power8Vector,
438 .Power9Altivec,
439 .Power9Vector,
440 .Popcntd,
441 .PpcPostraSched,
442 .PpcPreraSched,
443 .PartwordAtomics,
444 .Recipprec,
445 .Stfiwx,
446 .TwoConstNr,
447 .Vsx,
448 .VectorsUseTwoUnits,
449 }),
450 };
451};
lib/std/target/cpu/RiscVCpu.zig deleted-23
......@@ -1,23 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const RiscVCpu = enum {
5 GenericRv32,
6 GenericRv64,
7
8 const FeatureType = feature.RiscVFeature;
9
10 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
11 return cpu_infos[@enumToInt(self)];
12 }
13
14 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
15 CpuInfo(@This(), FeatureType).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
16 .RvcHints,
17 }),
18 CpuInfo(@This(), FeatureType).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
19 .Bit64,
20 .RvcHints,
21 }),
22 };
23};
lib/std/target/cpu/SparcCpu.zig deleted-216
......@@ -1,216 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const SparcCpu = enum {
5 At697e,
6 At697f,
7 F934,
8 Generic,
9 Gr712rc,
10 Gr740,
11 Hypersparc,
12 Leon2,
13 Leon3,
14 Leon4,
15 Ma2080,
16 Ma2085,
17 Ma2100,
18 Ma2150,
19 Ma2155,
20 Ma2450,
21 Ma2455,
22 Ma2480,
23 Ma2485,
24 Ma2x5x,
25 Ma2x8x,
26 Myriad2,
27 Myriad21,
28 Myriad22,
29 Myriad23,
30 Niagara,
31 Niagara2,
32 Niagara3,
33 Niagara4,
34 Sparclet,
35 Sparclite,
36 Sparclite86x,
37 Supersparc,
38 Tsc701,
39 Ultrasparc,
40 Ultrasparc3,
41 Ut699,
42 V7,
43 V8,
44 V9,
45
46 const FeatureType = feature.SparcFeature;
47
48 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
49 return cpu_infos[@enumToInt(self)];
50 }
51
52 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
53 CpuInfo(@This(), FeatureType).create(.At697e, "at697e", &[_]FeatureType {
54 .Leon,
55 .Insertnopload,
56 }),
57 CpuInfo(@This(), FeatureType).create(.At697f, "at697f", &[_]FeatureType {
58 .Leon,
59 .Insertnopload,
60 }),
61 CpuInfo(@This(), FeatureType).create(.F934, "f934", &[_]FeatureType {
62 }),
63 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
64 }),
65 CpuInfo(@This(), FeatureType).create(.Gr712rc, "gr712rc", &[_]FeatureType {
66 .Leon,
67 .Hasleoncasa,
68 }),
69 CpuInfo(@This(), FeatureType).create(.Gr740, "gr740", &[_]FeatureType {
70 .Leon,
71 .Leonpwrpsr,
72 .Hasleoncasa,
73 .Leoncyclecounter,
74 .Hasumacsmac,
75 }),
76 CpuInfo(@This(), FeatureType).create(.Hypersparc, "hypersparc", &[_]FeatureType {
77 }),
78 CpuInfo(@This(), FeatureType).create(.Leon2, "leon2", &[_]FeatureType {
79 .Leon,
80 }),
81 CpuInfo(@This(), FeatureType).create(.Leon3, "leon3", &[_]FeatureType {
82 .Leon,
83 .Hasumacsmac,
84 }),
85 CpuInfo(@This(), FeatureType).create(.Leon4, "leon4", &[_]FeatureType {
86 .Leon,
87 .Hasleoncasa,
88 .Hasumacsmac,
89 }),
90 CpuInfo(@This(), FeatureType).create(.Ma2080, "ma2080", &[_]FeatureType {
91 .Leon,
92 .Hasleoncasa,
93 }),
94 CpuInfo(@This(), FeatureType).create(.Ma2085, "ma2085", &[_]FeatureType {
95 .Leon,
96 .Hasleoncasa,
97 }),
98 CpuInfo(@This(), FeatureType).create(.Ma2100, "ma2100", &[_]FeatureType {
99 .Leon,
100 .Hasleoncasa,
101 }),
102 CpuInfo(@This(), FeatureType).create(.Ma2150, "ma2150", &[_]FeatureType {
103 .Leon,
104 .Hasleoncasa,
105 }),
106 CpuInfo(@This(), FeatureType).create(.Ma2155, "ma2155", &[_]FeatureType {
107 .Leon,
108 .Hasleoncasa,
109 }),
110 CpuInfo(@This(), FeatureType).create(.Ma2450, "ma2450", &[_]FeatureType {
111 .Leon,
112 .Hasleoncasa,
113 }),
114 CpuInfo(@This(), FeatureType).create(.Ma2455, "ma2455", &[_]FeatureType {
115 .Leon,
116 .Hasleoncasa,
117 }),
118 CpuInfo(@This(), FeatureType).create(.Ma2480, "ma2480", &[_]FeatureType {
119 .Leon,
120 .Hasleoncasa,
121 }),
122 CpuInfo(@This(), FeatureType).create(.Ma2485, "ma2485", &[_]FeatureType {
123 .Leon,
124 .Hasleoncasa,
125 }),
126 CpuInfo(@This(), FeatureType).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
127 .Leon,
128 .Hasleoncasa,
129 }),
130 CpuInfo(@This(), FeatureType).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
131 .Leon,
132 .Hasleoncasa,
133 }),
134 CpuInfo(@This(), FeatureType).create(.Myriad2, "myriad2", &[_]FeatureType {
135 .Leon,
136 .Hasleoncasa,
137 }),
138 CpuInfo(@This(), FeatureType).create(.Myriad21, "myriad2.1", &[_]FeatureType {
139 .Leon,
140 .Hasleoncasa,
141 }),
142 CpuInfo(@This(), FeatureType).create(.Myriad22, "myriad2.2", &[_]FeatureType {
143 .Leon,
144 .Hasleoncasa,
145 }),
146 CpuInfo(@This(), FeatureType).create(.Myriad23, "myriad2.3", &[_]FeatureType {
147 .Leon,
148 .Hasleoncasa,
149 }),
150 CpuInfo(@This(), FeatureType).create(.Niagara, "niagara", &[_]FeatureType {
151 .DeprecatedV8,
152 .V9,
153 .Vis,
154 .Vis2,
155 }),
156 CpuInfo(@This(), FeatureType).create(.Niagara2, "niagara2", &[_]FeatureType {
157 .DeprecatedV8,
158 .V9,
159 .Vis,
160 .Vis2,
161 .Popc,
162 }),
163 CpuInfo(@This(), FeatureType).create(.Niagara3, "niagara3", &[_]FeatureType {
164 .DeprecatedV8,
165 .V9,
166 .Vis,
167 .Vis2,
168 .Popc,
169 }),
170 CpuInfo(@This(), FeatureType).create(.Niagara4, "niagara4", &[_]FeatureType {
171 .DeprecatedV8,
172 .V9,
173 .Vis,
174 .Vis2,
175 .Vis3,
176 .Popc,
177 }),
178 CpuInfo(@This(), FeatureType).create(.Sparclet, "sparclet", &[_]FeatureType {
179 }),
180 CpuInfo(@This(), FeatureType).create(.Sparclite, "sparclite", &[_]FeatureType {
181 }),
182 CpuInfo(@This(), FeatureType).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
183 }),
184 CpuInfo(@This(), FeatureType).create(.Supersparc, "supersparc", &[_]FeatureType {
185 }),
186 CpuInfo(@This(), FeatureType).create(.Tsc701, "tsc701", &[_]FeatureType {
187 }),
188 CpuInfo(@This(), FeatureType).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
189 .DeprecatedV8,
190 .V9,
191 .Vis,
192 }),
193 CpuInfo(@This(), FeatureType).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
194 .DeprecatedV8,
195 .V9,
196 .Vis,
197 .Vis2,
198 }),
199 CpuInfo(@This(), FeatureType).create(.Ut699, "ut699", &[_]FeatureType {
200 .Leon,
201 .NoFmuls,
202 .NoFsmuld,
203 .Fixallfdivsqrt,
204 .Insertnopload,
205 }),
206 CpuInfo(@This(), FeatureType).create(.V7, "v7", &[_]FeatureType {
207 .NoFsmuld,
208 .SoftMulDiv,
209 }),
210 CpuInfo(@This(), FeatureType).create(.V8, "v8", &[_]FeatureType {
211 }),
212 CpuInfo(@This(), FeatureType).create(.V9, "v9", &[_]FeatureType {
213 .V9,
214 }),
215 };
216};
lib/std/target/cpu/SystemZCpu.zig deleted-279
......@@ -1,279 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const SystemZCpu = enum {
5 Arch10,
6 Arch11,
7 Arch12,
8 Arch13,
9 Arch8,
10 Arch9,
11 Generic,
12 Z10,
13 Z13,
14 Z14,
15 Z15,
16 Z196,
17 ZEC12,
18
19 const FeatureType = feature.SystemZFeature;
20
21 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
22 return cpu_infos[@enumToInt(self)];
23 }
24
25 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
26 CpuInfo(@This(), FeatureType).create(.Arch10, "arch10", &[_]FeatureType {
27 .DfpZonedConversion,
28 .DistinctOps,
29 .EnhancedDat2,
30 .ExecutionHint,
31 .FpExtension,
32 .FastSerialization,
33 .HighWord,
34 .InterlockedAccess1,
35 .LoadAndTrap,
36 .LoadStoreOnCond,
37 .MessageSecurityAssistExtension3,
38 .MessageSecurityAssistExtension4,
39 .MiscellaneousExtensions,
40 .PopulationCount,
41 .ProcessorAssist,
42 .ResetReferenceBitsMultiple,
43 .TransactionalExecution,
44 }),
45 CpuInfo(@This(), FeatureType).create(.Arch11, "arch11", &[_]FeatureType {
46 .DfpPackedConversion,
47 .DfpZonedConversion,
48 .DistinctOps,
49 .EnhancedDat2,
50 .ExecutionHint,
51 .FpExtension,
52 .FastSerialization,
53 .HighWord,
54 .InterlockedAccess1,
55 .LoadAndTrap,
56 .LoadAndZeroRightmostByte,
57 .LoadStoreOnCond,
58 .LoadStoreOnCond2,
59 .MessageSecurityAssistExtension3,
60 .MessageSecurityAssistExtension4,
61 .MessageSecurityAssistExtension5,
62 .MiscellaneousExtensions,
63 .PopulationCount,
64 .ProcessorAssist,
65 .ResetReferenceBitsMultiple,
66 .TransactionalExecution,
67 .Vector,
68 }),
69 CpuInfo(@This(), FeatureType).create(.Arch12, "arch12", &[_]FeatureType {
70 .DfpPackedConversion,
71 .DfpZonedConversion,
72 .DistinctOps,
73 .EnhancedDat2,
74 .ExecutionHint,
75 .FpExtension,
76 .FastSerialization,
77 .GuardedStorage,
78 .HighWord,
79 .InsertReferenceBitsMultiple,
80 .InterlockedAccess1,
81 .LoadAndTrap,
82 .LoadAndZeroRightmostByte,
83 .LoadStoreOnCond,
84 .LoadStoreOnCond2,
85 .MessageSecurityAssistExtension3,
86 .MessageSecurityAssistExtension4,
87 .MessageSecurityAssistExtension5,
88 .MessageSecurityAssistExtension7,
89 .MessageSecurityAssistExtension8,
90 .MiscellaneousExtensions,
91 .MiscellaneousExtensions2,
92 .PopulationCount,
93 .ProcessorAssist,
94 .ResetReferenceBitsMultiple,
95 .TransactionalExecution,
96 .Vector,
97 .VectorEnhancements1,
98 .VectorPackedDecimal,
99 }),
100 CpuInfo(@This(), FeatureType).create(.Arch13, "arch13", &[_]FeatureType {
101 .DfpPackedConversion,
102 .DfpZonedConversion,
103 .DeflateConversion,
104 .DistinctOps,
105 .EnhancedDat2,
106 .EnhancedSort,
107 .ExecutionHint,
108 .FpExtension,
109 .FastSerialization,
110 .GuardedStorage,
111 .HighWord,
112 .InsertReferenceBitsMultiple,
113 .InterlockedAccess1,
114 .LoadAndTrap,
115 .LoadAndZeroRightmostByte,
116 .LoadStoreOnCond,
117 .LoadStoreOnCond2,
118 .MessageSecurityAssistExtension3,
119 .MessageSecurityAssistExtension4,
120 .MessageSecurityAssistExtension5,
121 .MessageSecurityAssistExtension7,
122 .MessageSecurityAssistExtension8,
123 .MessageSecurityAssistExtension9,
124 .MiscellaneousExtensions,
125 .MiscellaneousExtensions2,
126 .MiscellaneousExtensions3,
127 .PopulationCount,
128 .ProcessorAssist,
129 .ResetReferenceBitsMultiple,
130 .TransactionalExecution,
131 .Vector,
132 .VectorEnhancements1,
133 .VectorEnhancements2,
134 .VectorPackedDecimal,
135 .VectorPackedDecimalEnhancement,
136 }),
137 CpuInfo(@This(), FeatureType).create(.Arch8, "arch8", &[_]FeatureType {
138 }),
139 CpuInfo(@This(), FeatureType).create(.Arch9, "arch9", &[_]FeatureType {
140 .DistinctOps,
141 .FpExtension,
142 .FastSerialization,
143 .HighWord,
144 .InterlockedAccess1,
145 .LoadStoreOnCond,
146 .MessageSecurityAssistExtension3,
147 .MessageSecurityAssistExtension4,
148 .PopulationCount,
149 .ResetReferenceBitsMultiple,
150 }),
151 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
152 }),
153 CpuInfo(@This(), FeatureType).create(.Z10, "z10", &[_]FeatureType {
154 }),
155 CpuInfo(@This(), FeatureType).create(.Z13, "z13", &[_]FeatureType {
156 .DfpPackedConversion,
157 .DfpZonedConversion,
158 .DistinctOps,
159 .EnhancedDat2,
160 .ExecutionHint,
161 .FpExtension,
162 .FastSerialization,
163 .HighWord,
164 .InterlockedAccess1,
165 .LoadAndTrap,
166 .LoadAndZeroRightmostByte,
167 .LoadStoreOnCond,
168 .LoadStoreOnCond2,
169 .MessageSecurityAssistExtension3,
170 .MessageSecurityAssistExtension4,
171 .MessageSecurityAssistExtension5,
172 .MiscellaneousExtensions,
173 .PopulationCount,
174 .ProcessorAssist,
175 .ResetReferenceBitsMultiple,
176 .TransactionalExecution,
177 .Vector,
178 }),
179 CpuInfo(@This(), FeatureType).create(.Z14, "z14", &[_]FeatureType {
180 .DfpPackedConversion,
181 .DfpZonedConversion,
182 .DistinctOps,
183 .EnhancedDat2,
184 .ExecutionHint,
185 .FpExtension,
186 .FastSerialization,
187 .GuardedStorage,
188 .HighWord,
189 .InsertReferenceBitsMultiple,
190 .InterlockedAccess1,
191 .LoadAndTrap,
192 .LoadAndZeroRightmostByte,
193 .LoadStoreOnCond,
194 .LoadStoreOnCond2,
195 .MessageSecurityAssistExtension3,
196 .MessageSecurityAssistExtension4,
197 .MessageSecurityAssistExtension5,
198 .MessageSecurityAssistExtension7,
199 .MessageSecurityAssistExtension8,
200 .MiscellaneousExtensions,
201 .MiscellaneousExtensions2,
202 .PopulationCount,
203 .ProcessorAssist,
204 .ResetReferenceBitsMultiple,
205 .TransactionalExecution,
206 .Vector,
207 .VectorEnhancements1,
208 .VectorPackedDecimal,
209 }),
210 CpuInfo(@This(), FeatureType).create(.Z15, "z15", &[_]FeatureType {
211 .DfpPackedConversion,
212 .DfpZonedConversion,
213 .DeflateConversion,
214 .DistinctOps,
215 .EnhancedDat2,
216 .EnhancedSort,
217 .ExecutionHint,
218 .FpExtension,
219 .FastSerialization,
220 .GuardedStorage,
221 .HighWord,
222 .InsertReferenceBitsMultiple,
223 .InterlockedAccess1,
224 .LoadAndTrap,
225 .LoadAndZeroRightmostByte,
226 .LoadStoreOnCond,
227 .LoadStoreOnCond2,
228 .MessageSecurityAssistExtension3,
229 .MessageSecurityAssistExtension4,
230 .MessageSecurityAssistExtension5,
231 .MessageSecurityAssistExtension7,
232 .MessageSecurityAssistExtension8,
233 .MessageSecurityAssistExtension9,
234 .MiscellaneousExtensions,
235 .MiscellaneousExtensions2,
236 .MiscellaneousExtensions3,
237 .PopulationCount,
238 .ProcessorAssist,
239 .ResetReferenceBitsMultiple,
240 .TransactionalExecution,
241 .Vector,
242 .VectorEnhancements1,
243 .VectorEnhancements2,
244 .VectorPackedDecimal,
245 .VectorPackedDecimalEnhancement,
246 }),
247 CpuInfo(@This(), FeatureType).create(.Z196, "z196", &[_]FeatureType {
248 .DistinctOps,
249 .FpExtension,
250 .FastSerialization,
251 .HighWord,
252 .InterlockedAccess1,
253 .LoadStoreOnCond,
254 .MessageSecurityAssistExtension3,
255 .MessageSecurityAssistExtension4,
256 .PopulationCount,
257 .ResetReferenceBitsMultiple,
258 }),
259 CpuInfo(@This(), FeatureType).create(.ZEC12, "zEC12", &[_]FeatureType {
260 .DfpZonedConversion,
261 .DistinctOps,
262 .EnhancedDat2,
263 .ExecutionHint,
264 .FpExtension,
265 .FastSerialization,
266 .HighWord,
267 .InterlockedAccess1,
268 .LoadAndTrap,
269 .LoadStoreOnCond,
270 .MessageSecurityAssistExtension3,
271 .MessageSecurityAssistExtension4,
272 .MiscellaneousExtensions,
273 .PopulationCount,
274 .ProcessorAssist,
275 .ResetReferenceBitsMultiple,
276 .TransactionalExecution,
277 }),
278 };
279};
lib/std/target/cpu/WebAssemblyCpu.zig deleted-28
......@@ -1,28 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const WebAssemblyCpu = enum {
5 BleedingEdge,
6 Generic,
7 Mvp,
8
9 const FeatureType = feature.WebAssemblyFeature;
10
11 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
12 return cpu_infos[@enumToInt(self)];
13 }
14
15 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
16 CpuInfo(@This(), FeatureType).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
17 .Atomics,
18 .MutableGlobals,
19 .NontrappingFptoint,
20 .Simd128,
21 .SignExt,
22 }),
23 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
24 }),
25 CpuInfo(@This(), FeatureType).create(.Mvp, "mvp", &[_]FeatureType {
26 }),
27 };
28};
lib/std/target/cpu/X86Cpu.zig deleted-1864
......@@ -1,1864 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const X86Cpu = enum {
5 Amdfam10,
6 Athlon,
7 Athlon4,
8 AthlonFx,
9 AthlonMp,
10 AthlonTbird,
11 AthlonXp,
12 Athlon64,
13 Athlon64Sse3,
14 Atom,
15 Barcelona,
16 Bdver1,
17 Bdver2,
18 Bdver3,
19 Bdver4,
20 Bonnell,
21 Broadwell,
22 Btver1,
23 Btver2,
24 C3,
25 C32,
26 Cannonlake,
27 Cascadelake,
28 Cooperlake,
29 CoreAvxI,
30 CoreAvx2,
31 Core2,
32 Corei7,
33 Corei7Avx,
34 Generic,
35 Geode,
36 Goldmont,
37 GoldmontPlus,
38 Haswell,
39 I386,
40 I486,
41 I586,
42 I686,
43 IcelakeClient,
44 IcelakeServer,
45 Ivybridge,
46 K6,
47 K62,
48 K63,
49 K8,
50 K8Sse3,
51 Knl,
52 Knm,
53 Lakemont,
54 Nehalem,
55 Nocona,
56 Opteron,
57 OpteronSse3,
58 Penryn,
59 Pentium,
60 PentiumM,
61 PentiumMmx,
62 Pentium2,
63 Pentium3,
64 Pentium3m,
65 Pentium4,
66 Pentium4m,
67 Pentiumpro,
68 Prescott,
69 Sandybridge,
70 Silvermont,
71 Skx,
72 Skylake,
73 SkylakeAvx512,
74 Slm,
75 Tigerlake,
76 Tremont,
77 Westmere,
78 WinchipC6,
79 Winchip2,
80 X8664,
81 Yonah,
82 Znver1,
83 Znver2,
84
85 const FeatureType = feature.X86Feature;
86
87 pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
88 return cpu_infos[@enumToInt(self)];
89 }
90
91 pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
92 CpuInfo(@This(), FeatureType).create(.Amdfam10, "amdfam10", &[_]FeatureType {
93 .Mmx,
94 .Dnowa3,
95 .Bit64,
96 .Cmov,
97 .Cx8,
98 .Cx16,
99 .Fxsr,
100 .FastScalarShiftMasks,
101 .Sahf,
102 .Lzcnt,
103 .Nopl,
104 .Popcnt,
105 .Sse,
106 .Sse4a,
107 .SlowShld,
108 .X87,
109 }),
110 CpuInfo(@This(), FeatureType).create(.Athlon, "athlon", &[_]FeatureType {
111 .Mmx,
112 .Dnowa3,
113 .Cmov,
114 .Cx8,
115 .Nopl,
116 .SlowShld,
117 .SlowUnalignedMem16,
118 .X87,
119 }),
120 CpuInfo(@This(), FeatureType).create(.Athlon4, "athlon-4", &[_]FeatureType {
121 .Mmx,
122 .Dnowa3,
123 .Cmov,
124 .Cx8,
125 .Fxsr,
126 .Nopl,
127 .Sse,
128 .SlowShld,
129 .SlowUnalignedMem16,
130 .X87,
131 }),
132 CpuInfo(@This(), FeatureType).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
133 .Mmx,
134 .Dnowa3,
135 .Bit64,
136 .Cmov,
137 .Cx8,
138 .Fxsr,
139 .FastScalarShiftMasks,
140 .Nopl,
141 .Sse,
142 .Sse2,
143 .SlowShld,
144 .SlowUnalignedMem16,
145 .X87,
146 }),
147 CpuInfo(@This(), FeatureType).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
148 .Mmx,
149 .Dnowa3,
150 .Cmov,
151 .Cx8,
152 .Fxsr,
153 .Nopl,
154 .Sse,
155 .SlowShld,
156 .SlowUnalignedMem16,
157 .X87,
158 }),
159 CpuInfo(@This(), FeatureType).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
160 .Mmx,
161 .Dnowa3,
162 .Cmov,
163 .Cx8,
164 .Nopl,
165 .SlowShld,
166 .SlowUnalignedMem16,
167 .X87,
168 }),
169 CpuInfo(@This(), FeatureType).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
170 .Mmx,
171 .Dnowa3,
172 .Cmov,
173 .Cx8,
174 .Fxsr,
175 .Nopl,
176 .Sse,
177 .SlowShld,
178 .SlowUnalignedMem16,
179 .X87,
180 }),
181 CpuInfo(@This(), FeatureType).create(.Athlon64, "athlon64", &[_]FeatureType {
182 .Mmx,
183 .Dnowa3,
184 .Bit64,
185 .Cmov,
186 .Cx8,
187 .Fxsr,
188 .FastScalarShiftMasks,
189 .Nopl,
190 .Sse,
191 .Sse2,
192 .SlowShld,
193 .SlowUnalignedMem16,
194 .X87,
195 }),
196 CpuInfo(@This(), FeatureType).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
197 .Mmx,
198 .Dnowa3,
199 .Bit64,
200 .Cmov,
201 .Cx8,
202 .Cx16,
203 .Fxsr,
204 .FastScalarShiftMasks,
205 .Nopl,
206 .Sse,
207 .Sse3,
208 .SlowShld,
209 .SlowUnalignedMem16,
210 .X87,
211 }),
212 CpuInfo(@This(), FeatureType).create(.Atom, "atom", &[_]FeatureType {
213 .Bit64,
214 .Cmov,
215 .Cx8,
216 .Cx16,
217 .Fxsr,
218 .Sahf,
219 .LeaSp,
220 .LeaUsesAg,
221 .Mmx,
222 .Movbe,
223 .Nopl,
224 .PadShortFunctions,
225 .Sse,
226 .Ssse3,
227 .IdivlToDivb,
228 .IdivqToDivl,
229 .SlowTwoMemOps,
230 .SlowUnalignedMem16,
231 .X87,
232 }),
233 CpuInfo(@This(), FeatureType).create(.Barcelona, "barcelona", &[_]FeatureType {
234 .Mmx,
235 .Dnowa3,
236 .Bit64,
237 .Cmov,
238 .Cx8,
239 .Cx16,
240 .Fxsr,
241 .FastScalarShiftMasks,
242 .Sahf,
243 .Lzcnt,
244 .Nopl,
245 .Popcnt,
246 .Sse,
247 .Sse4a,
248 .SlowShld,
249 .X87,
250 }),
251 CpuInfo(@This(), FeatureType).create(.Bdver1, "bdver1", &[_]FeatureType {
252 .Bit64,
253 .Sse,
254 .Aes,
255 .Branchfusion,
256 .Cmov,
257 .Cx8,
258 .Cx16,
259 .Fxsr,
260 .Fast11bytenop,
261 .FastScalarShiftMasks,
262 .Sahf,
263 .Lwp,
264 .Lzcnt,
265 .Mmx,
266 .Nopl,
267 .Pclmul,
268 .Popcnt,
269 .Prfchw,
270 .SlowShld,
271 .X87,
272 .Xop,
273 .Xsave,
274 }),
275 CpuInfo(@This(), FeatureType).create(.Bdver2, "bdver2", &[_]FeatureType {
276 .Bit64,
277 .Sse,
278 .Aes,
279 .Bmi,
280 .Branchfusion,
281 .Cmov,
282 .Cx8,
283 .Cx16,
284 .F16c,
285 .Fma,
286 .Fxsr,
287 .Fast11bytenop,
288 .FastBextr,
289 .FastScalarShiftMasks,
290 .Sahf,
291 .Lwp,
292 .Lzcnt,
293 .Mmx,
294 .Nopl,
295 .Pclmul,
296 .Popcnt,
297 .Prfchw,
298 .SlowShld,
299 .Tbm,
300 .X87,
301 .Xop,
302 .Xsave,
303 }),
304 CpuInfo(@This(), FeatureType).create(.Bdver3, "bdver3", &[_]FeatureType {
305 .Bit64,
306 .Sse,
307 .Aes,
308 .Bmi,
309 .Branchfusion,
310 .Cmov,
311 .Cx8,
312 .Cx16,
313 .F16c,
314 .Fma,
315 .Fsgsbase,
316 .Fxsr,
317 .Fast11bytenop,
318 .FastBextr,
319 .FastScalarShiftMasks,
320 .Sahf,
321 .Lwp,
322 .Lzcnt,
323 .Mmx,
324 .Nopl,
325 .Pclmul,
326 .Popcnt,
327 .Prfchw,
328 .SlowShld,
329 .Tbm,
330 .X87,
331 .Xop,
332 .Xsave,
333 .Xsaveopt,
334 }),
335 CpuInfo(@This(), FeatureType).create(.Bdver4, "bdver4", &[_]FeatureType {
336 .Bit64,
337 .Sse,
338 .Aes,
339 .Avx2,
340 .Bmi,
341 .Bmi2,
342 .Branchfusion,
343 .Cmov,
344 .Cx8,
345 .Cx16,
346 .F16c,
347 .Fma,
348 .Fsgsbase,
349 .Fxsr,
350 .Fast11bytenop,
351 .FastBextr,
352 .FastScalarShiftMasks,
353 .Sahf,
354 .Lwp,
355 .Lzcnt,
356 .Mmx,
357 .Mwaitx,
358 .Nopl,
359 .Pclmul,
360 .Popcnt,
361 .Prfchw,
362 .SlowShld,
363 .Tbm,
364 .X87,
365 .Xop,
366 .Xsave,
367 .Xsaveopt,
368 }),
369 CpuInfo(@This(), FeatureType).create(.Bonnell, "bonnell", &[_]FeatureType {
370 .Bit64,
371 .Cmov,
372 .Cx8,
373 .Cx16,
374 .Fxsr,
375 .Sahf,
376 .LeaSp,
377 .LeaUsesAg,
378 .Mmx,
379 .Movbe,
380 .Nopl,
381 .PadShortFunctions,
382 .Sse,
383 .Ssse3,
384 .IdivlToDivb,
385 .IdivqToDivl,
386 .SlowTwoMemOps,
387 .SlowUnalignedMem16,
388 .X87,
389 }),
390 CpuInfo(@This(), FeatureType).create(.Broadwell, "broadwell", &[_]FeatureType {
391 .Bit64,
392 .Adx,
393 .Sse,
394 .Avx,
395 .Avx2,
396 .Bmi,
397 .Bmi2,
398 .Cmov,
399 .Cx8,
400 .Cx16,
401 .Ermsb,
402 .F16c,
403 .Fma,
404 .Fsgsbase,
405 .Fxsr,
406 .FastShldRotate,
407 .FastScalarFsqrt,
408 .FastVariableShuffle,
409 .Invpcid,
410 .Sahf,
411 .Lzcnt,
412 .FalseDepsLzcntTzcnt,
413 .Mmx,
414 .Movbe,
415 .Macrofusion,
416 .MergeToThreewayBranch,
417 .Nopl,
418 .Pclmul,
419 .Popcnt,
420 .FalseDepsPopcnt,
421 .Prfchw,
422 .Rdrnd,
423 .Rdseed,
424 .Sse42,
425 .Slow3opsLea,
426 .IdivqToDivl,
427 .X87,
428 .Xsave,
429 .Xsaveopt,
430 }),
431 CpuInfo(@This(), FeatureType).create(.Btver1, "btver1", &[_]FeatureType {
432 .Bit64,
433 .Cmov,
434 .Cx8,
435 .Cx16,
436 .Fxsr,
437 .Fast15bytenop,
438 .FastScalarShiftMasks,
439 .FastVectorShiftMasks,
440 .Sahf,
441 .Lzcnt,
442 .Mmx,
443 .Nopl,
444 .Popcnt,
445 .Prfchw,
446 .Sse,
447 .Sse4a,
448 .Ssse3,
449 .SlowShld,
450 .X87,
451 }),
452 CpuInfo(@This(), FeatureType).create(.Btver2, "btver2", &[_]FeatureType {
453 .Bit64,
454 .Sse,
455 .Aes,
456 .Avx,
457 .Bmi,
458 .Cmov,
459 .Cx8,
460 .Cx16,
461 .F16c,
462 .Fxsr,
463 .Fast15bytenop,
464 .FastBextr,
465 .FastHops,
466 .FastLzcnt,
467 .FastPartialYmmOrZmmWrite,
468 .FastScalarShiftMasks,
469 .FastVectorShiftMasks,
470 .Sahf,
471 .Lzcnt,
472 .Mmx,
473 .Movbe,
474 .Nopl,
475 .Pclmul,
476 .Popcnt,
477 .Prfchw,
478 .Sse4a,
479 .Ssse3,
480 .SlowShld,
481 .X87,
482 .Xsave,
483 .Xsaveopt,
484 }),
485 CpuInfo(@This(), FeatureType).create(.C3, "c3", &[_]FeatureType {
486 .Mmx,
487 .Dnow3,
488 .SlowUnalignedMem16,
489 .X87,
490 }),
491 CpuInfo(@This(), FeatureType).create(.C32, "c3-2", &[_]FeatureType {
492 .Cmov,
493 .Cx8,
494 .Fxsr,
495 .Mmx,
496 .Sse,
497 .SlowUnalignedMem16,
498 .X87,
499 }),
500 CpuInfo(@This(), FeatureType).create(.Cannonlake, "cannonlake", &[_]FeatureType {
501 .Bit64,
502 .Adx,
503 .Sse,
504 .Aes,
505 .Avx,
506 .Avx2,
507 .Avx512f,
508 .Bmi,
509 .Bmi2,
510 .Avx512bw,
511 .Avx512cd,
512 .Clflushopt,
513 .Cmov,
514 .Cx8,
515 .Cx16,
516 .Avx512dq,
517 .Ermsb,
518 .F16c,
519 .Fma,
520 .Fsgsbase,
521 .Fxsr,
522 .FastShldRotate,
523 .FastScalarFsqrt,
524 .FastVariableShuffle,
525 .FastVectorFsqrt,
526 .FastGather,
527 .Avx512ifma,
528 .Invpcid,
529 .Sahf,
530 .Lzcnt,
531 .Mmx,
532 .Movbe,
533 .Macrofusion,
534 .MergeToThreewayBranch,
535 .Nopl,
536 .Pclmul,
537 .Pku,
538 .Popcnt,
539 .Prfchw,
540 .Prefer256Bit,
541 .Rdrnd,
542 .Rdseed,
543 .Sgx,
544 .Sha,
545 .Sse42,
546 .Slow3opsLea,
547 .IdivqToDivl,
548 .Avx512vbmi,
549 .Avx512vl,
550 .X87,
551 .Xsave,
552 .Xsavec,
553 .Xsaveopt,
554 .Xsaves,
555 }),
556 CpuInfo(@This(), FeatureType).create(.Cascadelake, "cascadelake", &[_]FeatureType {
557 .Bit64,
558 .Adx,
559 .Sse,
560 .Aes,
561 .Avx,
562 .Avx2,
563 .Avx512f,
564 .Bmi,
565 .Bmi2,
566 .Avx512bw,
567 .Avx512cd,
568 .Clflushopt,
569 .Clwb,
570 .Cmov,
571 .Cx8,
572 .Cx16,
573 .Avx512dq,
574 .Ermsb,
575 .F16c,
576 .Fma,
577 .Fsgsbase,
578 .Fxsr,
579 .FastShldRotate,
580 .FastScalarFsqrt,
581 .FastVariableShuffle,
582 .FastVectorFsqrt,
583 .FastGather,
584 .Invpcid,
585 .Sahf,
586 .Lzcnt,
587 .Mmx,
588 .Movbe,
589 .Macrofusion,
590 .MergeToThreewayBranch,
591 .Nopl,
592 .Pclmul,
593 .Pku,
594 .Popcnt,
595 .FalseDepsPopcnt,
596 .Prfchw,
597 .Prefer256Bit,
598 .Rdrnd,
599 .Rdseed,
600 .Sse42,
601 .Slow3opsLea,
602 .IdivqToDivl,
603 .Avx512vl,
604 .Avx512vnni,
605 .X87,
606 .Xsave,
607 .Xsavec,
608 .Xsaveopt,
609 .Xsaves,
610 }),
611 CpuInfo(@This(), FeatureType).create(.Cooperlake, "cooperlake", &[_]FeatureType {
612 .Bit64,
613 .Adx,
614 .Sse,
615 .Aes,
616 .Avx,
617 .Avx2,
618 .Avx512f,
619 .Avx512bf16,
620 .Bmi,
621 .Bmi2,
622 .Avx512bw,
623 .Avx512cd,
624 .Clflushopt,
625 .Clwb,
626 .Cmov,
627 .Cx8,
628 .Cx16,
629 .Avx512dq,
630 .Ermsb,
631 .F16c,
632 .Fma,
633 .Fsgsbase,
634 .Fxsr,
635 .FastShldRotate,
636 .FastScalarFsqrt,
637 .FastVariableShuffle,
638 .FastVectorFsqrt,
639 .FastGather,
640 .Invpcid,
641 .Sahf,
642 .Lzcnt,
643 .Mmx,
644 .Movbe,
645 .Macrofusion,
646 .MergeToThreewayBranch,
647 .Nopl,
648 .Pclmul,
649 .Pku,
650 .Popcnt,
651 .FalseDepsPopcnt,
652 .Prfchw,
653 .Prefer256Bit,
654 .Rdrnd,
655 .Rdseed,
656 .Sse42,
657 .Slow3opsLea,
658 .IdivqToDivl,
659 .Avx512vl,
660 .Avx512vnni,
661 .X87,
662 .Xsave,
663 .Xsavec,
664 .Xsaveopt,
665 .Xsaves,
666 }),
667 CpuInfo(@This(), FeatureType).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
668 .Bit64,
669 .Sse,
670 .Avx,
671 .Cmov,
672 .Cx8,
673 .Cx16,
674 .F16c,
675 .Fsgsbase,
676 .Fxsr,
677 .FastShldRotate,
678 .FastScalarFsqrt,
679 .Sahf,
680 .Mmx,
681 .Macrofusion,
682 .MergeToThreewayBranch,
683 .Nopl,
684 .Pclmul,
685 .Popcnt,
686 .FalseDepsPopcnt,
687 .Rdrnd,
688 .Sse42,
689 .Slow3opsLea,
690 .IdivqToDivl,
691 .SlowUnalignedMem32,
692 .X87,
693 .Xsave,
694 .Xsaveopt,
695 }),
696 CpuInfo(@This(), FeatureType).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
697 .Bit64,
698 .Sse,
699 .Avx,
700 .Avx2,
701 .Bmi,
702 .Bmi2,
703 .Cmov,
704 .Cx8,
705 .Cx16,
706 .Ermsb,
707 .F16c,
708 .Fma,
709 .Fsgsbase,
710 .Fxsr,
711 .FastShldRotate,
712 .FastScalarFsqrt,
713 .FastVariableShuffle,
714 .Invpcid,
715 .Sahf,
716 .Lzcnt,
717 .FalseDepsLzcntTzcnt,
718 .Mmx,
719 .Movbe,
720 .Macrofusion,
721 .MergeToThreewayBranch,
722 .Nopl,
723 .Pclmul,
724 .Popcnt,
725 .FalseDepsPopcnt,
726 .Rdrnd,
727 .Sse42,
728 .Slow3opsLea,
729 .IdivqToDivl,
730 .X87,
731 .Xsave,
732 .Xsaveopt,
733 }),
734 CpuInfo(@This(), FeatureType).create(.Core2, "core2", &[_]FeatureType {
735 .Bit64,
736 .Cmov,
737 .Cx8,
738 .Cx16,
739 .Fxsr,
740 .Sahf,
741 .Mmx,
742 .Macrofusion,
743 .Nopl,
744 .Sse,
745 .Ssse3,
746 .SlowUnalignedMem16,
747 .X87,
748 }),
749 CpuInfo(@This(), FeatureType).create(.Corei7, "corei7", &[_]FeatureType {
750 .Bit64,
751 .Cmov,
752 .Cx8,
753 .Cx16,
754 .Fxsr,
755 .Sahf,
756 .Mmx,
757 .Macrofusion,
758 .Nopl,
759 .Popcnt,
760 .Sse,
761 .Sse42,
762 .X87,
763 }),
764 CpuInfo(@This(), FeatureType).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
765 .Bit64,
766 .Sse,
767 .Avx,
768 .Cmov,
769 .Cx8,
770 .Cx16,
771 .Fxsr,
772 .FastShldRotate,
773 .FastScalarFsqrt,
774 .Sahf,
775 .Mmx,
776 .Macrofusion,
777 .MergeToThreewayBranch,
778 .Nopl,
779 .Pclmul,
780 .Popcnt,
781 .FalseDepsPopcnt,
782 .Sse42,
783 .Slow3opsLea,
784 .IdivqToDivl,
785 .SlowUnalignedMem32,
786 .X87,
787 .Xsave,
788 .Xsaveopt,
789 }),
790 CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
791 .Cx8,
792 .SlowUnalignedMem16,
793 .X87,
794 }),
795 CpuInfo(@This(), FeatureType).create(.Geode, "geode", &[_]FeatureType {
796 .Mmx,
797 .Dnowa3,
798 .Cx8,
799 .SlowUnalignedMem16,
800 .X87,
801 }),
802 CpuInfo(@This(), FeatureType).create(.Goldmont, "goldmont", &[_]FeatureType {
803 .Bit64,
804 .Sse,
805 .Aes,
806 .Clflushopt,
807 .Cmov,
808 .Cx8,
809 .Cx16,
810 .Fsgsbase,
811 .Fxsr,
812 .Sahf,
813 .Mmx,
814 .Movbe,
815 .Nopl,
816 .Pclmul,
817 .Popcnt,
818 .FalseDepsPopcnt,
819 .Prfchw,
820 .Rdrnd,
821 .Rdseed,
822 .Sha,
823 .Sse42,
824 .Ssse3,
825 .SlowIncdec,
826 .SlowLea,
827 .SlowTwoMemOps,
828 .X87,
829 .Xsave,
830 .Xsavec,
831 .Xsaveopt,
832 .Xsaves,
833 }),
834 CpuInfo(@This(), FeatureType).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
835 .Bit64,
836 .Sse,
837 .Aes,
838 .Clflushopt,
839 .Cmov,
840 .Cx8,
841 .Cx16,
842 .Fsgsbase,
843 .Fxsr,
844 .Sahf,
845 .Mmx,
846 .Movbe,
847 .Nopl,
848 .Pclmul,
849 .Popcnt,
850 .Prfchw,
851 .Ptwrite,
852 .Rdpid,
853 .Rdrnd,
854 .Rdseed,
855 .Sgx,
856 .Sha,
857 .Sse42,
858 .Ssse3,
859 .SlowIncdec,
860 .SlowLea,
861 .SlowTwoMemOps,
862 .X87,
863 .Xsave,
864 .Xsavec,
865 .Xsaveopt,
866 .Xsaves,
867 }),
868 CpuInfo(@This(), FeatureType).create(.Haswell, "haswell", &[_]FeatureType {
869 .Bit64,
870 .Sse,
871 .Avx,
872 .Avx2,
873 .Bmi,
874 .Bmi2,
875 .Cmov,
876 .Cx8,
877 .Cx16,
878 .Ermsb,
879 .F16c,
880 .Fma,
881 .Fsgsbase,
882 .Fxsr,
883 .FastShldRotate,
884 .FastScalarFsqrt,
885 .FastVariableShuffle,
886 .Invpcid,
887 .Sahf,
888 .Lzcnt,
889 .FalseDepsLzcntTzcnt,
890 .Mmx,
891 .Movbe,
892 .Macrofusion,
893 .MergeToThreewayBranch,
894 .Nopl,
895 .Pclmul,
896 .Popcnt,
897 .FalseDepsPopcnt,
898 .Rdrnd,
899 .Sse42,
900 .Slow3opsLea,
901 .IdivqToDivl,
902 .X87,
903 .Xsave,
904 .Xsaveopt,
905 }),
906 CpuInfo(@This(), FeatureType).create(.I386, "i386", &[_]FeatureType {
907 .SlowUnalignedMem16,
908 .X87,
909 }),
910 CpuInfo(@This(), FeatureType).create(.I486, "i486", &[_]FeatureType {
911 .SlowUnalignedMem16,
912 .X87,
913 }),
914 CpuInfo(@This(), FeatureType).create(.I586, "i586", &[_]FeatureType {
915 .Cx8,
916 .SlowUnalignedMem16,
917 .X87,
918 }),
919 CpuInfo(@This(), FeatureType).create(.I686, "i686", &[_]FeatureType {
920 .Cmov,
921 .Cx8,
922 .SlowUnalignedMem16,
923 .X87,
924 }),
925 CpuInfo(@This(), FeatureType).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
926 .Bit64,
927 .Adx,
928 .Sse,
929 .Aes,
930 .Avx,
931 .Avx2,
932 .Avx512f,
933 .Avx512bitalg,
934 .Bmi,
935 .Bmi2,
936 .Avx512bw,
937 .Avx512cd,
938 .Clflushopt,
939 .Clwb,
940 .Cmov,
941 .Cx8,
942 .Cx16,
943 .Avx512dq,
944 .Ermsb,
945 .F16c,
946 .Fma,
947 .Fsgsbase,
948 .Fxsr,
949 .FastShldRotate,
950 .FastScalarFsqrt,
951 .FastVariableShuffle,
952 .FastVectorFsqrt,
953 .Gfni,
954 .FastGather,
955 .Avx512ifma,
956 .Invpcid,
957 .Sahf,
958 .Lzcnt,
959 .Mmx,
960 .Movbe,
961 .Macrofusion,
962 .MergeToThreewayBranch,
963 .Nopl,
964 .Pclmul,
965 .Pku,
966 .Popcnt,
967 .Prfchw,
968 .Prefer256Bit,
969 .Rdpid,
970 .Rdrnd,
971 .Rdseed,
972 .Sgx,
973 .Sha,
974 .Sse42,
975 .Slow3opsLea,
976 .IdivqToDivl,
977 .Vaes,
978 .Avx512vbmi,
979 .Avx512vbmi2,
980 .Avx512vl,
981 .Avx512vnni,
982 .Vpclmulqdq,
983 .Avx512vpopcntdq,
984 .X87,
985 .Xsave,
986 .Xsavec,
987 .Xsaveopt,
988 .Xsaves,
989 }),
990 CpuInfo(@This(), FeatureType).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
991 .Bit64,
992 .Adx,
993 .Sse,
994 .Aes,
995 .Avx,
996 .Avx2,
997 .Avx512f,
998 .Avx512bitalg,
999 .Bmi,
1000 .Bmi2,
1001 .Avx512bw,
1002 .Avx512cd,
1003 .Clflushopt,
1004 .Clwb,
1005 .Cmov,
1006 .Cx8,
1007 .Cx16,
1008 .Avx512dq,
1009 .Ermsb,
1010 .F16c,
1011 .Fma,
1012 .Fsgsbase,
1013 .Fxsr,
1014 .FastShldRotate,
1015 .FastScalarFsqrt,
1016 .FastVariableShuffle,
1017 .FastVectorFsqrt,
1018 .Gfni,
1019 .FastGather,
1020 .Avx512ifma,
1021 .Invpcid,
1022 .Sahf,
1023 .Lzcnt,
1024 .Mmx,
1025 .Movbe,
1026 .Macrofusion,
1027 .MergeToThreewayBranch,
1028 .Nopl,
1029 .Pclmul,
1030 .Pconfig,
1031 .Pku,
1032 .Popcnt,
1033 .Prfchw,
1034 .Prefer256Bit,
1035 .Rdpid,
1036 .Rdrnd,
1037 .Rdseed,
1038 .Sgx,
1039 .Sha,
1040 .Sse42,
1041 .Slow3opsLea,
1042 .IdivqToDivl,
1043 .Vaes,
1044 .Avx512vbmi,
1045 .Avx512vbmi2,
1046 .Avx512vl,
1047 .Avx512vnni,
1048 .Vpclmulqdq,
1049 .Avx512vpopcntdq,
1050 .Wbnoinvd,
1051 .X87,
1052 .Xsave,
1053 .Xsavec,
1054 .Xsaveopt,
1055 .Xsaves,
1056 }),
1057 CpuInfo(@This(), FeatureType).create(.Ivybridge, "ivybridge", &[_]FeatureType {
1058 .Bit64,
1059 .Sse,
1060 .Avx,
1061 .Cmov,
1062 .Cx8,
1063 .Cx16,
1064 .F16c,
1065 .Fsgsbase,
1066 .Fxsr,
1067 .FastShldRotate,
1068 .FastScalarFsqrt,
1069 .Sahf,
1070 .Mmx,
1071 .Macrofusion,
1072 .MergeToThreewayBranch,
1073 .Nopl,
1074 .Pclmul,
1075 .Popcnt,
1076 .FalseDepsPopcnt,
1077 .Rdrnd,
1078 .Sse42,
1079 .Slow3opsLea,
1080 .IdivqToDivl,
1081 .SlowUnalignedMem32,
1082 .X87,
1083 .Xsave,
1084 .Xsaveopt,
1085 }),
1086 CpuInfo(@This(), FeatureType).create(.K6, "k6", &[_]FeatureType {
1087 .Cx8,
1088 .Mmx,
1089 .SlowUnalignedMem16,
1090 .X87,
1091 }),
1092 CpuInfo(@This(), FeatureType).create(.K62, "k6-2", &[_]FeatureType {
1093 .Mmx,
1094 .Dnow3,
1095 .Cx8,
1096 .SlowUnalignedMem16,
1097 .X87,
1098 }),
1099 CpuInfo(@This(), FeatureType).create(.K63, "k6-3", &[_]FeatureType {
1100 .Mmx,
1101 .Dnow3,
1102 .Cx8,
1103 .SlowUnalignedMem16,
1104 .X87,
1105 }),
1106 CpuInfo(@This(), FeatureType).create(.K8, "k8", &[_]FeatureType {
1107 .Mmx,
1108 .Dnowa3,
1109 .Bit64,
1110 .Cmov,
1111 .Cx8,
1112 .Fxsr,
1113 .FastScalarShiftMasks,
1114 .Nopl,
1115 .Sse,
1116 .Sse2,
1117 .SlowShld,
1118 .SlowUnalignedMem16,
1119 .X87,
1120 }),
1121 CpuInfo(@This(), FeatureType).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
1122 .Mmx,
1123 .Dnowa3,
1124 .Bit64,
1125 .Cmov,
1126 .Cx8,
1127 .Cx16,
1128 .Fxsr,
1129 .FastScalarShiftMasks,
1130 .Nopl,
1131 .Sse,
1132 .Sse3,
1133 .SlowShld,
1134 .SlowUnalignedMem16,
1135 .X87,
1136 }),
1137 CpuInfo(@This(), FeatureType).create(.Knl, "knl", &[_]FeatureType {
1138 .Bit64,
1139 .Adx,
1140 .Sse,
1141 .Aes,
1142 .Avx512f,
1143 .Bmi,
1144 .Bmi2,
1145 .Avx512cd,
1146 .Cmov,
1147 .Cx8,
1148 .Cx16,
1149 .Avx512er,
1150 .F16c,
1151 .Fma,
1152 .Fsgsbase,
1153 .Fxsr,
1154 .FastPartialYmmOrZmmWrite,
1155 .FastGather,
1156 .Sahf,
1157 .Lzcnt,
1158 .Mmx,
1159 .Movbe,
1160 .Nopl,
1161 .Pclmul,
1162 .Avx512pf,
1163 .Popcnt,
1164 .Prefetchwt1,
1165 .Prfchw,
1166 .Rdrnd,
1167 .Rdseed,
1168 .Slow3opsLea,
1169 .IdivqToDivl,
1170 .SlowIncdec,
1171 .SlowPmaddwd,
1172 .SlowTwoMemOps,
1173 .X87,
1174 .Xsave,
1175 .Xsaveopt,
1176 }),
1177 CpuInfo(@This(), FeatureType).create(.Knm, "knm", &[_]FeatureType {
1178 .Bit64,
1179 .Adx,
1180 .Sse,
1181 .Aes,
1182 .Avx512f,
1183 .Bmi,
1184 .Bmi2,
1185 .Avx512cd,
1186 .Cmov,
1187 .Cx8,
1188 .Cx16,
1189 .Avx512er,
1190 .F16c,
1191 .Fma,
1192 .Fsgsbase,
1193 .Fxsr,
1194 .FastPartialYmmOrZmmWrite,
1195 .FastGather,
1196 .Sahf,
1197 .Lzcnt,
1198 .Mmx,
1199 .Movbe,
1200 .Nopl,
1201 .Pclmul,
1202 .Avx512pf,
1203 .Popcnt,
1204 .Prefetchwt1,
1205 .Prfchw,
1206 .Rdrnd,
1207 .Rdseed,
1208 .Slow3opsLea,
1209 .IdivqToDivl,
1210 .SlowIncdec,
1211 .SlowPmaddwd,
1212 .SlowTwoMemOps,
1213 .Avx512vpopcntdq,
1214 .X87,
1215 .Xsave,
1216 .Xsaveopt,
1217 }),
1218 CpuInfo(@This(), FeatureType).create(.Lakemont, "lakemont", &[_]FeatureType {
1219 }),
1220 CpuInfo(@This(), FeatureType).create(.Nehalem, "nehalem", &[_]FeatureType {
1221 .Bit64,
1222 .Cmov,
1223 .Cx8,
1224 .Cx16,
1225 .Fxsr,
1226 .Sahf,
1227 .Mmx,
1228 .Macrofusion,
1229 .Nopl,
1230 .Popcnt,
1231 .Sse,
1232 .Sse42,
1233 .X87,
1234 }),
1235 CpuInfo(@This(), FeatureType).create(.Nocona, "nocona", &[_]FeatureType {
1236 .Bit64,
1237 .Cmov,
1238 .Cx8,
1239 .Cx16,
1240 .Fxsr,
1241 .Mmx,
1242 .Nopl,
1243 .Sse,
1244 .Sse3,
1245 .SlowUnalignedMem16,
1246 .X87,
1247 }),
1248 CpuInfo(@This(), FeatureType).create(.Opteron, "opteron", &[_]FeatureType {
1249 .Mmx,
1250 .Dnowa3,
1251 .Bit64,
1252 .Cmov,
1253 .Cx8,
1254 .Fxsr,
1255 .FastScalarShiftMasks,
1256 .Nopl,
1257 .Sse,
1258 .Sse2,
1259 .SlowShld,
1260 .SlowUnalignedMem16,
1261 .X87,
1262 }),
1263 CpuInfo(@This(), FeatureType).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
1264 .Mmx,
1265 .Dnowa3,
1266 .Bit64,
1267 .Cmov,
1268 .Cx8,
1269 .Cx16,
1270 .Fxsr,
1271 .FastScalarShiftMasks,
1272 .Nopl,
1273 .Sse,
1274 .Sse3,
1275 .SlowShld,
1276 .SlowUnalignedMem16,
1277 .X87,
1278 }),
1279 CpuInfo(@This(), FeatureType).create(.Penryn, "penryn", &[_]FeatureType {
1280 .Bit64,
1281 .Cmov,
1282 .Cx8,
1283 .Cx16,
1284 .Fxsr,
1285 .Sahf,
1286 .Mmx,
1287 .Macrofusion,
1288 .Nopl,
1289 .Sse,
1290 .Sse41,
1291 .SlowUnalignedMem16,
1292 .X87,
1293 }),
1294 CpuInfo(@This(), FeatureType).create(.Pentium, "pentium", &[_]FeatureType {
1295 .Cx8,
1296 .SlowUnalignedMem16,
1297 .X87,
1298 }),
1299 CpuInfo(@This(), FeatureType).create(.PentiumM, "pentium-m", &[_]FeatureType {
1300 .Cmov,
1301 .Cx8,
1302 .Fxsr,
1303 .Mmx,
1304 .Nopl,
1305 .Sse,
1306 .Sse2,
1307 .SlowUnalignedMem16,
1308 .X87,
1309 }),
1310 CpuInfo(@This(), FeatureType).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
1311 .Cx8,
1312 .Mmx,
1313 .SlowUnalignedMem16,
1314 .X87,
1315 }),
1316 CpuInfo(@This(), FeatureType).create(.Pentium2, "pentium2", &[_]FeatureType {
1317 .Cmov,
1318 .Cx8,
1319 .Fxsr,
1320 .Mmx,
1321 .Nopl,
1322 .SlowUnalignedMem16,
1323 .X87,
1324 }),
1325 CpuInfo(@This(), FeatureType).create(.Pentium3, "pentium3", &[_]FeatureType {
1326 .Cmov,
1327 .Cx8,
1328 .Fxsr,
1329 .Mmx,
1330 .Nopl,
1331 .Sse,
1332 .SlowUnalignedMem16,
1333 .X87,
1334 }),
1335 CpuInfo(@This(), FeatureType).create(.Pentium3m, "pentium3m", &[_]FeatureType {
1336 .Cmov,
1337 .Cx8,
1338 .Fxsr,
1339 .Mmx,
1340 .Nopl,
1341 .Sse,
1342 .SlowUnalignedMem16,
1343 .X87,
1344 }),
1345 CpuInfo(@This(), FeatureType).create(.Pentium4, "pentium4", &[_]FeatureType {
1346 .Cmov,
1347 .Cx8,
1348 .Fxsr,
1349 .Mmx,
1350 .Nopl,
1351 .Sse,
1352 .Sse2,
1353 .SlowUnalignedMem16,
1354 .X87,
1355 }),
1356 CpuInfo(@This(), FeatureType).create(.Pentium4m, "pentium4m", &[_]FeatureType {
1357 .Cmov,
1358 .Cx8,
1359 .Fxsr,
1360 .Mmx,
1361 .Nopl,
1362 .Sse,
1363 .Sse2,
1364 .SlowUnalignedMem16,
1365 .X87,
1366 }),
1367 CpuInfo(@This(), FeatureType).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
1368 .Cmov,
1369 .Cx8,
1370 .Nopl,
1371 .SlowUnalignedMem16,
1372 .X87,
1373 }),
1374 CpuInfo(@This(), FeatureType).create(.Prescott, "prescott", &[_]FeatureType {
1375 .Cmov,
1376 .Cx8,
1377 .Fxsr,
1378 .Mmx,
1379 .Nopl,
1380 .Sse,
1381 .Sse3,
1382 .SlowUnalignedMem16,
1383 .X87,
1384 }),
1385 CpuInfo(@This(), FeatureType).create(.Sandybridge, "sandybridge", &[_]FeatureType {
1386 .Bit64,
1387 .Sse,
1388 .Avx,
1389 .Cmov,
1390 .Cx8,
1391 .Cx16,
1392 .Fxsr,
1393 .FastShldRotate,
1394 .FastScalarFsqrt,
1395 .Sahf,
1396 .Mmx,
1397 .Macrofusion,
1398 .MergeToThreewayBranch,
1399 .Nopl,
1400 .Pclmul,
1401 .Popcnt,
1402 .FalseDepsPopcnt,
1403 .Sse42,
1404 .Slow3opsLea,
1405 .IdivqToDivl,
1406 .SlowUnalignedMem32,
1407 .X87,
1408 .Xsave,
1409 .Xsaveopt,
1410 }),
1411 CpuInfo(@This(), FeatureType).create(.Silvermont, "silvermont", &[_]FeatureType {
1412 .Bit64,
1413 .Cmov,
1414 .Cx8,
1415 .Cx16,
1416 .Fxsr,
1417 .Sahf,
1418 .Mmx,
1419 .Movbe,
1420 .Nopl,
1421 .Sse,
1422 .Pclmul,
1423 .Popcnt,
1424 .FalseDepsPopcnt,
1425 .Prfchw,
1426 .Rdrnd,
1427 .Sse42,
1428 .Ssse3,
1429 .IdivqToDivl,
1430 .SlowIncdec,
1431 .SlowLea,
1432 .SlowPmulld,
1433 .SlowTwoMemOps,
1434 .X87,
1435 }),
1436 CpuInfo(@This(), FeatureType).create(.Skx, "skx", &[_]FeatureType {
1437 .Bit64,
1438 .Adx,
1439 .Sse,
1440 .Aes,
1441 .Avx,
1442 .Avx2,
1443 .Avx512f,
1444 .Bmi,
1445 .Bmi2,
1446 .Avx512bw,
1447 .Avx512cd,
1448 .Clflushopt,
1449 .Clwb,
1450 .Cmov,
1451 .Cx8,
1452 .Cx16,
1453 .Avx512dq,
1454 .Ermsb,
1455 .F16c,
1456 .Fma,
1457 .Fsgsbase,
1458 .Fxsr,
1459 .FastShldRotate,
1460 .FastScalarFsqrt,
1461 .FastVariableShuffle,
1462 .FastVectorFsqrt,
1463 .FastGather,
1464 .Invpcid,
1465 .Sahf,
1466 .Lzcnt,
1467 .Mmx,
1468 .Movbe,
1469 .Macrofusion,
1470 .MergeToThreewayBranch,
1471 .Nopl,
1472 .Pclmul,
1473 .Pku,
1474 .Popcnt,
1475 .FalseDepsPopcnt,
1476 .Prfchw,
1477 .Prefer256Bit,
1478 .Rdrnd,
1479 .Rdseed,
1480 .Sse42,
1481 .Slow3opsLea,
1482 .IdivqToDivl,
1483 .Avx512vl,
1484 .X87,
1485 .Xsave,
1486 .Xsavec,
1487 .Xsaveopt,
1488 .Xsaves,
1489 }),
1490 CpuInfo(@This(), FeatureType).create(.Skylake, "skylake", &[_]FeatureType {
1491 .Bit64,
1492 .Adx,
1493 .Sse,
1494 .Aes,
1495 .Avx,
1496 .Avx2,
1497 .Bmi,
1498 .Bmi2,
1499 .Clflushopt,
1500 .Cmov,
1501 .Cx8,
1502 .Cx16,
1503 .Ermsb,
1504 .F16c,
1505 .Fma,
1506 .Fsgsbase,
1507 .Fxsr,
1508 .FastShldRotate,
1509 .FastScalarFsqrt,
1510 .FastVariableShuffle,
1511 .FastVectorFsqrt,
1512 .FastGather,
1513 .Invpcid,
1514 .Sahf,
1515 .Lzcnt,
1516 .Mmx,
1517 .Movbe,
1518 .Macrofusion,
1519 .MergeToThreewayBranch,
1520 .Nopl,
1521 .Pclmul,
1522 .Popcnt,
1523 .FalseDepsPopcnt,
1524 .Prfchw,
1525 .Rdrnd,
1526 .Rdseed,
1527 .Sgx,
1528 .Sse42,
1529 .Slow3opsLea,
1530 .IdivqToDivl,
1531 .X87,
1532 .Xsave,
1533 .Xsavec,
1534 .Xsaveopt,
1535 .Xsaves,
1536 }),
1537 CpuInfo(@This(), FeatureType).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
1538 .Bit64,
1539 .Adx,
1540 .Sse,
1541 .Aes,
1542 .Avx,
1543 .Avx2,
1544 .Avx512f,
1545 .Bmi,
1546 .Bmi2,
1547 .Avx512bw,
1548 .Avx512cd,
1549 .Clflushopt,
1550 .Clwb,
1551 .Cmov,
1552 .Cx8,
1553 .Cx16,
1554 .Avx512dq,
1555 .Ermsb,
1556 .F16c,
1557 .Fma,
1558 .Fsgsbase,
1559 .Fxsr,
1560 .FastShldRotate,
1561 .FastScalarFsqrt,
1562 .FastVariableShuffle,
1563 .FastVectorFsqrt,
1564 .FastGather,
1565 .Invpcid,
1566 .Sahf,
1567 .Lzcnt,
1568 .Mmx,
1569 .Movbe,
1570 .Macrofusion,
1571 .MergeToThreewayBranch,
1572 .Nopl,
1573 .Pclmul,
1574 .Pku,
1575 .Popcnt,
1576 .FalseDepsPopcnt,
1577 .Prfchw,
1578 .Prefer256Bit,
1579 .Rdrnd,
1580 .Rdseed,
1581 .Sse42,
1582 .Slow3opsLea,
1583 .IdivqToDivl,
1584 .Avx512vl,
1585 .X87,
1586 .Xsave,
1587 .Xsavec,
1588 .Xsaveopt,
1589 .Xsaves,
1590 }),
1591 CpuInfo(@This(), FeatureType).create(.Slm, "slm", &[_]FeatureType {
1592 .Bit64,
1593 .Cmov,
1594 .Cx8,
1595 .Cx16,
1596 .Fxsr,
1597 .Sahf,
1598 .Mmx,
1599 .Movbe,
1600 .Nopl,
1601 .Sse,
1602 .Pclmul,
1603 .Popcnt,
1604 .FalseDepsPopcnt,
1605 .Prfchw,
1606 .Rdrnd,
1607 .Sse42,
1608 .Ssse3,
1609 .IdivqToDivl,
1610 .SlowIncdec,
1611 .SlowLea,
1612 .SlowPmulld,
1613 .SlowTwoMemOps,
1614 .X87,
1615 }),
1616 CpuInfo(@This(), FeatureType).create(.Tigerlake, "tigerlake", &[_]FeatureType {
1617 .Bit64,
1618 .Adx,
1619 .Sse,
1620 .Aes,
1621 .Avx,
1622 .Avx2,
1623 .Avx512f,
1624 .Avx512bitalg,
1625 .Bmi,
1626 .Bmi2,
1627 .Avx512bw,
1628 .Avx512cd,
1629 .Clflushopt,
1630 .Clwb,
1631 .Cmov,
1632 .Cx8,
1633 .Cx16,
1634 .Avx512dq,
1635 .Ermsb,
1636 .F16c,
1637 .Fma,
1638 .Fsgsbase,
1639 .Fxsr,
1640 .FastShldRotate,
1641 .FastScalarFsqrt,
1642 .FastVariableShuffle,
1643 .FastVectorFsqrt,
1644 .Gfni,
1645 .FastGather,
1646 .Avx512ifma,
1647 .Invpcid,
1648 .Sahf,
1649 .Lzcnt,
1650 .Mmx,
1651 .Movbe,
1652 .Movdir64b,
1653 .Movdiri,
1654 .Macrofusion,
1655 .MergeToThreewayBranch,
1656 .Nopl,
1657 .Pclmul,
1658 .Pku,
1659 .Popcnt,
1660 .Prfchw,
1661 .Prefer256Bit,
1662 .Rdpid,
1663 .Rdrnd,
1664 .Rdseed,
1665 .Sgx,
1666 .Sha,
1667 .Shstk,
1668 .Sse42,
1669 .Slow3opsLea,
1670 .IdivqToDivl,
1671 .Vaes,
1672 .Avx512vbmi,
1673 .Avx512vbmi2,
1674 .Avx512vl,
1675 .Avx512vnni,
1676 .Avx512vp2intersect,
1677 .Vpclmulqdq,
1678 .Avx512vpopcntdq,
1679 .X87,
1680 .Xsave,
1681 .Xsavec,
1682 .Xsaveopt,
1683 .Xsaves,
1684 }),
1685 CpuInfo(@This(), FeatureType).create(.Tremont, "tremont", &[_]FeatureType {
1686 .Bit64,
1687 .Sse,
1688 .Aes,
1689 .Cldemote,
1690 .Clflushopt,
1691 .Cmov,
1692 .Cx8,
1693 .Cx16,
1694 .Fsgsbase,
1695 .Fxsr,
1696 .Gfni,
1697 .Sahf,
1698 .Mmx,
1699 .Movbe,
1700 .Movdir64b,
1701 .Movdiri,
1702 .Nopl,
1703 .Pclmul,
1704 .Popcnt,
1705 .Prfchw,
1706 .Ptwrite,
1707 .Rdpid,
1708 .Rdrnd,
1709 .Rdseed,
1710 .Sgx,
1711 .Sha,
1712 .Sse42,
1713 .Ssse3,
1714 .SlowIncdec,
1715 .SlowLea,
1716 .SlowTwoMemOps,
1717 .Waitpkg,
1718 .X87,
1719 .Xsave,
1720 .Xsavec,
1721 .Xsaveopt,
1722 .Xsaves,
1723 }),
1724 CpuInfo(@This(), FeatureType).create(.Westmere, "westmere", &[_]FeatureType {
1725 .Bit64,
1726 .Cmov,
1727 .Cx8,
1728 .Cx16,
1729 .Fxsr,
1730 .Sahf,
1731 .Mmx,
1732 .Macrofusion,
1733 .Nopl,
1734 .Sse,
1735 .Pclmul,
1736 .Popcnt,
1737 .Sse42,
1738 .X87,
1739 }),
1740 CpuInfo(@This(), FeatureType).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
1741 .Mmx,
1742 .SlowUnalignedMem16,
1743 .X87,
1744 }),
1745 CpuInfo(@This(), FeatureType).create(.Winchip2, "winchip2", &[_]FeatureType {
1746 .Mmx,
1747 .Dnow3,
1748 .SlowUnalignedMem16,
1749 .X87,
1750 }),
1751 CpuInfo(@This(), FeatureType).create(.X8664, "x86-64", &[_]FeatureType {
1752 .Bit64,
1753 .Cmov,
1754 .Cx8,
1755 .Fxsr,
1756 .Mmx,
1757 .Macrofusion,
1758 .Nopl,
1759 .Sse,
1760 .Sse2,
1761 .Slow3opsLea,
1762 .SlowIncdec,
1763 .X87,
1764 }),
1765 CpuInfo(@This(), FeatureType).create(.Yonah, "yonah", &[_]FeatureType {
1766 .Cmov,
1767 .Cx8,
1768 .Fxsr,
1769 .Mmx,
1770 .Nopl,
1771 .Sse,
1772 .Sse3,
1773 .SlowUnalignedMem16,
1774 .X87,
1775 }),
1776 CpuInfo(@This(), FeatureType).create(.Znver1, "znver1", &[_]FeatureType {
1777 .Bit64,
1778 .Adx,
1779 .Sse,
1780 .Aes,
1781 .Avx2,
1782 .Bmi,
1783 .Bmi2,
1784 .Branchfusion,
1785 .Clflushopt,
1786 .Clzero,
1787 .Cmov,
1788 .Cx8,
1789 .Cx16,
1790 .F16c,
1791 .Fma,
1792 .Fsgsbase,
1793 .Fxsr,
1794 .Fast15bytenop,
1795 .FastBextr,
1796 .FastLzcnt,
1797 .FastScalarShiftMasks,
1798 .Sahf,
1799 .Lzcnt,
1800 .Mmx,
1801 .Movbe,
1802 .Mwaitx,
1803 .Nopl,
1804 .Pclmul,
1805 .Popcnt,
1806 .Prfchw,
1807 .Rdrnd,
1808 .Rdseed,
1809 .Sha,
1810 .Sse4a,
1811 .SlowShld,
1812 .X87,
1813 .Xsave,
1814 .Xsavec,
1815 .Xsaveopt,
1816 .Xsaves,
1817 }),
1818 CpuInfo(@This(), FeatureType).create(.Znver2, "znver2", &[_]FeatureType {
1819 .Bit64,
1820 .Adx,
1821 .Sse,
1822 .Aes,
1823 .Avx2,
1824 .Bmi,
1825 .Bmi2,
1826 .Branchfusion,
1827 .Clflushopt,
1828 .Clwb,
1829 .Clzero,
1830 .Cmov,
1831 .Cx8,
1832 .Cx16,
1833 .F16c,
1834 .Fma,
1835 .Fsgsbase,
1836 .Fxsr,
1837 .Fast15bytenop,
1838 .FastBextr,
1839 .FastLzcnt,
1840 .FastScalarShiftMasks,
1841 .Sahf,
1842 .Lzcnt,
1843 .Mmx,
1844 .Movbe,
1845 .Mwaitx,
1846 .Nopl,
1847 .Pclmul,
1848 .Popcnt,
1849 .Prfchw,
1850 .Rdpid,
1851 .Rdrnd,
1852 .Rdseed,
1853 .Sha,
1854 .Sse4a,
1855 .SlowShld,
1856 .Wbnoinvd,
1857 .X87,
1858 .Xsave,
1859 .Xsavec,
1860 .Xsaveopt,
1861 .Xsaves,
1862 }),
1863 };
1864};
lib/std/target/cpu/empty.zig deleted-6
......@@ -1,6 +0,0 @@
1const feature = @import("std").target.feature;
2const CpuInfo = @import("std").target.cpu.CpuInfo;
3
4pub const EmptyCpu = struct {
5 pub const cpu_infos = [0]CpuInfo(@This(), feature.EmptyFeature) {};
6};
lib/std/target/feature.zig deleted-81
......@@ -1,81 +0,0 @@
1const builtin = @import("builtin");
2const std = @import("std");
3const Arch = std.Target.Arch;
4
5pub const AArch64Feature = @import("feature/AArch64Feature.zig").AArch64Feature;
6pub const AmdGpuFeature = @import("feature/AmdGpuFeature.zig").AmdGpuFeature;
7pub const ArmFeature = @import("feature/ArmFeature.zig").ArmFeature;
8pub const AvrFeature = @import("feature/AvrFeature.zig").AvrFeature;
9pub const BpfFeature = @import("feature/BpfFeature.zig").BpfFeature;
10pub const HexagonFeature = @import("feature/HexagonFeature.zig").HexagonFeature; pub const MipsFeature = @import("feature/MipsFeature.zig").MipsFeature;
11pub const Msp430Feature = @import("feature/Msp430Feature.zig").Msp430Feature;
12pub const NvptxFeature = @import("feature/NvptxFeature.zig").NvptxFeature;
13pub const PowerPcFeature = @import("feature/PowerPcFeature.zig").PowerPcFeature;
14pub const RiscVFeature = @import("feature/RiscVFeature.zig").RiscVFeature;
15pub const SparcFeature = @import("feature/SparcFeature.zig").SparcFeature;
16pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
17pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
18pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
19
20pub const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
21
22pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
23 return switch (arch) {
24 .arm, .armeb, .thumb, .thumbeb => ArmFeature,
25 .aarch64, .aarch64_be, .aarch64_32 => AArch64Feature,
26 .avr => AvrFeature,
27 .bpfel, .bpfeb => BpfFeature,
28 .hexagon => HexagonFeature,
29 .mips, .mipsel, .mips64, .mips64el => MipsFeature,
30 .msp430 => Msp430Feature,
31 .powerpc, .powerpc64, .powerpc64le => PowerPcFeature,
32 .amdgcn => AmdGpuFeature,
33 .riscv32, .riscv64 => RiscVFeature,
34 .sparc, .sparcv9, .sparcel => SparcFeature,
35 .s390x => SystemZFeature,
36 .i386, .x86_64 => X86Feature,
37 .nvptx, .nvptx64 => NvptxFeature,
38 .wasm32, .wasm64 => WebAssemblyFeature,
39
40 else => EmptyFeature,
41 };
42}
43
44pub fn ArchFeatureInfo(comptime arch: @TagType(Arch)) type {
45 return FeatureInfo(ArchFeature(arch));
46}
47
48pub fn FeatureInfo(comptime EnumType: type) type {
49 return struct {
50 value: EnumType,
51 name: []const u8,
52 description: []const u8,
53 llvm_name: []const u8,
54
55 subfeatures: []const EnumType,
56
57 const Self = @This();
58
59 pub fn create(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8) Self {
60 return Self {
61 .value = value,
62 .name = name,
63 .description = description,
64 .llvm_name = llvm_name,
65
66 .subfeatures = &[_]EnumType{},
67 };
68 }
69
70 pub fn createWithSubfeatures(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8, subfeatures: []const EnumType) Self {
71 return Self {
72 .value = value,
73 .name = name,
74 .description = description,
75 .llvm_name = llvm_name,
76
77 .subfeatures = subfeatures,
78 };
79 }
80 };
81}
lib/std/target/feature/AArch64Feature.zig deleted-750
......@@ -1,750 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const AArch64Feature = enum {
4 Aes,
5 Am,
6 AggressiveFma,
7 Altnzcv,
8 AlternateSextloadCvtF32Pattern,
9 ArithBccFusion,
10 ArithCbzFusion,
11 BalanceFpOps,
12 Bti,
13 Ccidx,
14 Ccpp,
15 Crc,
16 Ccdp,
17 CallSavedX8,
18 CallSavedX9,
19 CallSavedX10,
20 CallSavedX11,
21 CallSavedX12,
22 CallSavedX13,
23 CallSavedX14,
24 CallSavedX15,
25 CallSavedX18,
26 Complxnum,
27 Crypto,
28 CustomCheapAsMove,
29 Dit,
30 DisableLatencySchedHeuristic,
31 Dotprod,
32 Ete,
33 ExynosCheapAsMove,
34 Fmi,
35 Fp16fml,
36 FpArmv8,
37 Fptoint,
38 Force32bitJumpTables,
39 Fullfp16,
40 FuseAes,
41 FuseAddress,
42 FuseArithLogic,
43 FuseCsel,
44 FuseCryptoEor,
45 FuseLiterals,
46 Jsconv,
47 Lor,
48 Lse,
49 LslFast,
50 Mpam,
51 Mte,
52 Neon,
53 Nv,
54 NoNegImmediates,
55 Pa,
56 Pan,
57 PanRwv,
58 Perfmon,
59 UsePostraScheduler,
60 Predres,
61 PredictableSelectExpensive,
62 Uaops,
63 Ras,
64 Rasv8_4,
65 Rcpc,
66 RcpcImmo,
67 Rdm,
68 Rand,
69 ReserveX1,
70 ReserveX2,
71 ReserveX3,
72 ReserveX4,
73 ReserveX5,
74 ReserveX6,
75 ReserveX7,
76 ReserveX9,
77 ReserveX10,
78 ReserveX11,
79 ReserveX12,
80 ReserveX13,
81 ReserveX14,
82 ReserveX15,
83 ReserveX18,
84 ReserveX20,
85 ReserveX21,
86 ReserveX22,
87 ReserveX23,
88 ReserveX24,
89 ReserveX25,
90 ReserveX26,
91 ReserveX27,
92 ReserveX28,
93 Sb,
94 Sel2,
95 Sha2,
96 Sha3,
97 Sm4,
98 Spe,
99 Ssbs,
100 Sve,
101 Sve2,
102 Sve2Aes,
103 Sve2Bitperm,
104 Sve2Sha3,
105 Sve2Sm4,
106 SlowMisaligned128store,
107 SlowPaired128,
108 SlowStrqroStore,
109 Specrestrict,
110 StrictAlign,
111 TlbRmi,
112 Tme,
113 Tracev84,
114 Trbe,
115 TaggedGlobals,
116 UseAa,
117 TpidrEl1,
118 TpidrEl2,
119 TpidrEl3,
120 UseReciprocalSquareRoot,
121 Vh,
122 Zcm,
123 Zcz,
124 ZczFp,
125 ZczFpWorkaround,
126 ZczGp,
127 V81a,
128 V82a,
129 V83a,
130 V84a,
131 V85a,
132 A35,
133 A53,
134 A55,
135 A57,
136 A65,
137 A72,
138 A73,
139 A75,
140 A76,
141 Cyclone,
142 Exynosm1,
143 Exynosm2,
144 Exynosm3,
145 Exynosm4,
146 Falkor,
147 Kryo,
148 Neoversee1,
149 Neoversen1,
150 Saphira,
151 Tsv110,
152 Thunderx,
153 Thunderx2t99,
154 Thunderxt81,
155 Thunderxt83,
156 Thunderxt88,
157
158 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
159 return feature_infos[@enumToInt(self)];
160 }
161
162 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
163 FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
164 .FpArmv8,
165 }),
166 FeatureInfo(@This()).create(.Am, "am", "Enable v8.4-A Activity Monitors extension", "am"),
167 FeatureInfo(@This()).create(.AggressiveFma, "aggressive-fma", "Enable Aggressive FMA for floating-point.", "aggressive-fma"),
168 FeatureInfo(@This()).create(.Altnzcv, "altnzcv", "Enable alternative NZCV format for floating point comparisons", "altnzcv"),
169 FeatureInfo(@This()).create(.AlternateSextloadCvtF32Pattern, "alternate-sextload-cvt-f32-pattern", "Use alternative pattern for sextload convert to f32", "alternate-sextload-cvt-f32-pattern"),
170 FeatureInfo(@This()).create(.ArithBccFusion, "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", "arith-bcc-fusion"),
171 FeatureInfo(@This()).create(.ArithCbzFusion, "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", "arith-cbz-fusion"),
172 FeatureInfo(@This()).create(.BalanceFpOps, "balance-fp-ops", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", "balance-fp-ops"),
173 FeatureInfo(@This()).create(.Bti, "bti", "Enable Branch Target Identification", "bti"),
174 FeatureInfo(@This()).create(.Ccidx, "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", "ccidx"),
175 FeatureInfo(@This()).create(.Ccpp, "ccpp", "Enable v8.2 data Cache Clean to Point of Persistence", "ccpp"),
176 FeatureInfo(@This()).create(.Crc, "crc", "Enable ARMv8 CRC-32 checksum instructions", "crc"),
177 FeatureInfo(@This()).create(.Ccdp, "ccdp", "Enable v8.5 Cache Clean to Point of Deep Persistence", "ccdp"),
178 FeatureInfo(@This()).create(.CallSavedX8, "call-saved-x8", "Make X8 callee saved.", "call-saved-x8"),
179 FeatureInfo(@This()).create(.CallSavedX9, "call-saved-x9", "Make X9 callee saved.", "call-saved-x9"),
180 FeatureInfo(@This()).create(.CallSavedX10, "call-saved-x10", "Make X10 callee saved.", "call-saved-x10"),
181 FeatureInfo(@This()).create(.CallSavedX11, "call-saved-x11", "Make X11 callee saved.", "call-saved-x11"),
182 FeatureInfo(@This()).create(.CallSavedX12, "call-saved-x12", "Make X12 callee saved.", "call-saved-x12"),
183 FeatureInfo(@This()).create(.CallSavedX13, "call-saved-x13", "Make X13 callee saved.", "call-saved-x13"),
184 FeatureInfo(@This()).create(.CallSavedX14, "call-saved-x14", "Make X14 callee saved.", "call-saved-x14"),
185 FeatureInfo(@This()).create(.CallSavedX15, "call-saved-x15", "Make X15 callee saved.", "call-saved-x15"),
186 FeatureInfo(@This()).create(.CallSavedX18, "call-saved-x18", "Make X18 callee saved.", "call-saved-x18"),
187 FeatureInfo(@This()).createWithSubfeatures(.Complxnum, "complxnum", "Enable v8.3-A Floating-point complex number support", "complxnum", &[_]@This() {
188 .FpArmv8,
189 }),
190 FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable cryptographic instructions", "crypto", &[_]@This() {
191 .FpArmv8,
192 }),
193 FeatureInfo(@This()).create(.CustomCheapAsMove, "custom-cheap-as-move", "Use custom handling of cheap instructions", "custom-cheap-as-move"),
194 FeatureInfo(@This()).create(.Dit, "dit", "Enable v8.4-A Data Independent Timing instructions", "dit"),
195 FeatureInfo(@This()).create(.DisableLatencySchedHeuristic, "disable-latency-sched-heuristic", "Disable latency scheduling heuristic", "disable-latency-sched-heuristic"),
196 FeatureInfo(@This()).create(.Dotprod, "dotprod", "Enable dot product support", "dotprod"),
197 FeatureInfo(@This()).createWithSubfeatures(.Ete, "ete", "Enable Embedded Trace Extension", "ete", &[_]@This() {
198 .Trbe,
199 }),
200 FeatureInfo(@This()).createWithSubfeatures(.ExynosCheapAsMove, "exynos-cheap-as-move", "Use Exynos specific handling of cheap instructions", "exynos-cheap-as-move", &[_]@This() {
201 .CustomCheapAsMove,
202 }),
203 FeatureInfo(@This()).create(.Fmi, "fmi", "Enable v8.4-A Flag Manipulation Instructions", "fmi"),
204 FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable FP16 FML instructions", "fp16fml", &[_]@This() {
205 .FpArmv8,
206 }),
207 FeatureInfo(@This()).create(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8"),
208 FeatureInfo(@This()).create(.Fptoint, "fptoint", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", "fptoint"),
209 FeatureInfo(@This()).create(.Force32bitJumpTables, "force-32bit-jump-tables", "Force jump table entries to be 32-bits wide except at MinSize", "force-32bit-jump-tables"),
210 FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Full FP16", "fullfp16", &[_]@This() {
211 .FpArmv8,
212 }),
213 FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
214 FeatureInfo(@This()).create(.FuseAddress, "fuse-address", "CPU fuses address generation and memory operations", "fuse-address"),
215 FeatureInfo(@This()).create(.FuseArithLogic, "fuse-arith-logic", "CPU fuses arithmetic and logic operations", "fuse-arith-logic"),
216 FeatureInfo(@This()).create(.FuseCsel, "fuse-csel", "CPU fuses conditional select operations", "fuse-csel"),
217 FeatureInfo(@This()).create(.FuseCryptoEor, "fuse-crypto-eor", "CPU fuses AES/PMULL and EOR operations", "fuse-crypto-eor"),
218 FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
219 FeatureInfo(@This()).createWithSubfeatures(.Jsconv, "jsconv", "Enable v8.3-A JavaScript FP conversion enchancement", "jsconv", &[_]@This() {
220 .FpArmv8,
221 }),
222 FeatureInfo(@This()).create(.Lor, "lor", "Enables ARM v8.1 Limited Ordering Regions extension", "lor"),
223 FeatureInfo(@This()).create(.Lse, "lse", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", "lse"),
224 FeatureInfo(@This()).create(.LslFast, "lsl-fast", "CPU has a fastpath logical shift of up to 3 places", "lsl-fast"),
225 FeatureInfo(@This()).create(.Mpam, "mpam", "Enable v8.4-A Memory system Partitioning and Monitoring extension", "mpam"),
226 FeatureInfo(@This()).create(.Mte, "mte", "Enable Memory Tagging Extension", "mte"),
227 FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable Advanced SIMD instructions", "neon", &[_]@This() {
228 .FpArmv8,
229 }),
230 FeatureInfo(@This()).create(.Nv, "nv", "Enable v8.4-A Nested Virtualization Enchancement", "nv"),
231 FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
232 FeatureInfo(@This()).create(.Pa, "pa", "Enable v8.3-A Pointer Authentication enchancement", "pa"),
233 FeatureInfo(@This()).create(.Pan, "pan", "Enables ARM v8.1 Privileged Access-Never extension", "pan"),
234 FeatureInfo(@This()).createWithSubfeatures(.PanRwv, "pan-rwv", "Enable v8.2 PAN s1e1R and s1e1W Variants", "pan-rwv", &[_]@This() {
235 .Pan,
236 }),
237 FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable ARMv8 PMUv3 Performance Monitors extension", "perfmon"),
238 FeatureInfo(@This()).create(.UsePostraScheduler, "use-postra-scheduler", "Schedule again after register allocation", "use-postra-scheduler"),
239 FeatureInfo(@This()).create(.Predres, "predres", "Enable v8.5a execution and data prediction invalidation instructions", "predres"),
240 FeatureInfo(@This()).create(.PredictableSelectExpensive, "predictable-select-expensive", "Prefer likely predicted branches over selects", "predictable-select-expensive"),
241 FeatureInfo(@This()).create(.Uaops, "uaops", "Enable v8.2 UAO PState", "uaops"),
242 FeatureInfo(@This()).create(.Ras, "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", "ras"),
243 FeatureInfo(@This()).createWithSubfeatures(.Rasv8_4, "rasv8_4", "Enable v8.4-A Reliability, Availability and Serviceability extension", "rasv8_4", &[_]@This() {
244 .Ras,
245 }),
246 FeatureInfo(@This()).create(.Rcpc, "rcpc", "Enable support for RCPC extension", "rcpc"),
247 FeatureInfo(@This()).createWithSubfeatures(.RcpcImmo, "rcpc-immo", "Enable v8.4-A RCPC instructions with Immediate Offsets", "rcpc-immo", &[_]@This() {
248 .Rcpc,
249 }),
250 FeatureInfo(@This()).create(.Rdm, "rdm", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", "rdm"),
251 FeatureInfo(@This()).create(.Rand, "rand", "Enable Random Number generation instructions", "rand"),
252 FeatureInfo(@This()).create(.ReserveX1, "reserve-x1", "Reserve X1, making it unavailable as a GPR", "reserve-x1"),
253 FeatureInfo(@This()).create(.ReserveX2, "reserve-x2", "Reserve X2, making it unavailable as a GPR", "reserve-x2"),
254 FeatureInfo(@This()).create(.ReserveX3, "reserve-x3", "Reserve X3, making it unavailable as a GPR", "reserve-x3"),
255 FeatureInfo(@This()).create(.ReserveX4, "reserve-x4", "Reserve X4, making it unavailable as a GPR", "reserve-x4"),
256 FeatureInfo(@This()).create(.ReserveX5, "reserve-x5", "Reserve X5, making it unavailable as a GPR", "reserve-x5"),
257 FeatureInfo(@This()).create(.ReserveX6, "reserve-x6", "Reserve X6, making it unavailable as a GPR", "reserve-x6"),
258 FeatureInfo(@This()).create(.ReserveX7, "reserve-x7", "Reserve X7, making it unavailable as a GPR", "reserve-x7"),
259 FeatureInfo(@This()).create(.ReserveX9, "reserve-x9", "Reserve X9, making it unavailable as a GPR", "reserve-x9"),
260 FeatureInfo(@This()).create(.ReserveX10, "reserve-x10", "Reserve X10, making it unavailable as a GPR", "reserve-x10"),
261 FeatureInfo(@This()).create(.ReserveX11, "reserve-x11", "Reserve X11, making it unavailable as a GPR", "reserve-x11"),
262 FeatureInfo(@This()).create(.ReserveX12, "reserve-x12", "Reserve X12, making it unavailable as a GPR", "reserve-x12"),
263 FeatureInfo(@This()).create(.ReserveX13, "reserve-x13", "Reserve X13, making it unavailable as a GPR", "reserve-x13"),
264 FeatureInfo(@This()).create(.ReserveX14, "reserve-x14", "Reserve X14, making it unavailable as a GPR", "reserve-x14"),
265 FeatureInfo(@This()).create(.ReserveX15, "reserve-x15", "Reserve X15, making it unavailable as a GPR", "reserve-x15"),
266 FeatureInfo(@This()).create(.ReserveX18, "reserve-x18", "Reserve X18, making it unavailable as a GPR", "reserve-x18"),
267 FeatureInfo(@This()).create(.ReserveX20, "reserve-x20", "Reserve X20, making it unavailable as a GPR", "reserve-x20"),
268 FeatureInfo(@This()).create(.ReserveX21, "reserve-x21", "Reserve X21, making it unavailable as a GPR", "reserve-x21"),
269 FeatureInfo(@This()).create(.ReserveX22, "reserve-x22", "Reserve X22, making it unavailable as a GPR", "reserve-x22"),
270 FeatureInfo(@This()).create(.ReserveX23, "reserve-x23", "Reserve X23, making it unavailable as a GPR", "reserve-x23"),
271 FeatureInfo(@This()).create(.ReserveX24, "reserve-x24", "Reserve X24, making it unavailable as a GPR", "reserve-x24"),
272 FeatureInfo(@This()).create(.ReserveX25, "reserve-x25", "Reserve X25, making it unavailable as a GPR", "reserve-x25"),
273 FeatureInfo(@This()).create(.ReserveX26, "reserve-x26", "Reserve X26, making it unavailable as a GPR", "reserve-x26"),
274 FeatureInfo(@This()).create(.ReserveX27, "reserve-x27", "Reserve X27, making it unavailable as a GPR", "reserve-x27"),
275 FeatureInfo(@This()).create(.ReserveX28, "reserve-x28", "Reserve X28, making it unavailable as a GPR", "reserve-x28"),
276 FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5 Speculation Barrier", "sb"),
277 FeatureInfo(@This()).create(.Sel2, "sel2", "Enable v8.4-A Secure Exception Level 2 extension", "sel2"),
278 FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
279 .FpArmv8,
280 }),
281 FeatureInfo(@This()).createWithSubfeatures(.Sha3, "sha3", "Enable SHA512 and SHA3 support", "sha3", &[_]@This() {
282 .FpArmv8,
283 }),
284 FeatureInfo(@This()).createWithSubfeatures(.Sm4, "sm4", "Enable SM3 and SM4 support", "sm4", &[_]@This() {
285 .FpArmv8,
286 }),
287 FeatureInfo(@This()).create(.Spe, "spe", "Enable Statistical Profiling extension", "spe"),
288 FeatureInfo(@This()).create(.Ssbs, "ssbs", "Enable Speculative Store Bypass Safe bit", "ssbs"),
289 FeatureInfo(@This()).create(.Sve, "sve", "Enable Scalable Vector Extension (SVE) instructions", "sve"),
290 FeatureInfo(@This()).createWithSubfeatures(.Sve2, "sve2", "Enable Scalable Vector Extension 2 (SVE2) instructions", "sve2", &[_]@This() {
291 .Sve,
292 }),
293 FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
294 .FpArmv8,
295 .Sve,
296 }),
297 FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
298 .Sve,
299 }),
300 FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
301 .FpArmv8,
302 .Sve,
303 }),
304 FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
305 .FpArmv8,
306 .Sve,
307 }),
308 FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
309 FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
310 FeatureInfo(@This()).create(.SlowStrqroStore, "slow-strqro-store", "STR of Q register with register offset is slow", "slow-strqro-store"),
311 FeatureInfo(@This()).create(.Specrestrict, "specrestrict", "Enable architectural speculation restriction", "specrestrict"),
312 FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
313 FeatureInfo(@This()).create(.TlbRmi, "tlb-rmi", "Enable v8.4-A TLB Range and Maintenance Instructions", "tlb-rmi"),
314 FeatureInfo(@This()).create(.Tme, "tme", "Enable Transactional Memory Extension", "tme"),
315 FeatureInfo(@This()).create(.Tracev84, "tracev8.4", "Enable v8.4-A Trace extension", "tracev8.4"),
316 FeatureInfo(@This()).create(.Trbe, "trbe", "Enable Trace Buffer Extension", "trbe"),
317 FeatureInfo(@This()).create(.TaggedGlobals, "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", "tagged-globals"),
318 FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
319 FeatureInfo(@This()).create(.TpidrEl1, "tpidr-el1", "Permit use of TPIDR_EL1 for the TLS base", "tpidr-el1"),
320 FeatureInfo(@This()).create(.TpidrEl2, "tpidr-el2", "Permit use of TPIDR_EL2 for the TLS base", "tpidr-el2"),
321 FeatureInfo(@This()).create(.TpidrEl3, "tpidr-el3", "Permit use of TPIDR_EL3 for the TLS base", "tpidr-el3"),
322 FeatureInfo(@This()).create(.UseReciprocalSquareRoot, "use-reciprocal-square-root", "Use the reciprocal square root approximation", "use-reciprocal-square-root"),
323 FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
324 FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
325 FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
326 .ZczGp,
327 .ZczFp,
328 }),
329 FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
330 FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
331 FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
332 FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
333 .Lse,
334 .Rdm,
335 .Crc,
336 .Lor,
337 .Pan,
338 .Vh,
339 }),
340 FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
341 .Lse,
342 .Rdm,
343 .Pan,
344 .Crc,
345 .Lor,
346 .Uaops,
347 .Ras,
348 .Ccpp,
349 .Vh,
350 }),
351 FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
352 .Lse,
353 .Vh,
354 .Pa,
355 .Rdm,
356 .Pan,
357 .Crc,
358 .Lor,
359 .Uaops,
360 .Ras,
361 .Rcpc,
362 .Ccpp,
363 .Ccidx,
364 .FpArmv8,
365 }),
366 FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
367 .Rdm,
368 .Dit,
369 .Am,
370 .Ras,
371 .Rcpc,
372 .Sel2,
373 .Ccpp,
374 .Pa,
375 .Pan,
376 .Uaops,
377 .Tracev84,
378 .Mpam,
379 .Lse,
380 .Nv,
381 .Dotprod,
382 .TlbRmi,
383 .Lor,
384 .Ccidx,
385 .FpArmv8,
386 .Crc,
387 .Fmi,
388 .Vh,
389 }),
390 FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
391 .Vh,
392 .Rdm,
393 .Dit,
394 .Am,
395 .Ssbs,
396 .Specrestrict,
397 .Ras,
398 .Rcpc,
399 .Sel2,
400 .Ccpp,
401 .Pa,
402 .Bti,
403 .Ccdp,
404 .Pan,
405 .Uaops,
406 .Tracev84,
407 .Mpam,
408 .Lse,
409 .Sb,
410 .Nv,
411 .Altnzcv,
412 .Dotprod,
413 .TlbRmi,
414 .Lor,
415 .Ccidx,
416 .Predres,
417 .Crc,
418 .Fptoint,
419 .Fmi,
420 .FpArmv8,
421 }),
422 FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
423 .Perfmon,
424 .FpArmv8,
425 .Crc,
426 }),
427 FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
428 .Perfmon,
429 .UsePostraScheduler,
430 .Crc,
431 .CustomCheapAsMove,
432 .BalanceFpOps,
433 .UseAa,
434 .FpArmv8,
435 .FuseAes,
436 }),
437 FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
438 .Lse,
439 .Vh,
440 .Rdm,
441 .Perfmon,
442 .Pan,
443 .Dotprod,
444 .Crc,
445 .Lor,
446 .Uaops,
447 .Ras,
448 .Rcpc,
449 .Ccpp,
450 .FpArmv8,
451 .FuseAes,
452 }),
453 FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
454 .Perfmon,
455 .UsePostraScheduler,
456 .Crc,
457 .PredictableSelectExpensive,
458 .CustomCheapAsMove,
459 .BalanceFpOps,
460 .FuseLiterals,
461 .FpArmv8,
462 .FuseAes,
463 }),
464 FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
465 .Lse,
466 .Vh,
467 .Rdm,
468 .Pan,
469 .Dotprod,
470 .Crc,
471 .Ssbs,
472 .Lor,
473 .Uaops,
474 .Ras,
475 .Rcpc,
476 .Ccpp,
477 .FpArmv8,
478 }),
479 FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
480 .Perfmon,
481 .FpArmv8,
482 .Crc,
483 .FuseAes,
484 }),
485 FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
486 .Perfmon,
487 .FpArmv8,
488 .Crc,
489 .FuseAes,
490 }),
491 FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
492 .Lse,
493 .Vh,
494 .Rdm,
495 .Perfmon,
496 .Pan,
497 .Dotprod,
498 .Crc,
499 .Lor,
500 .Uaops,
501 .Ras,
502 .Rcpc,
503 .Ccpp,
504 .FpArmv8,
505 .FuseAes,
506 }),
507 FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
508 .Lse,
509 .Vh,
510 .Rdm,
511 .Pan,
512 .Dotprod,
513 .Crc,
514 .Ssbs,
515 .Lor,
516 .Uaops,
517 .Ras,
518 .Rcpc,
519 .Ccpp,
520 .FpArmv8,
521 }),
522 FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
523 .ArithBccFusion,
524 .ArithCbzFusion,
525 .ZczFp,
526 .AlternateSextloadCvtF32Pattern,
527 .DisableLatencySchedHeuristic,
528 .Perfmon,
529 .ZczGp,
530 .ZczFpWorkaround,
531 .Zcm,
532 .FpArmv8,
533 .FuseCryptoEor,
534 .FuseAes,
535 }),
536 FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
537 .ZczFp,
538 .Perfmon,
539 .UsePostraScheduler,
540 .Crc,
541 .UseReciprocalSquareRoot,
542 .CustomCheapAsMove,
543 .Force32bitJumpTables,
544 .SlowMisaligned128store,
545 .FpArmv8,
546 .SlowPaired128,
547 .FuseAes,
548 }),
549 FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
550 .ZczFp,
551 .Perfmon,
552 .UsePostraScheduler,
553 .Crc,
554 .CustomCheapAsMove,
555 .Force32bitJumpTables,
556 .SlowMisaligned128store,
557 .FpArmv8,
558 .SlowPaired128,
559 .FuseAes,
560 }),
561 FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
562 .FuseCsel,
563 .ZczFp,
564 .Perfmon,
565 .UsePostraScheduler,
566 .Crc,
567 .PredictableSelectExpensive,
568 .CustomCheapAsMove,
569 .Force32bitJumpTables,
570 .FuseLiterals,
571 .FuseAddress,
572 .LslFast,
573 .FpArmv8,
574 .FuseAes,
575 }),
576 FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
577 .ArithBccFusion,
578 .Vh,
579 .ArithCbzFusion,
580 .ZczFp,
581 .Rdm,
582 .UsePostraScheduler,
583 .Ras,
584 .Force32bitJumpTables,
585 .Ccpp,
586 .FuseCsel,
587 .Pan,
588 .Uaops,
589 .FuseLiterals,
590 .LslFast,
591 .Lse,
592 .Perfmon,
593 .Dotprod,
594 .Lor,
595 .FuseArithLogic,
596 .Crc,
597 .CustomCheapAsMove,
598 .FuseAddress,
599 .ZczGp,
600 .FpArmv8,
601 .FuseAes,
602 }),
603 FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
604 .ZczFp,
605 .Rdm,
606 .Perfmon,
607 .UsePostraScheduler,
608 .Crc,
609 .PredictableSelectExpensive,
610 .CustomCheapAsMove,
611 .ZczGp,
612 .FpArmv8,
613 .SlowStrqroStore,
614 .LslFast,
615 }),
616 FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
617 .ZczFp,
618 .Perfmon,
619 .UsePostraScheduler,
620 .Crc,
621 .PredictableSelectExpensive,
622 .CustomCheapAsMove,
623 .ZczGp,
624 .FpArmv8,
625 .LslFast,
626 }),
627 FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
628 .Lse,
629 .Vh,
630 .Rdm,
631 .Pan,
632 .Dotprod,
633 .Crc,
634 .Ssbs,
635 .Lor,
636 .Uaops,
637 .Ras,
638 .Rcpc,
639 .Ccpp,
640 .FpArmv8,
641 }),
642 FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
643 .Lse,
644 .Spe,
645 .Vh,
646 .Rdm,
647 .Pan,
648 .Dotprod,
649 .Crc,
650 .Ssbs,
651 .Lor,
652 .Uaops,
653 .Ras,
654 .Rcpc,
655 .Ccpp,
656 .FpArmv8,
657 }),
658 FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
659 .Spe,
660 .Vh,
661 .ZczFp,
662 .Rdm,
663 .UsePostraScheduler,
664 .Dit,
665 .Am,
666 .Ras,
667 .Rcpc,
668 .Sel2,
669 .Ccpp,
670 .Pa,
671 .Pan,
672 .Uaops,
673 .Tracev84,
674 .Mpam,
675 .LslFast,
676 .Lse,
677 .Nv,
678 .Perfmon,
679 .Dotprod,
680 .TlbRmi,
681 .Lor,
682 .Ccidx,
683 .PredictableSelectExpensive,
684 .Crc,
685 .CustomCheapAsMove,
686 .Fmi,
687 .ZczGp,
688 .FpArmv8,
689 }),
690 FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
691 .Lse,
692 .Spe,
693 .Vh,
694 .Rdm,
695 .Perfmon,
696 .UsePostraScheduler,
697 .Pan,
698 .Dotprod,
699 .Crc,
700 .Lor,
701 .Uaops,
702 .CustomCheapAsMove,
703 .Ras,
704 .Ccpp,
705 .FpArmv8,
706 .FuseAes,
707 }),
708 FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
709 .Perfmon,
710 .UsePostraScheduler,
711 .Crc,
712 .FpArmv8,
713 .PredictableSelectExpensive,
714 }),
715 FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
716 .Lse,
717 .ArithBccFusion,
718 .Vh,
719 .Rdm,
720 .UsePostraScheduler,
721 .Crc,
722 .Lor,
723 .Pan,
724 .AggressiveFma,
725 .FpArmv8,
726 .PredictableSelectExpensive,
727 }),
728 FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
729 .Perfmon,
730 .UsePostraScheduler,
731 .Crc,
732 .FpArmv8,
733 .PredictableSelectExpensive,
734 }),
735 FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
736 .Perfmon,
737 .UsePostraScheduler,
738 .Crc,
739 .FpArmv8,
740 .PredictableSelectExpensive,
741 }),
742 FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
743 .Perfmon,
744 .UsePostraScheduler,
745 .Crc,
746 .FpArmv8,
747 .PredictableSelectExpensive,
748 }),
749 };
750};
lib/std/target/feature/AmdGpuFeature.zig deleted-343
......@@ -1,343 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const AmdGpuFeature = enum {
4 BitInsts16,
5 AddNoCarryInsts,
6 ApertureRegs,
7 AtomicFaddInsts,
8 AutoWaitcntBeforeBarrier,
9 CiInsts,
10 CodeObjectV3,
11 Cumode,
12 DlInsts,
13 Dpp,
14 Dpp8,
15 NoSramEccSupport,
16 NoXnackSupport,
17 Dot1Insts,
18 Dot2Insts,
19 Dot3Insts,
20 Dot4Insts,
21 Dot5Insts,
22 Dot6Insts,
23 DumpCode,
24 Dumpcode,
25 EnableDs128,
26 LoadStoreOpt,
27 EnablePrtStrictNull,
28 SiScheduler,
29 UnsafeDsOffsetFolding,
30 Fmaf,
31 Fp16Denormals,
32 Fp32Denormals,
33 Fp64,
34 Fp64Denormals,
35 Fp64Fp16Denormals,
36 FpExceptions,
37 FastFmaf,
38 FlatAddressSpace,
39 FlatForGlobal,
40 FlatGlobalInsts,
41 FlatInstOffsets,
42 FlatScratchInsts,
43 FlatSegmentOffsetBug,
44 FmaMixInsts,
45 Gcn3Encoding,
46 Gfx7Gfx8Gfx9Insts,
47 Gfx8Insts,
48 Gfx9,
49 Gfx9Insts,
50 Gfx10,
51 Gfx10Insts,
52 InstFwdPrefetchBug,
53 IntClampInsts,
54 Inv2piInlineImm,
55 Ldsbankcount16,
56 Ldsbankcount32,
57 LdsBranchVmemWarHazard,
58 LdsMisalignedBug,
59 Localmemorysize0,
60 Localmemorysize32768,
61 Localmemorysize65536,
62 MaiInsts,
63 MfmaInlineLiteralBug,
64 MimgR128,
65 MadMixInsts,
66 MaxPrivateElementSize4,
67 MaxPrivateElementSize8,
68 MaxPrivateElementSize16,
69 Movrel,
70 NsaEncoding,
71 NsaToVmemBug,
72 NoDataDepHazard,
73 NoSdstCmpx,
74 Offset3fBug,
75 PkFmacF16Inst,
76 PromoteAlloca,
77 R128A16,
78 RegisterBanking,
79 Sdwa,
80 SdwaMav,
81 SdwaOmod,
82 SdwaOutModsVopc,
83 SdwaScalar,
84 SdwaSdst,
85 SgprInitBug,
86 SmemToVectorWriteHazard,
87 SMemrealtime,
88 SramEcc,
89 ScalarAtomics,
90 ScalarFlatScratchInsts,
91 ScalarStores,
92 SeaIslands,
93 SouthernIslands,
94 TrapHandler,
95 TrigReducedRange,
96 UnalignedBufferAccess,
97 UnalignedScratchAccess,
98 UnpackedD16Vmem,
99 VgprIndexMode,
100 VmemToScalarWriteHazard,
101 Vop3Literal,
102 Vop3p,
103 VcmpxExecWarHazard,
104 VcmpxPermlaneHazard,
105 VolcanicIslands,
106 Vscnt,
107 Wavefrontsize16,
108 Wavefrontsize32,
109 Wavefrontsize64,
110 Xnack,
111 HalfRate64Ops,
112
113 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
114 return feature_infos[@enumToInt(self)];
115 }
116
117 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
118 FeatureInfo(@This()).create(.BitInsts16, "16-bit-insts", "Has i16/f16 instructions", "16-bit-insts"),
119 FeatureInfo(@This()).create(.AddNoCarryInsts, "add-no-carry-insts", "Have VALU add/sub instructions without carry out", "add-no-carry-insts"),
120 FeatureInfo(@This()).create(.ApertureRegs, "aperture-regs", "Has Memory Aperture Base and Size Registers", "aperture-regs"),
121 FeatureInfo(@This()).create(.AtomicFaddInsts, "atomic-fadd-insts", "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", "atomic-fadd-insts"),
122 FeatureInfo(@This()).create(.AutoWaitcntBeforeBarrier, "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", "auto-waitcnt-before-barrier"),
123 FeatureInfo(@This()).create(.CiInsts, "ci-insts", "Additional instructions for CI+", "ci-insts"),
124 FeatureInfo(@This()).create(.CodeObjectV3, "code-object-v3", "Generate code object version 3", "code-object-v3"),
125 FeatureInfo(@This()).create(.Cumode, "cumode", "Enable CU wavefront execution mode", "cumode"),
126 FeatureInfo(@This()).create(.DlInsts, "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", "dl-insts"),
127 FeatureInfo(@This()).create(.Dpp, "dpp", "Support DPP (Data Parallel Primitives) extension", "dpp"),
128 FeatureInfo(@This()).create(.Dpp8, "dpp8", "Support DPP8 (Data Parallel Primitives) extension", "dpp8"),
129 FeatureInfo(@This()).create(.NoSramEccSupport, "no-sram-ecc-support", "Hardware does not support SRAM ECC", "no-sram-ecc-support"),
130 FeatureInfo(@This()).create(.NoXnackSupport, "no-xnack-support", "Hardware does not support XNACK", "no-xnack-support"),
131 FeatureInfo(@This()).create(.Dot1Insts, "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", "dot1-insts"),
132 FeatureInfo(@This()).create(.Dot2Insts, "dot2-insts", "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", "dot2-insts"),
133 FeatureInfo(@This()).create(.Dot3Insts, "dot3-insts", "Has v_dot8c_i32_i4 instruction", "dot3-insts"),
134 FeatureInfo(@This()).create(.Dot4Insts, "dot4-insts", "Has v_dot2c_i32_i16 instruction", "dot4-insts"),
135 FeatureInfo(@This()).create(.Dot5Insts, "dot5-insts", "Has v_dot2c_f32_f16 instruction", "dot5-insts"),
136 FeatureInfo(@This()).create(.Dot6Insts, "dot6-insts", "Has v_dot4c_i32_i8 instruction", "dot6-insts"),
137 FeatureInfo(@This()).create(.DumpCode, "DumpCode", "Dump MachineInstrs in the CodeEmitter", "DumpCode"),
138 FeatureInfo(@This()).create(.Dumpcode, "dumpcode", "Dump MachineInstrs in the CodeEmitter", "dumpcode"),
139 FeatureInfo(@This()).create(.EnableDs128, "enable-ds128", "Use ds_{read|write}_b128", "enable-ds128"),
140 FeatureInfo(@This()).create(.LoadStoreOpt, "load-store-opt", "Enable SI load/store optimizer pass", "load-store-opt"),
141 FeatureInfo(@This()).create(.EnablePrtStrictNull, "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", "enable-prt-strict-null"),
142 FeatureInfo(@This()).create(.SiScheduler, "si-scheduler", "Enable SI Machine Scheduler", "si-scheduler"),
143 FeatureInfo(@This()).create(.UnsafeDsOffsetFolding, "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", "unsafe-ds-offset-folding"),
144 FeatureInfo(@This()).create(.Fmaf, "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", "fmaf"),
145 FeatureInfo(@This()).createWithSubfeatures(.Fp16Denormals, "fp16-denormals", "Enable half precision denormal handling", "fp16-denormals", &[_]@This() {
146 .Fp64,
147 }),
148 FeatureInfo(@This()).create(.Fp32Denormals, "fp32-denormals", "Enable single precision denormal handling", "fp32-denormals"),
149 FeatureInfo(@This()).create(.Fp64, "fp64", "Enable double precision operations", "fp64"),
150 FeatureInfo(@This()).createWithSubfeatures(.Fp64Denormals, "fp64-denormals", "Enable double and half precision denormal handling", "fp64-denormals", &[_]@This() {
151 .Fp64,
152 }),
153 FeatureInfo(@This()).createWithSubfeatures(.Fp64Fp16Denormals, "fp64-fp16-denormals", "Enable double and half precision denormal handling", "fp64-fp16-denormals", &[_]@This() {
154 .Fp64,
155 }),
156 FeatureInfo(@This()).create(.FpExceptions, "fp-exceptions", "Enable floating point exceptions", "fp-exceptions"),
157 FeatureInfo(@This()).create(.FastFmaf, "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", "fast-fmaf"),
158 FeatureInfo(@This()).create(.FlatAddressSpace, "flat-address-space", "Support flat address space", "flat-address-space"),
159 FeatureInfo(@This()).create(.FlatForGlobal, "flat-for-global", "Force to generate flat instruction for global", "flat-for-global"),
160 FeatureInfo(@This()).create(.FlatGlobalInsts, "flat-global-insts", "Have global_* flat memory instructions", "flat-global-insts"),
161 FeatureInfo(@This()).create(.FlatInstOffsets, "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", "flat-inst-offsets"),
162 FeatureInfo(@This()).create(.FlatScratchInsts, "flat-scratch-insts", "Have scratch_* flat memory instructions", "flat-scratch-insts"),
163 FeatureInfo(@This()).create(.FlatSegmentOffsetBug, "flat-segment-offset-bug", "GFX10 bug, inst_offset ignored in flat segment", "flat-segment-offset-bug"),
164 FeatureInfo(@This()).create(.FmaMixInsts, "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", "fma-mix-insts"),
165 FeatureInfo(@This()).create(.Gcn3Encoding, "gcn3-encoding", "Encoding format for VI", "gcn3-encoding"),
166 FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
167 FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
168 FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
169 .ApertureRegs,
170 .IntClampInsts,
171 .SdwaOmod,
172 .SdwaScalar,
173 .AddNoCarryInsts,
174 .ScalarAtomics,
175 .SMemrealtime,
176 .Gcn3Encoding,
177 .CiInsts,
178 .FlatAddressSpace,
179 .Sdwa,
180 .Wavefrontsize64,
181 .SdwaSdst,
182 .FlatInstOffsets,
183 .ScalarStores,
184 .Gfx7Gfx8Gfx9Insts,
185 .R128A16,
186 .Dpp,
187 .Localmemorysize65536,
188 .Vop3p,
189 .BitInsts16,
190 .VgprIndexMode,
191 .Gfx8Insts,
192 .Inv2piInlineImm,
193 .Gfx9Insts,
194 .ScalarFlatScratchInsts,
195 .FlatGlobalInsts,
196 .FlatScratchInsts,
197 .Fp64,
198 .FastFmaf,
199 }),
200 FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
201 FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
202 .Vscnt,
203 .ApertureRegs,
204 .Gfx10Insts,
205 .IntClampInsts,
206 .PkFmacF16Inst,
207 .SdwaOmod,
208 .SdwaScalar,
209 .AddNoCarryInsts,
210 .Movrel,
211 .SMemrealtime,
212 .NoSdstCmpx,
213 .CiInsts,
214 .FlatAddressSpace,
215 .Sdwa,
216 .NoSramEccSupport,
217 .SdwaSdst,
218 .FlatInstOffsets,
219 .RegisterBanking,
220 .Dpp,
221 .Localmemorysize65536,
222 .Vop3p,
223 .BitInsts16,
224 .Dpp8,
225 .Gfx8Insts,
226 .Inv2piInlineImm,
227 .Gfx9Insts,
228 .FmaMixInsts,
229 .MimgR128,
230 .Vop3Literal,
231 .FlatGlobalInsts,
232 .FlatScratchInsts,
233 .Fp64,
234 .FastFmaf,
235 .NoDataDepHazard,
236 }),
237 FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
238 FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
239 FeatureInfo(@This()).create(.IntClampInsts, "int-clamp-insts", "Support clamp for integer destination", "int-clamp-insts"),
240 FeatureInfo(@This()).create(.Inv2piInlineImm, "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", "inv-2pi-inline-imm"),
241 FeatureInfo(@This()).create(.Ldsbankcount16, "ldsbankcount16", "The number of LDS banks per compute unit.", "ldsbankcount16"),
242 FeatureInfo(@This()).create(.Ldsbankcount32, "ldsbankcount32", "The number of LDS banks per compute unit.", "ldsbankcount32"),
243 FeatureInfo(@This()).create(.LdsBranchVmemWarHazard, "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", "lds-branch-vmem-war-hazard"),
244 FeatureInfo(@This()).create(.LdsMisalignedBug, "lds-misaligned-bug", "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode", "lds-misaligned-bug"),
245 FeatureInfo(@This()).create(.Localmemorysize0, "localmemorysize0", "The size of local memory in bytes", "localmemorysize0"),
246 FeatureInfo(@This()).create(.Localmemorysize32768, "localmemorysize32768", "The size of local memory in bytes", "localmemorysize32768"),
247 FeatureInfo(@This()).create(.Localmemorysize65536, "localmemorysize65536", "The size of local memory in bytes", "localmemorysize65536"),
248 FeatureInfo(@This()).create(.MaiInsts, "mai-insts", "Has mAI instructions", "mai-insts"),
249 FeatureInfo(@This()).create(.MfmaInlineLiteralBug, "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", "mfma-inline-literal-bug"),
250 FeatureInfo(@This()).create(.MimgR128, "mimg-r128", "Support 128-bit texture resources", "mimg-r128"),
251 FeatureInfo(@This()).create(.MadMixInsts, "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", "mad-mix-insts"),
252 FeatureInfo(@This()).create(.MaxPrivateElementSize4, "max-private-element-size-4", "Maximum private access size may be 4", "max-private-element-size-4"),
253 FeatureInfo(@This()).create(.MaxPrivateElementSize8, "max-private-element-size-8", "Maximum private access size may be 8", "max-private-element-size-8"),
254 FeatureInfo(@This()).create(.MaxPrivateElementSize16, "max-private-element-size-16", "Maximum private access size may be 16", "max-private-element-size-16"),
255 FeatureInfo(@This()).create(.Movrel, "movrel", "Has v_movrel*_b32 instructions", "movrel"),
256 FeatureInfo(@This()).create(.NsaEncoding, "nsa-encoding", "Support NSA encoding for image instructions", "nsa-encoding"),
257 FeatureInfo(@This()).create(.NsaToVmemBug, "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", "nsa-to-vmem-bug"),
258 FeatureInfo(@This()).create(.NoDataDepHazard, "no-data-dep-hazard", "Does not need SW waitstates", "no-data-dep-hazard"),
259 FeatureInfo(@This()).create(.NoSdstCmpx, "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", "no-sdst-cmpx"),
260 FeatureInfo(@This()).create(.Offset3fBug, "offset-3f-bug", "Branch offset of 3f hardware bug", "offset-3f-bug"),
261 FeatureInfo(@This()).create(.PkFmacF16Inst, "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", "pk-fmac-f16-inst"),
262 FeatureInfo(@This()).create(.PromoteAlloca, "promote-alloca", "Enable promote alloca pass", "promote-alloca"),
263 FeatureInfo(@This()).create(.R128A16, "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", "r128-a16"),
264 FeatureInfo(@This()).create(.RegisterBanking, "register-banking", "Has register banking", "register-banking"),
265 FeatureInfo(@This()).create(.Sdwa, "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", "sdwa"),
266 FeatureInfo(@This()).create(.SdwaMav, "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", "sdwa-mav"),
267 FeatureInfo(@This()).create(.SdwaOmod, "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", "sdwa-omod"),
268 FeatureInfo(@This()).create(.SdwaOutModsVopc, "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-out-mods-vopc"),
269 FeatureInfo(@This()).create(.SdwaScalar, "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", "sdwa-scalar"),
270 FeatureInfo(@This()).create(.SdwaSdst, "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-sdst"),
271 FeatureInfo(@This()).create(.SgprInitBug, "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", "sgpr-init-bug"),
272 FeatureInfo(@This()).create(.SmemToVectorWriteHazard, "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", "smem-to-vector-write-hazard"),
273 FeatureInfo(@This()).create(.SMemrealtime, "s-memrealtime", "Has s_memrealtime instruction", "s-memrealtime"),
274 FeatureInfo(@This()).create(.SramEcc, "sram-ecc", "Enable SRAM ECC", "sram-ecc"),
275 FeatureInfo(@This()).create(.ScalarAtomics, "scalar-atomics", "Has atomic scalar memory instructions", "scalar-atomics"),
276 FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
277 FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
278 FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
279 .Movrel,
280 .Gfx7Gfx8Gfx9Insts,
281 .Fp64,
282 .TrigReducedRange,
283 .CiInsts,
284 .FlatAddressSpace,
285 .Localmemorysize65536,
286 .Wavefrontsize64,
287 .NoSramEccSupport,
288 .MimgR128,
289 }),
290 FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
291 .Movrel,
292 .MimgR128,
293 .Fp64,
294 .TrigReducedRange,
295 .NoXnackSupport,
296 .Wavefrontsize64,
297 .NoSramEccSupport,
298 .Ldsbankcount32,
299 .Localmemorysize32768,
300 }),
301 FeatureInfo(@This()).create(.TrapHandler, "trap-handler", "Trap handler support", "trap-handler"),
302 FeatureInfo(@This()).create(.TrigReducedRange, "trig-reduced-range", "Requires use of fract on arguments to trig instructions", "trig-reduced-range"),
303 FeatureInfo(@This()).create(.UnalignedBufferAccess, "unaligned-buffer-access", "Support unaligned global loads and stores", "unaligned-buffer-access"),
304 FeatureInfo(@This()).create(.UnalignedScratchAccess, "unaligned-scratch-access", "Support unaligned scratch loads and stores", "unaligned-scratch-access"),
305 FeatureInfo(@This()).create(.UnpackedD16Vmem, "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", "unpacked-d16-vmem"),
306 FeatureInfo(@This()).create(.VgprIndexMode, "vgpr-index-mode", "Has VGPR mode register indexing", "vgpr-index-mode"),
307 FeatureInfo(@This()).create(.VmemToScalarWriteHazard, "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", "vmem-to-scalar-write-hazard"),
308 FeatureInfo(@This()).create(.Vop3Literal, "vop3-literal", "Can use one literal in VOP3", "vop3-literal"),
309 FeatureInfo(@This()).create(.Vop3p, "vop3p", "Has VOP3P packed instructions", "vop3p"),
310 FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
311 FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
312 FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
313 .IntClampInsts,
314 .SdwaMav,
315 .Movrel,
316 .SMemrealtime,
317 .Gcn3Encoding,
318 .TrigReducedRange,
319 .CiInsts,
320 .FlatAddressSpace,
321 .Sdwa,
322 .Wavefrontsize64,
323 .NoSramEccSupport,
324 .ScalarStores,
325 .Gfx7Gfx8Gfx9Insts,
326 .Dpp,
327 .Localmemorysize65536,
328 .BitInsts16,
329 .VgprIndexMode,
330 .Gfx8Insts,
331 .Inv2piInlineImm,
332 .MimgR128,
333 .SdwaOutModsVopc,
334 .Fp64,
335 }),
336 FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
337 FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),
338 FeatureInfo(@This()).create(.Wavefrontsize32, "wavefrontsize32", "The number of threads per wavefront", "wavefrontsize32"),
339 FeatureInfo(@This()).create(.Wavefrontsize64, "wavefrontsize64", "The number of threads per wavefront", "wavefrontsize64"),
340 FeatureInfo(@This()).create(.Xnack, "xnack", "Enable XNACK support", "xnack"),
341 FeatureInfo(@This()).create(.HalfRate64Ops, "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", "half-rate-64-ops"),
342 };
343};
lib/std/target/feature/ArmFeature.zig deleted-818
......@@ -1,818 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const ArmFeature = enum {
4 Armv2,
5 Armv2a,
6 Armv3,
7 Armv3m,
8 Armv4,
9 Armv4t,
10 Armv5t,
11 Armv5te,
12 Armv5tej,
13 Armv6,
14 Armv6j,
15 Armv6k,
16 Armv6kz,
17 Armv6M,
18 Armv6sM,
19 Armv6t2,
20 Armv7A,
21 Armv7eM,
22 Armv7k,
23 Armv7M,
24 Armv7R,
25 Armv7s,
26 Armv7ve,
27 Armv8A,
28 Armv8Mbase,
29 Armv8Mmain,
30 Armv8R,
31 Armv81A,
32 Armv81Mmain,
33 Armv82A,
34 Armv83A,
35 Armv84A,
36 Armv85A,
37 Msecext8,
38 Aclass,
39 Aes,
40 AcquireRelease,
41 AvoidMovsShop,
42 AvoidPartialCpsr,
43 Crc,
44 CheapPredicableCpsr,
45 VldnAlign,
46 Crypto,
47 D32,
48 Db,
49 Dfb,
50 Dsp,
51 DontWidenVmovs,
52 Dotprod,
53 ExecuteOnly,
54 ExpandFpMlx,
55 Fp16,
56 Fp16fml,
57 Fp64,
58 Fpao,
59 FpArmv8,
60 FpArmv8d16,
61 FpArmv8d16sp,
62 FpArmv8sp,
63 Fpregs,
64 Fpregs16,
65 Fpregs64,
66 Fullfp16,
67 FuseAes,
68 FuseLiterals,
69 HwdivArm,
70 Hwdiv,
71 NoBranchPredictor,
72 RetAddrStack,
73 Slowfpvmlx,
74 VmlxHazards,
75 Lob,
76 LongCalls,
77 Mclass,
78 Mp,
79 Mve1beat,
80 Mve2beat,
81 Mve4beat,
82 MuxedUnits,
83 Neon,
84 Neonfp,
85 NeonFpmovs,
86 NaclTrap,
87 Noarm,
88 NoMovt,
89 NoNegImmediates,
90 DisablePostraScheduler,
91 NonpipelinedVfp,
92 Perfmon,
93 Bit32,
94 PreferIshst,
95 LoopAlign,
96 PreferVmovsr,
97 ProfUnpr,
98 Ras,
99 Rclass,
100 ReadTpHard,
101 ReserveR9,
102 Sb,
103 Sha2,
104 SlowFpBrcc,
105 SlowLoadDSubreg,
106 SlowOddReg,
107 SlowVdup32,
108 SlowVgetlni32,
109 SplatVfpNeon,
110 StrictAlign,
111 Thumb2,
112 Trustzone,
113 UseAa,
114 UseMisched,
115 WideStrideVfp,
116 V7clrex,
117 Vfp2,
118 Vfp2sp,
119 Vfp3,
120 Vfp3d16,
121 Vfp3d16sp,
122 Vfp3sp,
123 Vfp4,
124 Vfp4d16,
125 Vfp4d16sp,
126 Vfp4sp,
127 VmlxForwarding,
128 Virtualization,
129 Zcz,
130 Mvefp,
131 Mve,
132 V4t,
133 V5te,
134 V5t,
135 V6k,
136 V6m,
137 V6,
138 V6t2,
139 V7,
140 V8m,
141 V8mmain,
142 V8,
143 V81mmain,
144 V81a,
145 V82a,
146 V83a,
147 V84a,
148 V85a,
149 Iwmmxt,
150 Iwmmxt2,
151 SoftFloat,
152 ThumbMode,
153 A5,
154 A7,
155 A8,
156 A9,
157 A12,
158 A15,
159 A17,
160 A32,
161 A35,
162 A53,
163 A55,
164 A57,
165 A72,
166 A73,
167 A75,
168 A76,
169 Exynos,
170 Krait,
171 Kryo,
172 M3,
173 R4,
174 R5,
175 R7,
176 R52,
177 Swift,
178 Xscale,
179
180 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
181 return feature_infos[@enumToInt(self)];
182 }
183
184 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
185 FeatureInfo(@This()).create(.Armv2, "armv2", "ARMv2 architecture", "armv2"),
186 FeatureInfo(@This()).create(.Armv2a, "armv2a", "ARMv2a architecture", "armv2a"),
187 FeatureInfo(@This()).create(.Armv3, "armv3", "ARMv3 architecture", "armv3"),
188 FeatureInfo(@This()).create(.Armv3m, "armv3m", "ARMv3m architecture", "armv3m"),
189 FeatureInfo(@This()).create(.Armv4, "armv4", "ARMv4 architecture", "armv4"),
190 FeatureInfo(@This()).createWithSubfeatures(.Armv4t, "armv4t", "ARMv4t architecture", "armv4t", &[_]@This() {
191 .V4t,
192 }),
193 FeatureInfo(@This()).createWithSubfeatures(.Armv5t, "armv5t", "ARMv5t architecture", "armv5t", &[_]@This() {
194 .V4t,
195 }),
196 FeatureInfo(@This()).createWithSubfeatures(.Armv5te, "armv5te", "ARMv5te architecture", "armv5te", &[_]@This() {
197 .V4t,
198 }),
199 FeatureInfo(@This()).createWithSubfeatures(.Armv5tej, "armv5tej", "ARMv5tej architecture", "armv5tej", &[_]@This() {
200 .V4t,
201 }),
202 FeatureInfo(@This()).createWithSubfeatures(.Armv6, "armv6", "ARMv6 architecture", "armv6", &[_]@This() {
203 .V4t,
204 .Dsp,
205 }),
206 FeatureInfo(@This()).createWithSubfeatures(.Armv6j, "armv6j", "ARMv7a architecture", "armv6j", &[_]@This() {
207 .V4t,
208 .Dsp,
209 }),
210 FeatureInfo(@This()).createWithSubfeatures(.Armv6k, "armv6k", "ARMv6k architecture", "armv6k", &[_]@This() {
211 .V4t,
212 }),
213 FeatureInfo(@This()).createWithSubfeatures(.Armv6kz, "armv6kz", "ARMv6kz architecture", "armv6kz", &[_]@This() {
214 .V4t,
215 .Trustzone,
216 }),
217 FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
218 .V4t,
219 .ThumbMode,
220 .Db,
221 .StrictAlign,
222 .Mclass,
223 .Noarm,
224 }),
225 FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
226 .V4t,
227 .ThumbMode,
228 .Db,
229 .StrictAlign,
230 .Mclass,
231 .Noarm,
232 }),
233 FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
234 .V4t,
235 .Thumb2,
236 .Dsp,
237 }),
238 FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
239 .Perfmon,
240 .V4t,
241 .D32,
242 .Fpregs,
243 .V7clrex,
244 .Dsp,
245 .Thumb2,
246 .Db,
247 .Aclass,
248 }),
249 FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
250 .Perfmon,
251 .V4t,
252 .ThumbMode,
253 .V7clrex,
254 .Dsp,
255 .Thumb2,
256 .Db,
257 .Mclass,
258 .Noarm,
259 .Hwdiv,
260 }),
261 FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
262 .Perfmon,
263 .V4t,
264 .D32,
265 .Fpregs,
266 .V7clrex,
267 .Dsp,
268 .Thumb2,
269 .Db,
270 .Aclass,
271 }),
272 FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
273 .Perfmon,
274 .V4t,
275 .ThumbMode,
276 .V7clrex,
277 .Thumb2,
278 .Db,
279 .Mclass,
280 .Noarm,
281 .Hwdiv,
282 }),
283 FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
284 .Perfmon,
285 .V4t,
286 .V7clrex,
287 .Dsp,
288 .Thumb2,
289 .Db,
290 .Hwdiv,
291 .Rclass,
292 }),
293 FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
294 .Perfmon,
295 .V4t,
296 .D32,
297 .Fpregs,
298 .V7clrex,
299 .Dsp,
300 .Thumb2,
301 .Db,
302 .Aclass,
303 }),
304 FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
305 .HwdivArm,
306 .Perfmon,
307 .D32,
308 .Mp,
309 .Fpregs,
310 .V4t,
311 .V7clrex,
312 .Dsp,
313 .Thumb2,
314 .Db,
315 .Aclass,
316 .Hwdiv,
317 .Trustzone,
318 }),
319 FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
320 .HwdivArm,
321 .Perfmon,
322 .D32,
323 .Fpregs,
324 .Crc,
325 .Mp,
326 .Fp16,
327 .Dsp,
328 .V4t,
329 .V7clrex,
330 .Db,
331 .Aclass,
332 .Thumb2,
333 .AcquireRelease,
334 .Hwdiv,
335 .Trustzone,
336 }),
337 FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
338 .V4t,
339 .ThumbMode,
340 .Msecext8,
341 .V7clrex,
342 .Db,
343 .StrictAlign,
344 .Mclass,
345 .Noarm,
346 .AcquireRelease,
347 .Hwdiv,
348 }),
349 FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
350 .Perfmon,
351 .V4t,
352 .ThumbMode,
353 .Msecext8,
354 .V7clrex,
355 .Thumb2,
356 .Db,
357 .Mclass,
358 .Noarm,
359 .AcquireRelease,
360 .Hwdiv,
361 }),
362 FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
363 .HwdivArm,
364 .Perfmon,
365 .D32,
366 .Crc,
367 .Fpregs,
368 .Mp,
369 .Dfb,
370 .Dsp,
371 .Fp16,
372 .V4t,
373 .Db,
374 .V7clrex,
375 .Thumb2,
376 .AcquireRelease,
377 .Hwdiv,
378 .Rclass,
379 }),
380 FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
381 .HwdivArm,
382 .Perfmon,
383 .D32,
384 .Fpregs,
385 .Crc,
386 .Mp,
387 .Fp16,
388 .Dsp,
389 .V4t,
390 .V7clrex,
391 .Db,
392 .Aclass,
393 .Thumb2,
394 .AcquireRelease,
395 .Hwdiv,
396 .Trustzone,
397 }),
398 FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
399 .Perfmon,
400 .V4t,
401 .ThumbMode,
402 .Msecext8,
403 .V7clrex,
404 .Thumb2,
405 .Db,
406 .Ras,
407 .Mclass,
408 .Noarm,
409 .AcquireRelease,
410 .Hwdiv,
411 .Lob,
412 }),
413 FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
414 .HwdivArm,
415 .Perfmon,
416 .D32,
417 .Fpregs,
418 .Crc,
419 .Mp,
420 .Fp16,
421 .Dsp,
422 .V4t,
423 .V7clrex,
424 .Db,
425 .Aclass,
426 .Thumb2,
427 .Ras,
428 .AcquireRelease,
429 .Hwdiv,
430 .Trustzone,
431 }),
432 FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
433 .HwdivArm,
434 .Perfmon,
435 .D32,
436 .Fpregs,
437 .Crc,
438 .Mp,
439 .Fp16,
440 .Dsp,
441 .V4t,
442 .V7clrex,
443 .Db,
444 .Aclass,
445 .Thumb2,
446 .Ras,
447 .AcquireRelease,
448 .Hwdiv,
449 .Trustzone,
450 }),
451 FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
452 .HwdivArm,
453 .Perfmon,
454 .D32,
455 .Fpregs,
456 .Crc,
457 .Mp,
458 .Fp16,
459 .Dsp,
460 .V4t,
461 .V7clrex,
462 .Db,
463 .Aclass,
464 .Thumb2,
465 .Ras,
466 .AcquireRelease,
467 .Hwdiv,
468 .Trustzone,
469 }),
470 FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
471 .HwdivArm,
472 .Perfmon,
473 .D32,
474 .Fpregs,
475 .Crc,
476 .Mp,
477 .Fp16,
478 .Dsp,
479 .V4t,
480 .V7clrex,
481 .Db,
482 .Aclass,
483 .Thumb2,
484 .Ras,
485 .Sb,
486 .AcquireRelease,
487 .Hwdiv,
488 .Trustzone,
489 }),
490 FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
491 FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
492 FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
493 .D32,
494 .Fpregs,
495 }),
496 FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
497 FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
498 FeatureInfo(@This()).create(.AvoidPartialCpsr, "avoid-partial-cpsr", "Avoid CPSR partial update for OOO execution", "avoid-partial-cpsr"),
499 FeatureInfo(@This()).create(.Crc, "crc", "Enable support for CRC instructions", "crc"),
500 FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
501 FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
502 FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
503 .D32,
504 .Fpregs,
505 }),
506 FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
507 FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
508 FeatureInfo(@This()).create(.Dfb, "dfb", "Has full data barrier (dfb) instruction", "dfb"),
509 FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
510 FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
511 FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
512 .D32,
513 .Fpregs,
514 }),
515 FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
516 FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
517 FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
518 FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
519 .Fpregs,
520 .Fp16,
521 }),
522 FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
523 .Fpregs,
524 }),
525 FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
526 FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
527 .D32,
528 .Fpregs,
529 .Fp16,
530 }),
531 FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
532 .Fpregs,
533 .Fp16,
534 }),
535 FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
536 .Fpregs,
537 .Fp16,
538 }),
539 FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
540 .D32,
541 .Fpregs,
542 .Fp16,
543 }),
544 FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
545 FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
546 .Fpregs,
547 }),
548 FeatureInfo(@This()).createWithSubfeatures(.Fpregs64, "fpregs64", "Enable 64-bit FP registers", "fpregs64", &[_]@This() {
549 .Fpregs,
550 }),
551 FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
552 .Fpregs,
553 .Fp16,
554 }),
555 FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
556 FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
557 FeatureInfo(@This()).create(.HwdivArm, "hwdiv-arm", "Enable divide instructions in ARM mode", "hwdiv-arm"),
558 FeatureInfo(@This()).create(.Hwdiv, "hwdiv", "Enable divide instructions in Thumb", "hwdiv"),
559 FeatureInfo(@This()).create(.NoBranchPredictor, "no-branch-predictor", "Has no branch predictor", "no-branch-predictor"),
560 FeatureInfo(@This()).create(.RetAddrStack, "ret-addr-stack", "Has return address stack", "ret-addr-stack"),
561 FeatureInfo(@This()).create(.Slowfpvmlx, "slowfpvmlx", "Disable VFP / NEON MAC instructions", "slowfpvmlx"),
562 FeatureInfo(@This()).create(.VmlxHazards, "vmlx-hazards", "Has VMLx hazards", "vmlx-hazards"),
563 FeatureInfo(@This()).create(.Lob, "lob", "Enable Low Overhead Branch extensions", "lob"),
564 FeatureInfo(@This()).create(.LongCalls, "long-calls", "Generate calls via indirect call instructions", "long-calls"),
565 FeatureInfo(@This()).create(.Mclass, "mclass", "Is microcontroller profile ('M' series)", "mclass"),
566 FeatureInfo(@This()).create(.Mp, "mp", "Supports Multiprocessing extension", "mp"),
567 FeatureInfo(@This()).create(.Mve1beat, "mve1beat", "Model MVE instructions as a 1 beat per tick architecture", "mve1beat"),
568 FeatureInfo(@This()).create(.Mve2beat, "mve2beat", "Model MVE instructions as a 2 beats per tick architecture", "mve2beat"),
569 FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
570 FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
571 FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
572 .D32,
573 .Fpregs,
574 }),
575 FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
576 FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
577 FeatureInfo(@This()).create(.NaclTrap, "nacl-trap", "NaCl trap", "nacl-trap"),
578 FeatureInfo(@This()).create(.Noarm, "noarm", "Does not support ARM mode execution", "noarm"),
579 FeatureInfo(@This()).create(.NoMovt, "no-movt", "Don't use movt/movw pairs for 32-bit imms", "no-movt"),
580 FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
581 FeatureInfo(@This()).create(.DisablePostraScheduler, "disable-postra-scheduler", "Don't schedule again after register allocation", "disable-postra-scheduler"),
582 FeatureInfo(@This()).create(.NonpipelinedVfp, "nonpipelined-vfp", "VFP instructions are not pipelined", "nonpipelined-vfp"),
583 FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable support for Performance Monitor extensions", "perfmon"),
584 FeatureInfo(@This()).create(.Bit32, "32bit", "Prefer 32-bit Thumb instrs", "32bit"),
585 FeatureInfo(@This()).create(.PreferIshst, "prefer-ishst", "Prefer ISHST barriers", "prefer-ishst"),
586 FeatureInfo(@This()).create(.LoopAlign, "loop-align", "Prefer 32-bit alignment for loops", "loop-align"),
587 FeatureInfo(@This()).create(.PreferVmovsr, "prefer-vmovsr", "Prefer VMOVSR", "prefer-vmovsr"),
588 FeatureInfo(@This()).create(.ProfUnpr, "prof-unpr", "Is profitable to unpredicate", "prof-unpr"),
589 FeatureInfo(@This()).create(.Ras, "ras", "Enable Reliability, Availability and Serviceability extensions", "ras"),
590 FeatureInfo(@This()).create(.Rclass, "rclass", "Is realtime profile ('R' series)", "rclass"),
591 FeatureInfo(@This()).create(.ReadTpHard, "read-tp-hard", "Reading thread pointer from register", "read-tp-hard"),
592 FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
593 FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
594 FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
595 .D32,
596 .Fpregs,
597 }),
598 FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
599 FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
600 FeatureInfo(@This()).create(.SlowOddReg, "slow-odd-reg", "VLDM/VSTM starting with an odd register is slow", "slow-odd-reg"),
601 FeatureInfo(@This()).create(.SlowVdup32, "slow-vdup32", "Has slow VDUP32 - prefer VMOV", "slow-vdup32"),
602 FeatureInfo(@This()).create(.SlowVgetlni32, "slow-vgetlni32", "Has slow VGETLNi32 - prefer VMOV", "slow-vgetlni32"),
603 FeatureInfo(@This()).createWithSubfeatures(.SplatVfpNeon, "splat-vfp-neon", "Splat register from VFP to NEON", "splat-vfp-neon", &[_]@This() {
604 .DontWidenVmovs,
605 }),
606 FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
607 FeatureInfo(@This()).create(.Thumb2, "thumb2", "Enable Thumb2 instructions", "thumb2"),
608 FeatureInfo(@This()).create(.Trustzone, "trustzone", "Enable support for TrustZone security extensions", "trustzone"),
609 FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
610 FeatureInfo(@This()).create(.UseMisched, "use-misched", "Use the MachineScheduler", "use-misched"),
611 FeatureInfo(@This()).create(.WideStrideVfp, "wide-stride-vfp", "Use a wide stride when allocating VFP registers", "wide-stride-vfp"),
612 FeatureInfo(@This()).create(.V7clrex, "v7clrex", "Has v7 clrex instruction", "v7clrex"),
613 FeatureInfo(@This()).createWithSubfeatures(.Vfp2, "vfp2", "Enable VFP2 instructions", "vfp2", &[_]@This() {
614 .Fpregs,
615 }),
616 FeatureInfo(@This()).createWithSubfeatures(.Vfp2sp, "vfp2sp", "Enable VFP2 instructions with no double precision", "vfp2sp", &[_]@This() {
617 .Fpregs,
618 }),
619 FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
620 .D32,
621 .Fpregs,
622 }),
623 FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
624 .Fpregs,
625 }),
626 FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16sp, "vfp3d16sp", "Enable VFP3 instructions with only 16 d-registers and no double precision", "vfp3d16sp", &[_]@This() {
627 .Fpregs,
628 }),
629 FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
630 .D32,
631 .Fpregs,
632 }),
633 FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
634 .D32,
635 .Fpregs,
636 .Fp16,
637 }),
638 FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
639 .Fpregs,
640 .Fp16,
641 }),
642 FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
643 .Fpregs,
644 .Fp16,
645 }),
646 FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
647 .D32,
648 .Fpregs,
649 .Fp16,
650 }),
651 FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
652 FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
653 .HwdivArm,
654 .Hwdiv,
655 }),
656 FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
657 FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
658 .Perfmon,
659 .V4t,
660 .Fpregs,
661 .V7clrex,
662 .Fp16,
663 .Dsp,
664 .Thumb2,
665 }),
666 FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
667 .Perfmon,
668 .V4t,
669 .Fpregs,
670 .V7clrex,
671 .Dsp,
672 .Thumb2,
673 }),
674 FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
675 FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
676 .V4t,
677 }),
678 FeatureInfo(@This()).createWithSubfeatures(.V5t, "v5t", "Support ARM v5T instructions", "v5t", &[_]@This() {
679 .V4t,
680 }),
681 FeatureInfo(@This()).createWithSubfeatures(.V6k, "v6k", "Support ARM v6k instructions", "v6k", &[_]@This() {
682 .V4t,
683 }),
684 FeatureInfo(@This()).createWithSubfeatures(.V6m, "v6m", "Support ARM v6M instructions", "v6m", &[_]@This() {
685 .V4t,
686 }),
687 FeatureInfo(@This()).createWithSubfeatures(.V6, "v6", "Support ARM v6 instructions", "v6", &[_]@This() {
688 .V4t,
689 }),
690 FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
691 .V4t,
692 .Thumb2,
693 }),
694 FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
695 .Perfmon,
696 .Thumb2,
697 .V4t,
698 .V7clrex,
699 }),
700 FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
701 .V4t,
702 }),
703 FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
704 .Perfmon,
705 .Thumb2,
706 .V4t,
707 .V7clrex,
708 }),
709 FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
710 .Perfmon,
711 .V4t,
712 .V7clrex,
713 .Thumb2,
714 .AcquireRelease,
715 }),
716 FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
717 .Perfmon,
718 .Thumb2,
719 .V4t,
720 .V7clrex,
721 }),
722 FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
723 .Perfmon,
724 .V4t,
725 .V7clrex,
726 .Thumb2,
727 .AcquireRelease,
728 }),
729 FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
730 .Perfmon,
731 .V4t,
732 .V7clrex,
733 .Thumb2,
734 .AcquireRelease,
735 }),
736 FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
737 .Perfmon,
738 .V4t,
739 .V7clrex,
740 .Thumb2,
741 .AcquireRelease,
742 }),
743 FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
744 .Perfmon,
745 .V4t,
746 .D32,
747 .Fpregs,
748 .V7clrex,
749 .Thumb2,
750 .AcquireRelease,
751 }),
752 FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
753 .Perfmon,
754 .V4t,
755 .D32,
756 .Fpregs,
757 .V7clrex,
758 .Thumb2,
759 .AcquireRelease,
760 .Sb,
761 }),
762 FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
763 .V4t,
764 }),
765 FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt2, "iwmmxt2", "ARMv5te architecture", "iwmmxt2", &[_]@This() {
766 .V4t,
767 }),
768 FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features.", "soft-float"),
769 FeatureInfo(@This()).create(.ThumbMode, "thumb-mode", "Thumb mode", "thumb-mode"),
770 FeatureInfo(@This()).create(.A5, "a5", "Cortex-A5 ARM processors", "a5"),
771 FeatureInfo(@This()).create(.A7, "a7", "Cortex-A7 ARM processors", "a7"),
772 FeatureInfo(@This()).create(.A8, "a8", "Cortex-A8 ARM processors", "a8"),
773 FeatureInfo(@This()).create(.A9, "a9", "Cortex-A9 ARM processors", "a9"),
774 FeatureInfo(@This()).create(.A12, "a12", "Cortex-A12 ARM processors", "a12"),
775 FeatureInfo(@This()).create(.A15, "a15", "Cortex-A15 ARM processors", "a15"),
776 FeatureInfo(@This()).create(.A17, "a17", "Cortex-A17 ARM processors", "a17"),
777 FeatureInfo(@This()).create(.A32, "a32", "Cortex-A32 ARM processors", "a32"),
778 FeatureInfo(@This()).create(.A35, "a35", "Cortex-A35 ARM processors", "a35"),
779 FeatureInfo(@This()).create(.A53, "a53", "Cortex-A53 ARM processors", "a53"),
780 FeatureInfo(@This()).create(.A55, "a55", "Cortex-A55 ARM processors", "a55"),
781 FeatureInfo(@This()).create(.A57, "a57", "Cortex-A57 ARM processors", "a57"),
782 FeatureInfo(@This()).create(.A72, "a72", "Cortex-A72 ARM processors", "a72"),
783 FeatureInfo(@This()).create(.A73, "a73", "Cortex-A73 ARM processors", "a73"),
784 FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
785 FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
786 FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
787 .HwdivArm,
788 .D32,
789 .Crc,
790 .Fpregs,
791 .RetAddrStack,
792 .SlowVgetlni32,
793 .WideStrideVfp,
794 .SlowVdup32,
795 .SlowFpBrcc,
796 .ProfUnpr,
797 .DontWidenVmovs,
798 .Zcz,
799 .Hwdiv,
800 .FuseAes,
801 .Slowfpvmlx,
802 .UseAa,
803 .FuseLiterals,
804 .ExpandFpMlx,
805 }),
806 FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
807 FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),
808 FeatureInfo(@This()).create(.M3, "m3", "Cortex-M3 ARM processors", "m3"),
809 FeatureInfo(@This()).create(.R4, "r4", "Cortex-R4 ARM processors", "r4"),
810 FeatureInfo(@This()).create(.R5, "r5", "Cortex-R5 ARM processors", "r5"),
811 FeatureInfo(@This()).create(.R7, "r7", "Cortex-R7 ARM processors", "r7"),
812 FeatureInfo(@This()).create(.R52, "r52", "Cortex-R52 ARM processors", "r52"),
813 FeatureInfo(@This()).create(.Swift, "swift", "Swift ARM processors", "swift"),
814 FeatureInfo(@This()).createWithSubfeatures(.Xscale, "xscale", "ARMv5te architecture", "xscale", &[_]@This() {
815 .V4t,
816 }),
817 };
818};
lib/std/target/feature/AvrFeature.zig deleted-230
......@@ -1,230 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const AvrFeature = enum {
4 Avr0,
5 Avr1,
6 Avr2,
7 Avr3,
8 Avr4,
9 Avr5,
10 Avr6,
11 Avr25,
12 Avr31,
13 Avr35,
14 Avr51,
15 Avrtiny,
16 Xmega,
17 Xmegau,
18 Addsubiw,
19 Break,
20 Des,
21 Eijmpcall,
22 Elpm,
23 Elpmx,
24 Ijmpcall,
25 Jmpcall,
26 Lpm,
27 Lpmx,
28 Movw,
29 Mul,
30 Rmw,
31 Spm,
32 Spmx,
33 Sram,
34 Special,
35 Smallstack,
36 Tinyencoding,
37
38 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
39 return feature_infos[@enumToInt(self)];
40 }
41
42 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
43 FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
44 FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
45 .Avr0,
46 .Lpm,
47 }),
48 FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
49 .Lpm,
50 .Avr0,
51 .Sram,
52 .Addsubiw,
53 .Ijmpcall,
54 }),
55 FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
56 .Lpm,
57 .Avr0,
58 .Sram,
59 .Jmpcall,
60 .Addsubiw,
61 .Ijmpcall,
62 }),
63 FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
64 .Lpm,
65 .Movw,
66 .Spm,
67 .Avr0,
68 .Sram,
69 .Addsubiw,
70 .Mul,
71 .Lpmx,
72 .Ijmpcall,
73 .Break,
74 }),
75 FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
76 .Lpm,
77 .Movw,
78 .Spm,
79 .Avr0,
80 .Sram,
81 .Jmpcall,
82 .Addsubiw,
83 .Mul,
84 .Lpmx,
85 .Ijmpcall,
86 .Break,
87 }),
88 FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
89 .Lpm,
90 .Elpm,
91 .Movw,
92 .Elpmx,
93 .Spm,
94 .Avr0,
95 .Sram,
96 .Jmpcall,
97 .Addsubiw,
98 .Mul,
99 .Lpmx,
100 .Ijmpcall,
101 .Break,
102 }),
103 FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
104 .Lpm,
105 .Movw,
106 .Spm,
107 .Avr0,
108 .Sram,
109 .Addsubiw,
110 .Lpmx,
111 .Ijmpcall,
112 .Break,
113 }),
114 FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
115 .Lpm,
116 .Elpm,
117 .Avr0,
118 .Sram,
119 .Jmpcall,
120 .Addsubiw,
121 .Ijmpcall,
122 }),
123 FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
124 .Lpm,
125 .Movw,
126 .Spm,
127 .Avr0,
128 .Sram,
129 .Jmpcall,
130 .Addsubiw,
131 .Lpmx,
132 .Ijmpcall,
133 .Break,
134 }),
135 FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
136 .Lpm,
137 .Elpm,
138 .Movw,
139 .Elpmx,
140 .Spm,
141 .Avr0,
142 .Sram,
143 .Jmpcall,
144 .Addsubiw,
145 .Mul,
146 .Lpmx,
147 .Ijmpcall,
148 .Break,
149 }),
150 FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
151 .Avr0,
152 .Sram,
153 .Break,
154 .Tinyencoding,
155 }),
156 FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
157 .Lpm,
158 .Elpm,
159 .Movw,
160 .Elpmx,
161 .Spm,
162 .Avr0,
163 .Sram,
164 .Jmpcall,
165 .Eijmpcall,
166 .Spmx,
167 .Addsubiw,
168 .Mul,
169 .Lpmx,
170 .Des,
171 .Ijmpcall,
172 .Break,
173 }),
174 FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
175 .Lpm,
176 .Elpm,
177 .Movw,
178 .Elpmx,
179 .Spm,
180 .Avr0,
181 .Sram,
182 .Jmpcall,
183 .Eijmpcall,
184 .Spmx,
185 .Addsubiw,
186 .Mul,
187 .Lpmx,
188 .Rmw,
189 .Des,
190 .Ijmpcall,
191 .Break,
192 }),
193 FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
194 FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
195 FeatureInfo(@This()).create(.Des, "des", "The device supports the `DES k` encryption instruction", "des"),
196 FeatureInfo(@This()).create(.Eijmpcall, "eijmpcall", "The device supports the `EIJMP`/`EICALL` instructions", "eijmpcall"),
197 FeatureInfo(@This()).create(.Elpm, "elpm", "The device supports the ELPM instruction", "elpm"),
198 FeatureInfo(@This()).create(.Elpmx, "elpmx", "The device supports the `ELPM Rd, Z[+]` instructions", "elpmx"),
199 FeatureInfo(@This()).create(.Ijmpcall, "ijmpcall", "The device supports `IJMP`/`ICALL`instructions", "ijmpcall"),
200 FeatureInfo(@This()).create(.Jmpcall, "jmpcall", "The device supports the `JMP` and `CALL` instructions", "jmpcall"),
201 FeatureInfo(@This()).create(.Lpm, "lpm", "The device supports the `LPM` instruction", "lpm"),
202 FeatureInfo(@This()).create(.Lpmx, "lpmx", "The device supports the `LPM Rd, Z[+]` instruction", "lpmx"),
203 FeatureInfo(@This()).create(.Movw, "movw", "The device supports the 16-bit MOVW instruction", "movw"),
204 FeatureInfo(@This()).create(.Mul, "mul", "The device supports the multiplication instructions", "mul"),
205 FeatureInfo(@This()).create(.Rmw, "rmw", "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT", "rmw"),
206 FeatureInfo(@This()).create(.Spm, "spm", "The device supports the `SPM` instruction", "spm"),
207 FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
208 FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
209 FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
210 .Lpm,
211 .Elpm,
212 .Elpmx,
213 .Movw,
214 .Spm,
215 .Eijmpcall,
216 .Spmx,
217 .Jmpcall,
218 .Sram,
219 .Addsubiw,
220 .Mul,
221 .Lpmx,
222 .Rmw,
223 .Des,
224 .Ijmpcall,
225 .Break,
226 }),
227 FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
228 FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),
229 };
230};
lib/std/target/feature/BpfFeature.zig deleted-17
......@@ -1,17 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const BpfFeature = enum {
4 Alu32,
5 Dummy,
6 Dwarfris,
7
8 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
9 return feature_infos[@enumToInt(self)];
10 }
11
12 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
13 FeatureInfo(@This()).create(.Alu32, "alu32", "Enable ALU32 instructions", "alu32"),
14 FeatureInfo(@This()).create(.Dummy, "dummy", "unused feature", "dummy"),
15 FeatureInfo(@This()).create(.Dwarfris, "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", "dwarfris"),
16 };
17};
lib/std/target/feature/HexagonFeature.zig deleted-76
......@@ -1,76 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const HexagonFeature = enum {
4 V5,
5 V55,
6 V60,
7 V62,
8 V65,
9 V66,
10 Hvx,
11 HvxLength64b,
12 HvxLength128b,
13 Hvxv60,
14 Hvxv62,
15 Hvxv65,
16 Hvxv66,
17 Zreg,
18 Duplex,
19 LongCalls,
20 Mem_noshuf,
21 Memops,
22 Nvj,
23 Nvs,
24 NoreturnStackElim,
25 Packets,
26 ReservedR19,
27 SmallData,
28
29 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
30 return feature_infos[@enumToInt(self)];
31 }
32
33 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
34 FeatureInfo(@This()).create(.V5, "v5", "Enable Hexagon V5 architecture", "v5"),
35 FeatureInfo(@This()).create(.V55, "v55", "Enable Hexagon V55 architecture", "v55"),
36 FeatureInfo(@This()).create(.V60, "v60", "Enable Hexagon V60 architecture", "v60"),
37 FeatureInfo(@This()).create(.V62, "v62", "Enable Hexagon V62 architecture", "v62"),
38 FeatureInfo(@This()).create(.V65, "v65", "Enable Hexagon V65 architecture", "v65"),
39 FeatureInfo(@This()).create(.V66, "v66", "Enable Hexagon V66 architecture", "v66"),
40 FeatureInfo(@This()).create(.Hvx, "hvx", "Hexagon HVX instructions", "hvx"),
41 FeatureInfo(@This()).createWithSubfeatures(.HvxLength64b, "hvx-length64b", "Hexagon HVX 64B instructions", "hvx-length64b", &[_]@This() {
42 .Hvx,
43 }),
44 FeatureInfo(@This()).createWithSubfeatures(.HvxLength128b, "hvx-length128b", "Hexagon HVX 128B instructions", "hvx-length128b", &[_]@This() {
45 .Hvx,
46 }),
47 FeatureInfo(@This()).createWithSubfeatures(.Hvxv60, "hvxv60", "Hexagon HVX instructions", "hvxv60", &[_]@This() {
48 .Hvx,
49 }),
50 FeatureInfo(@This()).createWithSubfeatures(.Hvxv62, "hvxv62", "Hexagon HVX instructions", "hvxv62", &[_]@This() {
51 .Hvx,
52 }),
53 FeatureInfo(@This()).createWithSubfeatures(.Hvxv65, "hvxv65", "Hexagon HVX instructions", "hvxv65", &[_]@This() {
54 .Hvx,
55 }),
56 FeatureInfo(@This()).createWithSubfeatures(.Hvxv66, "hvxv66", "Hexagon HVX instructions", "hvxv66", &[_]@This() {
57 .Hvx,
58 .Zreg,
59 }),
60 FeatureInfo(@This()).create(.Zreg, "zreg", "Hexagon ZReg extension instructions", "zreg"),
61 FeatureInfo(@This()).create(.Duplex, "duplex", "Enable generation of duplex instruction", "duplex"),
62 FeatureInfo(@This()).create(.LongCalls, "long-calls", "Use constant-extended calls", "long-calls"),
63 FeatureInfo(@This()).create(.Mem_noshuf, "mem_noshuf", "Supports mem_noshuf feature", "mem_noshuf"),
64 FeatureInfo(@This()).create(.Memops, "memops", "Use memop instructions", "memops"),
65 FeatureInfo(@This()).createWithSubfeatures(.Nvj, "nvj", "Support for new-value jumps", "nvj", &[_]@This() {
66 .Packets,
67 }),
68 FeatureInfo(@This()).createWithSubfeatures(.Nvs, "nvs", "Support for new-value stores", "nvs", &[_]@This() {
69 .Packets,
70 }),
71 FeatureInfo(@This()).create(.NoreturnStackElim, "noreturn-stack-elim", "Eliminate stack allocation in a noreturn function when possible", "noreturn-stack-elim"),
72 FeatureInfo(@This()).create(.Packets, "packets", "Support for instruction packets", "packets"),
73 FeatureInfo(@This()).create(.ReservedR19, "reserved-r19", "Reserve register R19", "reserved-r19"),
74 FeatureInfo(@This()).create(.SmallData, "small-data", "Allow GP-relative addressing of global variables", "small-data"),
75 };
76};
lib/std/target/feature/MipsFeature.zig deleted-238
......@@ -1,238 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const MipsFeature = enum {
4 Abs2008,
5 Crc,
6 Cnmips,
7 Dsp,
8 Dspr2,
9 Dspr3,
10 Eva,
11 Fp64,
12 Fpxx,
13 Ginv,
14 Gp64,
15 LongCalls,
16 Msa,
17 Mt,
18 Nomadd4,
19 Micromips,
20 Mips1,
21 Mips2,
22 Mips3,
23 Mips3_32,
24 Mips3_32r2,
25 Mips4,
26 Mips4_32,
27 Mips4_32r2,
28 Mips5,
29 Mips5_32r2,
30 Mips16,
31 Mips32,
32 Mips32r2,
33 Mips32r3,
34 Mips32r5,
35 Mips32r6,
36 Mips64,
37 Mips64r2,
38 Mips64r3,
39 Mips64r5,
40 Mips64r6,
41 Nan2008,
42 Noabicalls,
43 Nooddspreg,
44 Ptr64,
45 SingleFloat,
46 SoftFloat,
47 Sym32,
48 UseIndirectJumpHazard,
49 UseTccInDiv,
50 Vfpu,
51 Virt,
52 Xgot,
53 P5600,
54
55 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
56 return feature_infos[@enumToInt(self)];
57 }
58
59 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
60 FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
61 FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
62 FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
63 .Mips5_32r2,
64 .Mips3_32r2,
65 .Mips4_32r2,
66 .Gp64,
67 .Fp64,
68 .Mips4_32,
69 .Mips1,
70 .Mips3_32,
71 }),
72 FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
73 FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
74 .Dsp,
75 }),
76 FeatureInfo(@This()).createWithSubfeatures(.Dspr3, "dspr3", "Mips DSP-R3 ASE", "dspr3", &[_]@This() {
77 .Dsp,
78 }),
79 FeatureInfo(@This()).create(.Eva, "eva", "Mips EVA ASE", "eva"),
80 FeatureInfo(@This()).create(.Fp64, "fp64", "Support 64-bit FP registers", "fp64"),
81 FeatureInfo(@This()).create(.Fpxx, "fpxx", "Support for FPXX", "fpxx"),
82 FeatureInfo(@This()).create(.Ginv, "ginv", "Mips Global Invalidate ASE", "ginv"),
83 FeatureInfo(@This()).create(.Gp64, "gp64", "General Purpose Registers are 64-bit wide", "gp64"),
84 FeatureInfo(@This()).create(.LongCalls, "long-calls", "Disable use of the jal instruction", "long-calls"),
85 FeatureInfo(@This()).create(.Msa, "msa", "Mips MSA ASE", "msa"),
86 FeatureInfo(@This()).create(.Mt, "mt", "Mips MT ASE", "mt"),
87 FeatureInfo(@This()).create(.Nomadd4, "nomadd4", "Disable 4-operand madd.fmt and related instructions", "nomadd4"),
88 FeatureInfo(@This()).create(.Micromips, "micromips", "microMips mode", "micromips"),
89 FeatureInfo(@This()).create(.Mips1, "mips1", "Mips I ISA Support [highly experimental]", "mips1"),
90 FeatureInfo(@This()).createWithSubfeatures(.Mips2, "mips2", "Mips II ISA Support [highly experimental]", "mips2", &[_]@This() {
91 .Mips1,
92 }),
93 FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
94 .Mips3_32r2,
95 .Fp64,
96 .Gp64,
97 .Mips1,
98 .Mips3_32,
99 }),
100 FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
101 FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
102 FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
103 .Mips3_32r2,
104 .Mips4_32r2,
105 .Fp64,
106 .Gp64,
107 .Mips4_32,
108 .Mips1,
109 .Mips3_32,
110 }),
111 FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
112 FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
113 FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
114 .Mips5_32r2,
115 .Mips4_32r2,
116 .Mips3_32r2,
117 .Gp64,
118 .Fp64,
119 .Mips4_32,
120 .Mips1,
121 .Mips3_32,
122 }),
123 FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
124 FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
125 FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
126 .Mips4_32,
127 .Mips1,
128 .Mips3_32,
129 }),
130 FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
131 .Mips5_32r2,
132 .Mips4_32r2,
133 .Mips3_32r2,
134 .Mips4_32,
135 .Mips1,
136 .Mips3_32,
137 }),
138 FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
139 .Mips5_32r2,
140 .Mips3_32r2,
141 .Mips4_32r2,
142 .Mips4_32,
143 .Mips1,
144 .Mips3_32,
145 }),
146 FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
147 .Mips5_32r2,
148 .Mips3_32r2,
149 .Mips4_32r2,
150 .Mips4_32,
151 .Mips1,
152 .Mips3_32,
153 }),
154 FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
155 .Mips5_32r2,
156 .Mips3_32r2,
157 .Mips4_32r2,
158 .Abs2008,
159 .Nan2008,
160 .Fp64,
161 .Mips4_32,
162 .Mips1,
163 .Mips3_32,
164 }),
165 FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
166 .Mips5_32r2,
167 .Mips3_32r2,
168 .Mips4_32r2,
169 .Gp64,
170 .Fp64,
171 .Mips4_32,
172 .Mips1,
173 .Mips3_32,
174 }),
175 FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
176 .Mips5_32r2,
177 .Mips3_32r2,
178 .Mips4_32r2,
179 .Gp64,
180 .Fp64,
181 .Mips4_32,
182 .Mips1,
183 .Mips3_32,
184 }),
185 FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
186 .Mips5_32r2,
187 .Mips3_32r2,
188 .Mips4_32r2,
189 .Gp64,
190 .Fp64,
191 .Mips4_32,
192 .Mips1,
193 .Mips3_32,
194 }),
195 FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
196 .Mips5_32r2,
197 .Mips3_32r2,
198 .Mips4_32r2,
199 .Gp64,
200 .Fp64,
201 .Mips4_32,
202 .Mips1,
203 .Mips3_32,
204 }),
205 FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
206 .Mips5_32r2,
207 .Mips3_32r2,
208 .Nan2008,
209 .Abs2008,
210 .Mips4_32r2,
211 .Fp64,
212 .Gp64,
213 .Mips4_32,
214 .Mips1,
215 .Mips3_32,
216 }),
217 FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
218 FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
219 FeatureInfo(@This()).create(.Nooddspreg, "nooddspreg", "Disable odd numbered single-precision registers", "nooddspreg"),
220 FeatureInfo(@This()).create(.Ptr64, "ptr64", "Pointers are 64-bit wide", "ptr64"),
221 FeatureInfo(@This()).create(.SingleFloat, "single-float", "Only supports single precision float", "single-float"),
222 FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Does not support floating point instructions", "soft-float"),
223 FeatureInfo(@This()).create(.Sym32, "sym32", "Symbols are 32 bit on Mips64", "sym32"),
224 FeatureInfo(@This()).create(.UseIndirectJumpHazard, "use-indirect-jump-hazard", "Use indirect jump guards to prevent certain speculation based attacks", "use-indirect-jump-hazard"),
225 FeatureInfo(@This()).create(.UseTccInDiv, "use-tcc-in-div", "Force the assembler to use trapping", "use-tcc-in-div"),
226 FeatureInfo(@This()).create(.Vfpu, "vfpu", "Enable vector FPU instructions", "vfpu"),
227 FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
228 FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
229 FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
230 .Mips5_32r2,
231 .Mips3_32r2,
232 .Mips4_32r2,
233 .Mips4_32,
234 .Mips1,
235 .Mips3_32,
236 }),
237 };
238};
lib/std/target/feature/Msp430Feature.zig deleted-19
......@@ -1,19 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const Msp430Feature = enum {
4 Hwmult16,
5 Hwmult32,
6 Hwmultf5,
7 Ext,
8
9 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
10 return feature_infos[@enumToInt(self)];
11 }
12
13 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
14 FeatureInfo(@This()).create(.Hwmult16, "hwmult16", "Enable 16-bit hardware multiplier", "hwmult16"),
15 FeatureInfo(@This()).create(.Hwmult32, "hwmult32", "Enable 32-bit hardware multiplier", "hwmult32"),
16 FeatureInfo(@This()).create(.Hwmultf5, "hwmultf5", "Enable F5 series hardware multiplier", "hwmultf5"),
17 FeatureInfo(@This()).create(.Ext, "ext", "Enable MSP430-X extensions", "ext"),
18 };
19};
lib/std/target/feature/NvptxFeature.zig deleted-61
......@@ -1,61 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const NvptxFeature = enum {
4 Ptx32,
5 Ptx40,
6 Ptx41,
7 Ptx42,
8 Ptx43,
9 Ptx50,
10 Ptx60,
11 Ptx61,
12 Ptx63,
13 Ptx64,
14 Sm_20,
15 Sm_21,
16 Sm_30,
17 Sm_32,
18 Sm_35,
19 Sm_37,
20 Sm_50,
21 Sm_52,
22 Sm_53,
23 Sm_60,
24 Sm_61,
25 Sm_62,
26 Sm_70,
27 Sm_72,
28 Sm_75,
29
30 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
31 return feature_infos[@enumToInt(self)];
32 }
33
34 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
35 FeatureInfo(@This()).create(.Ptx32, "ptx32", "Use PTX version 3.2", "ptx32"),
36 FeatureInfo(@This()).create(.Ptx40, "ptx40", "Use PTX version 4.0", "ptx40"),
37 FeatureInfo(@This()).create(.Ptx41, "ptx41", "Use PTX version 4.1", "ptx41"),
38 FeatureInfo(@This()).create(.Ptx42, "ptx42", "Use PTX version 4.2", "ptx42"),
39 FeatureInfo(@This()).create(.Ptx43, "ptx43", "Use PTX version 4.3", "ptx43"),
40 FeatureInfo(@This()).create(.Ptx50, "ptx50", "Use PTX version 5.0", "ptx50"),
41 FeatureInfo(@This()).create(.Ptx60, "ptx60", "Use PTX version 6.0", "ptx60"),
42 FeatureInfo(@This()).create(.Ptx61, "ptx61", "Use PTX version 6.1", "ptx61"),
43 FeatureInfo(@This()).create(.Ptx63, "ptx63", "Use PTX version 6.3", "ptx63"),
44 FeatureInfo(@This()).create(.Ptx64, "ptx64", "Use PTX version 6.4", "ptx64"),
45 FeatureInfo(@This()).create(.Sm_20, "sm_20", "Target SM 2.0", "sm_20"),
46 FeatureInfo(@This()).create(.Sm_21, "sm_21", "Target SM 2.1", "sm_21"),
47 FeatureInfo(@This()).create(.Sm_30, "sm_30", "Target SM 3.0", "sm_30"),
48 FeatureInfo(@This()).create(.Sm_32, "sm_32", "Target SM 3.2", "sm_32"),
49 FeatureInfo(@This()).create(.Sm_35, "sm_35", "Target SM 3.5", "sm_35"),
50 FeatureInfo(@This()).create(.Sm_37, "sm_37", "Target SM 3.7", "sm_37"),
51 FeatureInfo(@This()).create(.Sm_50, "sm_50", "Target SM 5.0", "sm_50"),
52 FeatureInfo(@This()).create(.Sm_52, "sm_52", "Target SM 5.2", "sm_52"),
53 FeatureInfo(@This()).create(.Sm_53, "sm_53", "Target SM 5.3", "sm_53"),
54 FeatureInfo(@This()).create(.Sm_60, "sm_60", "Target SM 6.0", "sm_60"),
55 FeatureInfo(@This()).create(.Sm_61, "sm_61", "Target SM 6.1", "sm_61"),
56 FeatureInfo(@This()).create(.Sm_62, "sm_62", "Target SM 6.2", "sm_62"),
57 FeatureInfo(@This()).create(.Sm_70, "sm_70", "Target SM 7.0", "sm_70"),
58 FeatureInfo(@This()).create(.Sm_72, "sm_72", "Target SM 7.2", "sm_72"),
59 FeatureInfo(@This()).create(.Sm_75, "sm_75", "Target SM 7.5", "sm_75"),
60 };
61};
lib/std/target/feature/PowerPcFeature.zig deleted-163
......@@ -1,163 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const PowerPcFeature = enum {
4 Bit64,
5 Bitregs64,
6 Altivec,
7 Bpermd,
8 Booke,
9 Cmpb,
10 Crbits,
11 DirectMove,
12 E500,
13 Extdiv,
14 Fcpsgn,
15 Fpcvt,
16 Fprnd,
17 Fpu,
18 Fre,
19 Fres,
20 Frsqrte,
21 Frsqrtes,
22 Fsqrt,
23 Float128,
24 Htm,
25 HardFloat,
26 Icbt,
27 IsaV30Instructions,
28 Isel,
29 InvariantFunctionDescriptors,
30 Ldbrx,
31 Lfiwax,
32 Longcall,
33 Mfocrf,
34 Msync,
35 Power8Altivec,
36 Crypto,
37 Power8Vector,
38 Power9Altivec,
39 Power9Vector,
40 Popcntd,
41 Ppc4xx,
42 Ppc6xx,
43 PpcPostraSched,
44 PpcPreraSched,
45 PartwordAtomics,
46 Qpx,
47 Recipprec,
48 Spe,
49 Stfiwx,
50 SecurePlt,
51 SlowPopcntd,
52 TwoConstNr,
53 Vsx,
54 VectorsUseTwoUnits,
55
56 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
57 return feature_infos[@enumToInt(self)];
58 }
59
60 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
61 FeatureInfo(@This()).create(.Bit64, "64bit", "Enable 64-bit instructions", "64bit"),
62 FeatureInfo(@This()).create(.Bitregs64, "64bitregs", "Enable 64-bit registers usage for ppc32 [beta]", "64bitregs"),
63 FeatureInfo(@This()).createWithSubfeatures(.Altivec, "altivec", "Enable Altivec instructions", "altivec", &[_]@This() {
64 .HardFloat,
65 }),
66 FeatureInfo(@This()).create(.Bpermd, "bpermd", "Enable the bpermd instruction", "bpermd"),
67 FeatureInfo(@This()).createWithSubfeatures(.Booke, "booke", "Enable Book E instructions", "booke", &[_]@This() {
68 .Icbt,
69 }),
70 FeatureInfo(@This()).create(.Cmpb, "cmpb", "Enable the cmpb instruction", "cmpb"),
71 FeatureInfo(@This()).create(.Crbits, "crbits", "Use condition-register bits individually", "crbits"),
72 FeatureInfo(@This()).createWithSubfeatures(.DirectMove, "direct-move", "Enable Power8 direct move instructions", "direct-move", &[_]@This() {
73 .HardFloat,
74 }),
75 FeatureInfo(@This()).create(.E500, "e500", "Enable E500/E500mc instructions", "e500"),
76 FeatureInfo(@This()).create(.Extdiv, "extdiv", "Enable extended divide instructions", "extdiv"),
77 FeatureInfo(@This()).createWithSubfeatures(.Fcpsgn, "fcpsgn", "Enable the fcpsgn instruction", "fcpsgn", &[_]@This() {
78 .HardFloat,
79 }),
80 FeatureInfo(@This()).createWithSubfeatures(.Fpcvt, "fpcvt", "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", "fpcvt", &[_]@This() {
81 .HardFloat,
82 }),
83 FeatureInfo(@This()).createWithSubfeatures(.Fprnd, "fprnd", "Enable the fri[mnpz] instructions", "fprnd", &[_]@This() {
84 .HardFloat,
85 }),
86 FeatureInfo(@This()).createWithSubfeatures(.Fpu, "fpu", "Enable classic FPU instructions", "fpu", &[_]@This() {
87 .HardFloat,
88 }),
89 FeatureInfo(@This()).createWithSubfeatures(.Fre, "fre", "Enable the fre instruction", "fre", &[_]@This() {
90 .HardFloat,
91 }),
92 FeatureInfo(@This()).createWithSubfeatures(.Fres, "fres", "Enable the fres instruction", "fres", &[_]@This() {
93 .HardFloat,
94 }),
95 FeatureInfo(@This()).createWithSubfeatures(.Frsqrte, "frsqrte", "Enable the frsqrte instruction", "frsqrte", &[_]@This() {
96 .HardFloat,
97 }),
98 FeatureInfo(@This()).createWithSubfeatures(.Frsqrtes, "frsqrtes", "Enable the frsqrtes instruction", "frsqrtes", &[_]@This() {
99 .HardFloat,
100 }),
101 FeatureInfo(@This()).createWithSubfeatures(.Fsqrt, "fsqrt", "Enable the fsqrt instruction", "fsqrt", &[_]@This() {
102 .HardFloat,
103 }),
104 FeatureInfo(@This()).createWithSubfeatures(.Float128, "float128", "Enable the __float128 data type for IEEE-754R Binary128.", "float128", &[_]@This() {
105 .HardFloat,
106 }),
107 FeatureInfo(@This()).create(.Htm, "htm", "Enable Hardware Transactional Memory instructions", "htm"),
108 FeatureInfo(@This()).create(.HardFloat, "hard-float", "Enable floating-point instructions", "hard-float"),
109 FeatureInfo(@This()).create(.Icbt, "icbt", "Enable icbt instruction", "icbt"),
110 FeatureInfo(@This()).create(.IsaV30Instructions, "isa-v30-instructions", "Enable instructions added in ISA 3.0.", "isa-v30-instructions"),
111 FeatureInfo(@This()).create(.Isel, "isel", "Enable the isel instruction", "isel"),
112 FeatureInfo(@This()).create(.InvariantFunctionDescriptors, "invariant-function-descriptors", "Assume function descriptors are invariant", "invariant-function-descriptors"),
113 FeatureInfo(@This()).create(.Ldbrx, "ldbrx", "Enable the ldbrx instruction", "ldbrx"),
114 FeatureInfo(@This()).createWithSubfeatures(.Lfiwax, "lfiwax", "Enable the lfiwax instruction", "lfiwax", &[_]@This() {
115 .HardFloat,
116 }),
117 FeatureInfo(@This()).create(.Longcall, "longcall", "Always use indirect calls", "longcall"),
118 FeatureInfo(@This()).create(.Mfocrf, "mfocrf", "Enable the MFOCRF instruction", "mfocrf"),
119 FeatureInfo(@This()).createWithSubfeatures(.Msync, "msync", "Has only the msync instruction instead of sync", "msync", &[_]@This() {
120 .Icbt,
121 }),
122 FeatureInfo(@This()).createWithSubfeatures(.Power8Altivec, "power8-altivec", "Enable POWER8 Altivec instructions", "power8-altivec", &[_]@This() {
123 .HardFloat,
124 }),
125 FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable POWER8 Crypto instructions", "crypto", &[_]@This() {
126 .HardFloat,
127 }),
128 FeatureInfo(@This()).createWithSubfeatures(.Power8Vector, "power8-vector", "Enable POWER8 vector instructions", "power8-vector", &[_]@This() {
129 .HardFloat,
130 }),
131 FeatureInfo(@This()).createWithSubfeatures(.Power9Altivec, "power9-altivec", "Enable POWER9 Altivec instructions", "power9-altivec", &[_]@This() {
132 .IsaV30Instructions,
133 .HardFloat,
134 }),
135 FeatureInfo(@This()).createWithSubfeatures(.Power9Vector, "power9-vector", "Enable POWER9 vector instructions", "power9-vector", &[_]@This() {
136 .IsaV30Instructions,
137 .HardFloat,
138 }),
139 FeatureInfo(@This()).create(.Popcntd, "popcntd", "Enable the popcnt[dw] instructions", "popcntd"),
140 FeatureInfo(@This()).create(.Ppc4xx, "ppc4xx", "Enable PPC 4xx instructions", "ppc4xx"),
141 FeatureInfo(@This()).create(.Ppc6xx, "ppc6xx", "Enable PPC 6xx instructions", "ppc6xx"),
142 FeatureInfo(@This()).create(.PpcPostraSched, "ppc-postra-sched", "Use PowerPC post-RA scheduling strategy", "ppc-postra-sched"),
143 FeatureInfo(@This()).create(.PpcPreraSched, "ppc-prera-sched", "Use PowerPC pre-RA scheduling strategy", "ppc-prera-sched"),
144 FeatureInfo(@This()).create(.PartwordAtomics, "partword-atomics", "Enable l[bh]arx and st[bh]cx.", "partword-atomics"),
145 FeatureInfo(@This()).createWithSubfeatures(.Qpx, "qpx", "Enable QPX instructions", "qpx", &[_]@This() {
146 .HardFloat,
147 }),
148 FeatureInfo(@This()).create(.Recipprec, "recipprec", "Assume higher precision reciprocal estimates", "recipprec"),
149 FeatureInfo(@This()).createWithSubfeatures(.Spe, "spe", "Enable SPE instructions", "spe", &[_]@This() {
150 .HardFloat,
151 }),
152 FeatureInfo(@This()).createWithSubfeatures(.Stfiwx, "stfiwx", "Enable the stfiwx instruction", "stfiwx", &[_]@This() {
153 .HardFloat,
154 }),
155 FeatureInfo(@This()).create(.SecurePlt, "secure-plt", "Enable secure plt mode", "secure-plt"),
156 FeatureInfo(@This()).create(.SlowPopcntd, "slow-popcntd", "Has slow popcnt[dw] instructions", "slow-popcntd"),
157 FeatureInfo(@This()).create(.TwoConstNr, "two-const-nr", "Requires two constant Newton-Raphson computation", "two-const-nr"),
158 FeatureInfo(@This()).createWithSubfeatures(.Vsx, "vsx", "Enable VSX instructions", "vsx", &[_]@This() {
159 .HardFloat,
160 }),
161 FeatureInfo(@This()).create(.VectorsUseTwoUnits, "vectors-use-two-units", "Vectors use two units", "vectors-use-two-units"),
162 };
163};
lib/std/target/feature/RiscVFeature.zig deleted-31
......@@ -1,31 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const RiscVFeature = enum {
4 Bit64,
5 E,
6 RvcHints,
7 Relax,
8 A,
9 C,
10 D,
11 F,
12 M,
13
14 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
15 return feature_infos[@enumToInt(self)];
16 }
17
18 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
19 FeatureInfo(@This()).create(.Bit64, "64bit", "Implements RV64", "64bit"),
20 FeatureInfo(@This()).create(.E, "e", "Implements RV32E (provides 16 rather than 32 GPRs)", "e"),
21 FeatureInfo(@This()).create(.RvcHints, "rvc-hints", "Enable RVC Hint Instructions.", "rvc-hints"),
22 FeatureInfo(@This()).create(.Relax, "relax", "Enable Linker relaxation.", "relax"),
23 FeatureInfo(@This()).create(.A, "a", "'A' (Atomic Instructions)", "a"),
24 FeatureInfo(@This()).create(.C, "c", "'C' (Compressed Instructions)", "c"),
25 FeatureInfo(@This()).createWithSubfeatures(.D, "d", "'D' (Double-Precision Floating-Point)", "d", &[_]@This() {
26 .F,
27 }),
28 FeatureInfo(@This()).create(.F, "f", "'F' (Single-Precision Floating-Point)", "f"),
29 FeatureInfo(@This()).create(.M, "m", "'M' (Integer Multiplication and Division)", "m"),
30 };
31};
lib/std/target/feature/SparcFeature.zig deleted-49
......@@ -1,49 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const SparcFeature = enum {
4 Detectroundchange,
5 HardQuadFloat,
6 Leon,
7 NoFmuls,
8 NoFsmuld,
9 Leonpwrpsr,
10 SoftFloat,
11 SoftMulDiv,
12 DeprecatedV8,
13 V9,
14 Vis,
15 Vis2,
16 Vis3,
17 Fixallfdivsqrt,
18 Insertnopload,
19 Hasleoncasa,
20 Leoncyclecounter,
21 Hasumacsmac,
22 Popc,
23
24 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
25 return feature_infos[@enumToInt(self)];
26 }
27
28 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
29 FeatureInfo(@This()).create(.Detectroundchange, "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", "detectroundchange"),
30 FeatureInfo(@This()).create(.HardQuadFloat, "hard-quad-float", "Enable quad-word floating point instructions", "hard-quad-float"),
31 FeatureInfo(@This()).create(.Leon, "leon", "Enable LEON extensions", "leon"),
32 FeatureInfo(@This()).create(.NoFmuls, "no-fmuls", "Disable the fmuls instruction.", "no-fmuls"),
33 FeatureInfo(@This()).create(.NoFsmuld, "no-fsmuld", "Disable the fsmuld instruction.", "no-fsmuld"),
34 FeatureInfo(@This()).create(.Leonpwrpsr, "leonpwrpsr", "Enable the PWRPSR instruction", "leonpwrpsr"),
35 FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software emulation for floating point", "soft-float"),
36 FeatureInfo(@This()).create(.SoftMulDiv, "soft-mul-div", "Use software emulation for integer multiply and divide", "soft-mul-div"),
37 FeatureInfo(@This()).create(.DeprecatedV8, "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", "deprecated-v8"),
38 FeatureInfo(@This()).create(.V9, "v9", "Enable SPARC-V9 instructions", "v9"),
39 FeatureInfo(@This()).create(.Vis, "vis", "Enable UltraSPARC Visual Instruction Set extensions", "vis"),
40 FeatureInfo(@This()).create(.Vis2, "vis2", "Enable Visual Instruction Set extensions II", "vis2"),
41 FeatureInfo(@This()).create(.Vis3, "vis3", "Enable Visual Instruction Set extensions III", "vis3"),
42 FeatureInfo(@This()).create(.Fixallfdivsqrt, "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", "fixallfdivsqrt"),
43 FeatureInfo(@This()).create(.Insertnopload, "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", "insertnopload"),
44 FeatureInfo(@This()).create(.Hasleoncasa, "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", "hasleoncasa"),
45 FeatureInfo(@This()).create(.Leoncyclecounter, "leoncyclecounter", "Use the Leon cycle counter register", "leoncyclecounter"),
46 FeatureInfo(@This()).create(.Hasumacsmac, "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", "hasumacsmac"),
47 FeatureInfo(@This()).create(.Popc, "popc", "Use the popc (population count) instruction", "popc"),
48 };
49};
lib/std/target/feature/SystemZFeature.zig deleted-81
......@@ -1,81 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const SystemZFeature = enum {
4 DfpPackedConversion,
5 DfpZonedConversion,
6 DeflateConversion,
7 DistinctOps,
8 EnhancedDat2,
9 EnhancedSort,
10 ExecutionHint,
11 FpExtension,
12 FastSerialization,
13 GuardedStorage,
14 HighWord,
15 InsertReferenceBitsMultiple,
16 InterlockedAccess1,
17 LoadAndTrap,
18 LoadAndZeroRightmostByte,
19 LoadStoreOnCond,
20 LoadStoreOnCond2,
21 MessageSecurityAssistExtension3,
22 MessageSecurityAssistExtension4,
23 MessageSecurityAssistExtension5,
24 MessageSecurityAssistExtension7,
25 MessageSecurityAssistExtension8,
26 MessageSecurityAssistExtension9,
27 MiscellaneousExtensions,
28 MiscellaneousExtensions2,
29 MiscellaneousExtensions3,
30 PopulationCount,
31 ProcessorAssist,
32 ResetReferenceBitsMultiple,
33 TransactionalExecution,
34 Vector,
35 VectorEnhancements1,
36 VectorEnhancements2,
37 VectorPackedDecimal,
38 VectorPackedDecimalEnhancement,
39
40 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
41 return feature_infos[@enumToInt(self)];
42 }
43
44 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
45 FeatureInfo(@This()).create(.DfpPackedConversion, "dfp-packed-conversion", "Assume that the DFP packed-conversion facility is installed", "dfp-packed-conversion"),
46 FeatureInfo(@This()).create(.DfpZonedConversion, "dfp-zoned-conversion", "Assume that the DFP zoned-conversion facility is installed", "dfp-zoned-conversion"),
47 FeatureInfo(@This()).create(.DeflateConversion, "deflate-conversion", "Assume that the deflate-conversion facility is installed", "deflate-conversion"),
48 FeatureInfo(@This()).create(.DistinctOps, "distinct-ops", "Assume that the distinct-operands facility is installed", "distinct-ops"),
49 FeatureInfo(@This()).create(.EnhancedDat2, "enhanced-dat-2", "Assume that the enhanced-DAT facility 2 is installed", "enhanced-dat-2"),
50 FeatureInfo(@This()).create(.EnhancedSort, "enhanced-sort", "Assume that the enhanced-sort facility is installed", "enhanced-sort"),
51 FeatureInfo(@This()).create(.ExecutionHint, "execution-hint", "Assume that the execution-hint facility is installed", "execution-hint"),
52 FeatureInfo(@This()).create(.FpExtension, "fp-extension", "Assume that the floating-point extension facility is installed", "fp-extension"),
53 FeatureInfo(@This()).create(.FastSerialization, "fast-serialization", "Assume that the fast-serialization facility is installed", "fast-serialization"),
54 FeatureInfo(@This()).create(.GuardedStorage, "guarded-storage", "Assume that the guarded-storage facility is installed", "guarded-storage"),
55 FeatureInfo(@This()).create(.HighWord, "high-word", "Assume that the high-word facility is installed", "high-word"),
56 FeatureInfo(@This()).create(.InsertReferenceBitsMultiple, "insert-reference-bits-multiple", "Assume that the insert-reference-bits-multiple facility is installed", "insert-reference-bits-multiple"),
57 FeatureInfo(@This()).create(.InterlockedAccess1, "interlocked-access1", "Assume that interlocked-access facility 1 is installed", "interlocked-access1"),
58 FeatureInfo(@This()).create(.LoadAndTrap, "load-and-trap", "Assume that the load-and-trap facility is installed", "load-and-trap"),
59 FeatureInfo(@This()).create(.LoadAndZeroRightmostByte, "load-and-zero-rightmost-byte", "Assume that the load-and-zero-rightmost-byte facility is installed", "load-and-zero-rightmost-byte"),
60 FeatureInfo(@This()).create(.LoadStoreOnCond, "load-store-on-cond", "Assume that the load/store-on-condition facility is installed", "load-store-on-cond"),
61 FeatureInfo(@This()).create(.LoadStoreOnCond2, "load-store-on-cond-2", "Assume that the load/store-on-condition facility 2 is installed", "load-store-on-cond-2"),
62 FeatureInfo(@This()).create(.MessageSecurityAssistExtension3, "message-security-assist-extension3", "Assume that the message-security-assist extension facility 3 is installed", "message-security-assist-extension3"),
63 FeatureInfo(@This()).create(.MessageSecurityAssistExtension4, "message-security-assist-extension4", "Assume that the message-security-assist extension facility 4 is installed", "message-security-assist-extension4"),
64 FeatureInfo(@This()).create(.MessageSecurityAssistExtension5, "message-security-assist-extension5", "Assume that the message-security-assist extension facility 5 is installed", "message-security-assist-extension5"),
65 FeatureInfo(@This()).create(.MessageSecurityAssistExtension7, "message-security-assist-extension7", "Assume that the message-security-assist extension facility 7 is installed", "message-security-assist-extension7"),
66 FeatureInfo(@This()).create(.MessageSecurityAssistExtension8, "message-security-assist-extension8", "Assume that the message-security-assist extension facility 8 is installed", "message-security-assist-extension8"),
67 FeatureInfo(@This()).create(.MessageSecurityAssistExtension9, "message-security-assist-extension9", "Assume that the message-security-assist extension facility 9 is installed", "message-security-assist-extension9"),
68 FeatureInfo(@This()).create(.MiscellaneousExtensions, "miscellaneous-extensions", "Assume that the miscellaneous-extensions facility is installed", "miscellaneous-extensions"),
69 FeatureInfo(@This()).create(.MiscellaneousExtensions2, "miscellaneous-extensions-2", "Assume that the miscellaneous-extensions facility 2 is installed", "miscellaneous-extensions-2"),
70 FeatureInfo(@This()).create(.MiscellaneousExtensions3, "miscellaneous-extensions-3", "Assume that the miscellaneous-extensions facility 3 is installed", "miscellaneous-extensions-3"),
71 FeatureInfo(@This()).create(.PopulationCount, "population-count", "Assume that the population-count facility is installed", "population-count"),
72 FeatureInfo(@This()).create(.ProcessorAssist, "processor-assist", "Assume that the processor-assist facility is installed", "processor-assist"),
73 FeatureInfo(@This()).create(.ResetReferenceBitsMultiple, "reset-reference-bits-multiple", "Assume that the reset-reference-bits-multiple facility is installed", "reset-reference-bits-multiple"),
74 FeatureInfo(@This()).create(.TransactionalExecution, "transactional-execution", "Assume that the transactional-execution facility is installed", "transactional-execution"),
75 FeatureInfo(@This()).create(.Vector, "vector", "Assume that the vectory facility is installed", "vector"),
76 FeatureInfo(@This()).create(.VectorEnhancements1, "vector-enhancements-1", "Assume that the vector enhancements facility 1 is installed", "vector-enhancements-1"),
77 FeatureInfo(@This()).create(.VectorEnhancements2, "vector-enhancements-2", "Assume that the vector enhancements facility 2 is installed", "vector-enhancements-2"),
78 FeatureInfo(@This()).create(.VectorPackedDecimal, "vector-packed-decimal", "Assume that the vector packed decimal facility is installed", "vector-packed-decimal"),
79 FeatureInfo(@This()).create(.VectorPackedDecimalEnhancement, "vector-packed-decimal-enhancement", "Assume that the vector packed decimal enhancement facility is installed", "vector-packed-decimal-enhancement"),
80 };
81};
lib/std/target/feature/WebAssemblyFeature.zig deleted-33
......@@ -1,33 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const WebAssemblyFeature = enum {
4 Atomics,
5 BulkMemory,
6 ExceptionHandling,
7 Multivalue,
8 MutableGlobals,
9 NontrappingFptoint,
10 Simd128,
11 SignExt,
12 TailCall,
13 UnimplementedSimd128,
14
15 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
16 return feature_infos[@enumToInt(self)];
17 }
18
19 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
20 FeatureInfo(@This()).create(.Atomics, "atomics", "Enable Atomics", "atomics"),
21 FeatureInfo(@This()).create(.BulkMemory, "bulk-memory", "Enable bulk memory operations", "bulk-memory"),
22 FeatureInfo(@This()).create(.ExceptionHandling, "exception-handling", "Enable Wasm exception handling", "exception-handling"),
23 FeatureInfo(@This()).create(.Multivalue, "multivalue", "Enable multivalue blocks, instructions, and functions", "multivalue"),
24 FeatureInfo(@This()).create(.MutableGlobals, "mutable-globals", "Enable mutable globals", "mutable-globals"),
25 FeatureInfo(@This()).create(.NontrappingFptoint, "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", "nontrapping-fptoint"),
26 FeatureInfo(@This()).create(.Simd128, "simd128", "Enable 128-bit SIMD", "simd128"),
27 FeatureInfo(@This()).create(.SignExt, "sign-ext", "Enable sign extension operators", "sign-ext"),
28 FeatureInfo(@This()).create(.TailCall, "tail-call", "Enable tail call instructions", "tail-call"),
29 FeatureInfo(@This()).createWithSubfeatures(.UnimplementedSimd128, "unimplemented-simd128", "Enable 128-bit SIMD not yet implemented in engines", "unimplemented-simd128", &[_]@This() {
30 .Simd128,
31 }),
32 };
33};
lib/std/target/feature/X86Feature.zig deleted-342
......@@ -1,342 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const X86Feature = enum {
4 Dnow3,
5 Dnowa3,
6 Bit64,
7 Adx,
8 Aes,
9 Avx,
10 Avx2,
11 Avx512f,
12 Avx512bf16,
13 Avx512bitalg,
14 Bmi,
15 Bmi2,
16 Avx512bw,
17 Branchfusion,
18 Avx512cd,
19 Cldemote,
20 Clflushopt,
21 Clwb,
22 Clzero,
23 Cmov,
24 Cx8,
25 Cx16,
26 Avx512dq,
27 Mpx,
28 Enqcmd,
29 Avx512er,
30 Ermsb,
31 F16c,
32 Fma,
33 Fma4,
34 Fsgsbase,
35 Fxsr,
36 Fast11bytenop,
37 Fast15bytenop,
38 FastBextr,
39 FastHops,
40 FastLzcnt,
41 FastPartialYmmOrZmmWrite,
42 FastShldRotate,
43 FastScalarFsqrt,
44 FastScalarShiftMasks,
45 FastVariableShuffle,
46 FastVectorFsqrt,
47 FastVectorShiftMasks,
48 Gfni,
49 FastGather,
50 Avx512ifma,
51 Invpcid,
52 Sahf,
53 LeaSp,
54 LeaUsesAg,
55 Lwp,
56 Lzcnt,
57 FalseDepsLzcntTzcnt,
58 Mmx,
59 Movbe,
60 Movdir64b,
61 Movdiri,
62 Mwaitx,
63 Macrofusion,
64 MergeToThreewayBranch,
65 Nopl,
66 Pclmul,
67 Pconfig,
68 Avx512pf,
69 Pku,
70 Popcnt,
71 FalseDepsPopcnt,
72 Prefetchwt1,
73 Prfchw,
74 Ptwrite,
75 PadShortFunctions,
76 Prefer128Bit,
77 Prefer256Bit,
78 Rdpid,
79 Rdrnd,
80 Rdseed,
81 Rtm,
82 Retpoline,
83 RetpolineExternalThunk,
84 RetpolineIndirectBranches,
85 RetpolineIndirectCalls,
86 Sgx,
87 Sha,
88 Shstk,
89 Sse,
90 Sse2,
91 Sse3,
92 Sse4a,
93 Sse41,
94 Sse42,
95 SseUnalignedMem,
96 Ssse3,
97 Slow3opsLea,
98 IdivlToDivb,
99 IdivqToDivl,
100 SlowIncdec,
101 SlowLea,
102 SlowPmaddwd,
103 SlowPmulld,
104 SlowShld,
105 SlowTwoMemOps,
106 SlowUnalignedMem16,
107 SlowUnalignedMem32,
108 SoftFloat,
109 Tbm,
110 UseAa,
111 Vaes,
112 Avx512vbmi,
113 Avx512vbmi2,
114 Avx512vl,
115 Avx512vnni,
116 Avx512vp2intersect,
117 Vpclmulqdq,
118 Avx512vpopcntdq,
119 Waitpkg,
120 Wbnoinvd,
121 X87,
122 Xop,
123 Xsave,
124 Xsavec,
125 Xsaveopt,
126 Xsaves,
127 BitMode16,
128 BitMode32,
129 BitMode64,
130
131 pub fn getInfo(self: @This()) FeatureInfo(@This()) {
132 return feature_infos[@enumToInt(self)];
133 }
134
135 pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
136 FeatureInfo(@This()).createWithSubfeatures(.Dnow3, "3dnow", "Enable 3DNow! instructions", "3dnow", &[_]@This() {
137 .Mmx,
138 }),
139 FeatureInfo(@This()).createWithSubfeatures(.Dnowa3, "3dnowa", "Enable 3DNow! Athlon instructions", "3dnowa", &[_]@This() {
140 .Mmx,
141 }),
142 FeatureInfo(@This()).create(.Bit64, "64bit", "Support 64-bit instructions", "64bit"),
143 FeatureInfo(@This()).create(.Adx, "adx", "Support ADX instructions", "adx"),
144 FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES instructions", "aes", &[_]@This() {
145 .Sse,
146 }),
147 FeatureInfo(@This()).createWithSubfeatures(.Avx, "avx", "Enable AVX instructions", "avx", &[_]@This() {
148 .Sse,
149 }),
150 FeatureInfo(@This()).createWithSubfeatures(.Avx2, "avx2", "Enable AVX2 instructions", "avx2", &[_]@This() {
151 .Sse,
152 }),
153 FeatureInfo(@This()).createWithSubfeatures(.Avx512f, "avx512f", "Enable AVX-512 instructions", "avx512f", &[_]@This() {
154 .Sse,
155 }),
156 FeatureInfo(@This()).createWithSubfeatures(.Avx512bf16, "avx512bf16", "Support bfloat16 floating point", "avx512bf16", &[_]@This() {
157 .Sse,
158 }),
159 FeatureInfo(@This()).createWithSubfeatures(.Avx512bitalg, "avx512bitalg", "Enable AVX-512 Bit Algorithms", "avx512bitalg", &[_]@This() {
160 .Sse,
161 }),
162 FeatureInfo(@This()).create(.Bmi, "bmi", "Support BMI instructions", "bmi"),
163 FeatureInfo(@This()).create(.Bmi2, "bmi2", "Support BMI2 instructions", "bmi2"),
164 FeatureInfo(@This()).createWithSubfeatures(.Avx512bw, "avx512bw", "Enable AVX-512 Byte and Word Instructions", "avx512bw", &[_]@This() {
165 .Sse,
166 }),
167 FeatureInfo(@This()).create(.Branchfusion, "branchfusion", "CMP/TEST can be fused with conditional branches", "branchfusion"),
168 FeatureInfo(@This()).createWithSubfeatures(.Avx512cd, "avx512cd", "Enable AVX-512 Conflict Detection Instructions", "avx512cd", &[_]@This() {
169 .Sse,
170 }),
171 FeatureInfo(@This()).create(.Cldemote, "cldemote", "Enable Cache Demote", "cldemote"),
172 FeatureInfo(@This()).create(.Clflushopt, "clflushopt", "Flush A Cache Line Optimized", "clflushopt"),
173 FeatureInfo(@This()).create(.Clwb, "clwb", "Cache Line Write Back", "clwb"),
174 FeatureInfo(@This()).create(.Clzero, "clzero", "Enable Cache Line Zero", "clzero"),
175 FeatureInfo(@This()).create(.Cmov, "cmov", "Enable conditional move instructions", "cmov"),
176 FeatureInfo(@This()).create(.Cx8, "cx8", "Support CMPXCHG8B instructions", "cx8"),
177 FeatureInfo(@This()).createWithSubfeatures(.Cx16, "cx16", "64-bit with cmpxchg16b", "cx16", &[_]@This() {
178 .Cx8,
179 }),
180 FeatureInfo(@This()).createWithSubfeatures(.Avx512dq, "avx512dq", "Enable AVX-512 Doubleword and Quadword Instructions", "avx512dq", &[_]@This() {
181 .Sse,
182 }),
183 FeatureInfo(@This()).create(.Mpx, "mpx", "Deprecated. Support MPX instructions", "mpx"),
184 FeatureInfo(@This()).create(.Enqcmd, "enqcmd", "Has ENQCMD instructions", "enqcmd"),
185 FeatureInfo(@This()).createWithSubfeatures(.Avx512er, "avx512er", "Enable AVX-512 Exponential and Reciprocal Instructions", "avx512er", &[_]@This() {
186 .Sse,
187 }),
188 FeatureInfo(@This()).create(.Ermsb, "ermsb", "REP MOVS/STOS are fast", "ermsb"),
189 FeatureInfo(@This()).createWithSubfeatures(.F16c, "f16c", "Support 16-bit floating point conversion instructions", "f16c", &[_]@This() {
190 .Sse,
191 }),
192 FeatureInfo(@This()).createWithSubfeatures(.Fma, "fma", "Enable three-operand fused multiple-add", "fma", &[_]@This() {
193 .Sse,
194 }),
195 FeatureInfo(@This()).createWithSubfeatures(.Fma4, "fma4", "Enable four-operand fused multiple-add", "fma4", &[_]@This() {
196 .Sse,
197 }),
198 FeatureInfo(@This()).create(.Fsgsbase, "fsgsbase", "Support FS/GS Base instructions", "fsgsbase"),
199 FeatureInfo(@This()).create(.Fxsr, "fxsr", "Support fxsave/fxrestore instructions", "fxsr"),
200 FeatureInfo(@This()).create(.Fast11bytenop, "fast-11bytenop", "Target can quickly decode up to 11 byte NOPs", "fast-11bytenop"),
201 FeatureInfo(@This()).create(.Fast15bytenop, "fast-15bytenop", "Target can quickly decode up to 15 byte NOPs", "fast-15bytenop"),
202 FeatureInfo(@This()).create(.FastBextr, "fast-bextr", "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", "fast-bextr"),
203 FeatureInfo(@This()).createWithSubfeatures(.FastHops, "fast-hops", "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", "fast-hops", &[_]@This() {
204 .Sse,
205 }),
206 FeatureInfo(@This()).create(.FastLzcnt, "fast-lzcnt", "LZCNT instructions are as fast as most simple integer ops", "fast-lzcnt"),
207 FeatureInfo(@This()).create(.FastPartialYmmOrZmmWrite, "fast-partial-ymm-or-zmm-write", "Partial writes to YMM/ZMM registers are fast", "fast-partial-ymm-or-zmm-write"),
208 FeatureInfo(@This()).create(.FastShldRotate, "fast-shld-rotate", "SHLD can be used as a faster rotate", "fast-shld-rotate"),
209 FeatureInfo(@This()).create(.FastScalarFsqrt, "fast-scalar-fsqrt", "Scalar SQRT is fast (disable Newton-Raphson)", "fast-scalar-fsqrt"),
210 FeatureInfo(@This()).create(.FastScalarShiftMasks, "fast-scalar-shift-masks", "Prefer a left/right scalar logical shift pair over a shift+and pair", "fast-scalar-shift-masks"),
211 FeatureInfo(@This()).create(.FastVariableShuffle, "fast-variable-shuffle", "Shuffles with variable masks are fast", "fast-variable-shuffle"),
212 FeatureInfo(@This()).create(.FastVectorFsqrt, "fast-vector-fsqrt", "Vector SQRT is fast (disable Newton-Raphson)", "fast-vector-fsqrt"),
213 FeatureInfo(@This()).create(.FastVectorShiftMasks, "fast-vector-shift-masks", "Prefer a left/right vector logical shift pair over a shift+and pair", "fast-vector-shift-masks"),
214 FeatureInfo(@This()).createWithSubfeatures(.Gfni, "gfni", "Enable Galois Field Arithmetic Instructions", "gfni", &[_]@This() {
215 .Sse,
216 }),
217 FeatureInfo(@This()).create(.FastGather, "fast-gather", "Indicates if gather is reasonably fast", "fast-gather"),
218 FeatureInfo(@This()).createWithSubfeatures(.Avx512ifma, "avx512ifma", "Enable AVX-512 Integer Fused Multiple-Add", "avx512ifma", &[_]@This() {
219 .Sse,
220 }),
221 FeatureInfo(@This()).create(.Invpcid, "invpcid", "Invalidate Process-Context Identifier", "invpcid"),
222 FeatureInfo(@This()).create(.Sahf, "sahf", "Support LAHF and SAHF instructions", "sahf"),
223 FeatureInfo(@This()).create(.LeaSp, "lea-sp", "Use LEA for adjusting the stack pointer", "lea-sp"),
224 FeatureInfo(@This()).create(.LeaUsesAg, "lea-uses-ag", "LEA instruction needs inputs at AG stage", "lea-uses-ag"),
225 FeatureInfo(@This()).create(.Lwp, "lwp", "Enable LWP instructions", "lwp"),
226 FeatureInfo(@This()).create(.Lzcnt, "lzcnt", "Support LZCNT instruction", "lzcnt"),
227 FeatureInfo(@This()).create(.FalseDepsLzcntTzcnt, "false-deps-lzcnt-tzcnt", "LZCNT/TZCNT have a false dependency on dest register", "false-deps-lzcnt-tzcnt"),
228 FeatureInfo(@This()).create(.Mmx, "mmx", "Enable MMX instructions", "mmx"),
229 FeatureInfo(@This()).create(.Movbe, "movbe", "Support MOVBE instruction", "movbe"),
230 FeatureInfo(@This()).create(.Movdir64b, "movdir64b", "Support movdir64b instruction", "movdir64b"),
231 FeatureInfo(@This()).create(.Movdiri, "movdiri", "Support movdiri instruction", "movdiri"),
232 FeatureInfo(@This()).create(.Mwaitx, "mwaitx", "Enable MONITORX/MWAITX timer functionality", "mwaitx"),
233 FeatureInfo(@This()).create(.Macrofusion, "macrofusion", "Various instructions can be fused with conditional branches", "macrofusion"),
234 FeatureInfo(@This()).create(.MergeToThreewayBranch, "merge-to-threeway-branch", "Merge branches to a three-way conditional branch", "merge-to-threeway-branch"),
235 FeatureInfo(@This()).create(.Nopl, "nopl", "Enable NOPL instruction", "nopl"),
236 FeatureInfo(@This()).createWithSubfeatures(.Pclmul, "pclmul", "Enable packed carry-less multiplication instructions", "pclmul", &[_]@This() {
237 .Sse,
238 }),
239 FeatureInfo(@This()).create(.Pconfig, "pconfig", "platform configuration instruction", "pconfig"),
240 FeatureInfo(@This()).createWithSubfeatures(.Avx512pf, "avx512pf", "Enable AVX-512 PreFetch Instructions", "avx512pf", &[_]@This() {
241 .Sse,
242 }),
243 FeatureInfo(@This()).create(.Pku, "pku", "Enable protection keys", "pku"),
244 FeatureInfo(@This()).create(.Popcnt, "popcnt", "Support POPCNT instruction", "popcnt"),
245 FeatureInfo(@This()).create(.FalseDepsPopcnt, "false-deps-popcnt", "POPCNT has a false dependency on dest register", "false-deps-popcnt"),
246 FeatureInfo(@This()).create(.Prefetchwt1, "prefetchwt1", "Prefetch with Intent to Write and T1 Hint", "prefetchwt1"),
247 FeatureInfo(@This()).create(.Prfchw, "prfchw", "Support PRFCHW instructions", "prfchw"),
248 FeatureInfo(@This()).create(.Ptwrite, "ptwrite", "Support ptwrite instruction", "ptwrite"),
249 FeatureInfo(@This()).create(.PadShortFunctions, "pad-short-functions", "Pad short functions", "pad-short-functions"),
250 FeatureInfo(@This()).create(.Prefer128Bit, "prefer-128-bit", "Prefer 128-bit AVX instructions", "prefer-128-bit"),
251 FeatureInfo(@This()).create(.Prefer256Bit, "prefer-256-bit", "Prefer 256-bit AVX instructions", "prefer-256-bit"),
252 FeatureInfo(@This()).create(.Rdpid, "rdpid", "Support RDPID instructions", "rdpid"),
253 FeatureInfo(@This()).create(.Rdrnd, "rdrnd", "Support RDRAND instruction", "rdrnd"),
254 FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
255 FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
256 FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
257 .RetpolineIndirectCalls,
258 .RetpolineIndirectBranches,
259 }),
260 FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
261 .RetpolineIndirectCalls,
262 }),
263 FeatureInfo(@This()).create(.RetpolineIndirectBranches, "retpoline-indirect-branches", "Remove speculation of indirect branches from the generated code", "retpoline-indirect-branches"),
264 FeatureInfo(@This()).create(.RetpolineIndirectCalls, "retpoline-indirect-calls", "Remove speculation of indirect calls from the generated code", "retpoline-indirect-calls"),
265 FeatureInfo(@This()).create(.Sgx, "sgx", "Enable Software Guard Extensions", "sgx"),
266 FeatureInfo(@This()).createWithSubfeatures(.Sha, "sha", "Enable SHA instructions", "sha", &[_]@This() {
267 .Sse,
268 }),
269 FeatureInfo(@This()).create(.Shstk, "shstk", "Support CET Shadow-Stack instructions", "shstk"),
270 FeatureInfo(@This()).create(.Sse, "sse", "Enable SSE instructions", "sse"),
271 FeatureInfo(@This()).createWithSubfeatures(.Sse2, "sse2", "Enable SSE2 instructions", "sse2", &[_]@This() {
272 .Sse,
273 }),
274 FeatureInfo(@This()).createWithSubfeatures(.Sse3, "sse3", "Enable SSE3 instructions", "sse3", &[_]@This() {
275 .Sse,
276 }),
277 FeatureInfo(@This()).createWithSubfeatures(.Sse4a, "sse4a", "Support SSE 4a instructions", "sse4a", &[_]@This() {
278 .Sse,
279 }),
280 FeatureInfo(@This()).createWithSubfeatures(.Sse41, "sse4.1", "Enable SSE 4.1 instructions", "sse4.1", &[_]@This() {
281 .Sse,
282 }),
283 FeatureInfo(@This()).createWithSubfeatures(.Sse42, "sse4.2", "Enable SSE 4.2 instructions", "sse4.2", &[_]@This() {
284 .Sse,
285 }),
286 FeatureInfo(@This()).create(.SseUnalignedMem, "sse-unaligned-mem", "Allow unaligned memory operands with SSE instructions", "sse-unaligned-mem"),
287 FeatureInfo(@This()).createWithSubfeatures(.Ssse3, "ssse3", "Enable SSSE3 instructions", "ssse3", &[_]@This() {
288 .Sse,
289 }),
290 FeatureInfo(@This()).create(.Slow3opsLea, "slow-3ops-lea", "LEA instruction with 3 ops or certain registers is slow", "slow-3ops-lea"),
291 FeatureInfo(@This()).create(.IdivlToDivb, "idivl-to-divb", "Use 8-bit divide for positive values less than 256", "idivl-to-divb"),
292 FeatureInfo(@This()).create(.IdivqToDivl, "idivq-to-divl", "Use 32-bit divide for positive values less than 2^32", "idivq-to-divl"),
293 FeatureInfo(@This()).create(.SlowIncdec, "slow-incdec", "INC and DEC instructions are slower than ADD and SUB", "slow-incdec"),
294 FeatureInfo(@This()).create(.SlowLea, "slow-lea", "LEA instruction with certain arguments is slow", "slow-lea"),
295 FeatureInfo(@This()).create(.SlowPmaddwd, "slow-pmaddwd", "PMADDWD is slower than PMULLD", "slow-pmaddwd"),
296 FeatureInfo(@This()).create(.SlowPmulld, "slow-pmulld", "PMULLD instruction is slow", "slow-pmulld"),
297 FeatureInfo(@This()).create(.SlowShld, "slow-shld", "SHLD instruction is slow", "slow-shld"),
298 FeatureInfo(@This()).create(.SlowTwoMemOps, "slow-two-mem-ops", "Two memory operand instructions are slow", "slow-two-mem-ops"),
299 FeatureInfo(@This()).create(.SlowUnalignedMem16, "slow-unaligned-mem-16", "Slow unaligned 16-byte memory access", "slow-unaligned-mem-16"),
300 FeatureInfo(@This()).create(.SlowUnalignedMem32, "slow-unaligned-mem-32", "Slow unaligned 32-byte memory access", "slow-unaligned-mem-32"),
301 FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features", "soft-float"),
302 FeatureInfo(@This()).create(.Tbm, "tbm", "Enable TBM instructions", "tbm"),
303 FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
304 FeatureInfo(@This()).createWithSubfeatures(.Vaes, "vaes", "Promote selected AES instructions to AVX512/AVX registers", "vaes", &[_]@This() {
305 .Sse,
306 }),
307 FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi, "avx512vbmi", "Enable AVX-512 Vector Byte Manipulation Instructions", "avx512vbmi", &[_]@This() {
308 .Sse,
309 }),
310 FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi2, "avx512vbmi2", "Enable AVX-512 further Vector Byte Manipulation Instructions", "avx512vbmi2", &[_]@This() {
311 .Sse,
312 }),
313 FeatureInfo(@This()).createWithSubfeatures(.Avx512vl, "avx512vl", "Enable AVX-512 Vector Length eXtensions", "avx512vl", &[_]@This() {
314 .Sse,
315 }),
316 FeatureInfo(@This()).createWithSubfeatures(.Avx512vnni, "avx512vnni", "Enable AVX-512 Vector Neural Network Instructions", "avx512vnni", &[_]@This() {
317 .Sse,
318 }),
319 FeatureInfo(@This()).createWithSubfeatures(.Avx512vp2intersect, "avx512vp2intersect", "Enable AVX-512 vp2intersect", "avx512vp2intersect", &[_]@This() {
320 .Sse,
321 }),
322 FeatureInfo(@This()).createWithSubfeatures(.Vpclmulqdq, "vpclmulqdq", "Enable vpclmulqdq instructions", "vpclmulqdq", &[_]@This() {
323 .Sse,
324 }),
325 FeatureInfo(@This()).createWithSubfeatures(.Avx512vpopcntdq, "avx512vpopcntdq", "Enable AVX-512 Population Count Instructions", "avx512vpopcntdq", &[_]@This() {
326 .Sse,
327 }),
328 FeatureInfo(@This()).create(.Waitpkg, "waitpkg", "Wait and pause enhancements", "waitpkg"),
329 FeatureInfo(@This()).create(.Wbnoinvd, "wbnoinvd", "Write Back No Invalidate", "wbnoinvd"),
330 FeatureInfo(@This()).create(.X87, "x87", "Enable X87 float instructions", "x87"),
331 FeatureInfo(@This()).createWithSubfeatures(.Xop, "xop", "Enable XOP instructions", "xop", &[_]@This() {
332 .Sse,
333 }),
334 FeatureInfo(@This()).create(.Xsave, "xsave", "Support xsave instructions", "xsave"),
335 FeatureInfo(@This()).create(.Xsavec, "xsavec", "Support xsavec instructions", "xsavec"),
336 FeatureInfo(@This()).create(.Xsaveopt, "xsaveopt", "Support xsaveopt instructions", "xsaveopt"),
337 FeatureInfo(@This()).create(.Xsaves, "xsaves", "Support xsaves instructions", "xsaves"),
338 FeatureInfo(@This()).create(.BitMode16, "16bit-mode", "16-bit mode (i8086)", "16bit-mode"),
339 FeatureInfo(@This()).create(.BitMode32, "32bit-mode", "32-bit mode (80386)", "32bit-mode"),
340 FeatureInfo(@This()).create(.BitMode64, "64bit-mode", "64-bit mode (x86_64)", "64bit-mode"),
341 };
342};
lib/std/target/feature/empty.zig deleted-5
......@@ -1,5 +0,0 @@
1const FeatureInfo = @import("std").target.feature.FeatureInfo;
2
3pub const EmptyFeature = struct {
4 pub const feature_infos = [0]FeatureInfo(@This()) {};
5};
lib/std/target/hexagon.zig created+357
......@@ -0,0 +1,357 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_v5 = Feature{
5 .name = "v5",
6 .description = "Enable Hexagon V5 architecture",
7 .llvm_name = "v5",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_v55 = Feature{
13 .name = "v55",
14 .description = "Enable Hexagon V55 architecture",
15 .llvm_name = "v55",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_v60 = Feature{
21 .name = "v60",
22 .description = "Enable Hexagon V60 architecture",
23 .llvm_name = "v60",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_v62 = Feature{
29 .name = "v62",
30 .description = "Enable Hexagon V62 architecture",
31 .llvm_name = "v62",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_v65 = Feature{
37 .name = "v65",
38 .description = "Enable Hexagon V65 architecture",
39 .llvm_name = "v65",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_v66 = Feature{
45 .name = "v66",
46 .description = "Enable Hexagon V66 architecture",
47 .llvm_name = "v66",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_hvx = Feature{
53 .name = "hvx",
54 .description = "Hexagon HVX instructions",
55 .llvm_name = "hvx",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_hvxLength64b = Feature{
61 .name = "hvx-length64b",
62 .description = "Hexagon HVX 64B instructions",
63 .llvm_name = "hvx-length64b",
64 .subfeatures = &[_]*const Feature {
65 &feature_hvx,
66 },
67};
68
69pub const feature_hvxLength128b = Feature{
70 .name = "hvx-length128b",
71 .description = "Hexagon HVX 128B instructions",
72 .llvm_name = "hvx-length128b",
73 .subfeatures = &[_]*const Feature {
74 &feature_hvx,
75 },
76};
77
78pub const feature_hvxv60 = Feature{
79 .name = "hvxv60",
80 .description = "Hexagon HVX instructions",
81 .llvm_name = "hvxv60",
82 .subfeatures = &[_]*const Feature {
83 &feature_hvx,
84 },
85};
86
87pub const feature_hvxv62 = Feature{
88 .name = "hvxv62",
89 .description = "Hexagon HVX instructions",
90 .llvm_name = "hvxv62",
91 .subfeatures = &[_]*const Feature {
92 &feature_hvx,
93 },
94};
95
96pub const feature_hvxv65 = Feature{
97 .name = "hvxv65",
98 .description = "Hexagon HVX instructions",
99 .llvm_name = "hvxv65",
100 .subfeatures = &[_]*const Feature {
101 &feature_hvx,
102 },
103};
104
105pub const feature_hvxv66 = Feature{
106 .name = "hvxv66",
107 .description = "Hexagon HVX instructions",
108 .llvm_name = "hvxv66",
109 .subfeatures = &[_]*const Feature {
110 &feature_zreg,
111 &feature_hvx,
112 },
113};
114
115pub const feature_zreg = Feature{
116 .name = "zreg",
117 .description = "Hexagon ZReg extension instructions",
118 .llvm_name = "zreg",
119 .subfeatures = &[_]*const Feature {
120 },
121};
122
123pub const feature_duplex = Feature{
124 .name = "duplex",
125 .description = "Enable generation of duplex instruction",
126 .llvm_name = "duplex",
127 .subfeatures = &[_]*const Feature {
128 },
129};
130
131pub const feature_longCalls = Feature{
132 .name = "long-calls",
133 .description = "Use constant-extended calls",
134 .llvm_name = "long-calls",
135 .subfeatures = &[_]*const Feature {
136 },
137};
138
139pub const feature_mem_noshuf = Feature{
140 .name = "mem_noshuf",
141 .description = "Supports mem_noshuf feature",
142 .llvm_name = "mem_noshuf",
143 .subfeatures = &[_]*const Feature {
144 },
145};
146
147pub const feature_memops = Feature{
148 .name = "memops",
149 .description = "Use memop instructions",
150 .llvm_name = "memops",
151 .subfeatures = &[_]*const Feature {
152 },
153};
154
155pub const feature_nvj = Feature{
156 .name = "nvj",
157 .description = "Support for new-value jumps",
158 .llvm_name = "nvj",
159 .subfeatures = &[_]*const Feature {
160 &feature_packets,
161 },
162};
163
164pub const feature_nvs = Feature{
165 .name = "nvs",
166 .description = "Support for new-value stores",
167 .llvm_name = "nvs",
168 .subfeatures = &[_]*const Feature {
169 &feature_packets,
170 },
171};
172
173pub const feature_noreturnStackElim = Feature{
174 .name = "noreturn-stack-elim",
175 .description = "Eliminate stack allocation in a noreturn function when possible",
176 .llvm_name = "noreturn-stack-elim",
177 .subfeatures = &[_]*const Feature {
178 },
179};
180
181pub const feature_packets = Feature{
182 .name = "packets",
183 .description = "Support for instruction packets",
184 .llvm_name = "packets",
185 .subfeatures = &[_]*const Feature {
186 },
187};
188
189pub const feature_reservedR19 = Feature{
190 .name = "reserved-r19",
191 .description = "Reserve register R19",
192 .llvm_name = "reserved-r19",
193 .subfeatures = &[_]*const Feature {
194 },
195};
196
197pub const feature_smallData = Feature{
198 .name = "small-data",
199 .description = "Allow GP-relative addressing of global variables",
200 .llvm_name = "small-data",
201 .subfeatures = &[_]*const Feature {
202 },
203};
204
205pub const features = &[_]*const Feature {
206 &feature_v5,
207 &feature_v55,
208 &feature_v60,
209 &feature_v62,
210 &feature_v65,
211 &feature_v66,
212 &feature_hvx,
213 &feature_hvxLength64b,
214 &feature_hvxLength128b,
215 &feature_hvxv60,
216 &feature_hvxv62,
217 &feature_hvxv65,
218 &feature_hvxv66,
219 &feature_zreg,
220 &feature_duplex,
221 &feature_longCalls,
222 &feature_mem_noshuf,
223 &feature_memops,
224 &feature_nvj,
225 &feature_nvs,
226 &feature_noreturnStackElim,
227 &feature_packets,
228 &feature_reservedR19,
229 &feature_smallData,
230};
231
232pub const cpu_generic = Cpu{
233 .name = "generic",
234 .llvm_name = "generic",
235 .subfeatures = &[_]*const Feature {
236 &feature_v5,
237 &feature_v55,
238 &feature_v60,
239 &feature_duplex,
240 &feature_memops,
241 &feature_packets,
242 &feature_nvj,
243 &feature_nvs,
244 &feature_smallData,
245 },
246};
247
248pub const cpu_hexagonv5 = Cpu{
249 .name = "hexagonv5",
250 .llvm_name = "hexagonv5",
251 .subfeatures = &[_]*const Feature {
252 &feature_v5,
253 &feature_duplex,
254 &feature_memops,
255 &feature_packets,
256 &feature_nvj,
257 &feature_nvs,
258 &feature_smallData,
259 },
260};
261
262pub const cpu_hexagonv55 = Cpu{
263 .name = "hexagonv55",
264 .llvm_name = "hexagonv55",
265 .subfeatures = &[_]*const Feature {
266 &feature_v5,
267 &feature_v55,
268 &feature_duplex,
269 &feature_memops,
270 &feature_packets,
271 &feature_nvj,
272 &feature_nvs,
273 &feature_smallData,
274 },
275};
276
277pub const cpu_hexagonv60 = Cpu{
278 .name = "hexagonv60",
279 .llvm_name = "hexagonv60",
280 .subfeatures = &[_]*const Feature {
281 &feature_v5,
282 &feature_v55,
283 &feature_v60,
284 &feature_duplex,
285 &feature_memops,
286 &feature_packets,
287 &feature_nvj,
288 &feature_nvs,
289 &feature_smallData,
290 },
291};
292
293pub const cpu_hexagonv62 = Cpu{
294 .name = "hexagonv62",
295 .llvm_name = "hexagonv62",
296 .subfeatures = &[_]*const Feature {
297 &feature_v5,
298 &feature_v55,
299 &feature_v60,
300 &feature_v62,
301 &feature_duplex,
302 &feature_memops,
303 &feature_packets,
304 &feature_nvj,
305 &feature_nvs,
306 &feature_smallData,
307 },
308};
309
310pub const cpu_hexagonv65 = Cpu{
311 .name = "hexagonv65",
312 .llvm_name = "hexagonv65",
313 .subfeatures = &[_]*const Feature {
314 &feature_v5,
315 &feature_v55,
316 &feature_v60,
317 &feature_v62,
318 &feature_v65,
319 &feature_duplex,
320 &feature_mem_noshuf,
321 &feature_memops,
322 &feature_packets,
323 &feature_nvj,
324 &feature_nvs,
325 &feature_smallData,
326 },
327};
328
329pub const cpu_hexagonv66 = Cpu{
330 .name = "hexagonv66",
331 .llvm_name = "hexagonv66",
332 .subfeatures = &[_]*const Feature {
333 &feature_v5,
334 &feature_v55,
335 &feature_v60,
336 &feature_v62,
337 &feature_v65,
338 &feature_v66,
339 &feature_duplex,
340 &feature_mem_noshuf,
341 &feature_memops,
342 &feature_packets,
343 &feature_nvj,
344 &feature_nvs,
345 &feature_smallData,
346 },
347};
348
349pub const cpus = &[_]*const Cpu {
350 &cpu_generic,
351 &cpu_hexagonv5,
352 &cpu_hexagonv55,
353 &cpu_hexagonv60,
354 &cpu_hexagonv62,
355 &cpu_hexagonv65,
356 &cpu_hexagonv66,
357};
lib/std/target/mips.zig created+828
......@@ -0,0 +1,828 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_abs2008 = Feature{
5 .name = "abs2008",
6 .description = "Disable IEEE 754-2008 abs.fmt mode",
7 .llvm_name = "abs2008",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_crc = Feature{
13 .name = "crc",
14 .description = "Mips R6 CRC ASE",
15 .llvm_name = "crc",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_cnmips = Feature{
21 .name = "cnmips",
22 .description = "Octeon cnMIPS Support",
23 .llvm_name = "cnmips",
24 .subfeatures = &[_]*const Feature {
25 &feature_mips4_32,
26 &feature_mips3_32r2,
27 &feature_mips1,
28 &feature_gp64,
29 &feature_mips4_32r2,
30 &feature_mips5_32r2,
31 &feature_mips3_32,
32 &feature_fp64,
33 },
34};
35
36pub const feature_dsp = Feature{
37 .name = "dsp",
38 .description = "Mips DSP ASE",
39 .llvm_name = "dsp",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_dspr2 = Feature{
45 .name = "dspr2",
46 .description = "Mips DSP-R2 ASE",
47 .llvm_name = "dspr2",
48 .subfeatures = &[_]*const Feature {
49 &feature_dsp,
50 },
51};
52
53pub const feature_dspr3 = Feature{
54 .name = "dspr3",
55 .description = "Mips DSP-R3 ASE",
56 .llvm_name = "dspr3",
57 .subfeatures = &[_]*const Feature {
58 &feature_dsp,
59 },
60};
61
62pub const feature_eva = Feature{
63 .name = "eva",
64 .description = "Mips EVA ASE",
65 .llvm_name = "eva",
66 .subfeatures = &[_]*const Feature {
67 },
68};
69
70pub const feature_fp64 = Feature{
71 .name = "fp64",
72 .description = "Support 64-bit FP registers",
73 .llvm_name = "fp64",
74 .subfeatures = &[_]*const Feature {
75 },
76};
77
78pub const feature_fpxx = Feature{
79 .name = "fpxx",
80 .description = "Support for FPXX",
81 .llvm_name = "fpxx",
82 .subfeatures = &[_]*const Feature {
83 },
84};
85
86pub const feature_ginv = Feature{
87 .name = "ginv",
88 .description = "Mips Global Invalidate ASE",
89 .llvm_name = "ginv",
90 .subfeatures = &[_]*const Feature {
91 },
92};
93
94pub const feature_gp64 = Feature{
95 .name = "gp64",
96 .description = "General Purpose Registers are 64-bit wide",
97 .llvm_name = "gp64",
98 .subfeatures = &[_]*const Feature {
99 },
100};
101
102pub const feature_longCalls = Feature{
103 .name = "long-calls",
104 .description = "Disable use of the jal instruction",
105 .llvm_name = "long-calls",
106 .subfeatures = &[_]*const Feature {
107 },
108};
109
110pub const feature_msa = Feature{
111 .name = "msa",
112 .description = "Mips MSA ASE",
113 .llvm_name = "msa",
114 .subfeatures = &[_]*const Feature {
115 },
116};
117
118pub const feature_mt = Feature{
119 .name = "mt",
120 .description = "Mips MT ASE",
121 .llvm_name = "mt",
122 .subfeatures = &[_]*const Feature {
123 },
124};
125
126pub const feature_nomadd4 = Feature{
127 .name = "nomadd4",
128 .description = "Disable 4-operand madd.fmt and related instructions",
129 .llvm_name = "nomadd4",
130 .subfeatures = &[_]*const Feature {
131 },
132};
133
134pub const feature_micromips = Feature{
135 .name = "micromips",
136 .description = "microMips mode",
137 .llvm_name = "micromips",
138 .subfeatures = &[_]*const Feature {
139 },
140};
141
142pub const feature_mips1 = Feature{
143 .name = "mips1",
144 .description = "Mips I ISA Support [highly experimental]",
145 .llvm_name = "mips1",
146 .subfeatures = &[_]*const Feature {
147 },
148};
149
150pub const feature_mips2 = Feature{
151 .name = "mips2",
152 .description = "Mips II ISA Support [highly experimental]",
153 .llvm_name = "mips2",
154 .subfeatures = &[_]*const Feature {
155 &feature_mips1,
156 },
157};
158
159pub const feature_mips3 = Feature{
160 .name = "mips3",
161 .description = "MIPS III ISA Support [highly experimental]",
162 .llvm_name = "mips3",
163 .subfeatures = &[_]*const Feature {
164 &feature_mips3_32r2,
165 &feature_mips1,
166 &feature_gp64,
167 &feature_mips3_32,
168 &feature_fp64,
169 },
170};
171
172pub const feature_mips3_32 = Feature{
173 .name = "mips3_32",
174 .description = "Subset of MIPS-III that is also in MIPS32 [highly experimental]",
175 .llvm_name = "mips3_32",
176 .subfeatures = &[_]*const Feature {
177 },
178};
179
180pub const feature_mips3_32r2 = Feature{
181 .name = "mips3_32r2",
182 .description = "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]",
183 .llvm_name = "mips3_32r2",
184 .subfeatures = &[_]*const Feature {
185 },
186};
187
188pub const feature_mips4 = Feature{
189 .name = "mips4",
190 .description = "MIPS IV ISA Support",
191 .llvm_name = "mips4",
192 .subfeatures = &[_]*const Feature {
193 &feature_mips4_32,
194 &feature_mips3_32r2,
195 &feature_mips1,
196 &feature_gp64,
197 &feature_mips4_32r2,
198 &feature_mips3_32,
199 &feature_fp64,
200 },
201};
202
203pub const feature_mips4_32 = Feature{
204 .name = "mips4_32",
205 .description = "Subset of MIPS-IV that is also in MIPS32 [highly experimental]",
206 .llvm_name = "mips4_32",
207 .subfeatures = &[_]*const Feature {
208 },
209};
210
211pub const feature_mips4_32r2 = Feature{
212 .name = "mips4_32r2",
213 .description = "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]",
214 .llvm_name = "mips4_32r2",
215 .subfeatures = &[_]*const Feature {
216 },
217};
218
219pub const feature_mips5 = Feature{
220 .name = "mips5",
221 .description = "MIPS V ISA Support [highly experimental]",
222 .llvm_name = "mips5",
223 .subfeatures = &[_]*const Feature {
224 &feature_mips4_32,
225 &feature_mips3_32r2,
226 &feature_mips1,
227 &feature_gp64,
228 &feature_mips4_32r2,
229 &feature_mips5_32r2,
230 &feature_mips3_32,
231 &feature_fp64,
232 },
233};
234
235pub const feature_mips5_32r2 = Feature{
236 .name = "mips5_32r2",
237 .description = "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]",
238 .llvm_name = "mips5_32r2",
239 .subfeatures = &[_]*const Feature {
240 },
241};
242
243pub const feature_mips16 = Feature{
244 .name = "mips16",
245 .description = "Mips16 mode",
246 .llvm_name = "mips16",
247 .subfeatures = &[_]*const Feature {
248 },
249};
250
251pub const feature_mips32 = Feature{
252 .name = "mips32",
253 .description = "Mips32 ISA Support",
254 .llvm_name = "mips32",
255 .subfeatures = &[_]*const Feature {
256 &feature_mips4_32,
257 &feature_mips3_32,
258 &feature_mips1,
259 },
260};
261
262pub const feature_mips32r2 = Feature{
263 .name = "mips32r2",
264 .description = "Mips32r2 ISA Support",
265 .llvm_name = "mips32r2",
266 .subfeatures = &[_]*const Feature {
267 &feature_mips4_32,
268 &feature_mips3_32r2,
269 &feature_mips1,
270 &feature_mips4_32r2,
271 &feature_mips5_32r2,
272 &feature_mips3_32,
273 },
274};
275
276pub const feature_mips32r3 = Feature{
277 .name = "mips32r3",
278 .description = "Mips32r3 ISA Support",
279 .llvm_name = "mips32r3",
280 .subfeatures = &[_]*const Feature {
281 &feature_mips4_32,
282 &feature_mips3_32r2,
283 &feature_mips1,
284 &feature_mips4_32r2,
285 &feature_mips5_32r2,
286 &feature_mips3_32,
287 },
288};
289
290pub const feature_mips32r5 = Feature{
291 .name = "mips32r5",
292 .description = "Mips32r5 ISA Support",
293 .llvm_name = "mips32r5",
294 .subfeatures = &[_]*const Feature {
295 &feature_mips4_32,
296 &feature_mips3_32r2,
297 &feature_mips1,
298 &feature_mips4_32r2,
299 &feature_mips5_32r2,
300 &feature_mips3_32,
301 },
302};
303
304pub const feature_mips32r6 = Feature{
305 .name = "mips32r6",
306 .description = "Mips32r6 ISA Support [experimental]",
307 .llvm_name = "mips32r6",
308 .subfeatures = &[_]*const Feature {
309 &feature_mips4_32,
310 &feature_nan2008,
311 &feature_mips3_32r2,
312 &feature_mips1,
313 &feature_abs2008,
314 &feature_mips4_32r2,
315 &feature_mips5_32r2,
316 &feature_mips3_32,
317 &feature_fp64,
318 },
319};
320
321pub const feature_mips64 = Feature{
322 .name = "mips64",
323 .description = "Mips64 ISA Support",
324 .llvm_name = "mips64",
325 .subfeatures = &[_]*const Feature {
326 &feature_mips4_32,
327 &feature_mips3_32r2,
328 &feature_mips1,
329 &feature_gp64,
330 &feature_mips4_32r2,
331 &feature_mips5_32r2,
332 &feature_mips3_32,
333 &feature_fp64,
334 },
335};
336
337pub const feature_mips64r2 = Feature{
338 .name = "mips64r2",
339 .description = "Mips64r2 ISA Support",
340 .llvm_name = "mips64r2",
341 .subfeatures = &[_]*const Feature {
342 &feature_mips4_32,
343 &feature_mips3_32r2,
344 &feature_mips1,
345 &feature_gp64,
346 &feature_mips4_32r2,
347 &feature_mips5_32r2,
348 &feature_mips3_32,
349 &feature_fp64,
350 },
351};
352
353pub const feature_mips64r3 = Feature{
354 .name = "mips64r3",
355 .description = "Mips64r3 ISA Support",
356 .llvm_name = "mips64r3",
357 .subfeatures = &[_]*const Feature {
358 &feature_mips4_32,
359 &feature_mips3_32r2,
360 &feature_mips1,
361 &feature_gp64,
362 &feature_mips4_32r2,
363 &feature_mips5_32r2,
364 &feature_mips3_32,
365 &feature_fp64,
366 },
367};
368
369pub const feature_mips64r5 = Feature{
370 .name = "mips64r5",
371 .description = "Mips64r5 ISA Support",
372 .llvm_name = "mips64r5",
373 .subfeatures = &[_]*const Feature {
374 &feature_mips4_32,
375 &feature_mips3_32r2,
376 &feature_mips1,
377 &feature_gp64,
378 &feature_mips4_32r2,
379 &feature_mips5_32r2,
380 &feature_mips3_32,
381 &feature_fp64,
382 },
383};
384
385pub const feature_mips64r6 = Feature{
386 .name = "mips64r6",
387 .description = "Mips64r6 ISA Support [experimental]",
388 .llvm_name = "mips64r6",
389 .subfeatures = &[_]*const Feature {
390 &feature_mips4_32,
391 &feature_nan2008,
392 &feature_mips3_32r2,
393 &feature_mips1,
394 &feature_abs2008,
395 &feature_gp64,
396 &feature_mips4_32r2,
397 &feature_mips5_32r2,
398 &feature_mips3_32,
399 &feature_fp64,
400 },
401};
402
403pub const feature_nan2008 = Feature{
404 .name = "nan2008",
405 .description = "IEEE 754-2008 NaN encoding",
406 .llvm_name = "nan2008",
407 .subfeatures = &[_]*const Feature {
408 },
409};
410
411pub const feature_noabicalls = Feature{
412 .name = "noabicalls",
413 .description = "Disable SVR4-style position-independent code",
414 .llvm_name = "noabicalls",
415 .subfeatures = &[_]*const Feature {
416 },
417};
418
419pub const feature_nooddspreg = Feature{
420 .name = "nooddspreg",
421 .description = "Disable odd numbered single-precision registers",
422 .llvm_name = "nooddspreg",
423 .subfeatures = &[_]*const Feature {
424 },
425};
426
427pub const feature_ptr64 = Feature{
428 .name = "ptr64",
429 .description = "Pointers are 64-bit wide",
430 .llvm_name = "ptr64",
431 .subfeatures = &[_]*const Feature {
432 },
433};
434
435pub const feature_singleFloat = Feature{
436 .name = "single-float",
437 .description = "Only supports single precision float",
438 .llvm_name = "single-float",
439 .subfeatures = &[_]*const Feature {
440 },
441};
442
443pub const feature_softFloat = Feature{
444 .name = "soft-float",
445 .description = "Does not support floating point instructions",
446 .llvm_name = "soft-float",
447 .subfeatures = &[_]*const Feature {
448 },
449};
450
451pub const feature_sym32 = Feature{
452 .name = "sym32",
453 .description = "Symbols are 32 bit on Mips64",
454 .llvm_name = "sym32",
455 .subfeatures = &[_]*const Feature {
456 },
457};
458
459pub const feature_useIndirectJumpHazard = Feature{
460 .name = "use-indirect-jump-hazard",
461 .description = "Use indirect jump guards to prevent certain speculation based attacks",
462 .llvm_name = "use-indirect-jump-hazard",
463 .subfeatures = &[_]*const Feature {
464 },
465};
466
467pub const feature_useTccInDiv = Feature{
468 .name = "use-tcc-in-div",
469 .description = "Force the assembler to use trapping",
470 .llvm_name = "use-tcc-in-div",
471 .subfeatures = &[_]*const Feature {
472 },
473};
474
475pub const feature_vfpu = Feature{
476 .name = "vfpu",
477 .description = "Enable vector FPU instructions",
478 .llvm_name = "vfpu",
479 .subfeatures = &[_]*const Feature {
480 },
481};
482
483pub const feature_virt = Feature{
484 .name = "virt",
485 .description = "Mips Virtualization ASE",
486 .llvm_name = "virt",
487 .subfeatures = &[_]*const Feature {
488 },
489};
490
491pub const feature_xgot = Feature{
492 .name = "xgot",
493 .description = "Assume 32-bit GOT",
494 .llvm_name = "xgot",
495 .subfeatures = &[_]*const Feature {
496 },
497};
498
499pub const feature_p5600 = Feature{
500 .name = "p5600",
501 .description = "The P5600 Processor",
502 .llvm_name = "p5600",
503 .subfeatures = &[_]*const Feature {
504 &feature_mips4_32,
505 &feature_mips3_32r2,
506 &feature_mips1,
507 &feature_mips4_32r2,
508 &feature_mips5_32r2,
509 &feature_mips3_32,
510 },
511};
512
513pub const features = &[_]*const Feature {
514 &feature_abs2008,
515 &feature_crc,
516 &feature_cnmips,
517 &feature_dsp,
518 &feature_dspr2,
519 &feature_dspr3,
520 &feature_eva,
521 &feature_fp64,
522 &feature_fpxx,
523 &feature_ginv,
524 &feature_gp64,
525 &feature_longCalls,
526 &feature_msa,
527 &feature_mt,
528 &feature_nomadd4,
529 &feature_micromips,
530 &feature_mips1,
531 &feature_mips2,
532 &feature_mips3,
533 &feature_mips3_32,
534 &feature_mips3_32r2,
535 &feature_mips4,
536 &feature_mips4_32,
537 &feature_mips4_32r2,
538 &feature_mips5,
539 &feature_mips5_32r2,
540 &feature_mips16,
541 &feature_mips32,
542 &feature_mips32r2,
543 &feature_mips32r3,
544 &feature_mips32r5,
545 &feature_mips32r6,
546 &feature_mips64,
547 &feature_mips64r2,
548 &feature_mips64r3,
549 &feature_mips64r5,
550 &feature_mips64r6,
551 &feature_nan2008,
552 &feature_noabicalls,
553 &feature_nooddspreg,
554 &feature_ptr64,
555 &feature_singleFloat,
556 &feature_softFloat,
557 &feature_sym32,
558 &feature_useIndirectJumpHazard,
559 &feature_useTccInDiv,
560 &feature_vfpu,
561 &feature_virt,
562 &feature_xgot,
563 &feature_p5600,
564};
565
566pub const cpu_mips1 = Cpu{
567 .name = "mips1",
568 .llvm_name = "mips1",
569 .subfeatures = &[_]*const Feature {
570 &feature_mips1,
571 },
572};
573
574pub const cpu_mips2 = Cpu{
575 .name = "mips2",
576 .llvm_name = "mips2",
577 .subfeatures = &[_]*const Feature {
578 &feature_mips1,
579 &feature_mips2,
580 },
581};
582
583pub const cpu_mips3 = Cpu{
584 .name = "mips3",
585 .llvm_name = "mips3",
586 .subfeatures = &[_]*const Feature {
587 &feature_mips3_32r2,
588 &feature_mips1,
589 &feature_gp64,
590 &feature_mips3_32,
591 &feature_fp64,
592 &feature_mips3,
593 },
594};
595
596pub const cpu_mips32 = Cpu{
597 .name = "mips32",
598 .llvm_name = "mips32",
599 .subfeatures = &[_]*const Feature {
600 &feature_mips4_32,
601 &feature_mips3_32,
602 &feature_mips1,
603 &feature_mips32,
604 },
605};
606
607pub const cpu_mips32r2 = Cpu{
608 .name = "mips32r2",
609 .llvm_name = "mips32r2",
610 .subfeatures = &[_]*const Feature {
611 &feature_mips4_32,
612 &feature_mips3_32r2,
613 &feature_mips1,
614 &feature_mips4_32r2,
615 &feature_mips5_32r2,
616 &feature_mips3_32,
617 &feature_mips32r2,
618 },
619};
620
621pub const cpu_mips32r3 = Cpu{
622 .name = "mips32r3",
623 .llvm_name = "mips32r3",
624 .subfeatures = &[_]*const Feature {
625 &feature_mips4_32,
626 &feature_mips3_32r2,
627 &feature_mips1,
628 &feature_mips4_32r2,
629 &feature_mips5_32r2,
630 &feature_mips3_32,
631 &feature_mips32r3,
632 },
633};
634
635pub const cpu_mips32r5 = Cpu{
636 .name = "mips32r5",
637 .llvm_name = "mips32r5",
638 .subfeatures = &[_]*const Feature {
639 &feature_mips4_32,
640 &feature_mips3_32r2,
641 &feature_mips1,
642 &feature_mips4_32r2,
643 &feature_mips5_32r2,
644 &feature_mips3_32,
645 &feature_mips32r5,
646 },
647};
648
649pub const cpu_mips32r6 = Cpu{
650 .name = "mips32r6",
651 .llvm_name = "mips32r6",
652 .subfeatures = &[_]*const Feature {
653 &feature_mips4_32,
654 &feature_nan2008,
655 &feature_mips3_32r2,
656 &feature_mips1,
657 &feature_abs2008,
658 &feature_mips4_32r2,
659 &feature_mips5_32r2,
660 &feature_mips3_32,
661 &feature_fp64,
662 &feature_mips32r6,
663 },
664};
665
666pub const cpu_mips4 = Cpu{
667 .name = "mips4",
668 .llvm_name = "mips4",
669 .subfeatures = &[_]*const Feature {
670 &feature_mips4_32,
671 &feature_mips3_32r2,
672 &feature_mips1,
673 &feature_gp64,
674 &feature_mips4_32r2,
675 &feature_mips3_32,
676 &feature_fp64,
677 &feature_mips4,
678 },
679};
680
681pub const cpu_mips5 = Cpu{
682 .name = "mips5",
683 .llvm_name = "mips5",
684 .subfeatures = &[_]*const Feature {
685 &feature_mips4_32,
686 &feature_mips3_32r2,
687 &feature_mips1,
688 &feature_gp64,
689 &feature_mips4_32r2,
690 &feature_mips5_32r2,
691 &feature_mips3_32,
692 &feature_fp64,
693 &feature_mips5,
694 },
695};
696
697pub const cpu_mips64 = Cpu{
698 .name = "mips64",
699 .llvm_name = "mips64",
700 .subfeatures = &[_]*const Feature {
701 &feature_mips4_32,
702 &feature_mips3_32r2,
703 &feature_mips1,
704 &feature_gp64,
705 &feature_mips4_32r2,
706 &feature_mips5_32r2,
707 &feature_mips3_32,
708 &feature_fp64,
709 &feature_mips64,
710 },
711};
712
713pub const cpu_mips64r2 = Cpu{
714 .name = "mips64r2",
715 .llvm_name = "mips64r2",
716 .subfeatures = &[_]*const Feature {
717 &feature_mips4_32,
718 &feature_mips3_32r2,
719 &feature_mips1,
720 &feature_gp64,
721 &feature_mips4_32r2,
722 &feature_mips5_32r2,
723 &feature_mips3_32,
724 &feature_fp64,
725 &feature_mips64r2,
726 },
727};
728
729pub const cpu_mips64r3 = Cpu{
730 .name = "mips64r3",
731 .llvm_name = "mips64r3",
732 .subfeatures = &[_]*const Feature {
733 &feature_mips4_32,
734 &feature_mips3_32r2,
735 &feature_mips1,
736 &feature_gp64,
737 &feature_mips4_32r2,
738 &feature_mips5_32r2,
739 &feature_mips3_32,
740 &feature_fp64,
741 &feature_mips64r3,
742 },
743};
744
745pub const cpu_mips64r5 = Cpu{
746 .name = "mips64r5",
747 .llvm_name = "mips64r5",
748 .subfeatures = &[_]*const Feature {
749 &feature_mips4_32,
750 &feature_mips3_32r2,
751 &feature_mips1,
752 &feature_gp64,
753 &feature_mips4_32r2,
754 &feature_mips5_32r2,
755 &feature_mips3_32,
756 &feature_fp64,
757 &feature_mips64r5,
758 },
759};
760
761pub const cpu_mips64r6 = Cpu{
762 .name = "mips64r6",
763 .llvm_name = "mips64r6",
764 .subfeatures = &[_]*const Feature {
765 &feature_mips4_32,
766 &feature_nan2008,
767 &feature_mips3_32r2,
768 &feature_mips1,
769 &feature_abs2008,
770 &feature_gp64,
771 &feature_mips4_32r2,
772 &feature_mips5_32r2,
773 &feature_mips3_32,
774 &feature_fp64,
775 &feature_mips64r6,
776 },
777};
778
779pub const cpu_octeon = Cpu{
780 .name = "octeon",
781 .llvm_name = "octeon",
782 .subfeatures = &[_]*const Feature {
783 &feature_mips4_32,
784 &feature_mips3_32r2,
785 &feature_mips1,
786 &feature_gp64,
787 &feature_mips4_32r2,
788 &feature_mips5_32r2,
789 &feature_mips3_32,
790 &feature_fp64,
791 &feature_cnmips,
792 &feature_mips64r2,
793 },
794};
795
796pub const cpu_p5600 = Cpu{
797 .name = "p5600",
798 .llvm_name = "p5600",
799 .subfeatures = &[_]*const Feature {
800 &feature_mips4_32,
801 &feature_mips3_32r2,
802 &feature_mips1,
803 &feature_mips4_32r2,
804 &feature_mips5_32r2,
805 &feature_mips3_32,
806 &feature_p5600,
807 },
808};
809
810pub const cpus = &[_]*const Cpu {
811 &cpu_mips1,
812 &cpu_mips2,
813 &cpu_mips3,
814 &cpu_mips32,
815 &cpu_mips32r2,
816 &cpu_mips32r3,
817 &cpu_mips32r5,
818 &cpu_mips32r6,
819 &cpu_mips4,
820 &cpu_mips5,
821 &cpu_mips64,
822 &cpu_mips64r2,
823 &cpu_mips64r3,
824 &cpu_mips64r5,
825 &cpu_mips64r6,
826 &cpu_octeon,
827 &cpu_p5600,
828};
lib/std/target/msp430.zig created+69
......@@ -0,0 +1,69 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_hwmult16 = Feature{
5 .name = "hwmult16",
6 .description = "Enable 16-bit hardware multiplier",
7 .llvm_name = "hwmult16",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_hwmult32 = Feature{
13 .name = "hwmult32",
14 .description = "Enable 32-bit hardware multiplier",
15 .llvm_name = "hwmult32",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_hwmultf5 = Feature{
21 .name = "hwmultf5",
22 .description = "Enable F5 series hardware multiplier",
23 .llvm_name = "hwmultf5",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_ext = Feature{
29 .name = "ext",
30 .description = "Enable MSP430-X extensions",
31 .llvm_name = "ext",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const features = &[_]*const Feature {
37 &feature_hwmult16,
38 &feature_hwmult32,
39 &feature_hwmultf5,
40 &feature_ext,
41};
42
43pub const cpu_generic = Cpu{
44 .name = "generic",
45 .llvm_name = "generic",
46 .subfeatures = &[_]*const Feature {
47 },
48};
49
50pub const cpu_msp430 = Cpu{
51 .name = "msp430",
52 .llvm_name = "msp430",
53 .subfeatures = &[_]*const Feature {
54 },
55};
56
57pub const cpu_msp430x = Cpu{
58 .name = "msp430x",
59 .llvm_name = "msp430x",
60 .subfeatures = &[_]*const Feature {
61 &feature_ext,
62 },
63};
64
65pub const cpus = &[_]*const Cpu {
66 &cpu_generic,
67 &cpu_msp430,
68 &cpu_msp430x,
69};
lib/std/target/nvptx.zig created+379
......@@ -0,0 +1,379 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_ptx32 = Feature{
5 .name = "ptx32",
6 .description = "Use PTX version 3.2",
7 .llvm_name = "ptx32",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_ptx40 = Feature{
13 .name = "ptx40",
14 .description = "Use PTX version 4.0",
15 .llvm_name = "ptx40",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_ptx41 = Feature{
21 .name = "ptx41",
22 .description = "Use PTX version 4.1",
23 .llvm_name = "ptx41",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_ptx42 = Feature{
29 .name = "ptx42",
30 .description = "Use PTX version 4.2",
31 .llvm_name = "ptx42",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_ptx43 = Feature{
37 .name = "ptx43",
38 .description = "Use PTX version 4.3",
39 .llvm_name = "ptx43",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_ptx50 = Feature{
45 .name = "ptx50",
46 .description = "Use PTX version 5.0",
47 .llvm_name = "ptx50",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_ptx60 = Feature{
53 .name = "ptx60",
54 .description = "Use PTX version 6.0",
55 .llvm_name = "ptx60",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_ptx61 = Feature{
61 .name = "ptx61",
62 .description = "Use PTX version 6.1",
63 .llvm_name = "ptx61",
64 .subfeatures = &[_]*const Feature {
65 },
66};
67
68pub const feature_ptx63 = Feature{
69 .name = "ptx63",
70 .description = "Use PTX version 6.3",
71 .llvm_name = "ptx63",
72 .subfeatures = &[_]*const Feature {
73 },
74};
75
76pub const feature_ptx64 = Feature{
77 .name = "ptx64",
78 .description = "Use PTX version 6.4",
79 .llvm_name = "ptx64",
80 .subfeatures = &[_]*const Feature {
81 },
82};
83
84pub const feature_sm_20 = Feature{
85 .name = "sm_20",
86 .description = "Target SM 2.0",
87 .llvm_name = "sm_20",
88 .subfeatures = &[_]*const Feature {
89 },
90};
91
92pub const feature_sm_21 = Feature{
93 .name = "sm_21",
94 .description = "Target SM 2.1",
95 .llvm_name = "sm_21",
96 .subfeatures = &[_]*const Feature {
97 },
98};
99
100pub const feature_sm_30 = Feature{
101 .name = "sm_30",
102 .description = "Target SM 3.0",
103 .llvm_name = "sm_30",
104 .subfeatures = &[_]*const Feature {
105 },
106};
107
108pub const feature_sm_32 = Feature{
109 .name = "sm_32",
110 .description = "Target SM 3.2",
111 .llvm_name = "sm_32",
112 .subfeatures = &[_]*const Feature {
113 },
114};
115
116pub const feature_sm_35 = Feature{
117 .name = "sm_35",
118 .description = "Target SM 3.5",
119 .llvm_name = "sm_35",
120 .subfeatures = &[_]*const Feature {
121 },
122};
123
124pub const feature_sm_37 = Feature{
125 .name = "sm_37",
126 .description = "Target SM 3.7",
127 .llvm_name = "sm_37",
128 .subfeatures = &[_]*const Feature {
129 },
130};
131
132pub const feature_sm_50 = Feature{
133 .name = "sm_50",
134 .description = "Target SM 5.0",
135 .llvm_name = "sm_50",
136 .subfeatures = &[_]*const Feature {
137 },
138};
139
140pub const feature_sm_52 = Feature{
141 .name = "sm_52",
142 .description = "Target SM 5.2",
143 .llvm_name = "sm_52",
144 .subfeatures = &[_]*const Feature {
145 },
146};
147
148pub const feature_sm_53 = Feature{
149 .name = "sm_53",
150 .description = "Target SM 5.3",
151 .llvm_name = "sm_53",
152 .subfeatures = &[_]*const Feature {
153 },
154};
155
156pub const feature_sm_60 = Feature{
157 .name = "sm_60",
158 .description = "Target SM 6.0",
159 .llvm_name = "sm_60",
160 .subfeatures = &[_]*const Feature {
161 },
162};
163
164pub const feature_sm_61 = Feature{
165 .name = "sm_61",
166 .description = "Target SM 6.1",
167 .llvm_name = "sm_61",
168 .subfeatures = &[_]*const Feature {
169 },
170};
171
172pub const feature_sm_62 = Feature{
173 .name = "sm_62",
174 .description = "Target SM 6.2",
175 .llvm_name = "sm_62",
176 .subfeatures = &[_]*const Feature {
177 },
178};
179
180pub const feature_sm_70 = Feature{
181 .name = "sm_70",
182 .description = "Target SM 7.0",
183 .llvm_name = "sm_70",
184 .subfeatures = &[_]*const Feature {
185 },
186};
187
188pub const feature_sm_72 = Feature{
189 .name = "sm_72",
190 .description = "Target SM 7.2",
191 .llvm_name = "sm_72",
192 .subfeatures = &[_]*const Feature {
193 },
194};
195
196pub const feature_sm_75 = Feature{
197 .name = "sm_75",
198 .description = "Target SM 7.5",
199 .llvm_name = "sm_75",
200 .subfeatures = &[_]*const Feature {
201 },
202};
203
204pub const features = &[_]*const Feature {
205 &feature_ptx32,
206 &feature_ptx40,
207 &feature_ptx41,
208 &feature_ptx42,
209 &feature_ptx43,
210 &feature_ptx50,
211 &feature_ptx60,
212 &feature_ptx61,
213 &feature_ptx63,
214 &feature_ptx64,
215 &feature_sm_20,
216 &feature_sm_21,
217 &feature_sm_30,
218 &feature_sm_32,
219 &feature_sm_35,
220 &feature_sm_37,
221 &feature_sm_50,
222 &feature_sm_52,
223 &feature_sm_53,
224 &feature_sm_60,
225 &feature_sm_61,
226 &feature_sm_62,
227 &feature_sm_70,
228 &feature_sm_72,
229 &feature_sm_75,
230};
231
232pub const cpu_sm_20 = Cpu{
233 .name = "sm_20",
234 .llvm_name = "sm_20",
235 .subfeatures = &[_]*const Feature {
236 &feature_sm_20,
237 },
238};
239
240pub const cpu_sm_21 = Cpu{
241 .name = "sm_21",
242 .llvm_name = "sm_21",
243 .subfeatures = &[_]*const Feature {
244 &feature_sm_21,
245 },
246};
247
248pub const cpu_sm_30 = Cpu{
249 .name = "sm_30",
250 .llvm_name = "sm_30",
251 .subfeatures = &[_]*const Feature {
252 &feature_sm_30,
253 },
254};
255
256pub const cpu_sm_32 = Cpu{
257 .name = "sm_32",
258 .llvm_name = "sm_32",
259 .subfeatures = &[_]*const Feature {
260 &feature_ptx40,
261 &feature_sm_32,
262 },
263};
264
265pub const cpu_sm_35 = Cpu{
266 .name = "sm_35",
267 .llvm_name = "sm_35",
268 .subfeatures = &[_]*const Feature {
269 &feature_sm_35,
270 },
271};
272
273pub const cpu_sm_37 = Cpu{
274 .name = "sm_37",
275 .llvm_name = "sm_37",
276 .subfeatures = &[_]*const Feature {
277 &feature_ptx41,
278 &feature_sm_37,
279 },
280};
281
282pub const cpu_sm_50 = Cpu{
283 .name = "sm_50",
284 .llvm_name = "sm_50",
285 .subfeatures = &[_]*const Feature {
286 &feature_ptx40,
287 &feature_sm_50,
288 },
289};
290
291pub const cpu_sm_52 = Cpu{
292 .name = "sm_52",
293 .llvm_name = "sm_52",
294 .subfeatures = &[_]*const Feature {
295 &feature_ptx41,
296 &feature_sm_52,
297 },
298};
299
300pub const cpu_sm_53 = Cpu{
301 .name = "sm_53",
302 .llvm_name = "sm_53",
303 .subfeatures = &[_]*const Feature {
304 &feature_ptx42,
305 &feature_sm_53,
306 },
307};
308
309pub const cpu_sm_60 = Cpu{
310 .name = "sm_60",
311 .llvm_name = "sm_60",
312 .subfeatures = &[_]*const Feature {
313 &feature_ptx50,
314 &feature_sm_60,
315 },
316};
317
318pub const cpu_sm_61 = Cpu{
319 .name = "sm_61",
320 .llvm_name = "sm_61",
321 .subfeatures = &[_]*const Feature {
322 &feature_ptx50,
323 &feature_sm_61,
324 },
325};
326
327pub const cpu_sm_62 = Cpu{
328 .name = "sm_62",
329 .llvm_name = "sm_62",
330 .subfeatures = &[_]*const Feature {
331 &feature_ptx50,
332 &feature_sm_62,
333 },
334};
335
336pub const cpu_sm_70 = Cpu{
337 .name = "sm_70",
338 .llvm_name = "sm_70",
339 .subfeatures = &[_]*const Feature {
340 &feature_ptx60,
341 &feature_sm_70,
342 },
343};
344
345pub const cpu_sm_72 = Cpu{
346 .name = "sm_72",
347 .llvm_name = "sm_72",
348 .subfeatures = &[_]*const Feature {
349 &feature_ptx61,
350 &feature_sm_72,
351 },
352};
353
354pub const cpu_sm_75 = Cpu{
355 .name = "sm_75",
356 .llvm_name = "sm_75",
357 .subfeatures = &[_]*const Feature {
358 &feature_ptx63,
359 &feature_sm_75,
360 },
361};
362
363pub const cpus = &[_]*const Cpu {
364 &cpu_sm_20,
365 &cpu_sm_21,
366 &cpu_sm_30,
367 &cpu_sm_32,
368 &cpu_sm_35,
369 &cpu_sm_37,
370 &cpu_sm_50,
371 &cpu_sm_52,
372 &cpu_sm_53,
373 &cpu_sm_60,
374 &cpu_sm_61,
375 &cpu_sm_62,
376 &cpu_sm_70,
377 &cpu_sm_72,
378 &cpu_sm_75,
379};
lib/std/target/powerpc.zig created+1115
......@@ -0,0 +1,1115 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_bit64 = Feature{
5 .name = "64bit",
6 .description = "Enable 64-bit instructions",
7 .llvm_name = "64bit",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_bitregs64 = Feature{
13 .name = "64bitregs",
14 .description = "Enable 64-bit registers usage for ppc32 [beta]",
15 .llvm_name = "64bitregs",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_altivec = Feature{
21 .name = "altivec",
22 .description = "Enable Altivec instructions",
23 .llvm_name = "altivec",
24 .subfeatures = &[_]*const Feature {
25 &feature_hardFloat,
26 },
27};
28
29pub const feature_bpermd = Feature{
30 .name = "bpermd",
31 .description = "Enable the bpermd instruction",
32 .llvm_name = "bpermd",
33 .subfeatures = &[_]*const Feature {
34 },
35};
36
37pub const feature_booke = Feature{
38 .name = "booke",
39 .description = "Enable Book E instructions",
40 .llvm_name = "booke",
41 .subfeatures = &[_]*const Feature {
42 &feature_icbt,
43 },
44};
45
46pub const feature_cmpb = Feature{
47 .name = "cmpb",
48 .description = "Enable the cmpb instruction",
49 .llvm_name = "cmpb",
50 .subfeatures = &[_]*const Feature {
51 },
52};
53
54pub const feature_crbits = Feature{
55 .name = "crbits",
56 .description = "Use condition-register bits individually",
57 .llvm_name = "crbits",
58 .subfeatures = &[_]*const Feature {
59 },
60};
61
62pub const feature_directMove = Feature{
63 .name = "direct-move",
64 .description = "Enable Power8 direct move instructions",
65 .llvm_name = "direct-move",
66 .subfeatures = &[_]*const Feature {
67 &feature_hardFloat,
68 },
69};
70
71pub const feature_e500 = Feature{
72 .name = "e500",
73 .description = "Enable E500/E500mc instructions",
74 .llvm_name = "e500",
75 .subfeatures = &[_]*const Feature {
76 },
77};
78
79pub const feature_extdiv = Feature{
80 .name = "extdiv",
81 .description = "Enable extended divide instructions",
82 .llvm_name = "extdiv",
83 .subfeatures = &[_]*const Feature {
84 },
85};
86
87pub const feature_fcpsgn = Feature{
88 .name = "fcpsgn",
89 .description = "Enable the fcpsgn instruction",
90 .llvm_name = "fcpsgn",
91 .subfeatures = &[_]*const Feature {
92 &feature_hardFloat,
93 },
94};
95
96pub const feature_fpcvt = Feature{
97 .name = "fpcvt",
98 .description = "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
99 .llvm_name = "fpcvt",
100 .subfeatures = &[_]*const Feature {
101 &feature_hardFloat,
102 },
103};
104
105pub const feature_fprnd = Feature{
106 .name = "fprnd",
107 .description = "Enable the fri[mnpz] instructions",
108 .llvm_name = "fprnd",
109 .subfeatures = &[_]*const Feature {
110 &feature_hardFloat,
111 },
112};
113
114pub const feature_fpu = Feature{
115 .name = "fpu",
116 .description = "Enable classic FPU instructions",
117 .llvm_name = "fpu",
118 .subfeatures = &[_]*const Feature {
119 &feature_hardFloat,
120 },
121};
122
123pub const feature_fre = Feature{
124 .name = "fre",
125 .description = "Enable the fre instruction",
126 .llvm_name = "fre",
127 .subfeatures = &[_]*const Feature {
128 &feature_hardFloat,
129 },
130};
131
132pub const feature_fres = Feature{
133 .name = "fres",
134 .description = "Enable the fres instruction",
135 .llvm_name = "fres",
136 .subfeatures = &[_]*const Feature {
137 &feature_hardFloat,
138 },
139};
140
141pub const feature_frsqrte = Feature{
142 .name = "frsqrte",
143 .description = "Enable the frsqrte instruction",
144 .llvm_name = "frsqrte",
145 .subfeatures = &[_]*const Feature {
146 &feature_hardFloat,
147 },
148};
149
150pub const feature_frsqrtes = Feature{
151 .name = "frsqrtes",
152 .description = "Enable the frsqrtes instruction",
153 .llvm_name = "frsqrtes",
154 .subfeatures = &[_]*const Feature {
155 &feature_hardFloat,
156 },
157};
158
159pub const feature_fsqrt = Feature{
160 .name = "fsqrt",
161 .description = "Enable the fsqrt instruction",
162 .llvm_name = "fsqrt",
163 .subfeatures = &[_]*const Feature {
164 &feature_hardFloat,
165 },
166};
167
168pub const feature_float128 = Feature{
169 .name = "float128",
170 .description = "Enable the __float128 data type for IEEE-754R Binary128.",
171 .llvm_name = "float128",
172 .subfeatures = &[_]*const Feature {
173 &feature_hardFloat,
174 },
175};
176
177pub const feature_htm = Feature{
178 .name = "htm",
179 .description = "Enable Hardware Transactional Memory instructions",
180 .llvm_name = "htm",
181 .subfeatures = &[_]*const Feature {
182 },
183};
184
185pub const feature_hardFloat = Feature{
186 .name = "hard-float",
187 .description = "Enable floating-point instructions",
188 .llvm_name = "hard-float",
189 .subfeatures = &[_]*const Feature {
190 },
191};
192
193pub const feature_icbt = Feature{
194 .name = "icbt",
195 .description = "Enable icbt instruction",
196 .llvm_name = "icbt",
197 .subfeatures = &[_]*const Feature {
198 },
199};
200
201pub const feature_isaV30Instructions = Feature{
202 .name = "isa-v30-instructions",
203 .description = "Enable instructions added in ISA 3.0.",
204 .llvm_name = "isa-v30-instructions",
205 .subfeatures = &[_]*const Feature {
206 },
207};
208
209pub const feature_isel = Feature{
210 .name = "isel",
211 .description = "Enable the isel instruction",
212 .llvm_name = "isel",
213 .subfeatures = &[_]*const Feature {
214 },
215};
216
217pub const feature_invariantFunctionDescriptors = Feature{
218 .name = "invariant-function-descriptors",
219 .description = "Assume function descriptors are invariant",
220 .llvm_name = "invariant-function-descriptors",
221 .subfeatures = &[_]*const Feature {
222 },
223};
224
225pub const feature_ldbrx = Feature{
226 .name = "ldbrx",
227 .description = "Enable the ldbrx instruction",
228 .llvm_name = "ldbrx",
229 .subfeatures = &[_]*const Feature {
230 },
231};
232
233pub const feature_lfiwax = Feature{
234 .name = "lfiwax",
235 .description = "Enable the lfiwax instruction",
236 .llvm_name = "lfiwax",
237 .subfeatures = &[_]*const Feature {
238 &feature_hardFloat,
239 },
240};
241
242pub const feature_longcall = Feature{
243 .name = "longcall",
244 .description = "Always use indirect calls",
245 .llvm_name = "longcall",
246 .subfeatures = &[_]*const Feature {
247 },
248};
249
250pub const feature_mfocrf = Feature{
251 .name = "mfocrf",
252 .description = "Enable the MFOCRF instruction",
253 .llvm_name = "mfocrf",
254 .subfeatures = &[_]*const Feature {
255 },
256};
257
258pub const feature_msync = Feature{
259 .name = "msync",
260 .description = "Has only the msync instruction instead of sync",
261 .llvm_name = "msync",
262 .subfeatures = &[_]*const Feature {
263 &feature_icbt,
264 },
265};
266
267pub const feature_power8Altivec = Feature{
268 .name = "power8-altivec",
269 .description = "Enable POWER8 Altivec instructions",
270 .llvm_name = "power8-altivec",
271 .subfeatures = &[_]*const Feature {
272 &feature_hardFloat,
273 },
274};
275
276pub const feature_crypto = Feature{
277 .name = "crypto",
278 .description = "Enable POWER8 Crypto instructions",
279 .llvm_name = "crypto",
280 .subfeatures = &[_]*const Feature {
281 &feature_hardFloat,
282 },
283};
284
285pub const feature_power8Vector = Feature{
286 .name = "power8-vector",
287 .description = "Enable POWER8 vector instructions",
288 .llvm_name = "power8-vector",
289 .subfeatures = &[_]*const Feature {
290 &feature_hardFloat,
291 },
292};
293
294pub const feature_power9Altivec = Feature{
295 .name = "power9-altivec",
296 .description = "Enable POWER9 Altivec instructions",
297 .llvm_name = "power9-altivec",
298 .subfeatures = &[_]*const Feature {
299 &feature_isaV30Instructions,
300 &feature_hardFloat,
301 },
302};
303
304pub const feature_power9Vector = Feature{
305 .name = "power9-vector",
306 .description = "Enable POWER9 vector instructions",
307 .llvm_name = "power9-vector",
308 .subfeatures = &[_]*const Feature {
309 &feature_isaV30Instructions,
310 &feature_hardFloat,
311 },
312};
313
314pub const feature_popcntd = Feature{
315 .name = "popcntd",
316 .description = "Enable the popcnt[dw] instructions",
317 .llvm_name = "popcntd",
318 .subfeatures = &[_]*const Feature {
319 },
320};
321
322pub const feature_ppc4xx = Feature{
323 .name = "ppc4xx",
324 .description = "Enable PPC 4xx instructions",
325 .llvm_name = "ppc4xx",
326 .subfeatures = &[_]*const Feature {
327 },
328};
329
330pub const feature_ppc6xx = Feature{
331 .name = "ppc6xx",
332 .description = "Enable PPC 6xx instructions",
333 .llvm_name = "ppc6xx",
334 .subfeatures = &[_]*const Feature {
335 },
336};
337
338pub const feature_ppcPostraSched = Feature{
339 .name = "ppc-postra-sched",
340 .description = "Use PowerPC post-RA scheduling strategy",
341 .llvm_name = "ppc-postra-sched",
342 .subfeatures = &[_]*const Feature {
343 },
344};
345
346pub const feature_ppcPreraSched = Feature{
347 .name = "ppc-prera-sched",
348 .description = "Use PowerPC pre-RA scheduling strategy",
349 .llvm_name = "ppc-prera-sched",
350 .subfeatures = &[_]*const Feature {
351 },
352};
353
354pub const feature_partwordAtomics = Feature{
355 .name = "partword-atomics",
356 .description = "Enable l[bh]arx and st[bh]cx.",
357 .llvm_name = "partword-atomics",
358 .subfeatures = &[_]*const Feature {
359 },
360};
361
362pub const feature_qpx = Feature{
363 .name = "qpx",
364 .description = "Enable QPX instructions",
365 .llvm_name = "qpx",
366 .subfeatures = &[_]*const Feature {
367 &feature_hardFloat,
368 },
369};
370
371pub const feature_recipprec = Feature{
372 .name = "recipprec",
373 .description = "Assume higher precision reciprocal estimates",
374 .llvm_name = "recipprec",
375 .subfeatures = &[_]*const Feature {
376 },
377};
378
379pub const feature_spe = Feature{
380 .name = "spe",
381 .description = "Enable SPE instructions",
382 .llvm_name = "spe",
383 .subfeatures = &[_]*const Feature {
384 &feature_hardFloat,
385 },
386};
387
388pub const feature_stfiwx = Feature{
389 .name = "stfiwx",
390 .description = "Enable the stfiwx instruction",
391 .llvm_name = "stfiwx",
392 .subfeatures = &[_]*const Feature {
393 &feature_hardFloat,
394 },
395};
396
397pub const feature_securePlt = Feature{
398 .name = "secure-plt",
399 .description = "Enable secure plt mode",
400 .llvm_name = "secure-plt",
401 .subfeatures = &[_]*const Feature {
402 },
403};
404
405pub const feature_slowPopcntd = Feature{
406 .name = "slow-popcntd",
407 .description = "Has slow popcnt[dw] instructions",
408 .llvm_name = "slow-popcntd",
409 .subfeatures = &[_]*const Feature {
410 },
411};
412
413pub const feature_twoConstNr = Feature{
414 .name = "two-const-nr",
415 .description = "Requires two constant Newton-Raphson computation",
416 .llvm_name = "two-const-nr",
417 .subfeatures = &[_]*const Feature {
418 },
419};
420
421pub const feature_vsx = Feature{
422 .name = "vsx",
423 .description = "Enable VSX instructions",
424 .llvm_name = "vsx",
425 .subfeatures = &[_]*const Feature {
426 &feature_hardFloat,
427 },
428};
429
430pub const feature_vectorsUseTwoUnits = Feature{
431 .name = "vectors-use-two-units",
432 .description = "Vectors use two units",
433 .llvm_name = "vectors-use-two-units",
434 .subfeatures = &[_]*const Feature {
435 },
436};
437
438pub const features = &[_]*const Feature {
439 &feature_bit64,
440 &feature_bitregs64,
441 &feature_altivec,
442 &feature_bpermd,
443 &feature_booke,
444 &feature_cmpb,
445 &feature_crbits,
446 &feature_directMove,
447 &feature_e500,
448 &feature_extdiv,
449 &feature_fcpsgn,
450 &feature_fpcvt,
451 &feature_fprnd,
452 &feature_fpu,
453 &feature_fre,
454 &feature_fres,
455 &feature_frsqrte,
456 &feature_frsqrtes,
457 &feature_fsqrt,
458 &feature_float128,
459 &feature_htm,
460 &feature_hardFloat,
461 &feature_icbt,
462 &feature_isaV30Instructions,
463 &feature_isel,
464 &feature_invariantFunctionDescriptors,
465 &feature_ldbrx,
466 &feature_lfiwax,
467 &feature_longcall,
468 &feature_mfocrf,
469 &feature_msync,
470 &feature_power8Altivec,
471 &feature_crypto,
472 &feature_power8Vector,
473 &feature_power9Altivec,
474 &feature_power9Vector,
475 &feature_popcntd,
476 &feature_ppc4xx,
477 &feature_ppc6xx,
478 &feature_ppcPostraSched,
479 &feature_ppcPreraSched,
480 &feature_partwordAtomics,
481 &feature_qpx,
482 &feature_recipprec,
483 &feature_spe,
484 &feature_stfiwx,
485 &feature_securePlt,
486 &feature_slowPopcntd,
487 &feature_twoConstNr,
488 &feature_vsx,
489 &feature_vectorsUseTwoUnits,
490};
491
492pub const cpu_440 = Cpu{
493 .name = "440",
494 .llvm_name = "440",
495 .subfeatures = &[_]*const Feature {
496 &feature_icbt,
497 &feature_booke,
498 &feature_hardFloat,
499 &feature_fres,
500 &feature_frsqrte,
501 &feature_isel,
502 &feature_msync,
503 },
504};
505
506pub const cpu_450 = Cpu{
507 .name = "450",
508 .llvm_name = "450",
509 .subfeatures = &[_]*const Feature {
510 &feature_icbt,
511 &feature_booke,
512 &feature_hardFloat,
513 &feature_fres,
514 &feature_frsqrte,
515 &feature_isel,
516 &feature_msync,
517 },
518};
519
520pub const cpu_601 = Cpu{
521 .name = "601",
522 .llvm_name = "601",
523 .subfeatures = &[_]*const Feature {
524 &feature_hardFloat,
525 &feature_fpu,
526 },
527};
528
529pub const cpu_602 = Cpu{
530 .name = "602",
531 .llvm_name = "602",
532 .subfeatures = &[_]*const Feature {
533 &feature_hardFloat,
534 &feature_fpu,
535 },
536};
537
538pub const cpu_603 = Cpu{
539 .name = "603",
540 .llvm_name = "603",
541 .subfeatures = &[_]*const Feature {
542 &feature_hardFloat,
543 &feature_fres,
544 &feature_frsqrte,
545 },
546};
547
548pub const cpu_e603 = Cpu{
549 .name = "603e",
550 .llvm_name = "603e",
551 .subfeatures = &[_]*const Feature {
552 &feature_hardFloat,
553 &feature_fres,
554 &feature_frsqrte,
555 },
556};
557
558pub const cpu_ev603 = Cpu{
559 .name = "603ev",
560 .llvm_name = "603ev",
561 .subfeatures = &[_]*const Feature {
562 &feature_hardFloat,
563 &feature_fres,
564 &feature_frsqrte,
565 },
566};
567
568pub const cpu_604 = Cpu{
569 .name = "604",
570 .llvm_name = "604",
571 .subfeatures = &[_]*const Feature {
572 &feature_hardFloat,
573 &feature_fres,
574 &feature_frsqrte,
575 },
576};
577
578pub const cpu_e604 = Cpu{
579 .name = "604e",
580 .llvm_name = "604e",
581 .subfeatures = &[_]*const Feature {
582 &feature_hardFloat,
583 &feature_fres,
584 &feature_frsqrte,
585 },
586};
587
588pub const cpu_620 = Cpu{
589 .name = "620",
590 .llvm_name = "620",
591 .subfeatures = &[_]*const Feature {
592 &feature_hardFloat,
593 &feature_fres,
594 &feature_frsqrte,
595 },
596};
597
598pub const cpu_7400 = Cpu{
599 .name = "7400",
600 .llvm_name = "7400",
601 .subfeatures = &[_]*const Feature {
602 &feature_hardFloat,
603 &feature_altivec,
604 &feature_fres,
605 &feature_frsqrte,
606 },
607};
608
609pub const cpu_7450 = Cpu{
610 .name = "7450",
611 .llvm_name = "7450",
612 .subfeatures = &[_]*const Feature {
613 &feature_hardFloat,
614 &feature_altivec,
615 &feature_fres,
616 &feature_frsqrte,
617 },
618};
619
620pub const cpu_750 = Cpu{
621 .name = "750",
622 .llvm_name = "750",
623 .subfeatures = &[_]*const Feature {
624 &feature_hardFloat,
625 &feature_fres,
626 &feature_frsqrte,
627 },
628};
629
630pub const cpu_970 = Cpu{
631 .name = "970",
632 .llvm_name = "970",
633 .subfeatures = &[_]*const Feature {
634 &feature_bit64,
635 &feature_hardFloat,
636 &feature_altivec,
637 &feature_fres,
638 &feature_frsqrte,
639 &feature_fsqrt,
640 &feature_mfocrf,
641 &feature_stfiwx,
642 },
643};
644
645pub const cpu_a2 = Cpu{
646 .name = "a2",
647 .llvm_name = "a2",
648 .subfeatures = &[_]*const Feature {
649 &feature_bit64,
650 &feature_icbt,
651 &feature_booke,
652 &feature_cmpb,
653 &feature_hardFloat,
654 &feature_fcpsgn,
655 &feature_fpcvt,
656 &feature_fprnd,
657 &feature_fre,
658 &feature_fres,
659 &feature_frsqrte,
660 &feature_frsqrtes,
661 &feature_fsqrt,
662 &feature_isel,
663 &feature_ldbrx,
664 &feature_lfiwax,
665 &feature_mfocrf,
666 &feature_recipprec,
667 &feature_stfiwx,
668 &feature_slowPopcntd,
669 },
670};
671
672pub const cpu_a2q = Cpu{
673 .name = "a2q",
674 .llvm_name = "a2q",
675 .subfeatures = &[_]*const Feature {
676 &feature_bit64,
677 &feature_icbt,
678 &feature_booke,
679 &feature_cmpb,
680 &feature_hardFloat,
681 &feature_fcpsgn,
682 &feature_fpcvt,
683 &feature_fprnd,
684 &feature_fre,
685 &feature_fres,
686 &feature_frsqrte,
687 &feature_frsqrtes,
688 &feature_fsqrt,
689 &feature_isel,
690 &feature_ldbrx,
691 &feature_lfiwax,
692 &feature_mfocrf,
693 &feature_qpx,
694 &feature_recipprec,
695 &feature_stfiwx,
696 &feature_slowPopcntd,
697 },
698};
699
700pub const cpu_e500 = Cpu{
701 .name = "e500",
702 .llvm_name = "e500",
703 .subfeatures = &[_]*const Feature {
704 &feature_icbt,
705 &feature_booke,
706 &feature_isel,
707 },
708};
709
710pub const cpu_e500mc = Cpu{
711 .name = "e500mc",
712 .llvm_name = "e500mc",
713 .subfeatures = &[_]*const Feature {
714 &feature_icbt,
715 &feature_booke,
716 &feature_isel,
717 &feature_hardFloat,
718 &feature_stfiwx,
719 },
720};
721
722pub const cpu_e5500 = Cpu{
723 .name = "e5500",
724 .llvm_name = "e5500",
725 .subfeatures = &[_]*const Feature {
726 &feature_bit64,
727 &feature_icbt,
728 &feature_booke,
729 &feature_isel,
730 &feature_mfocrf,
731 &feature_hardFloat,
732 &feature_stfiwx,
733 },
734};
735
736pub const cpu_g3 = Cpu{
737 .name = "g3",
738 .llvm_name = "g3",
739 .subfeatures = &[_]*const Feature {
740 &feature_hardFloat,
741 &feature_fres,
742 &feature_frsqrte,
743 },
744};
745
746pub const cpu_g4 = Cpu{
747 .name = "g4",
748 .llvm_name = "g4",
749 .subfeatures = &[_]*const Feature {
750 &feature_hardFloat,
751 &feature_altivec,
752 &feature_fres,
753 &feature_frsqrte,
754 },
755};
756
757pub const cpu_g4Plus = Cpu{
758 .name = "g4+",
759 .llvm_name = "g4+",
760 .subfeatures = &[_]*const Feature {
761 &feature_hardFloat,
762 &feature_altivec,
763 &feature_fres,
764 &feature_frsqrte,
765 },
766};
767
768pub const cpu_g5 = Cpu{
769 .name = "g5",
770 .llvm_name = "g5",
771 .subfeatures = &[_]*const Feature {
772 &feature_bit64,
773 &feature_hardFloat,
774 &feature_altivec,
775 &feature_fres,
776 &feature_frsqrte,
777 &feature_fsqrt,
778 &feature_mfocrf,
779 &feature_stfiwx,
780 },
781};
782
783pub const cpu_generic = Cpu{
784 .name = "generic",
785 .llvm_name = "generic",
786 .subfeatures = &[_]*const Feature {
787 &feature_hardFloat,
788 },
789};
790
791pub const cpu_ppc = Cpu{
792 .name = "ppc",
793 .llvm_name = "ppc",
794 .subfeatures = &[_]*const Feature {
795 &feature_hardFloat,
796 },
797};
798
799pub const cpu_ppc32 = Cpu{
800 .name = "ppc32",
801 .llvm_name = "ppc32",
802 .subfeatures = &[_]*const Feature {
803 &feature_hardFloat,
804 },
805};
806
807pub const cpu_ppc64 = Cpu{
808 .name = "ppc64",
809 .llvm_name = "ppc64",
810 .subfeatures = &[_]*const Feature {
811 &feature_bit64,
812 &feature_hardFloat,
813 &feature_altivec,
814 &feature_fres,
815 &feature_frsqrte,
816 &feature_fsqrt,
817 &feature_mfocrf,
818 &feature_stfiwx,
819 },
820};
821
822pub const cpu_ppc64le = Cpu{
823 .name = "ppc64le",
824 .llvm_name = "ppc64le",
825 .subfeatures = &[_]*const Feature {
826 &feature_bit64,
827 &feature_hardFloat,
828 &feature_altivec,
829 &feature_bpermd,
830 &feature_cmpb,
831 &feature_directMove,
832 &feature_extdiv,
833 &feature_fcpsgn,
834 &feature_fpcvt,
835 &feature_fprnd,
836 &feature_fre,
837 &feature_fres,
838 &feature_frsqrte,
839 &feature_frsqrtes,
840 &feature_fsqrt,
841 &feature_htm,
842 &feature_icbt,
843 &feature_isel,
844 &feature_ldbrx,
845 &feature_lfiwax,
846 &feature_mfocrf,
847 &feature_power8Altivec,
848 &feature_crypto,
849 &feature_power8Vector,
850 &feature_popcntd,
851 &feature_partwordAtomics,
852 &feature_recipprec,
853 &feature_stfiwx,
854 &feature_twoConstNr,
855 &feature_vsx,
856 },
857};
858
859pub const cpu_pwr3 = Cpu{
860 .name = "pwr3",
861 .llvm_name = "pwr3",
862 .subfeatures = &[_]*const Feature {
863 &feature_bit64,
864 &feature_hardFloat,
865 &feature_altivec,
866 &feature_fres,
867 &feature_frsqrte,
868 &feature_mfocrf,
869 &feature_stfiwx,
870 },
871};
872
873pub const cpu_pwr4 = Cpu{
874 .name = "pwr4",
875 .llvm_name = "pwr4",
876 .subfeatures = &[_]*const Feature {
877 &feature_bit64,
878 &feature_hardFloat,
879 &feature_altivec,
880 &feature_fres,
881 &feature_frsqrte,
882 &feature_fsqrt,
883 &feature_mfocrf,
884 &feature_stfiwx,
885 },
886};
887
888pub const cpu_pwr5 = Cpu{
889 .name = "pwr5",
890 .llvm_name = "pwr5",
891 .subfeatures = &[_]*const Feature {
892 &feature_bit64,
893 &feature_hardFloat,
894 &feature_altivec,
895 &feature_fre,
896 &feature_fres,
897 &feature_frsqrte,
898 &feature_frsqrtes,
899 &feature_fsqrt,
900 &feature_mfocrf,
901 &feature_stfiwx,
902 },
903};
904
905pub const cpu_pwr5x = Cpu{
906 .name = "pwr5x",
907 .llvm_name = "pwr5x",
908 .subfeatures = &[_]*const Feature {
909 &feature_bit64,
910 &feature_hardFloat,
911 &feature_altivec,
912 &feature_fprnd,
913 &feature_fre,
914 &feature_fres,
915 &feature_frsqrte,
916 &feature_frsqrtes,
917 &feature_fsqrt,
918 &feature_mfocrf,
919 &feature_stfiwx,
920 },
921};
922
923pub const cpu_pwr6 = Cpu{
924 .name = "pwr6",
925 .llvm_name = "pwr6",
926 .subfeatures = &[_]*const Feature {
927 &feature_bit64,
928 &feature_hardFloat,
929 &feature_altivec,
930 &feature_cmpb,
931 &feature_fcpsgn,
932 &feature_fprnd,
933 &feature_fre,
934 &feature_fres,
935 &feature_frsqrte,
936 &feature_frsqrtes,
937 &feature_fsqrt,
938 &feature_lfiwax,
939 &feature_mfocrf,
940 &feature_recipprec,
941 &feature_stfiwx,
942 },
943};
944
945pub const cpu_pwr6x = Cpu{
946 .name = "pwr6x",
947 .llvm_name = "pwr6x",
948 .subfeatures = &[_]*const Feature {
949 &feature_bit64,
950 &feature_hardFloat,
951 &feature_altivec,
952 &feature_cmpb,
953 &feature_fcpsgn,
954 &feature_fprnd,
955 &feature_fre,
956 &feature_fres,
957 &feature_frsqrte,
958 &feature_frsqrtes,
959 &feature_fsqrt,
960 &feature_lfiwax,
961 &feature_mfocrf,
962 &feature_recipprec,
963 &feature_stfiwx,
964 },
965};
966
967pub const cpu_pwr7 = Cpu{
968 .name = "pwr7",
969 .llvm_name = "pwr7",
970 .subfeatures = &[_]*const Feature {
971 &feature_bit64,
972 &feature_hardFloat,
973 &feature_altivec,
974 &feature_bpermd,
975 &feature_cmpb,
976 &feature_extdiv,
977 &feature_fcpsgn,
978 &feature_fpcvt,
979 &feature_fprnd,
980 &feature_fre,
981 &feature_fres,
982 &feature_frsqrte,
983 &feature_frsqrtes,
984 &feature_fsqrt,
985 &feature_isel,
986 &feature_ldbrx,
987 &feature_lfiwax,
988 &feature_mfocrf,
989 &feature_popcntd,
990 &feature_recipprec,
991 &feature_stfiwx,
992 &feature_twoConstNr,
993 &feature_vsx,
994 },
995};
996
997pub const cpu_pwr8 = Cpu{
998 .name = "pwr8",
999 .llvm_name = "pwr8",
1000 .subfeatures = &[_]*const Feature {
1001 &feature_bit64,
1002 &feature_hardFloat,
1003 &feature_altivec,
1004 &feature_bpermd,
1005 &feature_cmpb,
1006 &feature_directMove,
1007 &feature_extdiv,
1008 &feature_fcpsgn,
1009 &feature_fpcvt,
1010 &feature_fprnd,
1011 &feature_fre,
1012 &feature_fres,
1013 &feature_frsqrte,
1014 &feature_frsqrtes,
1015 &feature_fsqrt,
1016 &feature_htm,
1017 &feature_icbt,
1018 &feature_isel,
1019 &feature_ldbrx,
1020 &feature_lfiwax,
1021 &feature_mfocrf,
1022 &feature_power8Altivec,
1023 &feature_crypto,
1024 &feature_power8Vector,
1025 &feature_popcntd,
1026 &feature_partwordAtomics,
1027 &feature_recipprec,
1028 &feature_stfiwx,
1029 &feature_twoConstNr,
1030 &feature_vsx,
1031 },
1032};
1033
1034pub const cpu_pwr9 = Cpu{
1035 .name = "pwr9",
1036 .llvm_name = "pwr9",
1037 .subfeatures = &[_]*const Feature {
1038 &feature_bit64,
1039 &feature_hardFloat,
1040 &feature_altivec,
1041 &feature_bpermd,
1042 &feature_cmpb,
1043 &feature_directMove,
1044 &feature_extdiv,
1045 &feature_fcpsgn,
1046 &feature_fpcvt,
1047 &feature_fprnd,
1048 &feature_fre,
1049 &feature_fres,
1050 &feature_frsqrte,
1051 &feature_frsqrtes,
1052 &feature_fsqrt,
1053 &feature_htm,
1054 &feature_icbt,
1055 &feature_isaV30Instructions,
1056 &feature_isel,
1057 &feature_ldbrx,
1058 &feature_lfiwax,
1059 &feature_mfocrf,
1060 &feature_power8Altivec,
1061 &feature_crypto,
1062 &feature_power8Vector,
1063 &feature_power9Altivec,
1064 &feature_power9Vector,
1065 &feature_popcntd,
1066 &feature_ppcPostraSched,
1067 &feature_ppcPreraSched,
1068 &feature_partwordAtomics,
1069 &feature_recipprec,
1070 &feature_stfiwx,
1071 &feature_twoConstNr,
1072 &feature_vsx,
1073 &feature_vectorsUseTwoUnits,
1074 },
1075};
1076
1077pub const cpus = &[_]*const Cpu {
1078 &cpu_440,
1079 &cpu_450,
1080 &cpu_601,
1081 &cpu_602,
1082 &cpu_603,
1083 &cpu_e603,
1084 &cpu_ev603,
1085 &cpu_604,
1086 &cpu_e604,
1087 &cpu_620,
1088 &cpu_7400,
1089 &cpu_7450,
1090 &cpu_750,
1091 &cpu_970,
1092 &cpu_a2,
1093 &cpu_a2q,
1094 &cpu_e500,
1095 &cpu_e500mc,
1096 &cpu_e5500,
1097 &cpu_g3,
1098 &cpu_g4,
1099 &cpu_g4Plus,
1100 &cpu_g5,
1101 &cpu_generic,
1102 &cpu_ppc,
1103 &cpu_ppc32,
1104 &cpu_ppc64,
1105 &cpu_ppc64le,
1106 &cpu_pwr3,
1107 &cpu_pwr4,
1108 &cpu_pwr5,
1109 &cpu_pwr5x,
1110 &cpu_pwr6,
1111 &cpu_pwr6x,
1112 &cpu_pwr7,
1113 &cpu_pwr8,
1114 &cpu_pwr9,
1115};
lib/std/target/riscv.zig created+109
......@@ -0,0 +1,109 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_bit64 = Feature{
5 .name = "64bit",
6 .description = "Implements RV64",
7 .llvm_name = "64bit",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_e = Feature{
13 .name = "e",
14 .description = "Implements RV32E (provides 16 rather than 32 GPRs)",
15 .llvm_name = "e",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_rvcHints = Feature{
21 .name = "rvc-hints",
22 .description = "Enable RVC Hint Instructions.",
23 .llvm_name = "rvc-hints",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_relax = Feature{
29 .name = "relax",
30 .description = "Enable Linker relaxation.",
31 .llvm_name = "relax",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_a = Feature{
37 .name = "a",
38 .description = "'A' (Atomic Instructions)",
39 .llvm_name = "a",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_c = Feature{
45 .name = "c",
46 .description = "'C' (Compressed Instructions)",
47 .llvm_name = "c",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_d = Feature{
53 .name = "d",
54 .description = "'D' (Double-Precision Floating-Point)",
55 .llvm_name = "d",
56 .subfeatures = &[_]*const Feature {
57 &feature_f,
58 },
59};
60
61pub const feature_f = Feature{
62 .name = "f",
63 .description = "'F' (Single-Precision Floating-Point)",
64 .llvm_name = "f",
65 .subfeatures = &[_]*const Feature {
66 },
67};
68
69pub const feature_m = Feature{
70 .name = "m",
71 .description = "'M' (Integer Multiplication and Division)",
72 .llvm_name = "m",
73 .subfeatures = &[_]*const Feature {
74 },
75};
76
77pub const features = &[_]*const Feature {
78 &feature_bit64,
79 &feature_e,
80 &feature_rvcHints,
81 &feature_relax,
82 &feature_a,
83 &feature_c,
84 &feature_d,
85 &feature_f,
86 &feature_m,
87};
88
89pub const cpu_genericRv32 = Cpu{
90 .name = "generic-rv32",
91 .llvm_name = "generic-rv32",
92 .subfeatures = &[_]*const Feature {
93 &feature_rvcHints,
94 },
95};
96
97pub const cpu_genericRv64 = Cpu{
98 .name = "generic-rv64",
99 .llvm_name = "generic-rv64",
100 .subfeatures = &[_]*const Feature {
101 &feature_bit64,
102 &feature_rvcHints,
103 },
104};
105
106pub const cpus = &[_]*const Cpu {
107 &cpu_genericRv32,
108 &cpu_genericRv64,
109};
lib/std/target/sparc.zig created+581
......@@ -0,0 +1,581 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_detectroundchange = Feature{
5 .name = "detectroundchange",
6 .description = "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode",
7 .llvm_name = "detectroundchange",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_hardQuadFloat = Feature{
13 .name = "hard-quad-float",
14 .description = "Enable quad-word floating point instructions",
15 .llvm_name = "hard-quad-float",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_leon = Feature{
21 .name = "leon",
22 .description = "Enable LEON extensions",
23 .llvm_name = "leon",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_noFmuls = Feature{
29 .name = "no-fmuls",
30 .description = "Disable the fmuls instruction.",
31 .llvm_name = "no-fmuls",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_noFsmuld = Feature{
37 .name = "no-fsmuld",
38 .description = "Disable the fsmuld instruction.",
39 .llvm_name = "no-fsmuld",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_leonpwrpsr = Feature{
45 .name = "leonpwrpsr",
46 .description = "Enable the PWRPSR instruction",
47 .llvm_name = "leonpwrpsr",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_softFloat = Feature{
53 .name = "soft-float",
54 .description = "Use software emulation for floating point",
55 .llvm_name = "soft-float",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_softMulDiv = Feature{
61 .name = "soft-mul-div",
62 .description = "Use software emulation for integer multiply and divide",
63 .llvm_name = "soft-mul-div",
64 .subfeatures = &[_]*const Feature {
65 },
66};
67
68pub const feature_deprecatedV8 = Feature{
69 .name = "deprecated-v8",
70 .description = "Enable deprecated V8 instructions in V9 mode",
71 .llvm_name = "deprecated-v8",
72 .subfeatures = &[_]*const Feature {
73 },
74};
75
76pub const feature_v9 = Feature{
77 .name = "v9",
78 .description = "Enable SPARC-V9 instructions",
79 .llvm_name = "v9",
80 .subfeatures = &[_]*const Feature {
81 },
82};
83
84pub const feature_vis = Feature{
85 .name = "vis",
86 .description = "Enable UltraSPARC Visual Instruction Set extensions",
87 .llvm_name = "vis",
88 .subfeatures = &[_]*const Feature {
89 },
90};
91
92pub const feature_vis2 = Feature{
93 .name = "vis2",
94 .description = "Enable Visual Instruction Set extensions II",
95 .llvm_name = "vis2",
96 .subfeatures = &[_]*const Feature {
97 },
98};
99
100pub const feature_vis3 = Feature{
101 .name = "vis3",
102 .description = "Enable Visual Instruction Set extensions III",
103 .llvm_name = "vis3",
104 .subfeatures = &[_]*const Feature {
105 },
106};
107
108pub const feature_fixallfdivsqrt = Feature{
109 .name = "fixallfdivsqrt",
110 .description = "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store",
111 .llvm_name = "fixallfdivsqrt",
112 .subfeatures = &[_]*const Feature {
113 },
114};
115
116pub const feature_insertnopload = Feature{
117 .name = "insertnopload",
118 .description = "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction",
119 .llvm_name = "insertnopload",
120 .subfeatures = &[_]*const Feature {
121 },
122};
123
124pub const feature_hasleoncasa = Feature{
125 .name = "hasleoncasa",
126 .description = "Enable CASA instruction for LEON3 and LEON4 processors",
127 .llvm_name = "hasleoncasa",
128 .subfeatures = &[_]*const Feature {
129 },
130};
131
132pub const feature_leoncyclecounter = Feature{
133 .name = "leoncyclecounter",
134 .description = "Use the Leon cycle counter register",
135 .llvm_name = "leoncyclecounter",
136 .subfeatures = &[_]*const Feature {
137 },
138};
139
140pub const feature_hasumacsmac = Feature{
141 .name = "hasumacsmac",
142 .description = "Enable UMAC and SMAC for LEON3 and LEON4 processors",
143 .llvm_name = "hasumacsmac",
144 .subfeatures = &[_]*const Feature {
145 },
146};
147
148pub const feature_popc = Feature{
149 .name = "popc",
150 .description = "Use the popc (population count) instruction",
151 .llvm_name = "popc",
152 .subfeatures = &[_]*const Feature {
153 },
154};
155
156pub const features = &[_]*const Feature {
157 &feature_detectroundchange,
158 &feature_hardQuadFloat,
159 &feature_leon,
160 &feature_noFmuls,
161 &feature_noFsmuld,
162 &feature_leonpwrpsr,
163 &feature_softFloat,
164 &feature_softMulDiv,
165 &feature_deprecatedV8,
166 &feature_v9,
167 &feature_vis,
168 &feature_vis2,
169 &feature_vis3,
170 &feature_fixallfdivsqrt,
171 &feature_insertnopload,
172 &feature_hasleoncasa,
173 &feature_leoncyclecounter,
174 &feature_hasumacsmac,
175 &feature_popc,
176};
177
178pub const cpu_at697e = Cpu{
179 .name = "at697e",
180 .llvm_name = "at697e",
181 .subfeatures = &[_]*const Feature {
182 &feature_leon,
183 &feature_insertnopload,
184 },
185};
186
187pub const cpu_at697f = Cpu{
188 .name = "at697f",
189 .llvm_name = "at697f",
190 .subfeatures = &[_]*const Feature {
191 &feature_leon,
192 &feature_insertnopload,
193 },
194};
195
196pub const cpu_f934 = Cpu{
197 .name = "f934",
198 .llvm_name = "f934",
199 .subfeatures = &[_]*const Feature {
200 },
201};
202
203pub const cpu_generic = Cpu{
204 .name = "generic",
205 .llvm_name = "generic",
206 .subfeatures = &[_]*const Feature {
207 },
208};
209
210pub const cpu_gr712rc = Cpu{
211 .name = "gr712rc",
212 .llvm_name = "gr712rc",
213 .subfeatures = &[_]*const Feature {
214 &feature_leon,
215 &feature_hasleoncasa,
216 },
217};
218
219pub const cpu_gr740 = Cpu{
220 .name = "gr740",
221 .llvm_name = "gr740",
222 .subfeatures = &[_]*const Feature {
223 &feature_leon,
224 &feature_leonpwrpsr,
225 &feature_hasleoncasa,
226 &feature_leoncyclecounter,
227 &feature_hasumacsmac,
228 },
229};
230
231pub const cpu_hypersparc = Cpu{
232 .name = "hypersparc",
233 .llvm_name = "hypersparc",
234 .subfeatures = &[_]*const Feature {
235 },
236};
237
238pub const cpu_leon2 = Cpu{
239 .name = "leon2",
240 .llvm_name = "leon2",
241 .subfeatures = &[_]*const Feature {
242 &feature_leon,
243 },
244};
245
246pub const cpu_leon3 = Cpu{
247 .name = "leon3",
248 .llvm_name = "leon3",
249 .subfeatures = &[_]*const Feature {
250 &feature_leon,
251 &feature_hasumacsmac,
252 },
253};
254
255pub const cpu_leon4 = Cpu{
256 .name = "leon4",
257 .llvm_name = "leon4",
258 .subfeatures = &[_]*const Feature {
259 &feature_leon,
260 &feature_hasleoncasa,
261 &feature_hasumacsmac,
262 },
263};
264
265pub const cpu_ma2080 = Cpu{
266 .name = "ma2080",
267 .llvm_name = "ma2080",
268 .subfeatures = &[_]*const Feature {
269 &feature_leon,
270 &feature_hasleoncasa,
271 },
272};
273
274pub const cpu_ma2085 = Cpu{
275 .name = "ma2085",
276 .llvm_name = "ma2085",
277 .subfeatures = &[_]*const Feature {
278 &feature_leon,
279 &feature_hasleoncasa,
280 },
281};
282
283pub const cpu_ma2100 = Cpu{
284 .name = "ma2100",
285 .llvm_name = "ma2100",
286 .subfeatures = &[_]*const Feature {
287 &feature_leon,
288 &feature_hasleoncasa,
289 },
290};
291
292pub const cpu_ma2150 = Cpu{
293 .name = "ma2150",
294 .llvm_name = "ma2150",
295 .subfeatures = &[_]*const Feature {
296 &feature_leon,
297 &feature_hasleoncasa,
298 },
299};
300
301pub const cpu_ma2155 = Cpu{
302 .name = "ma2155",
303 .llvm_name = "ma2155",
304 .subfeatures = &[_]*const Feature {
305 &feature_leon,
306 &feature_hasleoncasa,
307 },
308};
309
310pub const cpu_ma2450 = Cpu{
311 .name = "ma2450",
312 .llvm_name = "ma2450",
313 .subfeatures = &[_]*const Feature {
314 &feature_leon,
315 &feature_hasleoncasa,
316 },
317};
318
319pub const cpu_ma2455 = Cpu{
320 .name = "ma2455",
321 .llvm_name = "ma2455",
322 .subfeatures = &[_]*const Feature {
323 &feature_leon,
324 &feature_hasleoncasa,
325 },
326};
327
328pub const cpu_ma2480 = Cpu{
329 .name = "ma2480",
330 .llvm_name = "ma2480",
331 .subfeatures = &[_]*const Feature {
332 &feature_leon,
333 &feature_hasleoncasa,
334 },
335};
336
337pub const cpu_ma2485 = Cpu{
338 .name = "ma2485",
339 .llvm_name = "ma2485",
340 .subfeatures = &[_]*const Feature {
341 &feature_leon,
342 &feature_hasleoncasa,
343 },
344};
345
346pub const cpu_ma2x5x = Cpu{
347 .name = "ma2x5x",
348 .llvm_name = "ma2x5x",
349 .subfeatures = &[_]*const Feature {
350 &feature_leon,
351 &feature_hasleoncasa,
352 },
353};
354
355pub const cpu_ma2x8x = Cpu{
356 .name = "ma2x8x",
357 .llvm_name = "ma2x8x",
358 .subfeatures = &[_]*const Feature {
359 &feature_leon,
360 &feature_hasleoncasa,
361 },
362};
363
364pub const cpu_myriad2 = Cpu{
365 .name = "myriad2",
366 .llvm_name = "myriad2",
367 .subfeatures = &[_]*const Feature {
368 &feature_leon,
369 &feature_hasleoncasa,
370 },
371};
372
373pub const cpu_myriad21 = Cpu{
374 .name = "myriad2.1",
375 .llvm_name = "myriad2.1",
376 .subfeatures = &[_]*const Feature {
377 &feature_leon,
378 &feature_hasleoncasa,
379 },
380};
381
382pub const cpu_myriad22 = Cpu{
383 .name = "myriad2.2",
384 .llvm_name = "myriad2.2",
385 .subfeatures = &[_]*const Feature {
386 &feature_leon,
387 &feature_hasleoncasa,
388 },
389};
390
391pub const cpu_myriad23 = Cpu{
392 .name = "myriad2.3",
393 .llvm_name = "myriad2.3",
394 .subfeatures = &[_]*const Feature {
395 &feature_leon,
396 &feature_hasleoncasa,
397 },
398};
399
400pub const cpu_niagara = Cpu{
401 .name = "niagara",
402 .llvm_name = "niagara",
403 .subfeatures = &[_]*const Feature {
404 &feature_deprecatedV8,
405 &feature_v9,
406 &feature_vis,
407 &feature_vis2,
408 },
409};
410
411pub const cpu_niagara2 = Cpu{
412 .name = "niagara2",
413 .llvm_name = "niagara2",
414 .subfeatures = &[_]*const Feature {
415 &feature_deprecatedV8,
416 &feature_v9,
417 &feature_vis,
418 &feature_vis2,
419 &feature_popc,
420 },
421};
422
423pub const cpu_niagara3 = Cpu{
424 .name = "niagara3",
425 .llvm_name = "niagara3",
426 .subfeatures = &[_]*const Feature {
427 &feature_deprecatedV8,
428 &feature_v9,
429 &feature_vis,
430 &feature_vis2,
431 &feature_popc,
432 },
433};
434
435pub const cpu_niagara4 = Cpu{
436 .name = "niagara4",
437 .llvm_name = "niagara4",
438 .subfeatures = &[_]*const Feature {
439 &feature_deprecatedV8,
440 &feature_v9,
441 &feature_vis,
442 &feature_vis2,
443 &feature_vis3,
444 &feature_popc,
445 },
446};
447
448pub const cpu_sparclet = Cpu{
449 .name = "sparclet",
450 .llvm_name = "sparclet",
451 .subfeatures = &[_]*const Feature {
452 },
453};
454
455pub const cpu_sparclite = Cpu{
456 .name = "sparclite",
457 .llvm_name = "sparclite",
458 .subfeatures = &[_]*const Feature {
459 },
460};
461
462pub const cpu_sparclite86x = Cpu{
463 .name = "sparclite86x",
464 .llvm_name = "sparclite86x",
465 .subfeatures = &[_]*const Feature {
466 },
467};
468
469pub const cpu_supersparc = Cpu{
470 .name = "supersparc",
471 .llvm_name = "supersparc",
472 .subfeatures = &[_]*const Feature {
473 },
474};
475
476pub const cpu_tsc701 = Cpu{
477 .name = "tsc701",
478 .llvm_name = "tsc701",
479 .subfeatures = &[_]*const Feature {
480 },
481};
482
483pub const cpu_ultrasparc = Cpu{
484 .name = "ultrasparc",
485 .llvm_name = "ultrasparc",
486 .subfeatures = &[_]*const Feature {
487 &feature_deprecatedV8,
488 &feature_v9,
489 &feature_vis,
490 },
491};
492
493pub const cpu_ultrasparc3 = Cpu{
494 .name = "ultrasparc3",
495 .llvm_name = "ultrasparc3",
496 .subfeatures = &[_]*const Feature {
497 &feature_deprecatedV8,
498 &feature_v9,
499 &feature_vis,
500 &feature_vis2,
501 },
502};
503
504pub const cpu_ut699 = Cpu{
505 .name = "ut699",
506 .llvm_name = "ut699",
507 .subfeatures = &[_]*const Feature {
508 &feature_leon,
509 &feature_noFmuls,
510 &feature_noFsmuld,
511 &feature_fixallfdivsqrt,
512 &feature_insertnopload,
513 },
514};
515
516pub const cpu_v7 = Cpu{
517 .name = "v7",
518 .llvm_name = "v7",
519 .subfeatures = &[_]*const Feature {
520 &feature_noFsmuld,
521 &feature_softMulDiv,
522 },
523};
524
525pub const cpu_v8 = Cpu{
526 .name = "v8",
527 .llvm_name = "v8",
528 .subfeatures = &[_]*const Feature {
529 },
530};
531
532pub const cpu_v9 = Cpu{
533 .name = "v9",
534 .llvm_name = "v9",
535 .subfeatures = &[_]*const Feature {
536 &feature_v9,
537 },
538};
539
540pub const cpus = &[_]*const Cpu {
541 &cpu_at697e,
542 &cpu_at697f,
543 &cpu_f934,
544 &cpu_generic,
545 &cpu_gr712rc,
546 &cpu_gr740,
547 &cpu_hypersparc,
548 &cpu_leon2,
549 &cpu_leon3,
550 &cpu_leon4,
551 &cpu_ma2080,
552 &cpu_ma2085,
553 &cpu_ma2100,
554 &cpu_ma2150,
555 &cpu_ma2155,
556 &cpu_ma2450,
557 &cpu_ma2455,
558 &cpu_ma2480,
559 &cpu_ma2485,
560 &cpu_ma2x5x,
561 &cpu_ma2x8x,
562 &cpu_myriad2,
563 &cpu_myriad21,
564 &cpu_myriad22,
565 &cpu_myriad23,
566 &cpu_niagara,
567 &cpu_niagara2,
568 &cpu_niagara3,
569 &cpu_niagara4,
570 &cpu_sparclet,
571 &cpu_sparclite,
572 &cpu_sparclite86x,
573 &cpu_supersparc,
574 &cpu_tsc701,
575 &cpu_ultrasparc,
576 &cpu_ultrasparc3,
577 &cpu_ut699,
578 &cpu_v7,
579 &cpu_v8,
580 &cpu_v9,
581};
lib/std/target/systemz.zig created+653
......@@ -0,0 +1,653 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_dfpPackedConversion = Feature{
5 .name = "dfp-packed-conversion",
6 .description = "Assume that the DFP packed-conversion facility is installed",
7 .llvm_name = "dfp-packed-conversion",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_dfpZonedConversion = Feature{
13 .name = "dfp-zoned-conversion",
14 .description = "Assume that the DFP zoned-conversion facility is installed",
15 .llvm_name = "dfp-zoned-conversion",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_deflateConversion = Feature{
21 .name = "deflate-conversion",
22 .description = "Assume that the deflate-conversion facility is installed",
23 .llvm_name = "deflate-conversion",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_distinctOps = Feature{
29 .name = "distinct-ops",
30 .description = "Assume that the distinct-operands facility is installed",
31 .llvm_name = "distinct-ops",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_enhancedDat2 = Feature{
37 .name = "enhanced-dat-2",
38 .description = "Assume that the enhanced-DAT facility 2 is installed",
39 .llvm_name = "enhanced-dat-2",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_enhancedSort = Feature{
45 .name = "enhanced-sort",
46 .description = "Assume that the enhanced-sort facility is installed",
47 .llvm_name = "enhanced-sort",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_executionHint = Feature{
53 .name = "execution-hint",
54 .description = "Assume that the execution-hint facility is installed",
55 .llvm_name = "execution-hint",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_fpExtension = Feature{
61 .name = "fp-extension",
62 .description = "Assume that the floating-point extension facility is installed",
63 .llvm_name = "fp-extension",
64 .subfeatures = &[_]*const Feature {
65 },
66};
67
68pub const feature_fastSerialization = Feature{
69 .name = "fast-serialization",
70 .description = "Assume that the fast-serialization facility is installed",
71 .llvm_name = "fast-serialization",
72 .subfeatures = &[_]*const Feature {
73 },
74};
75
76pub const feature_guardedStorage = Feature{
77 .name = "guarded-storage",
78 .description = "Assume that the guarded-storage facility is installed",
79 .llvm_name = "guarded-storage",
80 .subfeatures = &[_]*const Feature {
81 },
82};
83
84pub const feature_highWord = Feature{
85 .name = "high-word",
86 .description = "Assume that the high-word facility is installed",
87 .llvm_name = "high-word",
88 .subfeatures = &[_]*const Feature {
89 },
90};
91
92pub const feature_insertReferenceBitsMultiple = Feature{
93 .name = "insert-reference-bits-multiple",
94 .description = "Assume that the insert-reference-bits-multiple facility is installed",
95 .llvm_name = "insert-reference-bits-multiple",
96 .subfeatures = &[_]*const Feature {
97 },
98};
99
100pub const feature_interlockedAccess1 = Feature{
101 .name = "interlocked-access1",
102 .description = "Assume that interlocked-access facility 1 is installed",
103 .llvm_name = "interlocked-access1",
104 .subfeatures = &[_]*const Feature {
105 },
106};
107
108pub const feature_loadAndTrap = Feature{
109 .name = "load-and-trap",
110 .description = "Assume that the load-and-trap facility is installed",
111 .llvm_name = "load-and-trap",
112 .subfeatures = &[_]*const Feature {
113 },
114};
115
116pub const feature_loadAndZeroRightmostByte = Feature{
117 .name = "load-and-zero-rightmost-byte",
118 .description = "Assume that the load-and-zero-rightmost-byte facility is installed",
119 .llvm_name = "load-and-zero-rightmost-byte",
120 .subfeatures = &[_]*const Feature {
121 },
122};
123
124pub const feature_loadStoreOnCond = Feature{
125 .name = "load-store-on-cond",
126 .description = "Assume that the load/store-on-condition facility is installed",
127 .llvm_name = "load-store-on-cond",
128 .subfeatures = &[_]*const Feature {
129 },
130};
131
132pub const feature_loadStoreOnCond2 = Feature{
133 .name = "load-store-on-cond-2",
134 .description = "Assume that the load/store-on-condition facility 2 is installed",
135 .llvm_name = "load-store-on-cond-2",
136 .subfeatures = &[_]*const Feature {
137 },
138};
139
140pub const feature_messageSecurityAssistExtension3 = Feature{
141 .name = "message-security-assist-extension3",
142 .description = "Assume that the message-security-assist extension facility 3 is installed",
143 .llvm_name = "message-security-assist-extension3",
144 .subfeatures = &[_]*const Feature {
145 },
146};
147
148pub const feature_messageSecurityAssistExtension4 = Feature{
149 .name = "message-security-assist-extension4",
150 .description = "Assume that the message-security-assist extension facility 4 is installed",
151 .llvm_name = "message-security-assist-extension4",
152 .subfeatures = &[_]*const Feature {
153 },
154};
155
156pub const feature_messageSecurityAssistExtension5 = Feature{
157 .name = "message-security-assist-extension5",
158 .description = "Assume that the message-security-assist extension facility 5 is installed",
159 .llvm_name = "message-security-assist-extension5",
160 .subfeatures = &[_]*const Feature {
161 },
162};
163
164pub const feature_messageSecurityAssistExtension7 = Feature{
165 .name = "message-security-assist-extension7",
166 .description = "Assume that the message-security-assist extension facility 7 is installed",
167 .llvm_name = "message-security-assist-extension7",
168 .subfeatures = &[_]*const Feature {
169 },
170};
171
172pub const feature_messageSecurityAssistExtension8 = Feature{
173 .name = "message-security-assist-extension8",
174 .description = "Assume that the message-security-assist extension facility 8 is installed",
175 .llvm_name = "message-security-assist-extension8",
176 .subfeatures = &[_]*const Feature {
177 },
178};
179
180pub const feature_messageSecurityAssistExtension9 = Feature{
181 .name = "message-security-assist-extension9",
182 .description = "Assume that the message-security-assist extension facility 9 is installed",
183 .llvm_name = "message-security-assist-extension9",
184 .subfeatures = &[_]*const Feature {
185 },
186};
187
188pub const feature_miscellaneousExtensions = Feature{
189 .name = "miscellaneous-extensions",
190 .description = "Assume that the miscellaneous-extensions facility is installed",
191 .llvm_name = "miscellaneous-extensions",
192 .subfeatures = &[_]*const Feature {
193 },
194};
195
196pub const feature_miscellaneousExtensions2 = Feature{
197 .name = "miscellaneous-extensions-2",
198 .description = "Assume that the miscellaneous-extensions facility 2 is installed",
199 .llvm_name = "miscellaneous-extensions-2",
200 .subfeatures = &[_]*const Feature {
201 },
202};
203
204pub const feature_miscellaneousExtensions3 = Feature{
205 .name = "miscellaneous-extensions-3",
206 .description = "Assume that the miscellaneous-extensions facility 3 is installed",
207 .llvm_name = "miscellaneous-extensions-3",
208 .subfeatures = &[_]*const Feature {
209 },
210};
211
212pub const feature_populationCount = Feature{
213 .name = "population-count",
214 .description = "Assume that the population-count facility is installed",
215 .llvm_name = "population-count",
216 .subfeatures = &[_]*const Feature {
217 },
218};
219
220pub const feature_processorAssist = Feature{
221 .name = "processor-assist",
222 .description = "Assume that the processor-assist facility is installed",
223 .llvm_name = "processor-assist",
224 .subfeatures = &[_]*const Feature {
225 },
226};
227
228pub const feature_resetReferenceBitsMultiple = Feature{
229 .name = "reset-reference-bits-multiple",
230 .description = "Assume that the reset-reference-bits-multiple facility is installed",
231 .llvm_name = "reset-reference-bits-multiple",
232 .subfeatures = &[_]*const Feature {
233 },
234};
235
236pub const feature_transactionalExecution = Feature{
237 .name = "transactional-execution",
238 .description = "Assume that the transactional-execution facility is installed",
239 .llvm_name = "transactional-execution",
240 .subfeatures = &[_]*const Feature {
241 },
242};
243
244pub const feature_vector = Feature{
245 .name = "vector",
246 .description = "Assume that the vectory facility is installed",
247 .llvm_name = "vector",
248 .subfeatures = &[_]*const Feature {
249 },
250};
251
252pub const feature_vectorEnhancements1 = Feature{
253 .name = "vector-enhancements-1",
254 .description = "Assume that the vector enhancements facility 1 is installed",
255 .llvm_name = "vector-enhancements-1",
256 .subfeatures = &[_]*const Feature {
257 },
258};
259
260pub const feature_vectorEnhancements2 = Feature{
261 .name = "vector-enhancements-2",
262 .description = "Assume that the vector enhancements facility 2 is installed",
263 .llvm_name = "vector-enhancements-2",
264 .subfeatures = &[_]*const Feature {
265 },
266};
267
268pub const feature_vectorPackedDecimal = Feature{
269 .name = "vector-packed-decimal",
270 .description = "Assume that the vector packed decimal facility is installed",
271 .llvm_name = "vector-packed-decimal",
272 .subfeatures = &[_]*const Feature {
273 },
274};
275
276pub const feature_vectorPackedDecimalEnhancement = Feature{
277 .name = "vector-packed-decimal-enhancement",
278 .description = "Assume that the vector packed decimal enhancement facility is installed",
279 .llvm_name = "vector-packed-decimal-enhancement",
280 .subfeatures = &[_]*const Feature {
281 },
282};
283
284pub const features = &[_]*const Feature {
285 &feature_dfpPackedConversion,
286 &feature_dfpZonedConversion,
287 &feature_deflateConversion,
288 &feature_distinctOps,
289 &feature_enhancedDat2,
290 &feature_enhancedSort,
291 &feature_executionHint,
292 &feature_fpExtension,
293 &feature_fastSerialization,
294 &feature_guardedStorage,
295 &feature_highWord,
296 &feature_insertReferenceBitsMultiple,
297 &feature_interlockedAccess1,
298 &feature_loadAndTrap,
299 &feature_loadAndZeroRightmostByte,
300 &feature_loadStoreOnCond,
301 &feature_loadStoreOnCond2,
302 &feature_messageSecurityAssistExtension3,
303 &feature_messageSecurityAssistExtension4,
304 &feature_messageSecurityAssistExtension5,
305 &feature_messageSecurityAssistExtension7,
306 &feature_messageSecurityAssistExtension8,
307 &feature_messageSecurityAssistExtension9,
308 &feature_miscellaneousExtensions,
309 &feature_miscellaneousExtensions2,
310 &feature_miscellaneousExtensions3,
311 &feature_populationCount,
312 &feature_processorAssist,
313 &feature_resetReferenceBitsMultiple,
314 &feature_transactionalExecution,
315 &feature_vector,
316 &feature_vectorEnhancements1,
317 &feature_vectorEnhancements2,
318 &feature_vectorPackedDecimal,
319 &feature_vectorPackedDecimalEnhancement,
320};
321
322pub const cpu_arch10 = Cpu{
323 .name = "arch10",
324 .llvm_name = "arch10",
325 .subfeatures = &[_]*const Feature {
326 &feature_dfpZonedConversion,
327 &feature_distinctOps,
328 &feature_enhancedDat2,
329 &feature_executionHint,
330 &feature_fpExtension,
331 &feature_fastSerialization,
332 &feature_highWord,
333 &feature_interlockedAccess1,
334 &feature_loadAndTrap,
335 &feature_loadStoreOnCond,
336 &feature_messageSecurityAssistExtension3,
337 &feature_messageSecurityAssistExtension4,
338 &feature_miscellaneousExtensions,
339 &feature_populationCount,
340 &feature_processorAssist,
341 &feature_resetReferenceBitsMultiple,
342 &feature_transactionalExecution,
343 },
344};
345
346pub const cpu_arch11 = Cpu{
347 .name = "arch11",
348 .llvm_name = "arch11",
349 .subfeatures = &[_]*const Feature {
350 &feature_dfpPackedConversion,
351 &feature_dfpZonedConversion,
352 &feature_distinctOps,
353 &feature_enhancedDat2,
354 &feature_executionHint,
355 &feature_fpExtension,
356 &feature_fastSerialization,
357 &feature_highWord,
358 &feature_interlockedAccess1,
359 &feature_loadAndTrap,
360 &feature_loadAndZeroRightmostByte,
361 &feature_loadStoreOnCond,
362 &feature_loadStoreOnCond2,
363 &feature_messageSecurityAssistExtension3,
364 &feature_messageSecurityAssistExtension4,
365 &feature_messageSecurityAssistExtension5,
366 &feature_miscellaneousExtensions,
367 &feature_populationCount,
368 &feature_processorAssist,
369 &feature_resetReferenceBitsMultiple,
370 &feature_transactionalExecution,
371 &feature_vector,
372 },
373};
374
375pub const cpu_arch12 = Cpu{
376 .name = "arch12",
377 .llvm_name = "arch12",
378 .subfeatures = &[_]*const Feature {
379 &feature_dfpPackedConversion,
380 &feature_dfpZonedConversion,
381 &feature_distinctOps,
382 &feature_enhancedDat2,
383 &feature_executionHint,
384 &feature_fpExtension,
385 &feature_fastSerialization,
386 &feature_guardedStorage,
387 &feature_highWord,
388 &feature_insertReferenceBitsMultiple,
389 &feature_interlockedAccess1,
390 &feature_loadAndTrap,
391 &feature_loadAndZeroRightmostByte,
392 &feature_loadStoreOnCond,
393 &feature_loadStoreOnCond2,
394 &feature_messageSecurityAssistExtension3,
395 &feature_messageSecurityAssistExtension4,
396 &feature_messageSecurityAssistExtension5,
397 &feature_messageSecurityAssistExtension7,
398 &feature_messageSecurityAssistExtension8,
399 &feature_miscellaneousExtensions,
400 &feature_miscellaneousExtensions2,
401 &feature_populationCount,
402 &feature_processorAssist,
403 &feature_resetReferenceBitsMultiple,
404 &feature_transactionalExecution,
405 &feature_vector,
406 &feature_vectorEnhancements1,
407 &feature_vectorPackedDecimal,
408 },
409};
410
411pub const cpu_arch13 = Cpu{
412 .name = "arch13",
413 .llvm_name = "arch13",
414 .subfeatures = &[_]*const Feature {
415 &feature_dfpPackedConversion,
416 &feature_dfpZonedConversion,
417 &feature_deflateConversion,
418 &feature_distinctOps,
419 &feature_enhancedDat2,
420 &feature_enhancedSort,
421 &feature_executionHint,
422 &feature_fpExtension,
423 &feature_fastSerialization,
424 &feature_guardedStorage,
425 &feature_highWord,
426 &feature_insertReferenceBitsMultiple,
427 &feature_interlockedAccess1,
428 &feature_loadAndTrap,
429 &feature_loadAndZeroRightmostByte,
430 &feature_loadStoreOnCond,
431 &feature_loadStoreOnCond2,
432 &feature_messageSecurityAssistExtension3,
433 &feature_messageSecurityAssistExtension4,
434 &feature_messageSecurityAssistExtension5,
435 &feature_messageSecurityAssistExtension7,
436 &feature_messageSecurityAssistExtension8,
437 &feature_messageSecurityAssistExtension9,
438 &feature_miscellaneousExtensions,
439 &feature_miscellaneousExtensions2,
440 &feature_miscellaneousExtensions3,
441 &feature_populationCount,
442 &feature_processorAssist,
443 &feature_resetReferenceBitsMultiple,
444 &feature_transactionalExecution,
445 &feature_vector,
446 &feature_vectorEnhancements1,
447 &feature_vectorEnhancements2,
448 &feature_vectorPackedDecimal,
449 &feature_vectorPackedDecimalEnhancement,
450 },
451};
452
453pub const cpu_arch8 = Cpu{
454 .name = "arch8",
455 .llvm_name = "arch8",
456 .subfeatures = &[_]*const Feature {
457 },
458};
459
460pub const cpu_arch9 = Cpu{
461 .name = "arch9",
462 .llvm_name = "arch9",
463 .subfeatures = &[_]*const Feature {
464 &feature_distinctOps,
465 &feature_fpExtension,
466 &feature_fastSerialization,
467 &feature_highWord,
468 &feature_interlockedAccess1,
469 &feature_loadStoreOnCond,
470 &feature_messageSecurityAssistExtension3,
471 &feature_messageSecurityAssistExtension4,
472 &feature_populationCount,
473 &feature_resetReferenceBitsMultiple,
474 },
475};
476
477pub const cpu_generic = Cpu{
478 .name = "generic",
479 .llvm_name = "generic",
480 .subfeatures = &[_]*const Feature {
481 },
482};
483
484pub const cpu_z10 = Cpu{
485 .name = "z10",
486 .llvm_name = "z10",
487 .subfeatures = &[_]*const Feature {
488 },
489};
490
491pub const cpu_z13 = Cpu{
492 .name = "z13",
493 .llvm_name = "z13",
494 .subfeatures = &[_]*const Feature {
495 &feature_dfpPackedConversion,
496 &feature_dfpZonedConversion,
497 &feature_distinctOps,
498 &feature_enhancedDat2,
499 &feature_executionHint,
500 &feature_fpExtension,
501 &feature_fastSerialization,
502 &feature_highWord,
503 &feature_interlockedAccess1,
504 &feature_loadAndTrap,
505 &feature_loadAndZeroRightmostByte,
506 &feature_loadStoreOnCond,
507 &feature_loadStoreOnCond2,
508 &feature_messageSecurityAssistExtension3,
509 &feature_messageSecurityAssistExtension4,
510 &feature_messageSecurityAssistExtension5,
511 &feature_miscellaneousExtensions,
512 &feature_populationCount,
513 &feature_processorAssist,
514 &feature_resetReferenceBitsMultiple,
515 &feature_transactionalExecution,
516 &feature_vector,
517 },
518};
519
520pub const cpu_z14 = Cpu{
521 .name = "z14",
522 .llvm_name = "z14",
523 .subfeatures = &[_]*const Feature {
524 &feature_dfpPackedConversion,
525 &feature_dfpZonedConversion,
526 &feature_distinctOps,
527 &feature_enhancedDat2,
528 &feature_executionHint,
529 &feature_fpExtension,
530 &feature_fastSerialization,
531 &feature_guardedStorage,
532 &feature_highWord,
533 &feature_insertReferenceBitsMultiple,
534 &feature_interlockedAccess1,
535 &feature_loadAndTrap,
536 &feature_loadAndZeroRightmostByte,
537 &feature_loadStoreOnCond,
538 &feature_loadStoreOnCond2,
539 &feature_messageSecurityAssistExtension3,
540 &feature_messageSecurityAssistExtension4,
541 &feature_messageSecurityAssistExtension5,
542 &feature_messageSecurityAssistExtension7,
543 &feature_messageSecurityAssistExtension8,
544 &feature_miscellaneousExtensions,
545 &feature_miscellaneousExtensions2,
546 &feature_populationCount,
547 &feature_processorAssist,
548 &feature_resetReferenceBitsMultiple,
549 &feature_transactionalExecution,
550 &feature_vector,
551 &feature_vectorEnhancements1,
552 &feature_vectorPackedDecimal,
553 },
554};
555
556pub const cpu_z15 = Cpu{
557 .name = "z15",
558 .llvm_name = "z15",
559 .subfeatures = &[_]*const Feature {
560 &feature_dfpPackedConversion,
561 &feature_dfpZonedConversion,
562 &feature_deflateConversion,
563 &feature_distinctOps,
564 &feature_enhancedDat2,
565 &feature_enhancedSort,
566 &feature_executionHint,
567 &feature_fpExtension,
568 &feature_fastSerialization,
569 &feature_guardedStorage,
570 &feature_highWord,
571 &feature_insertReferenceBitsMultiple,
572 &feature_interlockedAccess1,
573 &feature_loadAndTrap,
574 &feature_loadAndZeroRightmostByte,
575 &feature_loadStoreOnCond,
576 &feature_loadStoreOnCond2,
577 &feature_messageSecurityAssistExtension3,
578 &feature_messageSecurityAssistExtension4,
579 &feature_messageSecurityAssistExtension5,
580 &feature_messageSecurityAssistExtension7,
581 &feature_messageSecurityAssistExtension8,
582 &feature_messageSecurityAssistExtension9,
583 &feature_miscellaneousExtensions,
584 &feature_miscellaneousExtensions2,
585 &feature_miscellaneousExtensions3,
586 &feature_populationCount,
587 &feature_processorAssist,
588 &feature_resetReferenceBitsMultiple,
589 &feature_transactionalExecution,
590 &feature_vector,
591 &feature_vectorEnhancements1,
592 &feature_vectorEnhancements2,
593 &feature_vectorPackedDecimal,
594 &feature_vectorPackedDecimalEnhancement,
595 },
596};
597
598pub const cpu_z196 = Cpu{
599 .name = "z196",
600 .llvm_name = "z196",
601 .subfeatures = &[_]*const Feature {
602 &feature_distinctOps,
603 &feature_fpExtension,
604 &feature_fastSerialization,
605 &feature_highWord,
606 &feature_interlockedAccess1,
607 &feature_loadStoreOnCond,
608 &feature_messageSecurityAssistExtension3,
609 &feature_messageSecurityAssistExtension4,
610 &feature_populationCount,
611 &feature_resetReferenceBitsMultiple,
612 },
613};
614
615pub const cpu_zEC12 = Cpu{
616 .name = "zEC12",
617 .llvm_name = "zEC12",
618 .subfeatures = &[_]*const Feature {
619 &feature_dfpZonedConversion,
620 &feature_distinctOps,
621 &feature_enhancedDat2,
622 &feature_executionHint,
623 &feature_fpExtension,
624 &feature_fastSerialization,
625 &feature_highWord,
626 &feature_interlockedAccess1,
627 &feature_loadAndTrap,
628 &feature_loadStoreOnCond,
629 &feature_messageSecurityAssistExtension3,
630 &feature_messageSecurityAssistExtension4,
631 &feature_miscellaneousExtensions,
632 &feature_populationCount,
633 &feature_processorAssist,
634 &feature_resetReferenceBitsMultiple,
635 &feature_transactionalExecution,
636 },
637};
638
639pub const cpus = &[_]*const Cpu {
640 &cpu_arch10,
641 &cpu_arch11,
642 &cpu_arch12,
643 &cpu_arch13,
644 &cpu_arch8,
645 &cpu_arch9,
646 &cpu_generic,
647 &cpu_z10,
648 &cpu_z13,
649 &cpu_z14,
650 &cpu_z15,
651 &cpu_z196,
652 &cpu_zEC12,
653};
lib/std/target/wasm.zig created+128
......@@ -0,0 +1,128 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_atomics = Feature{
5 .name = "atomics",
6 .description = "Enable Atomics",
7 .llvm_name = "atomics",
8 .subfeatures = &[_]*const Feature {
9 },
10};
11
12pub const feature_bulkMemory = Feature{
13 .name = "bulk-memory",
14 .description = "Enable bulk memory operations",
15 .llvm_name = "bulk-memory",
16 .subfeatures = &[_]*const Feature {
17 },
18};
19
20pub const feature_exceptionHandling = Feature{
21 .name = "exception-handling",
22 .description = "Enable Wasm exception handling",
23 .llvm_name = "exception-handling",
24 .subfeatures = &[_]*const Feature {
25 },
26};
27
28pub const feature_multivalue = Feature{
29 .name = "multivalue",
30 .description = "Enable multivalue blocks, instructions, and functions",
31 .llvm_name = "multivalue",
32 .subfeatures = &[_]*const Feature {
33 },
34};
35
36pub const feature_mutableGlobals = Feature{
37 .name = "mutable-globals",
38 .description = "Enable mutable globals",
39 .llvm_name = "mutable-globals",
40 .subfeatures = &[_]*const Feature {
41 },
42};
43
44pub const feature_nontrappingFptoint = Feature{
45 .name = "nontrapping-fptoint",
46 .description = "Enable non-trapping float-to-int conversion operators",
47 .llvm_name = "nontrapping-fptoint",
48 .subfeatures = &[_]*const Feature {
49 },
50};
51
52pub const feature_simd128 = Feature{
53 .name = "simd128",
54 .description = "Enable 128-bit SIMD",
55 .llvm_name = "simd128",
56 .subfeatures = &[_]*const Feature {
57 },
58};
59
60pub const feature_signExt = Feature{
61 .name = "sign-ext",
62 .description = "Enable sign extension operators",
63 .llvm_name = "sign-ext",
64 .subfeatures = &[_]*const Feature {
65 },
66};
67
68pub const feature_tailCall = Feature{
69 .name = "tail-call",
70 .description = "Enable tail call instructions",
71 .llvm_name = "tail-call",
72 .subfeatures = &[_]*const Feature {
73 },
74};
75
76pub const feature_unimplementedSimd128 = Feature{
77 .name = "unimplemented-simd128",
78 .description = "Enable 128-bit SIMD not yet implemented in engines",
79 .llvm_name = "unimplemented-simd128",
80 .subfeatures = &[_]*const Feature {
81 &feature_simd128,
82 },
83};
84
85pub const features = &[_]*const Feature {
86 &feature_atomics,
87 &feature_bulkMemory,
88 &feature_exceptionHandling,
89 &feature_multivalue,
90 &feature_mutableGlobals,
91 &feature_nontrappingFptoint,
92 &feature_simd128,
93 &feature_signExt,
94 &feature_tailCall,
95 &feature_unimplementedSimd128,
96};
97
98pub const cpu_bleedingEdge = Cpu{
99 .name = "bleeding-edge",
100 .llvm_name = "bleeding-edge",
101 .subfeatures = &[_]*const Feature {
102 &feature_atomics,
103 &feature_mutableGlobals,
104 &feature_nontrappingFptoint,
105 &feature_simd128,
106 &feature_signExt,
107 },
108};
109
110pub const cpu_generic = Cpu{
111 .name = "generic",
112 .llvm_name = "generic",
113 .subfeatures = &[_]*const Feature {
114 },
115};
116
117pub const cpu_mvp = Cpu{
118 .name = "mvp",
119 .llvm_name = "mvp",
120 .subfeatures = &[_]*const Feature {
121 },
122};
123
124pub const cpus = &[_]*const Cpu {
125 &cpu_bleedingEdge,
126 &cpu_generic,
127 &cpu_mvp,
128};
lib/std/target/x86.zig created+3427
......@@ -0,0 +1,3427 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_dnow3 = Feature{
5 .name = "3dnow",
6 .description = "Enable 3DNow! instructions",
7 .llvm_name = "3dnow",
8 .subfeatures = &[_]*const Feature {
9 &feature_mmx,
10 },
11};
12
13pub const feature_dnowa3 = Feature{
14 .name = "3dnowa",
15 .description = "Enable 3DNow! Athlon instructions",
16 .llvm_name = "3dnowa",
17 .subfeatures = &[_]*const Feature {
18 &feature_mmx,
19 },
20};
21
22pub const feature_bit64 = Feature{
23 .name = "64bit",
24 .description = "Support 64-bit instructions",
25 .llvm_name = "64bit",
26 .subfeatures = &[_]*const Feature {
27 },
28};
29
30pub const feature_adx = Feature{
31 .name = "adx",
32 .description = "Support ADX instructions",
33 .llvm_name = "adx",
34 .subfeatures = &[_]*const Feature {
35 },
36};
37
38pub const feature_aes = Feature{
39 .name = "aes",
40 .description = "Enable AES instructions",
41 .llvm_name = "aes",
42 .subfeatures = &[_]*const Feature {
43 &feature_sse,
44 },
45};
46
47pub const feature_avx = Feature{
48 .name = "avx",
49 .description = "Enable AVX instructions",
50 .llvm_name = "avx",
51 .subfeatures = &[_]*const Feature {
52 &feature_sse,
53 },
54};
55
56pub const feature_avx2 = Feature{
57 .name = "avx2",
58 .description = "Enable AVX2 instructions",
59 .llvm_name = "avx2",
60 .subfeatures = &[_]*const Feature {
61 &feature_sse,
62 },
63};
64
65pub const feature_avx512f = Feature{
66 .name = "avx512f",
67 .description = "Enable AVX-512 instructions",
68 .llvm_name = "avx512f",
69 .subfeatures = &[_]*const Feature {
70 &feature_sse,
71 },
72};
73
74pub const feature_avx512bf16 = Feature{
75 .name = "avx512bf16",
76 .description = "Support bfloat16 floating point",
77 .llvm_name = "avx512bf16",
78 .subfeatures = &[_]*const Feature {
79 &feature_sse,
80 },
81};
82
83pub const feature_avx512bitalg = Feature{
84 .name = "avx512bitalg",
85 .description = "Enable AVX-512 Bit Algorithms",
86 .llvm_name = "avx512bitalg",
87 .subfeatures = &[_]*const Feature {
88 &feature_sse,
89 },
90};
91
92pub const feature_bmi = Feature{
93 .name = "bmi",
94 .description = "Support BMI instructions",
95 .llvm_name = "bmi",
96 .subfeatures = &[_]*const Feature {
97 },
98};
99
100pub const feature_bmi2 = Feature{
101 .name = "bmi2",
102 .description = "Support BMI2 instructions",
103 .llvm_name = "bmi2",
104 .subfeatures = &[_]*const Feature {
105 },
106};
107
108pub const feature_avx512bw = Feature{
109 .name = "avx512bw",
110 .description = "Enable AVX-512 Byte and Word Instructions",
111 .llvm_name = "avx512bw",
112 .subfeatures = &[_]*const Feature {
113 &feature_sse,
114 },
115};
116
117pub const feature_branchfusion = Feature{
118 .name = "branchfusion",
119 .description = "CMP/TEST can be fused with conditional branches",
120 .llvm_name = "branchfusion",
121 .subfeatures = &[_]*const Feature {
122 },
123};
124
125pub const feature_avx512cd = Feature{
126 .name = "avx512cd",
127 .description = "Enable AVX-512 Conflict Detection Instructions",
128 .llvm_name = "avx512cd",
129 .subfeatures = &[_]*const Feature {
130 &feature_sse,
131 },
132};
133
134pub const feature_cldemote = Feature{
135 .name = "cldemote",
136 .description = "Enable Cache Demote",
137 .llvm_name = "cldemote",
138 .subfeatures = &[_]*const Feature {
139 },
140};
141
142pub const feature_clflushopt = Feature{
143 .name = "clflushopt",
144 .description = "Flush A Cache Line Optimized",
145 .llvm_name = "clflushopt",
146 .subfeatures = &[_]*const Feature {
147 },
148};
149
150pub const feature_clwb = Feature{
151 .name = "clwb",
152 .description = "Cache Line Write Back",
153 .llvm_name = "clwb",
154 .subfeatures = &[_]*const Feature {
155 },
156};
157
158pub const feature_clzero = Feature{
159 .name = "clzero",
160 .description = "Enable Cache Line Zero",
161 .llvm_name = "clzero",
162 .subfeatures = &[_]*const Feature {
163 },
164};
165
166pub const feature_cmov = Feature{
167 .name = "cmov",
168 .description = "Enable conditional move instructions",
169 .llvm_name = "cmov",
170 .subfeatures = &[_]*const Feature {
171 },
172};
173
174pub const feature_cx8 = Feature{
175 .name = "cx8",
176 .description = "Support CMPXCHG8B instructions",
177 .llvm_name = "cx8",
178 .subfeatures = &[_]*const Feature {
179 },
180};
181
182pub const feature_cx16 = Feature{
183 .name = "cx16",
184 .description = "64-bit with cmpxchg16b",
185 .llvm_name = "cx16",
186 .subfeatures = &[_]*const Feature {
187 &feature_cx8,
188 },
189};
190
191pub const feature_avx512dq = Feature{
192 .name = "avx512dq",
193 .description = "Enable AVX-512 Doubleword and Quadword Instructions",
194 .llvm_name = "avx512dq",
195 .subfeatures = &[_]*const Feature {
196 &feature_sse,
197 },
198};
199
200pub const feature_mpx = Feature{
201 .name = "mpx",
202 .description = "Deprecated. Support MPX instructions",
203 .llvm_name = "mpx",
204 .subfeatures = &[_]*const Feature {
205 },
206};
207
208pub const feature_enqcmd = Feature{
209 .name = "enqcmd",
210 .description = "Has ENQCMD instructions",
211 .llvm_name = "enqcmd",
212 .subfeatures = &[_]*const Feature {
213 },
214};
215
216pub const feature_avx512er = Feature{
217 .name = "avx512er",
218 .description = "Enable AVX-512 Exponential and Reciprocal Instructions",
219 .llvm_name = "avx512er",
220 .subfeatures = &[_]*const Feature {
221 &feature_sse,
222 },
223};
224
225pub const feature_ermsb = Feature{
226 .name = "ermsb",
227 .description = "REP MOVS/STOS are fast",
228 .llvm_name = "ermsb",
229 .subfeatures = &[_]*const Feature {
230 },
231};
232
233pub const feature_f16c = Feature{
234 .name = "f16c",
235 .description = "Support 16-bit floating point conversion instructions",
236 .llvm_name = "f16c",
237 .subfeatures = &[_]*const Feature {
238 &feature_sse,
239 },
240};
241
242pub const feature_fma = Feature{
243 .name = "fma",
244 .description = "Enable three-operand fused multiple-add",
245 .llvm_name = "fma",
246 .subfeatures = &[_]*const Feature {
247 &feature_sse,
248 },
249};
250
251pub const feature_fma4 = Feature{
252 .name = "fma4",
253 .description = "Enable four-operand fused multiple-add",
254 .llvm_name = "fma4",
255 .subfeatures = &[_]*const Feature {
256 &feature_sse,
257 },
258};
259
260pub const feature_fsgsbase = Feature{
261 .name = "fsgsbase",
262 .description = "Support FS/GS Base instructions",
263 .llvm_name = "fsgsbase",
264 .subfeatures = &[_]*const Feature {
265 },
266};
267
268pub const feature_fxsr = Feature{
269 .name = "fxsr",
270 .description = "Support fxsave/fxrestore instructions",
271 .llvm_name = "fxsr",
272 .subfeatures = &[_]*const Feature {
273 },
274};
275
276pub const feature_fast11bytenop = Feature{
277 .name = "fast-11bytenop",
278 .description = "Target can quickly decode up to 11 byte NOPs",
279 .llvm_name = "fast-11bytenop",
280 .subfeatures = &[_]*const Feature {
281 },
282};
283
284pub const feature_fast15bytenop = Feature{
285 .name = "fast-15bytenop",
286 .description = "Target can quickly decode up to 15 byte NOPs",
287 .llvm_name = "fast-15bytenop",
288 .subfeatures = &[_]*const Feature {
289 },
290};
291
292pub const feature_fastBextr = Feature{
293 .name = "fast-bextr",
294 .description = "Indicates that the BEXTR instruction is implemented as a single uop with good throughput",
295 .llvm_name = "fast-bextr",
296 .subfeatures = &[_]*const Feature {
297 },
298};
299
300pub const feature_fastHops = Feature{
301 .name = "fast-hops",
302 .description = "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles",
303 .llvm_name = "fast-hops",
304 .subfeatures = &[_]*const Feature {
305 &feature_sse,
306 },
307};
308
309pub const feature_fastLzcnt = Feature{
310 .name = "fast-lzcnt",
311 .description = "LZCNT instructions are as fast as most simple integer ops",
312 .llvm_name = "fast-lzcnt",
313 .subfeatures = &[_]*const Feature {
314 },
315};
316
317pub const feature_fastPartialYmmOrZmmWrite = Feature{
318 .name = "fast-partial-ymm-or-zmm-write",
319 .description = "Partial writes to YMM/ZMM registers are fast",
320 .llvm_name = "fast-partial-ymm-or-zmm-write",
321 .subfeatures = &[_]*const Feature {
322 },
323};
324
325pub const feature_fastShldRotate = Feature{
326 .name = "fast-shld-rotate",
327 .description = "SHLD can be used as a faster rotate",
328 .llvm_name = "fast-shld-rotate",
329 .subfeatures = &[_]*const Feature {
330 },
331};
332
333pub const feature_fastScalarFsqrt = Feature{
334 .name = "fast-scalar-fsqrt",
335 .description = "Scalar SQRT is fast (disable Newton-Raphson)",
336 .llvm_name = "fast-scalar-fsqrt",
337 .subfeatures = &[_]*const Feature {
338 },
339};
340
341pub const feature_fastScalarShiftMasks = Feature{
342 .name = "fast-scalar-shift-masks",
343 .description = "Prefer a left/right scalar logical shift pair over a shift+and pair",
344 .llvm_name = "fast-scalar-shift-masks",
345 .subfeatures = &[_]*const Feature {
346 },
347};
348
349pub const feature_fastVariableShuffle = Feature{
350 .name = "fast-variable-shuffle",
351 .description = "Shuffles with variable masks are fast",
352 .llvm_name = "fast-variable-shuffle",
353 .subfeatures = &[_]*const Feature {
354 },
355};
356
357pub const feature_fastVectorFsqrt = Feature{
358 .name = "fast-vector-fsqrt",
359 .description = "Vector SQRT is fast (disable Newton-Raphson)",
360 .llvm_name = "fast-vector-fsqrt",
361 .subfeatures = &[_]*const Feature {
362 },
363};
364
365pub const feature_fastVectorShiftMasks = Feature{
366 .name = "fast-vector-shift-masks",
367 .description = "Prefer a left/right vector logical shift pair over a shift+and pair",
368 .llvm_name = "fast-vector-shift-masks",
369 .subfeatures = &[_]*const Feature {
370 },
371};
372
373pub const feature_gfni = Feature{
374 .name = "gfni",
375 .description = "Enable Galois Field Arithmetic Instructions",
376 .llvm_name = "gfni",
377 .subfeatures = &[_]*const Feature {
378 &feature_sse,
379 },
380};
381
382pub const feature_fastGather = Feature{
383 .name = "fast-gather",
384 .description = "Indicates if gather is reasonably fast",
385 .llvm_name = "fast-gather",
386 .subfeatures = &[_]*const Feature {
387 },
388};
389
390pub const feature_avx512ifma = Feature{
391 .name = "avx512ifma",
392 .description = "Enable AVX-512 Integer Fused Multiple-Add",
393 .llvm_name = "avx512ifma",
394 .subfeatures = &[_]*const Feature {
395 &feature_sse,
396 },
397};
398
399pub const feature_invpcid = Feature{
400 .name = "invpcid",
401 .description = "Invalidate Process-Context Identifier",
402 .llvm_name = "invpcid",
403 .subfeatures = &[_]*const Feature {
404 },
405};
406
407pub const feature_sahf = Feature{
408 .name = "sahf",
409 .description = "Support LAHF and SAHF instructions",
410 .llvm_name = "sahf",
411 .subfeatures = &[_]*const Feature {
412 },
413};
414
415pub const feature_leaSp = Feature{
416 .name = "lea-sp",
417 .description = "Use LEA for adjusting the stack pointer",
418 .llvm_name = "lea-sp",
419 .subfeatures = &[_]*const Feature {
420 },
421};
422
423pub const feature_leaUsesAg = Feature{
424 .name = "lea-uses-ag",
425 .description = "LEA instruction needs inputs at AG stage",
426 .llvm_name = "lea-uses-ag",
427 .subfeatures = &[_]*const Feature {
428 },
429};
430
431pub const feature_lwp = Feature{
432 .name = "lwp",
433 .description = "Enable LWP instructions",
434 .llvm_name = "lwp",
435 .subfeatures = &[_]*const Feature {
436 },
437};
438
439pub const feature_lzcnt = Feature{
440 .name = "lzcnt",
441 .description = "Support LZCNT instruction",
442 .llvm_name = "lzcnt",
443 .subfeatures = &[_]*const Feature {
444 },
445};
446
447pub const feature_falseDepsLzcntTzcnt = Feature{
448 .name = "false-deps-lzcnt-tzcnt",
449 .description = "LZCNT/TZCNT have a false dependency on dest register",
450 .llvm_name = "false-deps-lzcnt-tzcnt",
451 .subfeatures = &[_]*const Feature {
452 },
453};
454
455pub const feature_mmx = Feature{
456 .name = "mmx",
457 .description = "Enable MMX instructions",
458 .llvm_name = "mmx",
459 .subfeatures = &[_]*const Feature {
460 },
461};
462
463pub const feature_movbe = Feature{
464 .name = "movbe",
465 .description = "Support MOVBE instruction",
466 .llvm_name = "movbe",
467 .subfeatures = &[_]*const Feature {
468 },
469};
470
471pub const feature_movdir64b = Feature{
472 .name = "movdir64b",
473 .description = "Support movdir64b instruction",
474 .llvm_name = "movdir64b",
475 .subfeatures = &[_]*const Feature {
476 },
477};
478
479pub const feature_movdiri = Feature{
480 .name = "movdiri",
481 .description = "Support movdiri instruction",
482 .llvm_name = "movdiri",
483 .subfeatures = &[_]*const Feature {
484 },
485};
486
487pub const feature_mwaitx = Feature{
488 .name = "mwaitx",
489 .description = "Enable MONITORX/MWAITX timer functionality",
490 .llvm_name = "mwaitx",
491 .subfeatures = &[_]*const Feature {
492 },
493};
494
495pub const feature_macrofusion = Feature{
496 .name = "macrofusion",
497 .description = "Various instructions can be fused with conditional branches",
498 .llvm_name = "macrofusion",
499 .subfeatures = &[_]*const Feature {
500 },
501};
502
503pub const feature_mergeToThreewayBranch = Feature{
504 .name = "merge-to-threeway-branch",
505 .description = "Merge branches to a three-way conditional branch",
506 .llvm_name = "merge-to-threeway-branch",
507 .subfeatures = &[_]*const Feature {
508 },
509};
510
511pub const feature_nopl = Feature{
512 .name = "nopl",
513 .description = "Enable NOPL instruction",
514 .llvm_name = "nopl",
515 .subfeatures = &[_]*const Feature {
516 },
517};
518
519pub const feature_pclmul = Feature{
520 .name = "pclmul",
521 .description = "Enable packed carry-less multiplication instructions",
522 .llvm_name = "pclmul",
523 .subfeatures = &[_]*const Feature {
524 &feature_sse,
525 },
526};
527
528pub const feature_pconfig = Feature{
529 .name = "pconfig",
530 .description = "platform configuration instruction",
531 .llvm_name = "pconfig",
532 .subfeatures = &[_]*const Feature {
533 },
534};
535
536pub const feature_avx512pf = Feature{
537 .name = "avx512pf",
538 .description = "Enable AVX-512 PreFetch Instructions",
539 .llvm_name = "avx512pf",
540 .subfeatures = &[_]*const Feature {
541 &feature_sse,
542 },
543};
544
545pub const feature_pku = Feature{
546 .name = "pku",
547 .description = "Enable protection keys",
548 .llvm_name = "pku",
549 .subfeatures = &[_]*const Feature {
550 },
551};
552
553pub const feature_popcnt = Feature{
554 .name = "popcnt",
555 .description = "Support POPCNT instruction",
556 .llvm_name = "popcnt",
557 .subfeatures = &[_]*const Feature {
558 },
559};
560
561pub const feature_falseDepsPopcnt = Feature{
562 .name = "false-deps-popcnt",
563 .description = "POPCNT has a false dependency on dest register",
564 .llvm_name = "false-deps-popcnt",
565 .subfeatures = &[_]*const Feature {
566 },
567};
568
569pub const feature_prefetchwt1 = Feature{
570 .name = "prefetchwt1",
571 .description = "Prefetch with Intent to Write and T1 Hint",
572 .llvm_name = "prefetchwt1",
573 .subfeatures = &[_]*const Feature {
574 },
575};
576
577pub const feature_prfchw = Feature{
578 .name = "prfchw",
579 .description = "Support PRFCHW instructions",
580 .llvm_name = "prfchw",
581 .subfeatures = &[_]*const Feature {
582 },
583};
584
585pub const feature_ptwrite = Feature{
586 .name = "ptwrite",
587 .description = "Support ptwrite instruction",
588 .llvm_name = "ptwrite",
589 .subfeatures = &[_]*const Feature {
590 },
591};
592
593pub const feature_padShortFunctions = Feature{
594 .name = "pad-short-functions",
595 .description = "Pad short functions",
596 .llvm_name = "pad-short-functions",
597 .subfeatures = &[_]*const Feature {
598 },
599};
600
601pub const feature_prefer128Bit = Feature{
602 .name = "prefer-128-bit",
603 .description = "Prefer 128-bit AVX instructions",
604 .llvm_name = "prefer-128-bit",
605 .subfeatures = &[_]*const Feature {
606 },
607};
608
609pub const feature_prefer256Bit = Feature{
610 .name = "prefer-256-bit",
611 .description = "Prefer 256-bit AVX instructions",
612 .llvm_name = "prefer-256-bit",
613 .subfeatures = &[_]*const Feature {
614 },
615};
616
617pub const feature_rdpid = Feature{
618 .name = "rdpid",
619 .description = "Support RDPID instructions",
620 .llvm_name = "rdpid",
621 .subfeatures = &[_]*const Feature {
622 },
623};
624
625pub const feature_rdrnd = Feature{
626 .name = "rdrnd",
627 .description = "Support RDRAND instruction",
628 .llvm_name = "rdrnd",
629 .subfeatures = &[_]*const Feature {
630 },
631};
632
633pub const feature_rdseed = Feature{
634 .name = "rdseed",
635 .description = "Support RDSEED instruction",
636 .llvm_name = "rdseed",
637 .subfeatures = &[_]*const Feature {
638 },
639};
640
641pub const feature_rtm = Feature{
642 .name = "rtm",
643 .description = "Support RTM instructions",
644 .llvm_name = "rtm",
645 .subfeatures = &[_]*const Feature {
646 },
647};
648
649pub const feature_retpoline = Feature{
650 .name = "retpoline",
651 .description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct",
652 .llvm_name = "retpoline",
653 .subfeatures = &[_]*const Feature {
654 &feature_retpolineIndirectCalls,
655 &feature_retpolineIndirectBranches,
656 },
657};
658
659pub const feature_retpolineExternalThunk = Feature{
660 .name = "retpoline-external-thunk",
661 .description = "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature",
662 .llvm_name = "retpoline-external-thunk",
663 .subfeatures = &[_]*const Feature {
664 &feature_retpolineIndirectCalls,
665 },
666};
667
668pub const feature_retpolineIndirectBranches = Feature{
669 .name = "retpoline-indirect-branches",
670 .description = "Remove speculation of indirect branches from the generated code",
671 .llvm_name = "retpoline-indirect-branches",
672 .subfeatures = &[_]*const Feature {
673 },
674};
675
676pub const feature_retpolineIndirectCalls = Feature{
677 .name = "retpoline-indirect-calls",
678 .description = "Remove speculation of indirect calls from the generated code",
679 .llvm_name = "retpoline-indirect-calls",
680 .subfeatures = &[_]*const Feature {
681 },
682};
683
684pub const feature_sgx = Feature{
685 .name = "sgx",
686 .description = "Enable Software Guard Extensions",
687 .llvm_name = "sgx",
688 .subfeatures = &[_]*const Feature {
689 },
690};
691
692pub const feature_sha = Feature{
693 .name = "sha",
694 .description = "Enable SHA instructions",
695 .llvm_name = "sha",
696 .subfeatures = &[_]*const Feature {
697 &feature_sse,
698 },
699};
700
701pub const feature_shstk = Feature{
702 .name = "shstk",
703 .description = "Support CET Shadow-Stack instructions",
704 .llvm_name = "shstk",
705 .subfeatures = &[_]*const Feature {
706 },
707};
708
709pub const feature_sse = Feature{
710 .name = "sse",
711 .description = "Enable SSE instructions",
712 .llvm_name = "sse",
713 .subfeatures = &[_]*const Feature {
714 },
715};
716
717pub const feature_sse2 = Feature{
718 .name = "sse2",
719 .description = "Enable SSE2 instructions",
720 .llvm_name = "sse2",
721 .subfeatures = &[_]*const Feature {
722 &feature_sse,
723 },
724};
725
726pub const feature_sse3 = Feature{
727 .name = "sse3",
728 .description = "Enable SSE3 instructions",
729 .llvm_name = "sse3",
730 .subfeatures = &[_]*const Feature {
731 &feature_sse,
732 },
733};
734
735pub const feature_sse4a = Feature{
736 .name = "sse4a",
737 .description = "Support SSE 4a instructions",
738 .llvm_name = "sse4a",
739 .subfeatures = &[_]*const Feature {
740 &feature_sse,
741 },
742};
743
744pub const feature_sse41 = Feature{
745 .name = "sse4.1",
746 .description = "Enable SSE 4.1 instructions",
747 .llvm_name = "sse4.1",
748 .subfeatures = &[_]*const Feature {
749 &feature_sse,
750 },
751};
752
753pub const feature_sse42 = Feature{
754 .name = "sse4.2",
755 .description = "Enable SSE 4.2 instructions",
756 .llvm_name = "sse4.2",
757 .subfeatures = &[_]*const Feature {
758 &feature_sse,
759 },
760};
761
762pub const feature_sseUnalignedMem = Feature{
763 .name = "sse-unaligned-mem",
764 .description = "Allow unaligned memory operands with SSE instructions",
765 .llvm_name = "sse-unaligned-mem",
766 .subfeatures = &[_]*const Feature {
767 },
768};
769
770pub const feature_ssse3 = Feature{
771 .name = "ssse3",
772 .description = "Enable SSSE3 instructions",
773 .llvm_name = "ssse3",
774 .subfeatures = &[_]*const Feature {
775 &feature_sse,
776 },
777};
778
779pub const feature_slow3opsLea = Feature{
780 .name = "slow-3ops-lea",
781 .description = "LEA instruction with 3 ops or certain registers is slow",
782 .llvm_name = "slow-3ops-lea",
783 .subfeatures = &[_]*const Feature {
784 },
785};
786
787pub const feature_idivlToDivb = Feature{
788 .name = "idivl-to-divb",
789 .description = "Use 8-bit divide for positive values less than 256",
790 .llvm_name = "idivl-to-divb",
791 .subfeatures = &[_]*const Feature {
792 },
793};
794
795pub const feature_idivqToDivl = Feature{
796 .name = "idivq-to-divl",
797 .description = "Use 32-bit divide for positive values less than 2^32",
798 .llvm_name = "idivq-to-divl",
799 .subfeatures = &[_]*const Feature {
800 },
801};
802
803pub const feature_slowIncdec = Feature{
804 .name = "slow-incdec",
805 .description = "INC and DEC instructions are slower than ADD and SUB",
806 .llvm_name = "slow-incdec",
807 .subfeatures = &[_]*const Feature {
808 },
809};
810
811pub const feature_slowLea = Feature{
812 .name = "slow-lea",
813 .description = "LEA instruction with certain arguments is slow",
814 .llvm_name = "slow-lea",
815 .subfeatures = &[_]*const Feature {
816 },
817};
818
819pub const feature_slowPmaddwd = Feature{
820 .name = "slow-pmaddwd",
821 .description = "PMADDWD is slower than PMULLD",
822 .llvm_name = "slow-pmaddwd",
823 .subfeatures = &[_]*const Feature {
824 },
825};
826
827pub const feature_slowPmulld = Feature{
828 .name = "slow-pmulld",
829 .description = "PMULLD instruction is slow",
830 .llvm_name = "slow-pmulld",
831 .subfeatures = &[_]*const Feature {
832 },
833};
834
835pub const feature_slowShld = Feature{
836 .name = "slow-shld",
837 .description = "SHLD instruction is slow",
838 .llvm_name = "slow-shld",
839 .subfeatures = &[_]*const Feature {
840 },
841};
842
843pub const feature_slowTwoMemOps = Feature{
844 .name = "slow-two-mem-ops",
845 .description = "Two memory operand instructions are slow",
846 .llvm_name = "slow-two-mem-ops",
847 .subfeatures = &[_]*const Feature {
848 },
849};
850
851pub const feature_slowUnalignedMem16 = Feature{
852 .name = "slow-unaligned-mem-16",
853 .description = "Slow unaligned 16-byte memory access",
854 .llvm_name = "slow-unaligned-mem-16",
855 .subfeatures = &[_]*const Feature {
856 },
857};
858
859pub const feature_slowUnalignedMem32 = Feature{
860 .name = "slow-unaligned-mem-32",
861 .description = "Slow unaligned 32-byte memory access",
862 .llvm_name = "slow-unaligned-mem-32",
863 .subfeatures = &[_]*const Feature {
864 },
865};
866
867pub const feature_softFloat = Feature{
868 .name = "soft-float",
869 .description = "Use software floating point features",
870 .llvm_name = "soft-float",
871 .subfeatures = &[_]*const Feature {
872 },
873};
874
875pub const feature_tbm = Feature{
876 .name = "tbm",
877 .description = "Enable TBM instructions",
878 .llvm_name = "tbm",
879 .subfeatures = &[_]*const Feature {
880 },
881};
882
883pub const feature_useAa = Feature{
884 .name = "use-aa",
885 .description = "Use alias analysis during codegen",
886 .llvm_name = "use-aa",
887 .subfeatures = &[_]*const Feature {
888 },
889};
890
891pub const feature_vaes = Feature{
892 .name = "vaes",
893 .description = "Promote selected AES instructions to AVX512/AVX registers",
894 .llvm_name = "vaes",
895 .subfeatures = &[_]*const Feature {
896 &feature_sse,
897 },
898};
899
900pub const feature_avx512vbmi = Feature{
901 .name = "avx512vbmi",
902 .description = "Enable AVX-512 Vector Byte Manipulation Instructions",
903 .llvm_name = "avx512vbmi",
904 .subfeatures = &[_]*const Feature {
905 &feature_sse,
906 },
907};
908
909pub const feature_avx512vbmi2 = Feature{
910 .name = "avx512vbmi2",
911 .description = "Enable AVX-512 further Vector Byte Manipulation Instructions",
912 .llvm_name = "avx512vbmi2",
913 .subfeatures = &[_]*const Feature {
914 &feature_sse,
915 },
916};
917
918pub const feature_avx512vl = Feature{
919 .name = "avx512vl",
920 .description = "Enable AVX-512 Vector Length eXtensions",
921 .llvm_name = "avx512vl",
922 .subfeatures = &[_]*const Feature {
923 &feature_sse,
924 },
925};
926
927pub const feature_avx512vnni = Feature{
928 .name = "avx512vnni",
929 .description = "Enable AVX-512 Vector Neural Network Instructions",
930 .llvm_name = "avx512vnni",
931 .subfeatures = &[_]*const Feature {
932 &feature_sse,
933 },
934};
935
936pub const feature_avx512vp2intersect = Feature{
937 .name = "avx512vp2intersect",
938 .description = "Enable AVX-512 vp2intersect",
939 .llvm_name = "avx512vp2intersect",
940 .subfeatures = &[_]*const Feature {
941 &feature_sse,
942 },
943};
944
945pub const feature_vpclmulqdq = Feature{
946 .name = "vpclmulqdq",
947 .description = "Enable vpclmulqdq instructions",
948 .llvm_name = "vpclmulqdq",
949 .subfeatures = &[_]*const Feature {
950 &feature_sse,
951 },
952};
953
954pub const feature_avx512vpopcntdq = Feature{
955 .name = "avx512vpopcntdq",
956 .description = "Enable AVX-512 Population Count Instructions",
957 .llvm_name = "avx512vpopcntdq",
958 .subfeatures = &[_]*const Feature {
959 &feature_sse,
960 },
961};
962
963pub const feature_waitpkg = Feature{
964 .name = "waitpkg",
965 .description = "Wait and pause enhancements",
966 .llvm_name = "waitpkg",
967 .subfeatures = &[_]*const Feature {
968 },
969};
970
971pub const feature_wbnoinvd = Feature{
972 .name = "wbnoinvd",
973 .description = "Write Back No Invalidate",
974 .llvm_name = "wbnoinvd",
975 .subfeatures = &[_]*const Feature {
976 },
977};
978
979pub const feature_x87 = Feature{
980 .name = "x87",
981 .description = "Enable X87 float instructions",
982 .llvm_name = "x87",
983 .subfeatures = &[_]*const Feature {
984 },
985};
986
987pub const feature_xop = Feature{
988 .name = "xop",
989 .description = "Enable XOP instructions",
990 .llvm_name = "xop",
991 .subfeatures = &[_]*const Feature {
992 &feature_sse,
993 },
994};
995
996pub const feature_xsave = Feature{
997 .name = "xsave",
998 .description = "Support xsave instructions",
999 .llvm_name = "xsave",
1000 .subfeatures = &[_]*const Feature {
1001 },
1002};
1003
1004pub const feature_xsavec = Feature{
1005 .name = "xsavec",
1006 .description = "Support xsavec instructions",
1007 .llvm_name = "xsavec",
1008 .subfeatures = &[_]*const Feature {
1009 },
1010};
1011
1012pub const feature_xsaveopt = Feature{
1013 .name = "xsaveopt",
1014 .description = "Support xsaveopt instructions",
1015 .llvm_name = "xsaveopt",
1016 .subfeatures = &[_]*const Feature {
1017 },
1018};
1019
1020pub const feature_xsaves = Feature{
1021 .name = "xsaves",
1022 .description = "Support xsaves instructions",
1023 .llvm_name = "xsaves",
1024 .subfeatures = &[_]*const Feature {
1025 },
1026};
1027
1028pub const feature_bitMode16 = Feature{
1029 .name = "16bit-mode",
1030 .description = "16-bit mode (i8086)",
1031 .llvm_name = "16bit-mode",
1032 .subfeatures = &[_]*const Feature {
1033 },
1034};
1035
1036pub const feature_bitMode32 = Feature{
1037 .name = "32bit-mode",
1038 .description = "32-bit mode (80386)",
1039 .llvm_name = "32bit-mode",
1040 .subfeatures = &[_]*const Feature {
1041 },
1042};
1043
1044pub const feature_bitMode64 = Feature{
1045 .name = "64bit-mode",
1046 .description = "64-bit mode (x86_64)",
1047 .llvm_name = "64bit-mode",
1048 .subfeatures = &[_]*const Feature {
1049 },
1050};
1051
1052pub const features = &[_]*const Feature {
1053 &feature_dnow3,
1054 &feature_dnowa3,
1055 &feature_bit64,
1056 &feature_adx,
1057 &feature_aes,
1058 &feature_avx,
1059 &feature_avx2,
1060 &feature_avx512f,
1061 &feature_avx512bf16,
1062 &feature_avx512bitalg,
1063 &feature_bmi,
1064 &feature_bmi2,
1065 &feature_avx512bw,
1066 &feature_branchfusion,
1067 &feature_avx512cd,
1068 &feature_cldemote,
1069 &feature_clflushopt,
1070 &feature_clwb,
1071 &feature_clzero,
1072 &feature_cmov,
1073 &feature_cx8,
1074 &feature_cx16,
1075 &feature_avx512dq,
1076 &feature_mpx,
1077 &feature_enqcmd,
1078 &feature_avx512er,
1079 &feature_ermsb,
1080 &feature_f16c,
1081 &feature_fma,
1082 &feature_fma4,
1083 &feature_fsgsbase,
1084 &feature_fxsr,
1085 &feature_fast11bytenop,
1086 &feature_fast15bytenop,
1087 &feature_fastBextr,
1088 &feature_fastHops,
1089 &feature_fastLzcnt,
1090 &feature_fastPartialYmmOrZmmWrite,
1091 &feature_fastShldRotate,
1092 &feature_fastScalarFsqrt,
1093 &feature_fastScalarShiftMasks,
1094 &feature_fastVariableShuffle,
1095 &feature_fastVectorFsqrt,
1096 &feature_fastVectorShiftMasks,
1097 &feature_gfni,
1098 &feature_fastGather,
1099 &feature_avx512ifma,
1100 &feature_invpcid,
1101 &feature_sahf,
1102 &feature_leaSp,
1103 &feature_leaUsesAg,
1104 &feature_lwp,
1105 &feature_lzcnt,
1106 &feature_falseDepsLzcntTzcnt,
1107 &feature_mmx,
1108 &feature_movbe,
1109 &feature_movdir64b,
1110 &feature_movdiri,
1111 &feature_mwaitx,
1112 &feature_macrofusion,
1113 &feature_mergeToThreewayBranch,
1114 &feature_nopl,
1115 &feature_pclmul,
1116 &feature_pconfig,
1117 &feature_avx512pf,
1118 &feature_pku,
1119 &feature_popcnt,
1120 &feature_falseDepsPopcnt,
1121 &feature_prefetchwt1,
1122 &feature_prfchw,
1123 &feature_ptwrite,
1124 &feature_padShortFunctions,
1125 &feature_prefer128Bit,
1126 &feature_prefer256Bit,
1127 &feature_rdpid,
1128 &feature_rdrnd,
1129 &feature_rdseed,
1130 &feature_rtm,
1131 &feature_retpoline,
1132 &feature_retpolineExternalThunk,
1133 &feature_retpolineIndirectBranches,
1134 &feature_retpolineIndirectCalls,
1135 &feature_sgx,
1136 &feature_sha,
1137 &feature_shstk,
1138 &feature_sse,
1139 &feature_sse2,
1140 &feature_sse3,
1141 &feature_sse4a,
1142 &feature_sse41,
1143 &feature_sse42,
1144 &feature_sseUnalignedMem,
1145 &feature_ssse3,
1146 &feature_slow3opsLea,
1147 &feature_idivlToDivb,
1148 &feature_idivqToDivl,
1149 &feature_slowIncdec,
1150 &feature_slowLea,
1151 &feature_slowPmaddwd,
1152 &feature_slowPmulld,
1153 &feature_slowShld,
1154 &feature_slowTwoMemOps,
1155 &feature_slowUnalignedMem16,
1156 &feature_slowUnalignedMem32,
1157 &feature_softFloat,
1158 &feature_tbm,
1159 &feature_useAa,
1160 &feature_vaes,
1161 &feature_avx512vbmi,
1162 &feature_avx512vbmi2,
1163 &feature_avx512vl,
1164 &feature_avx512vnni,
1165 &feature_avx512vp2intersect,
1166 &feature_vpclmulqdq,
1167 &feature_avx512vpopcntdq,
1168 &feature_waitpkg,
1169 &feature_wbnoinvd,
1170 &feature_x87,
1171 &feature_xop,
1172 &feature_xsave,
1173 &feature_xsavec,
1174 &feature_xsaveopt,
1175 &feature_xsaves,
1176 &feature_bitMode16,
1177 &feature_bitMode32,
1178 &feature_bitMode64,
1179};
1180
1181pub const cpu_amdfam10 = Cpu{
1182 .name = "amdfam10",
1183 .llvm_name = "amdfam10",
1184 .subfeatures = &[_]*const Feature {
1185 &feature_mmx,
1186 &feature_dnowa3,
1187 &feature_bit64,
1188 &feature_cmov,
1189 &feature_cx8,
1190 &feature_cx16,
1191 &feature_fxsr,
1192 &feature_fastScalarShiftMasks,
1193 &feature_sahf,
1194 &feature_lzcnt,
1195 &feature_nopl,
1196 &feature_popcnt,
1197 &feature_sse,
1198 &feature_sse4a,
1199 &feature_slowShld,
1200 &feature_x87,
1201 },
1202};
1203
1204pub const cpu_athlon = Cpu{
1205 .name = "athlon",
1206 .llvm_name = "athlon",
1207 .subfeatures = &[_]*const Feature {
1208 &feature_mmx,
1209 &feature_dnowa3,
1210 &feature_cmov,
1211 &feature_cx8,
1212 &feature_nopl,
1213 &feature_slowShld,
1214 &feature_slowUnalignedMem16,
1215 &feature_x87,
1216 },
1217};
1218
1219pub const cpu_athlon4 = Cpu{
1220 .name = "athlon-4",
1221 .llvm_name = "athlon-4",
1222 .subfeatures = &[_]*const Feature {
1223 &feature_mmx,
1224 &feature_dnowa3,
1225 &feature_cmov,
1226 &feature_cx8,
1227 &feature_fxsr,
1228 &feature_nopl,
1229 &feature_sse,
1230 &feature_slowShld,
1231 &feature_slowUnalignedMem16,
1232 &feature_x87,
1233 },
1234};
1235
1236pub const cpu_athlonFx = Cpu{
1237 .name = "athlon-fx",
1238 .llvm_name = "athlon-fx",
1239 .subfeatures = &[_]*const Feature {
1240 &feature_mmx,
1241 &feature_dnowa3,
1242 &feature_bit64,
1243 &feature_cmov,
1244 &feature_cx8,
1245 &feature_fxsr,
1246 &feature_fastScalarShiftMasks,
1247 &feature_nopl,
1248 &feature_sse,
1249 &feature_sse2,
1250 &feature_slowShld,
1251 &feature_slowUnalignedMem16,
1252 &feature_x87,
1253 },
1254};
1255
1256pub const cpu_athlonMp = Cpu{
1257 .name = "athlon-mp",
1258 .llvm_name = "athlon-mp",
1259 .subfeatures = &[_]*const Feature {
1260 &feature_mmx,
1261 &feature_dnowa3,
1262 &feature_cmov,
1263 &feature_cx8,
1264 &feature_fxsr,
1265 &feature_nopl,
1266 &feature_sse,
1267 &feature_slowShld,
1268 &feature_slowUnalignedMem16,
1269 &feature_x87,
1270 },
1271};
1272
1273pub const cpu_athlonTbird = Cpu{
1274 .name = "athlon-tbird",
1275 .llvm_name = "athlon-tbird",
1276 .subfeatures = &[_]*const Feature {
1277 &feature_mmx,
1278 &feature_dnowa3,
1279 &feature_cmov,
1280 &feature_cx8,
1281 &feature_nopl,
1282 &feature_slowShld,
1283 &feature_slowUnalignedMem16,
1284 &feature_x87,
1285 },
1286};
1287
1288pub const cpu_athlonXp = Cpu{
1289 .name = "athlon-xp",
1290 .llvm_name = "athlon-xp",
1291 .subfeatures = &[_]*const Feature {
1292 &feature_mmx,
1293 &feature_dnowa3,
1294 &feature_cmov,
1295 &feature_cx8,
1296 &feature_fxsr,
1297 &feature_nopl,
1298 &feature_sse,
1299 &feature_slowShld,
1300 &feature_slowUnalignedMem16,
1301 &feature_x87,
1302 },
1303};
1304
1305pub const cpu_athlon64 = Cpu{
1306 .name = "athlon64",
1307 .llvm_name = "athlon64",
1308 .subfeatures = &[_]*const Feature {
1309 &feature_mmx,
1310 &feature_dnowa3,
1311 &feature_bit64,
1312 &feature_cmov,
1313 &feature_cx8,
1314 &feature_fxsr,
1315 &feature_fastScalarShiftMasks,
1316 &feature_nopl,
1317 &feature_sse,
1318 &feature_sse2,
1319 &feature_slowShld,
1320 &feature_slowUnalignedMem16,
1321 &feature_x87,
1322 },
1323};
1324
1325pub const cpu_athlon64Sse3 = Cpu{
1326 .name = "athlon64-sse3",
1327 .llvm_name = "athlon64-sse3",
1328 .subfeatures = &[_]*const Feature {
1329 &feature_mmx,
1330 &feature_dnowa3,
1331 &feature_bit64,
1332 &feature_cmov,
1333 &feature_cx8,
1334 &feature_cx16,
1335 &feature_fxsr,
1336 &feature_fastScalarShiftMasks,
1337 &feature_nopl,
1338 &feature_sse,
1339 &feature_sse3,
1340 &feature_slowShld,
1341 &feature_slowUnalignedMem16,
1342 &feature_x87,
1343 },
1344};
1345
1346pub const cpu_atom = Cpu{
1347 .name = "atom",
1348 .llvm_name = "atom",
1349 .subfeatures = &[_]*const Feature {
1350 &feature_bit64,
1351 &feature_cmov,
1352 &feature_cx8,
1353 &feature_cx16,
1354 &feature_fxsr,
1355 &feature_sahf,
1356 &feature_leaSp,
1357 &feature_leaUsesAg,
1358 &feature_mmx,
1359 &feature_movbe,
1360 &feature_nopl,
1361 &feature_padShortFunctions,
1362 &feature_sse,
1363 &feature_ssse3,
1364 &feature_idivlToDivb,
1365 &feature_idivqToDivl,
1366 &feature_slowTwoMemOps,
1367 &feature_slowUnalignedMem16,
1368 &feature_x87,
1369 },
1370};
1371
1372pub const cpu_barcelona = Cpu{
1373 .name = "barcelona",
1374 .llvm_name = "barcelona",
1375 .subfeatures = &[_]*const Feature {
1376 &feature_mmx,
1377 &feature_dnowa3,
1378 &feature_bit64,
1379 &feature_cmov,
1380 &feature_cx8,
1381 &feature_cx16,
1382 &feature_fxsr,
1383 &feature_fastScalarShiftMasks,
1384 &feature_sahf,
1385 &feature_lzcnt,
1386 &feature_nopl,
1387 &feature_popcnt,
1388 &feature_sse,
1389 &feature_sse4a,
1390 &feature_slowShld,
1391 &feature_x87,
1392 },
1393};
1394
1395pub const cpu_bdver1 = Cpu{
1396 .name = "bdver1",
1397 .llvm_name = "bdver1",
1398 .subfeatures = &[_]*const Feature {
1399 &feature_bit64,
1400 &feature_sse,
1401 &feature_aes,
1402 &feature_branchfusion,
1403 &feature_cmov,
1404 &feature_cx8,
1405 &feature_cx16,
1406 &feature_fxsr,
1407 &feature_fast11bytenop,
1408 &feature_fastScalarShiftMasks,
1409 &feature_sahf,
1410 &feature_lwp,
1411 &feature_lzcnt,
1412 &feature_mmx,
1413 &feature_nopl,
1414 &feature_pclmul,
1415 &feature_popcnt,
1416 &feature_prfchw,
1417 &feature_slowShld,
1418 &feature_x87,
1419 &feature_xop,
1420 &feature_xsave,
1421 },
1422};
1423
1424pub const cpu_bdver2 = Cpu{
1425 .name = "bdver2",
1426 .llvm_name = "bdver2",
1427 .subfeatures = &[_]*const Feature {
1428 &feature_bit64,
1429 &feature_sse,
1430 &feature_aes,
1431 &feature_bmi,
1432 &feature_branchfusion,
1433 &feature_cmov,
1434 &feature_cx8,
1435 &feature_cx16,
1436 &feature_f16c,
1437 &feature_fma,
1438 &feature_fxsr,
1439 &feature_fast11bytenop,
1440 &feature_fastBextr,
1441 &feature_fastScalarShiftMasks,
1442 &feature_sahf,
1443 &feature_lwp,
1444 &feature_lzcnt,
1445 &feature_mmx,
1446 &feature_nopl,
1447 &feature_pclmul,
1448 &feature_popcnt,
1449 &feature_prfchw,
1450 &feature_slowShld,
1451 &feature_tbm,
1452 &feature_x87,
1453 &feature_xop,
1454 &feature_xsave,
1455 },
1456};
1457
1458pub const cpu_bdver3 = Cpu{
1459 .name = "bdver3",
1460 .llvm_name = "bdver3",
1461 .subfeatures = &[_]*const Feature {
1462 &feature_bit64,
1463 &feature_sse,
1464 &feature_aes,
1465 &feature_bmi,
1466 &feature_branchfusion,
1467 &feature_cmov,
1468 &feature_cx8,
1469 &feature_cx16,
1470 &feature_f16c,
1471 &feature_fma,
1472 &feature_fsgsbase,
1473 &feature_fxsr,
1474 &feature_fast11bytenop,
1475 &feature_fastBextr,
1476 &feature_fastScalarShiftMasks,
1477 &feature_sahf,
1478 &feature_lwp,
1479 &feature_lzcnt,
1480 &feature_mmx,
1481 &feature_nopl,
1482 &feature_pclmul,
1483 &feature_popcnt,
1484 &feature_prfchw,
1485 &feature_slowShld,
1486 &feature_tbm,
1487 &feature_x87,
1488 &feature_xop,
1489 &feature_xsave,
1490 &feature_xsaveopt,
1491 },
1492};
1493
1494pub const cpu_bdver4 = Cpu{
1495 .name = "bdver4",
1496 .llvm_name = "bdver4",
1497 .subfeatures = &[_]*const Feature {
1498 &feature_bit64,
1499 &feature_sse,
1500 &feature_aes,
1501 &feature_avx2,
1502 &feature_bmi,
1503 &feature_bmi2,
1504 &feature_branchfusion,
1505 &feature_cmov,
1506 &feature_cx8,
1507 &feature_cx16,
1508 &feature_f16c,
1509 &feature_fma,
1510 &feature_fsgsbase,
1511 &feature_fxsr,
1512 &feature_fast11bytenop,
1513 &feature_fastBextr,
1514 &feature_fastScalarShiftMasks,
1515 &feature_sahf,
1516 &feature_lwp,
1517 &feature_lzcnt,
1518 &feature_mmx,
1519 &feature_mwaitx,
1520 &feature_nopl,
1521 &feature_pclmul,
1522 &feature_popcnt,
1523 &feature_prfchw,
1524 &feature_slowShld,
1525 &feature_tbm,
1526 &feature_x87,
1527 &feature_xop,
1528 &feature_xsave,
1529 &feature_xsaveopt,
1530 },
1531};
1532
1533pub const cpu_bonnell = Cpu{
1534 .name = "bonnell",
1535 .llvm_name = "bonnell",
1536 .subfeatures = &[_]*const Feature {
1537 &feature_bit64,
1538 &feature_cmov,
1539 &feature_cx8,
1540 &feature_cx16,
1541 &feature_fxsr,
1542 &feature_sahf,
1543 &feature_leaSp,
1544 &feature_leaUsesAg,
1545 &feature_mmx,
1546 &feature_movbe,
1547 &feature_nopl,
1548 &feature_padShortFunctions,
1549 &feature_sse,
1550 &feature_ssse3,
1551 &feature_idivlToDivb,
1552 &feature_idivqToDivl,
1553 &feature_slowTwoMemOps,
1554 &feature_slowUnalignedMem16,
1555 &feature_x87,
1556 },
1557};
1558
1559pub const cpu_broadwell = Cpu{
1560 .name = "broadwell",
1561 .llvm_name = "broadwell",
1562 .subfeatures = &[_]*const Feature {
1563 &feature_bit64,
1564 &feature_adx,
1565 &feature_sse,
1566 &feature_avx,
1567 &feature_avx2,
1568 &feature_bmi,
1569 &feature_bmi2,
1570 &feature_cmov,
1571 &feature_cx8,
1572 &feature_cx16,
1573 &feature_ermsb,
1574 &feature_f16c,
1575 &feature_fma,
1576 &feature_fsgsbase,
1577 &feature_fxsr,
1578 &feature_fastShldRotate,
1579 &feature_fastScalarFsqrt,
1580 &feature_fastVariableShuffle,
1581 &feature_invpcid,
1582 &feature_sahf,
1583 &feature_lzcnt,
1584 &feature_falseDepsLzcntTzcnt,
1585 &feature_mmx,
1586 &feature_movbe,
1587 &feature_macrofusion,
1588 &feature_mergeToThreewayBranch,
1589 &feature_nopl,
1590 &feature_pclmul,
1591 &feature_popcnt,
1592 &feature_falseDepsPopcnt,
1593 &feature_prfchw,
1594 &feature_rdrnd,
1595 &feature_rdseed,
1596 &feature_sse42,
1597 &feature_slow3opsLea,
1598 &feature_idivqToDivl,
1599 &feature_x87,
1600 &feature_xsave,
1601 &feature_xsaveopt,
1602 },
1603};
1604
1605pub const cpu_btver1 = Cpu{
1606 .name = "btver1",
1607 .llvm_name = "btver1",
1608 .subfeatures = &[_]*const Feature {
1609 &feature_bit64,
1610 &feature_cmov,
1611 &feature_cx8,
1612 &feature_cx16,
1613 &feature_fxsr,
1614 &feature_fast15bytenop,
1615 &feature_fastScalarShiftMasks,
1616 &feature_fastVectorShiftMasks,
1617 &feature_sahf,
1618 &feature_lzcnt,
1619 &feature_mmx,
1620 &feature_nopl,
1621 &feature_popcnt,
1622 &feature_prfchw,
1623 &feature_sse,
1624 &feature_sse4a,
1625 &feature_ssse3,
1626 &feature_slowShld,
1627 &feature_x87,
1628 },
1629};
1630
1631pub const cpu_btver2 = Cpu{
1632 .name = "btver2",
1633 .llvm_name = "btver2",
1634 .subfeatures = &[_]*const Feature {
1635 &feature_bit64,
1636 &feature_sse,
1637 &feature_aes,
1638 &feature_avx,
1639 &feature_bmi,
1640 &feature_cmov,
1641 &feature_cx8,
1642 &feature_cx16,
1643 &feature_f16c,
1644 &feature_fxsr,
1645 &feature_fast15bytenop,
1646 &feature_fastBextr,
1647 &feature_fastHops,
1648 &feature_fastLzcnt,
1649 &feature_fastPartialYmmOrZmmWrite,
1650 &feature_fastScalarShiftMasks,
1651 &feature_fastVectorShiftMasks,
1652 &feature_sahf,
1653 &feature_lzcnt,
1654 &feature_mmx,
1655 &feature_movbe,
1656 &feature_nopl,
1657 &feature_pclmul,
1658 &feature_popcnt,
1659 &feature_prfchw,
1660 &feature_sse4a,
1661 &feature_ssse3,
1662 &feature_slowShld,
1663 &feature_x87,
1664 &feature_xsave,
1665 &feature_xsaveopt,
1666 },
1667};
1668
1669pub const cpu_c3 = Cpu{
1670 .name = "c3",
1671 .llvm_name = "c3",
1672 .subfeatures = &[_]*const Feature {
1673 &feature_mmx,
1674 &feature_dnow3,
1675 &feature_slowUnalignedMem16,
1676 &feature_x87,
1677 },
1678};
1679
1680pub const cpu_c32 = Cpu{
1681 .name = "c3-2",
1682 .llvm_name = "c3-2",
1683 .subfeatures = &[_]*const Feature {
1684 &feature_cmov,
1685 &feature_cx8,
1686 &feature_fxsr,
1687 &feature_mmx,
1688 &feature_sse,
1689 &feature_slowUnalignedMem16,
1690 &feature_x87,
1691 },
1692};
1693
1694pub const cpu_cannonlake = Cpu{
1695 .name = "cannonlake",
1696 .llvm_name = "cannonlake",
1697 .subfeatures = &[_]*const Feature {
1698 &feature_bit64,
1699 &feature_adx,
1700 &feature_sse,
1701 &feature_aes,
1702 &feature_avx,
1703 &feature_avx2,
1704 &feature_avx512f,
1705 &feature_bmi,
1706 &feature_bmi2,
1707 &feature_avx512bw,
1708 &feature_avx512cd,
1709 &feature_clflushopt,
1710 &feature_cmov,
1711 &feature_cx8,
1712 &feature_cx16,
1713 &feature_avx512dq,
1714 &feature_ermsb,
1715 &feature_f16c,
1716 &feature_fma,
1717 &feature_fsgsbase,
1718 &feature_fxsr,
1719 &feature_fastShldRotate,
1720 &feature_fastScalarFsqrt,
1721 &feature_fastVariableShuffle,
1722 &feature_fastVectorFsqrt,
1723 &feature_fastGather,
1724 &feature_avx512ifma,
1725 &feature_invpcid,
1726 &feature_sahf,
1727 &feature_lzcnt,
1728 &feature_mmx,
1729 &feature_movbe,
1730 &feature_macrofusion,
1731 &feature_mergeToThreewayBranch,
1732 &feature_nopl,
1733 &feature_pclmul,
1734 &feature_pku,
1735 &feature_popcnt,
1736 &feature_prfchw,
1737 &feature_prefer256Bit,
1738 &feature_rdrnd,
1739 &feature_rdseed,
1740 &feature_sgx,
1741 &feature_sha,
1742 &feature_sse42,
1743 &feature_slow3opsLea,
1744 &feature_idivqToDivl,
1745 &feature_avx512vbmi,
1746 &feature_avx512vl,
1747 &feature_x87,
1748 &feature_xsave,
1749 &feature_xsavec,
1750 &feature_xsaveopt,
1751 &feature_xsaves,
1752 },
1753};
1754
1755pub const cpu_cascadelake = Cpu{
1756 .name = "cascadelake",
1757 .llvm_name = "cascadelake",
1758 .subfeatures = &[_]*const Feature {
1759 &feature_bit64,
1760 &feature_adx,
1761 &feature_sse,
1762 &feature_aes,
1763 &feature_avx,
1764 &feature_avx2,
1765 &feature_avx512f,
1766 &feature_bmi,
1767 &feature_bmi2,
1768 &feature_avx512bw,
1769 &feature_avx512cd,
1770 &feature_clflushopt,
1771 &feature_clwb,
1772 &feature_cmov,
1773 &feature_cx8,
1774 &feature_cx16,
1775 &feature_avx512dq,
1776 &feature_ermsb,
1777 &feature_f16c,
1778 &feature_fma,
1779 &feature_fsgsbase,
1780 &feature_fxsr,
1781 &feature_fastShldRotate,
1782 &feature_fastScalarFsqrt,
1783 &feature_fastVariableShuffle,
1784 &feature_fastVectorFsqrt,
1785 &feature_fastGather,
1786 &feature_invpcid,
1787 &feature_sahf,
1788 &feature_lzcnt,
1789 &feature_mmx,
1790 &feature_movbe,
1791 &feature_macrofusion,
1792 &feature_mergeToThreewayBranch,
1793 &feature_nopl,
1794 &feature_pclmul,
1795 &feature_pku,
1796 &feature_popcnt,
1797 &feature_falseDepsPopcnt,
1798 &feature_prfchw,
1799 &feature_prefer256Bit,
1800 &feature_rdrnd,
1801 &feature_rdseed,
1802 &feature_sse42,
1803 &feature_slow3opsLea,
1804 &feature_idivqToDivl,
1805 &feature_avx512vl,
1806 &feature_avx512vnni,
1807 &feature_x87,
1808 &feature_xsave,
1809 &feature_xsavec,
1810 &feature_xsaveopt,
1811 &feature_xsaves,
1812 },
1813};
1814
1815pub const cpu_cooperlake = Cpu{
1816 .name = "cooperlake",
1817 .llvm_name = "cooperlake",
1818 .subfeatures = &[_]*const Feature {
1819 &feature_bit64,
1820 &feature_adx,
1821 &feature_sse,
1822 &feature_aes,
1823 &feature_avx,
1824 &feature_avx2,
1825 &feature_avx512f,
1826 &feature_avx512bf16,
1827 &feature_bmi,
1828 &feature_bmi2,
1829 &feature_avx512bw,
1830 &feature_avx512cd,
1831 &feature_clflushopt,
1832 &feature_clwb,
1833 &feature_cmov,
1834 &feature_cx8,
1835 &feature_cx16,
1836 &feature_avx512dq,
1837 &feature_ermsb,
1838 &feature_f16c,
1839 &feature_fma,
1840 &feature_fsgsbase,
1841 &feature_fxsr,
1842 &feature_fastShldRotate,
1843 &feature_fastScalarFsqrt,
1844 &feature_fastVariableShuffle,
1845 &feature_fastVectorFsqrt,
1846 &feature_fastGather,
1847 &feature_invpcid,
1848 &feature_sahf,
1849 &feature_lzcnt,
1850 &feature_mmx,
1851 &feature_movbe,
1852 &feature_macrofusion,
1853 &feature_mergeToThreewayBranch,
1854 &feature_nopl,
1855 &feature_pclmul,
1856 &feature_pku,
1857 &feature_popcnt,
1858 &feature_falseDepsPopcnt,
1859 &feature_prfchw,
1860 &feature_prefer256Bit,
1861 &feature_rdrnd,
1862 &feature_rdseed,
1863 &feature_sse42,
1864 &feature_slow3opsLea,
1865 &feature_idivqToDivl,
1866 &feature_avx512vl,
1867 &feature_avx512vnni,
1868 &feature_x87,
1869 &feature_xsave,
1870 &feature_xsavec,
1871 &feature_xsaveopt,
1872 &feature_xsaves,
1873 },
1874};
1875
1876pub const cpu_coreAvxI = Cpu{
1877 .name = "core-avx-i",
1878 .llvm_name = "core-avx-i",
1879 .subfeatures = &[_]*const Feature {
1880 &feature_bit64,
1881 &feature_sse,
1882 &feature_avx,
1883 &feature_cmov,
1884 &feature_cx8,
1885 &feature_cx16,
1886 &feature_f16c,
1887 &feature_fsgsbase,
1888 &feature_fxsr,
1889 &feature_fastShldRotate,
1890 &feature_fastScalarFsqrt,
1891 &feature_sahf,
1892 &feature_mmx,
1893 &feature_macrofusion,
1894 &feature_mergeToThreewayBranch,
1895 &feature_nopl,
1896 &feature_pclmul,
1897 &feature_popcnt,
1898 &feature_falseDepsPopcnt,
1899 &feature_rdrnd,
1900 &feature_sse42,
1901 &feature_slow3opsLea,
1902 &feature_idivqToDivl,
1903 &feature_slowUnalignedMem32,
1904 &feature_x87,
1905 &feature_xsave,
1906 &feature_xsaveopt,
1907 },
1908};
1909
1910pub const cpu_coreAvx2 = Cpu{
1911 .name = "core-avx2",
1912 .llvm_name = "core-avx2",
1913 .subfeatures = &[_]*const Feature {
1914 &feature_bit64,
1915 &feature_sse,
1916 &feature_avx,
1917 &feature_avx2,
1918 &feature_bmi,
1919 &feature_bmi2,
1920 &feature_cmov,
1921 &feature_cx8,
1922 &feature_cx16,
1923 &feature_ermsb,
1924 &feature_f16c,
1925 &feature_fma,
1926 &feature_fsgsbase,
1927 &feature_fxsr,
1928 &feature_fastShldRotate,
1929 &feature_fastScalarFsqrt,
1930 &feature_fastVariableShuffle,
1931 &feature_invpcid,
1932 &feature_sahf,
1933 &feature_lzcnt,
1934 &feature_falseDepsLzcntTzcnt,
1935 &feature_mmx,
1936 &feature_movbe,
1937 &feature_macrofusion,
1938 &feature_mergeToThreewayBranch,
1939 &feature_nopl,
1940 &feature_pclmul,
1941 &feature_popcnt,
1942 &feature_falseDepsPopcnt,
1943 &feature_rdrnd,
1944 &feature_sse42,
1945 &feature_slow3opsLea,
1946 &feature_idivqToDivl,
1947 &feature_x87,
1948 &feature_xsave,
1949 &feature_xsaveopt,
1950 },
1951};
1952
1953pub const cpu_core2 = Cpu{
1954 .name = "core2",
1955 .llvm_name = "core2",
1956 .subfeatures = &[_]*const Feature {
1957 &feature_bit64,
1958 &feature_cmov,
1959 &feature_cx8,
1960 &feature_cx16,
1961 &feature_fxsr,
1962 &feature_sahf,
1963 &feature_mmx,
1964 &feature_macrofusion,
1965 &feature_nopl,
1966 &feature_sse,
1967 &feature_ssse3,
1968 &feature_slowUnalignedMem16,
1969 &feature_x87,
1970 },
1971};
1972
1973pub const cpu_corei7 = Cpu{
1974 .name = "corei7",
1975 .llvm_name = "corei7",
1976 .subfeatures = &[_]*const Feature {
1977 &feature_bit64,
1978 &feature_cmov,
1979 &feature_cx8,
1980 &feature_cx16,
1981 &feature_fxsr,
1982 &feature_sahf,
1983 &feature_mmx,
1984 &feature_macrofusion,
1985 &feature_nopl,
1986 &feature_popcnt,
1987 &feature_sse,
1988 &feature_sse42,
1989 &feature_x87,
1990 },
1991};
1992
1993pub const cpu_corei7Avx = Cpu{
1994 .name = "corei7-avx",
1995 .llvm_name = "corei7-avx",
1996 .subfeatures = &[_]*const Feature {
1997 &feature_bit64,
1998 &feature_sse,
1999 &feature_avx,
2000 &feature_cmov,
2001 &feature_cx8,
2002 &feature_cx16,
2003 &feature_fxsr,
2004 &feature_fastShldRotate,
2005 &feature_fastScalarFsqrt,
2006 &feature_sahf,
2007 &feature_mmx,
2008 &feature_macrofusion,
2009 &feature_mergeToThreewayBranch,
2010 &feature_nopl,
2011 &feature_pclmul,
2012 &feature_popcnt,
2013 &feature_falseDepsPopcnt,
2014 &feature_sse42,
2015 &feature_slow3opsLea,
2016 &feature_idivqToDivl,
2017 &feature_slowUnalignedMem32,
2018 &feature_x87,
2019 &feature_xsave,
2020 &feature_xsaveopt,
2021 },
2022};
2023
2024pub const cpu_generic = Cpu{
2025 .name = "generic",
2026 .llvm_name = "generic",
2027 .subfeatures = &[_]*const Feature {
2028 &feature_cx8,
2029 &feature_slowUnalignedMem16,
2030 &feature_x87,
2031 },
2032};
2033
2034pub const cpu_geode = Cpu{
2035 .name = "geode",
2036 .llvm_name = "geode",
2037 .subfeatures = &[_]*const Feature {
2038 &feature_mmx,
2039 &feature_dnowa3,
2040 &feature_cx8,
2041 &feature_slowUnalignedMem16,
2042 &feature_x87,
2043 },
2044};
2045
2046pub const cpu_goldmont = Cpu{
2047 .name = "goldmont",
2048 .llvm_name = "goldmont",
2049 .subfeatures = &[_]*const Feature {
2050 &feature_bit64,
2051 &feature_sse,
2052 &feature_aes,
2053 &feature_clflushopt,
2054 &feature_cmov,
2055 &feature_cx8,
2056 &feature_cx16,
2057 &feature_fsgsbase,
2058 &feature_fxsr,
2059 &feature_sahf,
2060 &feature_mmx,
2061 &feature_movbe,
2062 &feature_nopl,
2063 &feature_pclmul,
2064 &feature_popcnt,
2065 &feature_falseDepsPopcnt,
2066 &feature_prfchw,
2067 &feature_rdrnd,
2068 &feature_rdseed,
2069 &feature_sha,
2070 &feature_sse42,
2071 &feature_ssse3,
2072 &feature_slowIncdec,
2073 &feature_slowLea,
2074 &feature_slowTwoMemOps,
2075 &feature_x87,
2076 &feature_xsave,
2077 &feature_xsavec,
2078 &feature_xsaveopt,
2079 &feature_xsaves,
2080 },
2081};
2082
2083pub const cpu_goldmontPlus = Cpu{
2084 .name = "goldmont-plus",
2085 .llvm_name = "goldmont-plus",
2086 .subfeatures = &[_]*const Feature {
2087 &feature_bit64,
2088 &feature_sse,
2089 &feature_aes,
2090 &feature_clflushopt,
2091 &feature_cmov,
2092 &feature_cx8,
2093 &feature_cx16,
2094 &feature_fsgsbase,
2095 &feature_fxsr,
2096 &feature_sahf,
2097 &feature_mmx,
2098 &feature_movbe,
2099 &feature_nopl,
2100 &feature_pclmul,
2101 &feature_popcnt,
2102 &feature_prfchw,
2103 &feature_ptwrite,
2104 &feature_rdpid,
2105 &feature_rdrnd,
2106 &feature_rdseed,
2107 &feature_sgx,
2108 &feature_sha,
2109 &feature_sse42,
2110 &feature_ssse3,
2111 &feature_slowIncdec,
2112 &feature_slowLea,
2113 &feature_slowTwoMemOps,
2114 &feature_x87,
2115 &feature_xsave,
2116 &feature_xsavec,
2117 &feature_xsaveopt,
2118 &feature_xsaves,
2119 },
2120};
2121
2122pub const cpu_haswell = Cpu{
2123 .name = "haswell",
2124 .llvm_name = "haswell",
2125 .subfeatures = &[_]*const Feature {
2126 &feature_bit64,
2127 &feature_sse,
2128 &feature_avx,
2129 &feature_avx2,
2130 &feature_bmi,
2131 &feature_bmi2,
2132 &feature_cmov,
2133 &feature_cx8,
2134 &feature_cx16,
2135 &feature_ermsb,
2136 &feature_f16c,
2137 &feature_fma,
2138 &feature_fsgsbase,
2139 &feature_fxsr,
2140 &feature_fastShldRotate,
2141 &feature_fastScalarFsqrt,
2142 &feature_fastVariableShuffle,
2143 &feature_invpcid,
2144 &feature_sahf,
2145 &feature_lzcnt,
2146 &feature_falseDepsLzcntTzcnt,
2147 &feature_mmx,
2148 &feature_movbe,
2149 &feature_macrofusion,
2150 &feature_mergeToThreewayBranch,
2151 &feature_nopl,
2152 &feature_pclmul,
2153 &feature_popcnt,
2154 &feature_falseDepsPopcnt,
2155 &feature_rdrnd,
2156 &feature_sse42,
2157 &feature_slow3opsLea,
2158 &feature_idivqToDivl,
2159 &feature_x87,
2160 &feature_xsave,
2161 &feature_xsaveopt,
2162 },
2163};
2164
2165pub const cpu_i386 = Cpu{
2166 .name = "i386",
2167 .llvm_name = "i386",
2168 .subfeatures = &[_]*const Feature {
2169 &feature_slowUnalignedMem16,
2170 &feature_x87,
2171 },
2172};
2173
2174pub const cpu_i486 = Cpu{
2175 .name = "i486",
2176 .llvm_name = "i486",
2177 .subfeatures = &[_]*const Feature {
2178 &feature_slowUnalignedMem16,
2179 &feature_x87,
2180 },
2181};
2182
2183pub const cpu_i586 = Cpu{
2184 .name = "i586",
2185 .llvm_name = "i586",
2186 .subfeatures = &[_]*const Feature {
2187 &feature_cx8,
2188 &feature_slowUnalignedMem16,
2189 &feature_x87,
2190 },
2191};
2192
2193pub const cpu_i686 = Cpu{
2194 .name = "i686",
2195 .llvm_name = "i686",
2196 .subfeatures = &[_]*const Feature {
2197 &feature_cmov,
2198 &feature_cx8,
2199 &feature_slowUnalignedMem16,
2200 &feature_x87,
2201 },
2202};
2203
2204pub const cpu_icelakeClient = Cpu{
2205 .name = "icelake-client",
2206 .llvm_name = "icelake-client",
2207 .subfeatures = &[_]*const Feature {
2208 &feature_bit64,
2209 &feature_adx,
2210 &feature_sse,
2211 &feature_aes,
2212 &feature_avx,
2213 &feature_avx2,
2214 &feature_avx512f,
2215 &feature_avx512bitalg,
2216 &feature_bmi,
2217 &feature_bmi2,
2218 &feature_avx512bw,
2219 &feature_avx512cd,
2220 &feature_clflushopt,
2221 &feature_clwb,
2222 &feature_cmov,
2223 &feature_cx8,
2224 &feature_cx16,
2225 &feature_avx512dq,
2226 &feature_ermsb,
2227 &feature_f16c,
2228 &feature_fma,
2229 &feature_fsgsbase,
2230 &feature_fxsr,
2231 &feature_fastShldRotate,
2232 &feature_fastScalarFsqrt,
2233 &feature_fastVariableShuffle,
2234 &feature_fastVectorFsqrt,
2235 &feature_gfni,
2236 &feature_fastGather,
2237 &feature_avx512ifma,
2238 &feature_invpcid,
2239 &feature_sahf,
2240 &feature_lzcnt,
2241 &feature_mmx,
2242 &feature_movbe,
2243 &feature_macrofusion,
2244 &feature_mergeToThreewayBranch,
2245 &feature_nopl,
2246 &feature_pclmul,
2247 &feature_pku,
2248 &feature_popcnt,
2249 &feature_prfchw,
2250 &feature_prefer256Bit,
2251 &feature_rdpid,
2252 &feature_rdrnd,
2253 &feature_rdseed,
2254 &feature_sgx,
2255 &feature_sha,
2256 &feature_sse42,
2257 &feature_slow3opsLea,
2258 &feature_idivqToDivl,
2259 &feature_vaes,
2260 &feature_avx512vbmi,
2261 &feature_avx512vbmi2,
2262 &feature_avx512vl,
2263 &feature_avx512vnni,
2264 &feature_vpclmulqdq,
2265 &feature_avx512vpopcntdq,
2266 &feature_x87,
2267 &feature_xsave,
2268 &feature_xsavec,
2269 &feature_xsaveopt,
2270 &feature_xsaves,
2271 },
2272};
2273
2274pub const cpu_icelakeServer = Cpu{
2275 .name = "icelake-server",
2276 .llvm_name = "icelake-server",
2277 .subfeatures = &[_]*const Feature {
2278 &feature_bit64,
2279 &feature_adx,
2280 &feature_sse,
2281 &feature_aes,
2282 &feature_avx,
2283 &feature_avx2,
2284 &feature_avx512f,
2285 &feature_avx512bitalg,
2286 &feature_bmi,
2287 &feature_bmi2,
2288 &feature_avx512bw,
2289 &feature_avx512cd,
2290 &feature_clflushopt,
2291 &feature_clwb,
2292 &feature_cmov,
2293 &feature_cx8,
2294 &feature_cx16,
2295 &feature_avx512dq,
2296 &feature_ermsb,
2297 &feature_f16c,
2298 &feature_fma,
2299 &feature_fsgsbase,
2300 &feature_fxsr,
2301 &feature_fastShldRotate,
2302 &feature_fastScalarFsqrt,
2303 &feature_fastVariableShuffle,
2304 &feature_fastVectorFsqrt,
2305 &feature_gfni,
2306 &feature_fastGather,
2307 &feature_avx512ifma,
2308 &feature_invpcid,
2309 &feature_sahf,
2310 &feature_lzcnt,
2311 &feature_mmx,
2312 &feature_movbe,
2313 &feature_macrofusion,
2314 &feature_mergeToThreewayBranch,
2315 &feature_nopl,
2316 &feature_pclmul,
2317 &feature_pconfig,
2318 &feature_pku,
2319 &feature_popcnt,
2320 &feature_prfchw,
2321 &feature_prefer256Bit,
2322 &feature_rdpid,
2323 &feature_rdrnd,
2324 &feature_rdseed,
2325 &feature_sgx,
2326 &feature_sha,
2327 &feature_sse42,
2328 &feature_slow3opsLea,
2329 &feature_idivqToDivl,
2330 &feature_vaes,
2331 &feature_avx512vbmi,
2332 &feature_avx512vbmi2,
2333 &feature_avx512vl,
2334 &feature_avx512vnni,
2335 &feature_vpclmulqdq,
2336 &feature_avx512vpopcntdq,
2337 &feature_wbnoinvd,
2338 &feature_x87,
2339 &feature_xsave,
2340 &feature_xsavec,
2341 &feature_xsaveopt,
2342 &feature_xsaves,
2343 },
2344};
2345
2346pub const cpu_ivybridge = Cpu{
2347 .name = "ivybridge",
2348 .llvm_name = "ivybridge",
2349 .subfeatures = &[_]*const Feature {
2350 &feature_bit64,
2351 &feature_sse,
2352 &feature_avx,
2353 &feature_cmov,
2354 &feature_cx8,
2355 &feature_cx16,
2356 &feature_f16c,
2357 &feature_fsgsbase,
2358 &feature_fxsr,
2359 &feature_fastShldRotate,
2360 &feature_fastScalarFsqrt,
2361 &feature_sahf,
2362 &feature_mmx,
2363 &feature_macrofusion,
2364 &feature_mergeToThreewayBranch,
2365 &feature_nopl,
2366 &feature_pclmul,
2367 &feature_popcnt,
2368 &feature_falseDepsPopcnt,
2369 &feature_rdrnd,
2370 &feature_sse42,
2371 &feature_slow3opsLea,
2372 &feature_idivqToDivl,
2373 &feature_slowUnalignedMem32,
2374 &feature_x87,
2375 &feature_xsave,
2376 &feature_xsaveopt,
2377 },
2378};
2379
2380pub const cpu_k6 = Cpu{
2381 .name = "k6",
2382 .llvm_name = "k6",
2383 .subfeatures = &[_]*const Feature {
2384 &feature_cx8,
2385 &feature_mmx,
2386 &feature_slowUnalignedMem16,
2387 &feature_x87,
2388 },
2389};
2390
2391pub const cpu_k62 = Cpu{
2392 .name = "k6-2",
2393 .llvm_name = "k6-2",
2394 .subfeatures = &[_]*const Feature {
2395 &feature_mmx,
2396 &feature_dnow3,
2397 &feature_cx8,
2398 &feature_slowUnalignedMem16,
2399 &feature_x87,
2400 },
2401};
2402
2403pub const cpu_k63 = Cpu{
2404 .name = "k6-3",
2405 .llvm_name = "k6-3",
2406 .subfeatures = &[_]*const Feature {
2407 &feature_mmx,
2408 &feature_dnow3,
2409 &feature_cx8,
2410 &feature_slowUnalignedMem16,
2411 &feature_x87,
2412 },
2413};
2414
2415pub const cpu_k8 = Cpu{
2416 .name = "k8",
2417 .llvm_name = "k8",
2418 .subfeatures = &[_]*const Feature {
2419 &feature_mmx,
2420 &feature_dnowa3,
2421 &feature_bit64,
2422 &feature_cmov,
2423 &feature_cx8,
2424 &feature_fxsr,
2425 &feature_fastScalarShiftMasks,
2426 &feature_nopl,
2427 &feature_sse,
2428 &feature_sse2,
2429 &feature_slowShld,
2430 &feature_slowUnalignedMem16,
2431 &feature_x87,
2432 },
2433};
2434
2435pub const cpu_k8Sse3 = Cpu{
2436 .name = "k8-sse3",
2437 .llvm_name = "k8-sse3",
2438 .subfeatures = &[_]*const Feature {
2439 &feature_mmx,
2440 &feature_dnowa3,
2441 &feature_bit64,
2442 &feature_cmov,
2443 &feature_cx8,
2444 &feature_cx16,
2445 &feature_fxsr,
2446 &feature_fastScalarShiftMasks,
2447 &feature_nopl,
2448 &feature_sse,
2449 &feature_sse3,
2450 &feature_slowShld,
2451 &feature_slowUnalignedMem16,
2452 &feature_x87,
2453 },
2454};
2455
2456pub const cpu_knl = Cpu{
2457 .name = "knl",
2458 .llvm_name = "knl",
2459 .subfeatures = &[_]*const Feature {
2460 &feature_bit64,
2461 &feature_adx,
2462 &feature_sse,
2463 &feature_aes,
2464 &feature_avx512f,
2465 &feature_bmi,
2466 &feature_bmi2,
2467 &feature_avx512cd,
2468 &feature_cmov,
2469 &feature_cx8,
2470 &feature_cx16,
2471 &feature_avx512er,
2472 &feature_f16c,
2473 &feature_fma,
2474 &feature_fsgsbase,
2475 &feature_fxsr,
2476 &feature_fastPartialYmmOrZmmWrite,
2477 &feature_fastGather,
2478 &feature_sahf,
2479 &feature_lzcnt,
2480 &feature_mmx,
2481 &feature_movbe,
2482 &feature_nopl,
2483 &feature_pclmul,
2484 &feature_avx512pf,
2485 &feature_popcnt,
2486 &feature_prefetchwt1,
2487 &feature_prfchw,
2488 &feature_rdrnd,
2489 &feature_rdseed,
2490 &feature_slow3opsLea,
2491 &feature_idivqToDivl,
2492 &feature_slowIncdec,
2493 &feature_slowPmaddwd,
2494 &feature_slowTwoMemOps,
2495 &feature_x87,
2496 &feature_xsave,
2497 &feature_xsaveopt,
2498 },
2499};
2500
2501pub const cpu_knm = Cpu{
2502 .name = "knm",
2503 .llvm_name = "knm",
2504 .subfeatures = &[_]*const Feature {
2505 &feature_bit64,
2506 &feature_adx,
2507 &feature_sse,
2508 &feature_aes,
2509 &feature_avx512f,
2510 &feature_bmi,
2511 &feature_bmi2,
2512 &feature_avx512cd,
2513 &feature_cmov,
2514 &feature_cx8,
2515 &feature_cx16,
2516 &feature_avx512er,
2517 &feature_f16c,
2518 &feature_fma,
2519 &feature_fsgsbase,
2520 &feature_fxsr,
2521 &feature_fastPartialYmmOrZmmWrite,
2522 &feature_fastGather,
2523 &feature_sahf,
2524 &feature_lzcnt,
2525 &feature_mmx,
2526 &feature_movbe,
2527 &feature_nopl,
2528 &feature_pclmul,
2529 &feature_avx512pf,
2530 &feature_popcnt,
2531 &feature_prefetchwt1,
2532 &feature_prfchw,
2533 &feature_rdrnd,
2534 &feature_rdseed,
2535 &feature_slow3opsLea,
2536 &feature_idivqToDivl,
2537 &feature_slowIncdec,
2538 &feature_slowPmaddwd,
2539 &feature_slowTwoMemOps,
2540 &feature_avx512vpopcntdq,
2541 &feature_x87,
2542 &feature_xsave,
2543 &feature_xsaveopt,
2544 },
2545};
2546
2547pub const cpu_lakemont = Cpu{
2548 .name = "lakemont",
2549 .llvm_name = "lakemont",
2550 .subfeatures = &[_]*const Feature {
2551 },
2552};
2553
2554pub const cpu_nehalem = Cpu{
2555 .name = "nehalem",
2556 .llvm_name = "nehalem",
2557 .subfeatures = &[_]*const Feature {
2558 &feature_bit64,
2559 &feature_cmov,
2560 &feature_cx8,
2561 &feature_cx16,
2562 &feature_fxsr,
2563 &feature_sahf,
2564 &feature_mmx,
2565 &feature_macrofusion,
2566 &feature_nopl,
2567 &feature_popcnt,
2568 &feature_sse,
2569 &feature_sse42,
2570 &feature_x87,
2571 },
2572};
2573
2574pub const cpu_nocona = Cpu{
2575 .name = "nocona",
2576 .llvm_name = "nocona",
2577 .subfeatures = &[_]*const Feature {
2578 &feature_bit64,
2579 &feature_cmov,
2580 &feature_cx8,
2581 &feature_cx16,
2582 &feature_fxsr,
2583 &feature_mmx,
2584 &feature_nopl,
2585 &feature_sse,
2586 &feature_sse3,
2587 &feature_slowUnalignedMem16,
2588 &feature_x87,
2589 },
2590};
2591
2592pub const cpu_opteron = Cpu{
2593 .name = "opteron",
2594 .llvm_name = "opteron",
2595 .subfeatures = &[_]*const Feature {
2596 &feature_mmx,
2597 &feature_dnowa3,
2598 &feature_bit64,
2599 &feature_cmov,
2600 &feature_cx8,
2601 &feature_fxsr,
2602 &feature_fastScalarShiftMasks,
2603 &feature_nopl,
2604 &feature_sse,
2605 &feature_sse2,
2606 &feature_slowShld,
2607 &feature_slowUnalignedMem16,
2608 &feature_x87,
2609 },
2610};
2611
2612pub const cpu_opteronSse3 = Cpu{
2613 .name = "opteron-sse3",
2614 .llvm_name = "opteron-sse3",
2615 .subfeatures = &[_]*const Feature {
2616 &feature_mmx,
2617 &feature_dnowa3,
2618 &feature_bit64,
2619 &feature_cmov,
2620 &feature_cx8,
2621 &feature_cx16,
2622 &feature_fxsr,
2623 &feature_fastScalarShiftMasks,
2624 &feature_nopl,
2625 &feature_sse,
2626 &feature_sse3,
2627 &feature_slowShld,
2628 &feature_slowUnalignedMem16,
2629 &feature_x87,
2630 },
2631};
2632
2633pub const cpu_penryn = Cpu{
2634 .name = "penryn",
2635 .llvm_name = "penryn",
2636 .subfeatures = &[_]*const Feature {
2637 &feature_bit64,
2638 &feature_cmov,
2639 &feature_cx8,
2640 &feature_cx16,
2641 &feature_fxsr,
2642 &feature_sahf,
2643 &feature_mmx,
2644 &feature_macrofusion,
2645 &feature_nopl,
2646 &feature_sse,
2647 &feature_sse41,
2648 &feature_slowUnalignedMem16,
2649 &feature_x87,
2650 },
2651};
2652
2653pub const cpu_pentium = Cpu{
2654 .name = "pentium",
2655 .llvm_name = "pentium",
2656 .subfeatures = &[_]*const Feature {
2657 &feature_cx8,
2658 &feature_slowUnalignedMem16,
2659 &feature_x87,
2660 },
2661};
2662
2663pub const cpu_pentiumM = Cpu{
2664 .name = "pentium-m",
2665 .llvm_name = "pentium-m",
2666 .subfeatures = &[_]*const Feature {
2667 &feature_cmov,
2668 &feature_cx8,
2669 &feature_fxsr,
2670 &feature_mmx,
2671 &feature_nopl,
2672 &feature_sse,
2673 &feature_sse2,
2674 &feature_slowUnalignedMem16,
2675 &feature_x87,
2676 },
2677};
2678
2679pub const cpu_pentiumMmx = Cpu{
2680 .name = "pentium-mmx",
2681 .llvm_name = "pentium-mmx",
2682 .subfeatures = &[_]*const Feature {
2683 &feature_cx8,
2684 &feature_mmx,
2685 &feature_slowUnalignedMem16,
2686 &feature_x87,
2687 },
2688};
2689
2690pub const cpu_pentium2 = Cpu{
2691 .name = "pentium2",
2692 .llvm_name = "pentium2",
2693 .subfeatures = &[_]*const Feature {
2694 &feature_cmov,
2695 &feature_cx8,
2696 &feature_fxsr,
2697 &feature_mmx,
2698 &feature_nopl,
2699 &feature_slowUnalignedMem16,
2700 &feature_x87,
2701 },
2702};
2703
2704pub const cpu_pentium3 = Cpu{
2705 .name = "pentium3",
2706 .llvm_name = "pentium3",
2707 .subfeatures = &[_]*const Feature {
2708 &feature_cmov,
2709 &feature_cx8,
2710 &feature_fxsr,
2711 &feature_mmx,
2712 &feature_nopl,
2713 &feature_sse,
2714 &feature_slowUnalignedMem16,
2715 &feature_x87,
2716 },
2717};
2718
2719pub const cpu_pentium3m = Cpu{
2720 .name = "pentium3m",
2721 .llvm_name = "pentium3m",
2722 .subfeatures = &[_]*const Feature {
2723 &feature_cmov,
2724 &feature_cx8,
2725 &feature_fxsr,
2726 &feature_mmx,
2727 &feature_nopl,
2728 &feature_sse,
2729 &feature_slowUnalignedMem16,
2730 &feature_x87,
2731 },
2732};
2733
2734pub const cpu_pentium4 = Cpu{
2735 .name = "pentium4",
2736 .llvm_name = "pentium4",
2737 .subfeatures = &[_]*const Feature {
2738 &feature_cmov,
2739 &feature_cx8,
2740 &feature_fxsr,
2741 &feature_mmx,
2742 &feature_nopl,
2743 &feature_sse,
2744 &feature_sse2,
2745 &feature_slowUnalignedMem16,
2746 &feature_x87,
2747 },
2748};
2749
2750pub const cpu_pentium4m = Cpu{
2751 .name = "pentium4m",
2752 .llvm_name = "pentium4m",
2753 .subfeatures = &[_]*const Feature {
2754 &feature_cmov,
2755 &feature_cx8,
2756 &feature_fxsr,
2757 &feature_mmx,
2758 &feature_nopl,
2759 &feature_sse,
2760 &feature_sse2,
2761 &feature_slowUnalignedMem16,
2762 &feature_x87,
2763 },
2764};
2765
2766pub const cpu_pentiumpro = Cpu{
2767 .name = "pentiumpro",
2768 .llvm_name = "pentiumpro",
2769 .subfeatures = &[_]*const Feature {
2770 &feature_cmov,
2771 &feature_cx8,
2772 &feature_nopl,
2773 &feature_slowUnalignedMem16,
2774 &feature_x87,
2775 },
2776};
2777
2778pub const cpu_prescott = Cpu{
2779 .name = "prescott",
2780 .llvm_name = "prescott",
2781 .subfeatures = &[_]*const Feature {
2782 &feature_cmov,
2783 &feature_cx8,
2784 &feature_fxsr,
2785 &feature_mmx,
2786 &feature_nopl,
2787 &feature_sse,
2788 &feature_sse3,
2789 &feature_slowUnalignedMem16,
2790 &feature_x87,
2791 },
2792};
2793
2794pub const cpu_sandybridge = Cpu{
2795 .name = "sandybridge",
2796 .llvm_name = "sandybridge",
2797 .subfeatures = &[_]*const Feature {
2798 &feature_bit64,
2799 &feature_sse,
2800 &feature_avx,
2801 &feature_cmov,
2802 &feature_cx8,
2803 &feature_cx16,
2804 &feature_fxsr,
2805 &feature_fastShldRotate,
2806 &feature_fastScalarFsqrt,
2807 &feature_sahf,
2808 &feature_mmx,
2809 &feature_macrofusion,
2810 &feature_mergeToThreewayBranch,
2811 &feature_nopl,
2812 &feature_pclmul,
2813 &feature_popcnt,
2814 &feature_falseDepsPopcnt,
2815 &feature_sse42,
2816 &feature_slow3opsLea,
2817 &feature_idivqToDivl,
2818 &feature_slowUnalignedMem32,
2819 &feature_x87,
2820 &feature_xsave,
2821 &feature_xsaveopt,
2822 },
2823};
2824
2825pub const cpu_silvermont = Cpu{
2826 .name = "silvermont",
2827 .llvm_name = "silvermont",
2828 .subfeatures = &[_]*const Feature {
2829 &feature_bit64,
2830 &feature_cmov,
2831 &feature_cx8,
2832 &feature_cx16,
2833 &feature_fxsr,
2834 &feature_sahf,
2835 &feature_mmx,
2836 &feature_movbe,
2837 &feature_nopl,
2838 &feature_sse,
2839 &feature_pclmul,
2840 &feature_popcnt,
2841 &feature_falseDepsPopcnt,
2842 &feature_prfchw,
2843 &feature_rdrnd,
2844 &feature_sse42,
2845 &feature_ssse3,
2846 &feature_idivqToDivl,
2847 &feature_slowIncdec,
2848 &feature_slowLea,
2849 &feature_slowPmulld,
2850 &feature_slowTwoMemOps,
2851 &feature_x87,
2852 },
2853};
2854
2855pub const cpu_skx = Cpu{
2856 .name = "skx",
2857 .llvm_name = "skx",
2858 .subfeatures = &[_]*const Feature {
2859 &feature_bit64,
2860 &feature_adx,
2861 &feature_sse,
2862 &feature_aes,
2863 &feature_avx,
2864 &feature_avx2,
2865 &feature_avx512f,
2866 &feature_bmi,
2867 &feature_bmi2,
2868 &feature_avx512bw,
2869 &feature_avx512cd,
2870 &feature_clflushopt,
2871 &feature_clwb,
2872 &feature_cmov,
2873 &feature_cx8,
2874 &feature_cx16,
2875 &feature_avx512dq,
2876 &feature_ermsb,
2877 &feature_f16c,
2878 &feature_fma,
2879 &feature_fsgsbase,
2880 &feature_fxsr,
2881 &feature_fastShldRotate,
2882 &feature_fastScalarFsqrt,
2883 &feature_fastVariableShuffle,
2884 &feature_fastVectorFsqrt,
2885 &feature_fastGather,
2886 &feature_invpcid,
2887 &feature_sahf,
2888 &feature_lzcnt,
2889 &feature_mmx,
2890 &feature_movbe,
2891 &feature_macrofusion,
2892 &feature_mergeToThreewayBranch,
2893 &feature_nopl,
2894 &feature_pclmul,
2895 &feature_pku,
2896 &feature_popcnt,
2897 &feature_falseDepsPopcnt,
2898 &feature_prfchw,
2899 &feature_prefer256Bit,
2900 &feature_rdrnd,
2901 &feature_rdseed,
2902 &feature_sse42,
2903 &feature_slow3opsLea,
2904 &feature_idivqToDivl,
2905 &feature_avx512vl,
2906 &feature_x87,
2907 &feature_xsave,
2908 &feature_xsavec,
2909 &feature_xsaveopt,
2910 &feature_xsaves,
2911 },
2912};
2913
2914pub const cpu_skylake = Cpu{
2915 .name = "skylake",
2916 .llvm_name = "skylake",
2917 .subfeatures = &[_]*const Feature {
2918 &feature_bit64,
2919 &feature_adx,
2920 &feature_sse,
2921 &feature_aes,
2922 &feature_avx,
2923 &feature_avx2,
2924 &feature_bmi,
2925 &feature_bmi2,
2926 &feature_clflushopt,
2927 &feature_cmov,
2928 &feature_cx8,
2929 &feature_cx16,
2930 &feature_ermsb,
2931 &feature_f16c,
2932 &feature_fma,
2933 &feature_fsgsbase,
2934 &feature_fxsr,
2935 &feature_fastShldRotate,
2936 &feature_fastScalarFsqrt,
2937 &feature_fastVariableShuffle,
2938 &feature_fastVectorFsqrt,
2939 &feature_fastGather,
2940 &feature_invpcid,
2941 &feature_sahf,
2942 &feature_lzcnt,
2943 &feature_mmx,
2944 &feature_movbe,
2945 &feature_macrofusion,
2946 &feature_mergeToThreewayBranch,
2947 &feature_nopl,
2948 &feature_pclmul,
2949 &feature_popcnt,
2950 &feature_falseDepsPopcnt,
2951 &feature_prfchw,
2952 &feature_rdrnd,
2953 &feature_rdseed,
2954 &feature_sgx,
2955 &feature_sse42,
2956 &feature_slow3opsLea,
2957 &feature_idivqToDivl,
2958 &feature_x87,
2959 &feature_xsave,
2960 &feature_xsavec,
2961 &feature_xsaveopt,
2962 &feature_xsaves,
2963 },
2964};
2965
2966pub const cpu_skylakeAvx512 = Cpu{
2967 .name = "skylake-avx512",
2968 .llvm_name = "skylake-avx512",
2969 .subfeatures = &[_]*const Feature {
2970 &feature_bit64,
2971 &feature_adx,
2972 &feature_sse,
2973 &feature_aes,
2974 &feature_avx,
2975 &feature_avx2,
2976 &feature_avx512f,
2977 &feature_bmi,
2978 &feature_bmi2,
2979 &feature_avx512bw,
2980 &feature_avx512cd,
2981 &feature_clflushopt,
2982 &feature_clwb,
2983 &feature_cmov,
2984 &feature_cx8,
2985 &feature_cx16,
2986 &feature_avx512dq,
2987 &feature_ermsb,
2988 &feature_f16c,
2989 &feature_fma,
2990 &feature_fsgsbase,
2991 &feature_fxsr,
2992 &feature_fastShldRotate,
2993 &feature_fastScalarFsqrt,
2994 &feature_fastVariableShuffle,
2995 &feature_fastVectorFsqrt,
2996 &feature_fastGather,
2997 &feature_invpcid,
2998 &feature_sahf,
2999 &feature_lzcnt,
3000 &feature_mmx,
3001 &feature_movbe,
3002 &feature_macrofusion,
3003 &feature_mergeToThreewayBranch,
3004 &feature_nopl,
3005 &feature_pclmul,
3006 &feature_pku,
3007 &feature_popcnt,
3008 &feature_falseDepsPopcnt,
3009 &feature_prfchw,
3010 &feature_prefer256Bit,
3011 &feature_rdrnd,
3012 &feature_rdseed,
3013 &feature_sse42,
3014 &feature_slow3opsLea,
3015 &feature_idivqToDivl,
3016 &feature_avx512vl,
3017 &feature_x87,
3018 &feature_xsave,
3019 &feature_xsavec,
3020 &feature_xsaveopt,
3021 &feature_xsaves,
3022 },
3023};
3024
3025pub const cpu_slm = Cpu{
3026 .name = "slm",
3027 .llvm_name = "slm",
3028 .subfeatures = &[_]*const Feature {
3029 &feature_bit64,
3030 &feature_cmov,
3031 &feature_cx8,
3032 &feature_cx16,
3033 &feature_fxsr,
3034 &feature_sahf,
3035 &feature_mmx,
3036 &feature_movbe,
3037 &feature_nopl,
3038 &feature_sse,
3039 &feature_pclmul,
3040 &feature_popcnt,
3041 &feature_falseDepsPopcnt,
3042 &feature_prfchw,
3043 &feature_rdrnd,
3044 &feature_sse42,
3045 &feature_ssse3,
3046 &feature_idivqToDivl,
3047 &feature_slowIncdec,
3048 &feature_slowLea,
3049 &feature_slowPmulld,
3050 &feature_slowTwoMemOps,
3051 &feature_x87,
3052 },
3053};
3054
3055pub const cpu_tigerlake = Cpu{
3056 .name = "tigerlake",
3057 .llvm_name = "tigerlake",
3058 .subfeatures = &[_]*const Feature {
3059 &feature_bit64,
3060 &feature_adx,
3061 &feature_sse,
3062 &feature_aes,
3063 &feature_avx,
3064 &feature_avx2,
3065 &feature_avx512f,
3066 &feature_avx512bitalg,
3067 &feature_bmi,
3068 &feature_bmi2,
3069 &feature_avx512bw,
3070 &feature_avx512cd,
3071 &feature_clflushopt,
3072 &feature_clwb,
3073 &feature_cmov,
3074 &feature_cx8,
3075 &feature_cx16,
3076 &feature_avx512dq,
3077 &feature_ermsb,
3078 &feature_f16c,
3079 &feature_fma,
3080 &feature_fsgsbase,
3081 &feature_fxsr,
3082 &feature_fastShldRotate,
3083 &feature_fastScalarFsqrt,
3084 &feature_fastVariableShuffle,
3085 &feature_fastVectorFsqrt,
3086 &feature_gfni,
3087 &feature_fastGather,
3088 &feature_avx512ifma,
3089 &feature_invpcid,
3090 &feature_sahf,
3091 &feature_lzcnt,
3092 &feature_mmx,
3093 &feature_movbe,
3094 &feature_movdir64b,
3095 &feature_movdiri,
3096 &feature_macrofusion,
3097 &feature_mergeToThreewayBranch,
3098 &feature_nopl,
3099 &feature_pclmul,
3100 &feature_pku,
3101 &feature_popcnt,
3102 &feature_prfchw,
3103 &feature_prefer256Bit,
3104 &feature_rdpid,
3105 &feature_rdrnd,
3106 &feature_rdseed,
3107 &feature_sgx,
3108 &feature_sha,
3109 &feature_shstk,
3110 &feature_sse42,
3111 &feature_slow3opsLea,
3112 &feature_idivqToDivl,
3113 &feature_vaes,
3114 &feature_avx512vbmi,
3115 &feature_avx512vbmi2,
3116 &feature_avx512vl,
3117 &feature_avx512vnni,
3118 &feature_avx512vp2intersect,
3119 &feature_vpclmulqdq,
3120 &feature_avx512vpopcntdq,
3121 &feature_x87,
3122 &feature_xsave,
3123 &feature_xsavec,
3124 &feature_xsaveopt,
3125 &feature_xsaves,
3126 },
3127};
3128
3129pub const cpu_tremont = Cpu{
3130 .name = "tremont",
3131 .llvm_name = "tremont",
3132 .subfeatures = &[_]*const Feature {
3133 &feature_bit64,
3134 &feature_sse,
3135 &feature_aes,
3136 &feature_cldemote,
3137 &feature_clflushopt,
3138 &feature_cmov,
3139 &feature_cx8,
3140 &feature_cx16,
3141 &feature_fsgsbase,
3142 &feature_fxsr,
3143 &feature_gfni,
3144 &feature_sahf,
3145 &feature_mmx,
3146 &feature_movbe,
3147 &feature_movdir64b,
3148 &feature_movdiri,
3149 &feature_nopl,
3150 &feature_pclmul,
3151 &feature_popcnt,
3152 &feature_prfchw,
3153 &feature_ptwrite,
3154 &feature_rdpid,
3155 &feature_rdrnd,
3156 &feature_rdseed,
3157 &feature_sgx,
3158 &feature_sha,
3159 &feature_sse42,
3160 &feature_ssse3,
3161 &feature_slowIncdec,
3162 &feature_slowLea,
3163 &feature_slowTwoMemOps,
3164 &feature_waitpkg,
3165 &feature_x87,
3166 &feature_xsave,
3167 &feature_xsavec,
3168 &feature_xsaveopt,
3169 &feature_xsaves,
3170 },
3171};
3172
3173pub const cpu_westmere = Cpu{
3174 .name = "westmere",
3175 .llvm_name = "westmere",
3176 .subfeatures = &[_]*const Feature {
3177 &feature_bit64,
3178 &feature_cmov,
3179 &feature_cx8,
3180 &feature_cx16,
3181 &feature_fxsr,
3182 &feature_sahf,
3183 &feature_mmx,
3184 &feature_macrofusion,
3185 &feature_nopl,
3186 &feature_sse,
3187 &feature_pclmul,
3188 &feature_popcnt,
3189 &feature_sse42,
3190 &feature_x87,
3191 },
3192};
3193
3194pub const cpu_winchipC6 = Cpu{
3195 .name = "winchip-c6",
3196 .llvm_name = "winchip-c6",
3197 .subfeatures = &[_]*const Feature {
3198 &feature_mmx,
3199 &feature_slowUnalignedMem16,
3200 &feature_x87,
3201 },
3202};
3203
3204pub const cpu_winchip2 = Cpu{
3205 .name = "winchip2",
3206 .llvm_name = "winchip2",
3207 .subfeatures = &[_]*const Feature {
3208 &feature_mmx,
3209 &feature_dnow3,
3210 &feature_slowUnalignedMem16,
3211 &feature_x87,
3212 },
3213};
3214
3215pub const cpu_x8664 = Cpu{
3216 .name = "x86-64",
3217 .llvm_name = "x86-64",
3218 .subfeatures = &[_]*const Feature {
3219 &feature_bit64,
3220 &feature_cmov,
3221 &feature_cx8,
3222 &feature_fxsr,
3223 &feature_mmx,
3224 &feature_macrofusion,
3225 &feature_nopl,
3226 &feature_sse,
3227 &feature_sse2,
3228 &feature_slow3opsLea,
3229 &feature_slowIncdec,
3230 &feature_x87,
3231 },
3232};
3233
3234pub const cpu_yonah = Cpu{
3235 .name = "yonah",
3236 .llvm_name = "yonah",
3237 .subfeatures = &[_]*const Feature {
3238 &feature_cmov,
3239 &feature_cx8,
3240 &feature_fxsr,
3241 &feature_mmx,
3242 &feature_nopl,
3243 &feature_sse,
3244 &feature_sse3,
3245 &feature_slowUnalignedMem16,
3246 &feature_x87,
3247 },
3248};
3249
3250pub const cpu_znver1 = Cpu{
3251 .name = "znver1",
3252 .llvm_name = "znver1",
3253 .subfeatures = &[_]*const Feature {
3254 &feature_bit64,
3255 &feature_adx,
3256 &feature_sse,
3257 &feature_aes,
3258 &feature_avx2,
3259 &feature_bmi,
3260 &feature_bmi2,
3261 &feature_branchfusion,
3262 &feature_clflushopt,
3263 &feature_clzero,
3264 &feature_cmov,
3265 &feature_cx8,
3266 &feature_cx16,
3267 &feature_f16c,
3268 &feature_fma,
3269 &feature_fsgsbase,
3270 &feature_fxsr,
3271 &feature_fast15bytenop,
3272 &feature_fastBextr,
3273 &feature_fastLzcnt,
3274 &feature_fastScalarShiftMasks,
3275 &feature_sahf,
3276 &feature_lzcnt,
3277 &feature_mmx,
3278 &feature_movbe,
3279 &feature_mwaitx,
3280 &feature_nopl,
3281 &feature_pclmul,
3282 &feature_popcnt,
3283 &feature_prfchw,
3284 &feature_rdrnd,
3285 &feature_rdseed,
3286 &feature_sha,
3287 &feature_sse4a,
3288 &feature_slowShld,
3289 &feature_x87,
3290 &feature_xsave,
3291 &feature_xsavec,
3292 &feature_xsaveopt,
3293 &feature_xsaves,
3294 },
3295};
3296
3297pub const cpu_znver2 = Cpu{
3298 .name = "znver2",
3299 .llvm_name = "znver2",
3300 .subfeatures = &[_]*const Feature {
3301 &feature_bit64,
3302 &feature_adx,
3303 &feature_sse,
3304 &feature_aes,
3305 &feature_avx2,
3306 &feature_bmi,
3307 &feature_bmi2,
3308 &feature_branchfusion,
3309 &feature_clflushopt,
3310 &feature_clwb,
3311 &feature_clzero,
3312 &feature_cmov,
3313 &feature_cx8,
3314 &feature_cx16,
3315 &feature_f16c,
3316 &feature_fma,
3317 &feature_fsgsbase,
3318 &feature_fxsr,
3319 &feature_fast15bytenop,
3320 &feature_fastBextr,
3321 &feature_fastLzcnt,
3322 &feature_fastScalarShiftMasks,
3323 &feature_sahf,
3324 &feature_lzcnt,
3325 &feature_mmx,
3326 &feature_movbe,
3327 &feature_mwaitx,
3328 &feature_nopl,
3329 &feature_pclmul,
3330 &feature_popcnt,
3331 &feature_prfchw,
3332 &feature_rdpid,
3333 &feature_rdrnd,
3334 &feature_rdseed,
3335 &feature_sha,
3336 &feature_sse4a,
3337 &feature_slowShld,
3338 &feature_wbnoinvd,
3339 &feature_x87,
3340 &feature_xsave,
3341 &feature_xsavec,
3342 &feature_xsaveopt,
3343 &feature_xsaves,
3344 },
3345};
3346
3347pub const cpus = &[_]*const Cpu {
3348 &cpu_amdfam10,
3349 &cpu_athlon,
3350 &cpu_athlon4,
3351 &cpu_athlonFx,
3352 &cpu_athlonMp,
3353 &cpu_athlonTbird,
3354 &cpu_athlonXp,
3355 &cpu_athlon64,
3356 &cpu_athlon64Sse3,
3357 &cpu_atom,
3358 &cpu_barcelona,
3359 &cpu_bdver1,
3360 &cpu_bdver2,
3361 &cpu_bdver3,
3362 &cpu_bdver4,
3363 &cpu_bonnell,
3364 &cpu_broadwell,
3365 &cpu_btver1,
3366 &cpu_btver2,
3367 &cpu_c3,
3368 &cpu_c32,
3369 &cpu_cannonlake,
3370 &cpu_cascadelake,
3371 &cpu_cooperlake,
3372 &cpu_coreAvxI,
3373 &cpu_coreAvx2,
3374 &cpu_core2,
3375 &cpu_corei7,
3376 &cpu_corei7Avx,
3377 &cpu_generic,
3378 &cpu_geode,
3379 &cpu_goldmont,
3380 &cpu_goldmontPlus,
3381 &cpu_haswell,
3382 &cpu_i386,
3383 &cpu_i486,
3384 &cpu_i586,
3385 &cpu_i686,
3386 &cpu_icelakeClient,
3387 &cpu_icelakeServer,
3388 &cpu_ivybridge,
3389 &cpu_k6,
3390 &cpu_k62,
3391 &cpu_k63,
3392 &cpu_k8,
3393 &cpu_k8Sse3,
3394 &cpu_knl,
3395 &cpu_knm,
3396 &cpu_lakemont,
3397 &cpu_nehalem,
3398 &cpu_nocona,
3399 &cpu_opteron,
3400 &cpu_opteronSse3,
3401 &cpu_penryn,
3402 &cpu_pentium,
3403 &cpu_pentiumM,
3404 &cpu_pentiumMmx,
3405 &cpu_pentium2,
3406 &cpu_pentium3,
3407 &cpu_pentium3m,
3408 &cpu_pentium4,
3409 &cpu_pentium4m,
3410 &cpu_pentiumpro,
3411 &cpu_prescott,
3412 &cpu_sandybridge,
3413 &cpu_silvermont,
3414 &cpu_skx,
3415 &cpu_skylake,
3416 &cpu_skylakeAvx512,
3417 &cpu_slm,
3418 &cpu_tigerlake,
3419 &cpu_tremont,
3420 &cpu_westmere,
3421 &cpu_winchipC6,
3422 &cpu_winchip2,
3423 &cpu_x8664,
3424 &cpu_yonah,
3425 &cpu_znver1,
3426 &cpu_znver2,
3427};
src-self-hosted/stage1.zig+40-48
......@@ -6,8 +6,6 @@ const io = std.io;
66const mem = std.mem;
77const fs = std.fs;
88const process = std.process;
9const feature = std.target.feature;
10const cpu = std.target.cpu;
119const Allocator = mem.Allocator;
1210const ArrayList = std.ArrayList;
1311const Buffer = std.Buffer;
......@@ -546,34 +544,30 @@ fn print_features_for_arch(arch_name: []const u8, show_subfeatures: bool) !void
546544 return;
547545 };
548546
549 inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
550 if (@enumToInt(arch) == arch_enum_field.value) {
551 const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
547 try stdout_stream.print("Available features for {}:\n", .{ @tagName(arch) });
552548
553 const feature_infos = feature.ArchFeature(enum_arch).feature_infos;
549 const features = std.target.getFeaturesForArch(arch);
554550
555 try stdout_stream.print("Available features for {}:\n", .{ arch_enum_field.name });
556
557 var longest_len: usize = 0;
558 for (feature_infos) |feature_info| {
559 if (feature_info.name.len > longest_len) longest_len = feature_info.name.len;
560 }
551 var longest_len: usize = 0;
552 for (features) |feature| {
553 if (feature.name.len > longest_len) {
554 longest_len = feature.name.len;
555 }
556 }
561557
562 for (feature_infos) |feature_info| {
563 try stdout_stream.print(" {}", .{ feature_info.name });
564
565 var i: usize = 0;
566 while (i < longest_len - feature_info.name.len) : (i += 1) {
567 try stdout_stream.write(" ");
568 }
558 for (features) |feature| {
559 try stdout_stream.print(" {}", .{ feature.name });
560
561 var i: usize = 0;
562 while (i < longest_len - feature.name.len) : (i += 1) {
563 try stdout_stream.write(" ");
564 }
569565
570 try stdout_stream.print(" - {}\n", .{ feature_info.description });
566 try stdout_stream.print(" - {}\n", .{ feature.description });
571567
572 if (show_subfeatures and feature_info.subfeatures.len > 0) {
573 for (feature_info.subfeatures) |subfeature| {
574 try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
575 }
576 }
568 if (show_subfeatures and feature.subfeatures.len > 0) {
569 for (feature.subfeatures) |subfeature| {
570 try stdout_stream.print(" {}\n", .{ subfeature.name });
577571 }
578572 }
579573 }
......@@ -594,35 +588,33 @@ fn print_cpus_for_arch(arch_name: []const u8, show_subfeatures: bool) !void {
594588 return;
595589 };
596590
597 inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
598 if (@enumToInt(arch) == arch_enum_field.value) {
599 const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
600
601 const cpu_infos = cpu.ArchCpu(enum_arch).cpu_infos;
591 const cpus = std.target.getCpusForArch(arch);
602592
603 try stdout_stream.print("Available cpus for {}:\n", .{ arch_enum_field.name });
593 try stdout_stream.print("Available cpus for {}:\n", .{ @tagName(arch) });
604594
605 var longest_len: usize = 0;
606 for (cpu_infos) |cpu_info| {
607 if (cpu_info.name.len > longest_len) longest_len = cpu_info.name.len;
608 }
595 var longest_len: usize = 0;
596 for (cpus) |cpu| {
597 if (cpu.name.len > longest_len) {
598 longest_len = cpu.name.len;
599 }
600 }
609601
610 for (cpu_infos) |cpu_info| {
611 try stdout_stream.print(" {}", .{ cpu_info.name });
612
613 var i: usize = 0;
614 while (i < longest_len - cpu_info.name.len) : (i += 1) {
615 try stdout_stream.write(" ");
616 }
602 for (cpus) |cpu| {
603 try stdout_stream.print(" {}", .{ cpu.name });
604
605 var i: usize = 0;
606 while (i < longest_len - cpu.name.len) : (i += 1) {
607 try stdout_stream.write(" ");
608 }
617609
618 try stdout_stream.write("\n");
610 try stdout_stream.write("\n");
619611
620 if (show_subfeatures and cpu_info.features.len > 0) {
621 for (cpu_info.features) |subfeature| {
622 try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
623 }
624 }
612 if (show_subfeatures and cpu.subfeatures.len > 0) {
613 for (cpu.subfeatures) |subfeature| {
614 try stdout_stream.print(" {}\n", .{ subfeature.name });
625615 }
626616 }
627617 }
628618}
619
620// use target_arch_name(ZigLLVM_ArchType) to get name from main.cpp 'target'.