| author | |
| committer | |
| log | c217fd2b9ca06d51b8c67a7a556e61ae71a25dbb |
| tree | e9be8fff60e7b1d1d42305b9c6bfcd910a0ae60b |
| parent | 3a5142af8dcafea7062588b9d217ae82735c0bac |
| signature |
2 files changed, 52 insertions(+), 0 deletions(-)
src/Zcu.zig+19| ... | @@ -3607,17 +3607,21 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu | ... | @@ -3607,17 +3607,21 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu |
| 3607 | .x86_64_vectorcall, | 3607 | .x86_64_vectorcall, |
| 3608 | .x86_64_regcall_v3_sysv, | 3608 | .x86_64_regcall_v3_sysv, |
| 3609 | .x86_64_regcall_v4_win, | 3609 | .x86_64_regcall_v4_win, |
| 3610 | .x86_64_interrupt, | ||
| 3610 | .x86_fastcall, | 3611 | .x86_fastcall, |
| 3611 | .x86_thiscall, | 3612 | .x86_thiscall, |
| 3612 | .x86_vectorcall, | 3613 | .x86_vectorcall, |
| 3613 | .x86_regcall_v3, | 3614 | .x86_regcall_v3, |
| 3614 | .x86_regcall_v4_win, | 3615 | .x86_regcall_v4_win, |
| 3616 | .x86_interrupt, | ||
| 3615 | .aarch64_vfabi, | 3617 | .aarch64_vfabi, |
| 3616 | .aarch64_vfabi_sve, | 3618 | .aarch64_vfabi_sve, |
| 3617 | .arm_aapcs, | 3619 | .arm_aapcs, |
| 3620 | .csky_interrupt, | ||
| 3618 | .riscv64_lp64_v, | 3621 | .riscv64_lp64_v, |
| 3619 | .riscv32_ilp32_v, | 3622 | .riscv32_ilp32_v, |
| 3620 | .m68k_rtd, | 3623 | .m68k_rtd, |
| 3624 | .m68k_interrupt, | ||
| 3621 | => |opts| opts.incoming_stack_alignment == null, | 3625 | => |opts| opts.incoming_stack_alignment == null, |
| 3622 | 3626 | ||
| 3623 | .arm_aapcs_vfp, | 3627 | .arm_aapcs_vfp, |
| ... | @@ -3625,11 +3629,26 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu | ... | @@ -3625,11 +3629,26 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu |
| 3625 | .arm_aapcs16_vfp, | 3629 | .arm_aapcs16_vfp, |
| 3626 | => |opts| opts.incoming_stack_alignment == null and target.os.tag == .watchos, | 3630 | => |opts| opts.incoming_stack_alignment == null and target.os.tag == .watchos, |
| 3627 | 3631 | ||
| 3632 | .arm_interrupt, | ||
| 3633 | => |opts| opts.incoming_stack_alignment == null, | ||
| 3634 | |||
| 3635 | .mips_interrupt, | ||
| 3636 | .mips64_interrupt, | ||
| 3637 | => |opts| opts.incoming_stack_alignment == null, | ||
| 3638 | |||
| 3639 | .riscv32_interrupt, | ||
| 3640 | .riscv64_interrupt, | ||
| 3641 | => |opts| opts.incoming_stack_alignment == null, | ||
| 3642 | |||
| 3628 | .x86_sysv, | 3643 | .x86_sysv, |
| 3629 | .x86_win, | 3644 | .x86_win, |
| 3630 | .x86_stdcall, | 3645 | .x86_stdcall, |
| 3631 | => |opts| opts.incoming_stack_alignment == null and opts.register_params == 0, | 3646 | => |opts| opts.incoming_stack_alignment == null and opts.register_params == 0, |
| 3632 | 3647 | ||
| 3648 | .avr_interrupt, | ||
| 3649 | .avr_signal, | ||
| 3650 | => true, | ||
| 3651 | |||
| 3633 | .naked => true, | 3652 | .naked => true, |
| 3634 | 3653 | ||
| 3635 | else => false, | 3654 | else => false, |
src/codegen/c.zig+33| ... | @@ -7622,11 +7622,44 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8 | ... | @@ -7622,11 +7622,44 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8 |
| 7622 | 7622 | ||
| 7623 | .aarch64_vfabi => "aarch64_vector_pcs", | 7623 | .aarch64_vfabi => "aarch64_vector_pcs", |
| 7624 | .aarch64_vfabi_sve => "aarch64_sve_pcs", | 7624 | .aarch64_vfabi_sve => "aarch64_sve_pcs", |
| 7625 | |||
| 7625 | .arm_aapcs => "pcs(\"aapcs\")", | 7626 | .arm_aapcs => "pcs(\"aapcs\")", |
| 7626 | .arm_aapcs_vfp, .arm_aapcs16_vfp => "pcs(\"aapcs-vfp\")", | 7627 | .arm_aapcs_vfp, .arm_aapcs16_vfp => "pcs(\"aapcs-vfp\")", |
| 7628 | |||
| 7629 | .arm_interrupt => |opts| switch (opts.type) { | ||
| 7630 | .generic => "interrupt", | ||
| 7631 | .irq => "interrupt(\"IRQ\")", | ||
| 7632 | .fiq => "interrupt(\"FIQ\")", | ||
| 7633 | .swi => "interrupt(\"SWI\")", | ||
| 7634 | .abort => "interrupt(\"ABORT\")", | ||
| 7635 | .undef => "interrupt(\"UNDEF\")", | ||
| 7636 | }, | ||
| 7637 | |||
| 7638 | .avr_signal => "signal", | ||
| 7639 | |||
| 7640 | .mips_interrupt, | ||
| 7641 | .mips64_interrupt, | ||
| 7642 | => |opts| switch (opts.mode) { | ||
| 7643 | inline else => |m| "interrupt(\"" ++ @tagName(m) ++ "\")", | ||
| 7644 | }, | ||
| 7645 | |||
| 7627 | .riscv64_lp64_v, .riscv32_ilp32_v => "riscv_vector_cc", | 7646 | .riscv64_lp64_v, .riscv32_ilp32_v => "riscv_vector_cc", |
| 7647 | |||
| 7648 | .riscv32_interrupt, | ||
| 7649 | .riscv64_interrupt, | ||
| 7650 | => |opts| switch (opts.mode) { | ||
| 7651 | inline else => |m| "interrupt(\"" ++ @tagName(m) ++ "\")", | ||
| 7652 | }, | ||
| 7653 | |||
| 7628 | .m68k_rtd => "m68k_rtd", | 7654 | .m68k_rtd => "m68k_rtd", |
| 7629 | 7655 | ||
| 7656 | .avr_interrupt, | ||
| 7657 | .csky_interrupt, | ||
| 7658 | .m68k_interrupt, | ||
| 7659 | .x86_interrupt, | ||
| 7660 | .x86_64_interrupt, | ||
| 7661 | => "interrupt", | ||
| 7662 | |||
| 7630 | else => unreachable, // `Zcu.callconvSupported` | 7663 | else => unreachable, // `Zcu.callconvSupported` |
| 7631 | }; | 7664 | }; |
| 7632 | } | 7665 | } |