| author | |
| committer | |
| log | c2beaba85a87b5985fe9f1676ad2bc4888dd6c1a |
| tree | 690fb4576cf0eb250de74eec9fc328e59822731d |
| parent | 221f1d898c39e9ea25f1d7fc9642bfbb3c97e894 |
Previously, the registers included r0, r1, r2, r3 which are not
included in the callee saved registers according to the Procedure Call
Standard for the ARM Architecture.1 files changed, 1 insertions(+), 1 deletions(-)
src/codegen/arm.zig+1-1| ... | ... | @@ -186,7 +186,7 @@ pub const Psr = enum { |
| 186 | 186 | spsr, |
| 187 | 187 | }; |
| 188 | 188 | |
| 189 | pub const callee_preserved_regs = [_]Register{ .r0, .r1, .r2, .r3, .r4, .r5, .r6, .r7, .r8, .r10 }; | |
| 189 | pub const callee_preserved_regs = [_]Register{ .r4, .r5, .r6, .r7, .r8, .r10 }; | |
| 190 | 190 | pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 }; |
| 191 | 191 | pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 }; |
| 192 | 192 |