| ... | ... | @@ -2693,9 +2693,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 2693 | 2693 | |
| 2694 | 2694 | switch (abi_size) { |
| 2695 | 2695 | 1, 4 => { |
| 2696 | | const offset = if (adj_off <= math.maxInt(u12)) blk: { |
| 2697 | | break :blk Instruction.Offset.imm(@intCast(u12, adj_off)); |
| 2698 | | } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0); |
| 2696 | const offset = if (math.cast(u12, adj_off)) |imm| blk: { |
| 2697 | break :blk Instruction.Offset.imm(imm); |
| 2698 | } else |_| Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0); |
| 2699 | 2699 | const str = switch (abi_size) { |
| 2700 | 2700 | 1 => Instruction.strb, |
| 2701 | 2701 | 4 => Instruction.str, |
| ... | ... | @@ -2856,12 +2856,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 2856 | 2856 | |
| 2857 | 2857 | switch (abi_size) { |
| 2858 | 2858 | 4, 8 => { |
| 2859 | | const offset = if (adj_off <= math.maxInt(u12)) blk: { |
| 2860 | | break :blk Instruction.LoadStoreOffset.imm(@intCast(u12, adj_off)); |
| 2861 | | } else Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off })); |
| 2862 | | const rn: Register = switch (abi_size) { |
| 2863 | | 4 => .w29, |
| 2864 | | 8 => .x29, |
| 2859 | const offset = if (math.cast(i9, adj_off)) |imm| |
| 2860 | Instruction.LoadStoreOffset.imm_post_index(-imm) |
| 2861 | else |_| |
| 2862 | Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off })); |
| 2863 | const rn: Register = switch (arch) { |
| 2864 | .aarch64, .aarch64_be => .x29, |
| 2865 | .aarch64_32 => .w29, |
| 2865 | 2866 | else => unreachable, |
| 2866 | 2867 | }; |
| 2867 | 2868 | |