Commit c772fef715c2faec422fb68b69b912780d68762e | zig

author	xtex <xtex@astrafall.org> 2026-08-30 20:43:21+08:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2026-08-30 22:54:04+02:00
log	c772fef715c2faec422fb68b69b912780d68762e
tree	b75a2d6b9eb855c2e9c5ddfeeeab110e71370803
parent	14bac1ffcf044c01362776cceb9ff8d381285fd4

loongarch: use movfr2gr for bit_cast only if values are stored in FPR

For f80 (and f64/f32 on platforms without FP support),
values should be stored in GPRs or stacks. Therefore,
movfr2gr and movgr2fr should not be used.

2 files changed, 31 insertions(+), 5 deletions(-)

src
- codegen
  - loongarch
    Select.zig
    bits.zig

src/codegen/loongarch/Select.zig+30-4

 @@ -3758,12 +3758,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
                 } else if (dst_tag == .float and src_tag == .float) {
                     assert(dst_ty.floatBits(isel.target) == src_ty.floatBits(isel.target));
                     try dst_vi.value.defMove(isel, ty_op.operand);
-                } else if (dst_ty.isAbiInt(zcu) and src_tag == .float) {
+                } else if (dst_ty.isAbiInt(zcu) and src_tag == .float and isel.canUseFprForFloat(src_ty)) {
                     const dst_int_info = dst_ty.intInfo(zcu);
                     assert(dst_int_info.bits == src_ty.floatBits(isel.target));
                     try dst_vi.value.reextendToGarbage(isel);
-                    const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloating(dst_int_info.bits)) orelse break :unused;
+                    const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloatBits(dst_int_info.bits)) orelse break :unused;
                     const src_vi = try isel.use(ty_op.operand);
                     const src_mat = try src_vi.matReg(isel);
                     const src_reg = src_mat.reg();
 @@ -3773,12 +3773,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
                         64 => .@"movfr2gr.d"(dst_reg, src_reg),
                     });
                     try src_mat.finish(isel);
-                } else if (dst_tag == .float and src_ty.isAbiInt(zcu)) {
+                } else if (dst_tag == .float and src_ty.isAbiInt(zcu) and isel.canUseFprForFloat(dst_ty)) {
                     const src_int_info = src_ty.intInfo(zcu);
                     assert(dst_ty.floatBits(isel.target) == src_int_info.bits);
                     try dst_vi.value.reextendToGarbage(isel);
-                    const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloating(src_int_info.bits)) orelse break :unused;
+                    const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloatBits(src_int_info.bits)) orelse break :unused;
                     const src_vi = try isel.use(ty_op.operand);
                     const src_mat = try src_vi.matReg(isel);
                     const src_reg = src_mat.reg();
 @@ -7258,6 +7258,32 @@ fn gprAlignment(isel: *Select) std.mem.Alignment {
     };
 }
+fn fprBits(isel: *Select) u7 {
+    const cpu = &isel.target.cpu;
+    if (cpu.has(.loongarch, .d)) {
+        return 64;
+    } else if (cpu.has(.loongarch, .f)) {
+        return 32;
+    } else {
+        return 0;
+    }
+}
+fn vectorBits(isel: *Select) u7 {
+    const cpu = &isel.target.cpu;
+    if (cpu.has(.loongarch, .lasx)) {
+        return 256;
+    } else if (cpu.has(.loongarch, .lsx)) {
+        return 128;
+    } else {
+        return isel.fprBits();
+    }
+}
+fn canUseFprForFloat(isel: *Select, ty: ZigType) bool {
+    return ty.floatBits(isel.target) <= isel.fprBits();
+}
 fn typeOfField(isel: *Select, ty: ZigType, offset: u64) ?ZigType {
     const zcu = isel.pt.zcu;
     const ip = &zcu.intern_pool;

src/codegen/loongarch/bits.zig+1-1

...	@@ -85,7 +85,7 @@ pub const Register = enum(u7) {	...	@@ -85,7 +85,7 @@ pub const Register = enum(u7) {
85	};	85	};
86	}	86	}
87		87
88	pub fn fromFloating(bits: u16) Modifier {	88	pub fn fromFloatBits(bits: u16) Modifier {
89	return switch (bits) {	89	return switch (bits) {
90	else => unreachable,	90	else => unreachable,
91	32 => .floating32,	91	32 => .floating32,