authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-01-17 06:54:56+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-04-25 21:54:47+02:00
logca0b3318a08e80ae64bb97bfaf35ab237ed0e507
tree0a670d15572ea8de66fd2820de2722d131632972
parentc855c61432f484a1e4016366d7d178bb90d3e552
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: update CPU and feature data to LLVM 22

22 files changed, 2008 insertions(+), 395 deletions(-)

lib/compiler/aro/aro/Compilation.zig-3
...@@ -498,7 +498,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {...@@ -498,7 +498,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
498 .{ .fma, "__FMA__" },498 .{ .fma, "__FMA__" },
499 .{ .f16c, "__F16C__" },499 .{ .f16c, "__F16C__" },
500 .{ .gfni, "__GFNI__" },500 .{ .gfni, "__GFNI__" },
501 .{ .evex512, "__EVEX512__" },
502501
503 .{ .avx10_1, "__AVX10_1__" },502 .{ .avx10_1, "__AVX10_1__" },
504 .{ .avx10_1, "__AVX10_1_512__" },503 .{ .avx10_1, "__AVX10_1_512__" },
...@@ -560,7 +559,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {...@@ -560,7 +559,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
560 .{ .amx_complex, "__AMX_COMPLEX__" },559 .{ .amx_complex, "__AMX_COMPLEX__" },
561 .{ .amx_fp8, "__AMX_FP8__" },560 .{ .amx_fp8, "__AMX_FP8__" },
562 .{ .amx_movrs, "__AMX_MOVRS__" },561 .{ .amx_movrs, "__AMX_MOVRS__" },
563 .{ .amx_transpose, "__AMX_TRANSPOSE__" },
564 .{ .amx_avx512, "__AMX_AVX512__" },562 .{ .amx_avx512, "__AMX_AVX512__" },
565 .{ .amx_tf32, "__AMX_TF32__" },563 .{ .amx_tf32, "__AMX_TF32__" },
566 .{ .cmpccxadd, "__CMPCCXADD__" },564 .{ .cmpccxadd, "__CMPCCXADD__" },
...@@ -798,7 +796,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {...@@ -798,7 +796,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
798 .{ .fullfp16, "FP16_SCALAR_ARITHMETIC" },796 .{ .fullfp16, "FP16_SCALAR_ARITHMETIC" },
799 .{ .dotprod, "DOTPROD" },797 .{ .dotprod, "DOTPROD" },
800 .{ .mte, "MEMORY_TAGGING" },798 .{ .mte, "MEMORY_TAGGING" },
801 .{ .tme, "TME" },
802 .{ .i8mm, "MATMUL_INT8" },799 .{ .i8mm, "MATMUL_INT8" },
803 .{ .lse, "ATOMICS" },800 .{ .lse, "ATOMICS" },
804 .{ .f64mm, "SVE_MATMUL_FP64" },801 .{ .f64mm, "SVE_MATMUL_FP64" },
lib/std/Target.zig+2-1
...@@ -1225,7 +1225,7 @@ pub const Cpu = struct {...@@ -1225,7 +1225,7 @@ pub const Cpu = struct {
1225 pub const Set = struct {1225 pub const Set = struct {
1226 ints: [usize_count]usize,1226 ints: [usize_count]usize,
12271227
1228 pub const needed_bit_count = 317;1228 pub const needed_bit_count = 347;
1229 pub const byte_count = (needed_bit_count + 7) / 8;1229 pub const byte_count = (needed_bit_count + 7) / 8;
1230 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);1230 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
1231 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));1231 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
...@@ -2061,6 +2061,7 @@ pub const Cpu = struct {...@@ -2061,6 +2061,7 @@ pub const Cpu = struct {
2061 .hppa => &hppa.cpu.pa_7300lc,2061 .hppa => &hppa.cpu.pa_7300lc,
2062 .kvx => &kvx.cpu.coolidge_v2,2062 .kvx => &kvx.cpu.coolidge_v2,
2063 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.2063 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
2064 .loongarch32 => &loongarch.cpu.la32v1_0,
2064 .loongarch64 => &loongarch.cpu.la64v1_0,2065 .loongarch64 => &loongarch.cpu.la64v1_0,
2065 .m68k => &m68k.cpu.M68000,2066 .m68k => &m68k.cpu.M68000,
2066 .mips => &mips.cpu.mips32r2,2067 .mips => &mips.cpu.mips32r2,
lib/std/Target/aarch64.zig+620-77
...@@ -9,6 +9,7 @@ pub const Feature = enum {...@@ -9,6 +9,7 @@ pub const Feature = enum {
9 addr_lsl_slow_14,9 addr_lsl_slow_14,
10 aes,10 aes,
11 aggressive_fma,11 aggressive_fma,
12 aggressive_interleaving,
12 alternate_sextload_cvt_f32_pattern,13 alternate_sextload_cvt_f32_pattern,
13 altnzcv,14 altnzcv,
14 alu_lsl_fast,15 alu_lsl_fast,
...@@ -22,6 +23,7 @@ pub const Feature = enum {...@@ -22,6 +23,7 @@ pub const Feature = enum {
22 bf16,23 bf16,
23 brbe,24 brbe,
24 bti,25 bti,
26 btie,
25 call_saved_x10,27 call_saved_x10,
26 call_saved_x11,28 call_saved_x11,
27 call_saved_x12,29 call_saved_x12,
...@@ -36,6 +38,7 @@ pub const Feature = enum {...@@ -36,6 +38,7 @@ pub const Feature = enum {
36 ccpp,38 ccpp,
37 chk,39 chk,
38 clrbhb,40 clrbhb,
41 cmh,
39 cmp_bcc_fusion,42 cmp_bcc_fusion,
40 cmpbr,43 cmpbr,
41 complxnum,44 complxnum,
...@@ -48,7 +51,9 @@ pub const Feature = enum {...@@ -48,7 +51,9 @@ pub const Feature = enum {
48 disable_fast_inc_vl,51 disable_fast_inc_vl,
49 disable_latency_sched_heuristic,52 disable_latency_sched_heuristic,
50 disable_ldp,53 disable_ldp,
54 disable_maximize_scalable_bandwidth,
51 disable_stp,55 disable_stp,
56 disable_unpredicated_ld_st_lower,
52 dit,57 dit,
53 dotprod,58 dotprod,
54 ecv,59 ecv,
...@@ -58,6 +63,9 @@ pub const Feature = enum {...@@ -58,6 +63,9 @@ pub const Feature = enum {
58 ete,63 ete,
59 execute_only,64 execute_only,
60 exynos_cheap_as_move,65 exynos_cheap_as_move,
66 f16f32dot,
67 f16f32mm,
68 f16mm,
61 f32mm,69 f32mm,
62 f64mm,70 f64mm,
63 f8f16mm,71 f8f16mm,
...@@ -86,7 +94,9 @@ pub const Feature = enum {...@@ -86,7 +94,9 @@ pub const Feature = enum {
86 fuse_arith_logic,94 fuse_arith_logic,
87 fuse_crypto_eor,95 fuse_crypto_eor,
88 fuse_csel,96 fuse_csel,
97 fuse_cset,
89 fuse_literals,98 fuse_literals,
99 gcie,
90 gcs,100 gcs,
91 harden_sls_blr,101 harden_sls_blr,
92 harden_sls_nocomdat,102 harden_sls_nocomdat,
...@@ -99,22 +109,27 @@ pub const Feature = enum {...@@ -99,22 +109,27 @@ pub const Feature = enum {
99 ldp_aligned_only,109 ldp_aligned_only,
100 lor,110 lor,
101 ls64,111 ls64,
112 lscp,
102 lse,113 lse,
103 lse128,114 lse128,
104 lse2,115 lse2,
105 lsfe,116 lsfe,
106 lsui,117 lsui,
107 lut,118 lut,
119 max_interleave_factor_4,
108 mec,120 mec,
109 mops,121 mops,
122 mops_go,
110 mpam,123 mpam,
124 mpamv2,
111 mte,125 mte,
126 mtetc,
112 neon,127 neon,
113 nmi,128 nmi,
114 no_bti_at_return_twice,129 no_bti_at_return_twice,
115 no_neg_immediates,130 no_neg_immediates,
116 no_sve_fp_ld1r,131 no_sve_fp_ld1r,
117 no_zcz_fp,132 no_zcz_fpr64,
118 nv,133 nv,
119 occmo,134 occmo,
120 olympus,135 olympus,
...@@ -125,6 +140,7 @@ pub const Feature = enum {...@@ -125,6 +140,7 @@ pub const Feature = enum {
125 pauth_lr,140 pauth_lr,
126 pcdphint,141 pcdphint,
127 perfmon,142 perfmon,
143 poe2,
128 pops,144 pops,
129 predictable_select_expensive,145 predictable_select_expensive,
130 predres,146 predres,
...@@ -174,6 +190,7 @@ pub const Feature = enum {...@@ -174,6 +190,7 @@ pub const Feature = enum {
174 sme2,190 sme2,
175 sme2p1,191 sme2p1,
176 sme2p2,192 sme2p2,
193 sme2p3,
177 sme_b16b16,194 sme_b16b16,
178 sme_f16f16,195 sme_f16f16,
179 sme_f64f64,196 sme_f64f64,
...@@ -206,19 +223,22 @@ pub const Feature = enum {...@@ -206,19 +223,22 @@ pub const Feature = enum {
206 sve2_sm4,223 sve2_sm4,
207 sve2p1,224 sve2p1,
208 sve2p2,225 sve2p2,
226 sve2p3,
209 sve_aes,227 sve_aes,
210 sve_aes2,228 sve_aes2,
211 sve_b16b16,229 sve_b16b16,
230 sve_b16mm,
212 sve_bfscale,231 sve_bfscale,
213 sve_bitperm,232 sve_bitperm,
214 sve_f16f32mm,233 sve_f16f32mm,
215 sve_sha3,234 sve_sha3,
216 sve_sm4,235 sve_sm4,
217 tagged_globals,236 tagged_globals,
237 tev,
218 the,238 the,
219 tlb_rmi,239 tlb_rmi,
240 tlbid,
220 tlbiw,241 tlbiw,
221 tme,
222 tpidr_el1,242 tpidr_el1,
223 tpidr_el2,243 tpidr_el2,
224 tpidr_el3,244 tpidr_el3,
...@@ -230,6 +250,7 @@ pub const Feature = enum {...@@ -230,6 +250,7 @@ pub const Feature = enum {
230 use_fixed_over_scalable_if_equal_cost,250 use_fixed_over_scalable_if_equal_cost,
231 use_postra_scheduler,251 use_postra_scheduler,
232 use_reciprocal_square_root,252 use_reciprocal_square_root,
253 use_wzr_to_vec_move,
233 v8_1a,254 v8_1a,
234 v8_2a,255 v8_2a,
235 v8_3a,256 v8_3a,
...@@ -247,17 +268,20 @@ pub const Feature = enum {...@@ -247,17 +268,20 @@ pub const Feature = enum {
247 v9_4a,268 v9_4a,
248 v9_5a,269 v9_5a,
249 v9_6a,270 v9_6a,
271 v9_7a,
250 v9a,272 v9a,
251 vh,273 vh,
252 wfxt,274 wfxt,
253 xs,275 xs,
276 zcm_fpr128,
254 zcm_fpr32,277 zcm_fpr32,
255 zcm_fpr64,278 zcm_fpr64,
256 zcm_gpr32,279 zcm_gpr32,
257 zcm_gpr64,280 zcm_gpr64,
258 zcz,
259 zcz_fp_workaround,281 zcz_fp_workaround,
260 zcz_gp,282 zcz_fpr128,
283 zcz_gpr32,
284 zcz_gpr64,
261};285};
262286
263pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;287pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
...@@ -274,9 +298,12 @@ pub const all_features = blk: {...@@ -274,9 +298,12 @@ pub const all_features = blk: {
274 .llvm_name = "a320",298 .llvm_name = "a320",
275 .description = "Cortex-A320 ARM processors",299 .description = "Cortex-A320 ARM processors",
276 .dependencies = featureSet(&[_]Feature{300 .dependencies = featureSet(&[_]Feature{
301 .aggressive_interleaving,
277 .fuse_adrp_add,302 .fuse_adrp_add,
278 .fuse_aes,303 .fuse_aes,
304 .use_fixed_over_scalable_if_equal_cost,
279 .use_postra_scheduler,305 .use_postra_scheduler,
306 .use_wzr_to_vec_move,
280 }),307 }),
281 };308 };
282 result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{309 result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{
...@@ -296,6 +323,11 @@ pub const all_features = blk: {...@@ -296,6 +323,11 @@ pub const all_features = blk: {
296 .description = "Enable Aggressive FMA for floating-point.",323 .description = "Enable Aggressive FMA for floating-point.",
297 .dependencies = featureSet(&[_]Feature{}),324 .dependencies = featureSet(&[_]Feature{}),
298 };325 };
326 result[@intFromEnum(Feature.aggressive_interleaving)] = .{
327 .llvm_name = "aggressive-interleaving",
328 .description = "Make use of aggressive interleaving during vectorization",
329 .dependencies = featureSet(&[_]Feature{}),
330 };
299 result[@intFromEnum(Feature.alternate_sextload_cvt_f32_pattern)] = .{331 result[@intFromEnum(Feature.alternate_sextload_cvt_f32_pattern)] = .{
300 .llvm_name = "alternate-sextload-cvt-f32-pattern",332 .llvm_name = "alternate-sextload-cvt-f32-pattern",
301 .description = "Use alternative pattern for sextload convert to f32",333 .description = "Use alternative pattern for sextload convert to f32",
...@@ -367,6 +399,11 @@ pub const all_features = blk: {...@@ -367,6 +399,11 @@ pub const all_features = blk: {
367 .description = "Enable Branch Target Identification",399 .description = "Enable Branch Target Identification",
368 .dependencies = featureSet(&[_]Feature{}),400 .dependencies = featureSet(&[_]Feature{}),
369 };401 };
402 result[@intFromEnum(Feature.btie)] = .{
403 .llvm_name = "btie",
404 .description = "Enable Enhanced Branch Target Identification extension",
405 .dependencies = featureSet(&[_]Feature{}),
406 };
370 result[@intFromEnum(Feature.call_saved_x10)] = .{407 result[@intFromEnum(Feature.call_saved_x10)] = .{
371 .llvm_name = "call-saved-x10",408 .llvm_name = "call-saved-x10",
372 .description = "Make X10 callee saved.",409 .description = "Make X10 callee saved.",
...@@ -439,6 +476,11 @@ pub const all_features = blk: {...@@ -439,6 +476,11 @@ pub const all_features = blk: {
439 .description = "Enable Clear BHB instruction",476 .description = "Enable Clear BHB instruction",
440 .dependencies = featureSet(&[_]Feature{}),477 .dependencies = featureSet(&[_]Feature{}),
441 };478 };
479 result[@intFromEnum(Feature.cmh)] = .{
480 .llvm_name = "cmh",
481 .description = "Enable Armv9.7-A Contention Management Hints",
482 .dependencies = featureSet(&[_]Feature{}),
483 };
442 result[@intFromEnum(Feature.cmp_bcc_fusion)] = .{484 result[@intFromEnum(Feature.cmp_bcc_fusion)] = .{
443 .llvm_name = "cmp-bcc-fusion",485 .llvm_name = "cmp-bcc-fusion",
444 .description = "CPU fuses cmp+bcc operations",486 .description = "CPU fuses cmp+bcc operations",
...@@ -506,11 +548,21 @@ pub const all_features = blk: {...@@ -506,11 +548,21 @@ pub const all_features = blk: {
506 .description = "Do not emit ldp",548 .description = "Do not emit ldp",
507 .dependencies = featureSet(&[_]Feature{}),549 .dependencies = featureSet(&[_]Feature{}),
508 };550 };
551 result[@intFromEnum(Feature.disable_maximize_scalable_bandwidth)] = .{
552 .llvm_name = "disable-maximize-scalable-bandwidth",
553 .description = "Determine the maximum scalable vector length for a loop by the largest scalar type rather than the smallest",
554 .dependencies = featureSet(&[_]Feature{}),
555 };
509 result[@intFromEnum(Feature.disable_stp)] = .{556 result[@intFromEnum(Feature.disable_stp)] = .{
510 .llvm_name = "disable-stp",557 .llvm_name = "disable-stp",
511 .description = "Do not emit stp",558 .description = "Do not emit stp",
512 .dependencies = featureSet(&[_]Feature{}),559 .dependencies = featureSet(&[_]Feature{}),
513 };560 };
561 result[@intFromEnum(Feature.disable_unpredicated_ld_st_lower)] = .{
562 .llvm_name = "disable-unpredicated-ld-st-lower",
563 .description = "Disable lowering unpredicated loads/stores as LDR/STR",
564 .dependencies = featureSet(&[_]Feature{}),
565 };
514 result[@intFromEnum(Feature.dit)] = .{566 result[@intFromEnum(Feature.dit)] = .{
515 .llvm_name = "dit",567 .llvm_name = "dit",
516 .description = "Enable Armv8.4-A Data Independent Timing instructions",568 .description = "Enable Armv8.4-A Data Independent Timing instructions",
...@@ -560,6 +612,30 @@ pub const all_features = blk: {...@@ -560,6 +612,30 @@ pub const all_features = blk: {
560 .description = "Use Exynos specific handling of cheap instructions",612 .description = "Use Exynos specific handling of cheap instructions",
561 .dependencies = featureSet(&[_]Feature{}),613 .dependencies = featureSet(&[_]Feature{}),
562 };614 };
615 result[@intFromEnum(Feature.f16f32dot)] = .{
616 .llvm_name = "f16f32dot",
617 .description = "Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision",
618 .dependencies = featureSet(&[_]Feature{
619 .fullfp16,
620 .neon,
621 }),
622 };
623 result[@intFromEnum(Feature.f16f32mm)] = .{
624 .llvm_name = "f16f32mm",
625 .description = "Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision",
626 .dependencies = featureSet(&[_]Feature{
627 .fullfp16,
628 .neon,
629 }),
630 };
631 result[@intFromEnum(Feature.f16mm)] = .{
632 .llvm_name = "f16mm",
633 .description = "Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate",
634 .dependencies = featureSet(&[_]Feature{
635 .fullfp16,
636 .neon,
637 }),
638 };
563 result[@intFromEnum(Feature.f32mm)] = .{639 result[@intFromEnum(Feature.f32mm)] = .{
564 .llvm_name = "f32mm",640 .llvm_name = "f32mm",
565 .description = "Enable Matrix Multiply FP32 Extension",641 .description = "Enable Matrix Multiply FP32 Extension",
...@@ -729,7 +805,12 @@ pub const all_features = blk: {...@@ -729,7 +805,12 @@ pub const all_features = blk: {
729 };805 };
730 result[@intFromEnum(Feature.fuse_csel)] = .{806 result[@intFromEnum(Feature.fuse_csel)] = .{
731 .llvm_name = "fuse-csel",807 .llvm_name = "fuse-csel",
732 .description = "CPU fuses conditional select operations",808 .description = "CPU can fuse CMP and CSEL operations",
809 .dependencies = featureSet(&[_]Feature{}),
810 };
811 result[@intFromEnum(Feature.fuse_cset)] = .{
812 .llvm_name = "fuse-cset",
813 .description = "CPU can fuse CMP and CSET operations",
733 .dependencies = featureSet(&[_]Feature{}),814 .dependencies = featureSet(&[_]Feature{}),
734 };815 };
735 result[@intFromEnum(Feature.fuse_literals)] = .{816 result[@intFromEnum(Feature.fuse_literals)] = .{
...@@ -737,6 +818,11 @@ pub const all_features = blk: {...@@ -737,6 +818,11 @@ pub const all_features = blk: {
737 .description = "CPU fuses literal generation operations",818 .description = "CPU fuses literal generation operations",
738 .dependencies = featureSet(&[_]Feature{}),819 .dependencies = featureSet(&[_]Feature{}),
739 };820 };
821 result[@intFromEnum(Feature.gcie)] = .{
822 .llvm_name = "gcie",
823 .description = "Enable GICv5 (Generic Interrupt Controller) CPU Interface Extension",
824 .dependencies = featureSet(&[_]Feature{}),
825 };
740 result[@intFromEnum(Feature.gcs)] = .{826 result[@intFromEnum(Feature.gcs)] = .{
741 .llvm_name = "gcs",827 .llvm_name = "gcs",
742 .description = "Enable Armv9.4-A Guarded Call Stack Extension",828 .description = "Enable Armv9.4-A Guarded Call Stack Extension",
...@@ -805,6 +891,11 @@ pub const all_features = blk: {...@@ -805,6 +891,11 @@ pub const all_features = blk: {
805 .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension",891 .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension",
806 .dependencies = featureSet(&[_]Feature{}),892 .dependencies = featureSet(&[_]Feature{}),
807 };893 };
894 result[@intFromEnum(Feature.lscp)] = .{
895 .llvm_name = "lscp",
896 .description = "Enable Armv9.7-A Load-acquire and store-release pair extension",
897 .dependencies = featureSet(&[_]Feature{}),
898 };
808 result[@intFromEnum(Feature.lse)] = .{899 result[@intFromEnum(Feature.lse)] = .{
809 .llvm_name = "lse",900 .llvm_name = "lse",
810 .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions",901 .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions",
...@@ -841,6 +932,11 @@ pub const all_features = blk: {...@@ -841,6 +932,11 @@ pub const all_features = blk: {
841 .neon,932 .neon,
842 }),933 }),
843 };934 };
935 result[@intFromEnum(Feature.max_interleave_factor_4)] = .{
936 .llvm_name = "max-interleave-factor-4",
937 .description = "Set the MaxInterleaveFactor to 4 (from the default 2)",
938 .dependencies = featureSet(&[_]Feature{}),
939 };
844 result[@intFromEnum(Feature.mec)] = .{940 result[@intFromEnum(Feature.mec)] = .{
845 .llvm_name = "mec",941 .llvm_name = "mec",
846 .description = "Enable Memory Encryption Contexts Extension",942 .description = "Enable Memory Encryption Contexts Extension",
...@@ -853,16 +949,36 @@ pub const all_features = blk: {...@@ -853,16 +949,36 @@ pub const all_features = blk: {
853 .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",949 .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",
854 .dependencies = featureSet(&[_]Feature{}),950 .dependencies = featureSet(&[_]Feature{}),
855 };951 };
952 result[@intFromEnum(Feature.mops_go)] = .{
953 .llvm_name = "mops-go",
954 .description = "Enable memset acceleration granule only",
955 .dependencies = featureSet(&[_]Feature{
956 .mops,
957 .mte,
958 }),
959 };
856 result[@intFromEnum(Feature.mpam)] = .{960 result[@intFromEnum(Feature.mpam)] = .{
857 .llvm_name = "mpam",961 .llvm_name = "mpam",
858 .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension",962 .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension",
859 .dependencies = featureSet(&[_]Feature{}),963 .dependencies = featureSet(&[_]Feature{}),
860 };964 };
965 result[@intFromEnum(Feature.mpamv2)] = .{
966 .llvm_name = "mpamv2",
967 .description = "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions",
968 .dependencies = featureSet(&[_]Feature{}),
969 };
861 result[@intFromEnum(Feature.mte)] = .{970 result[@intFromEnum(Feature.mte)] = .{
862 .llvm_name = "mte",971 .llvm_name = "mte",
863 .description = "Enable Memory Tagging Extension",972 .description = "Enable Memory Tagging Extension",
864 .dependencies = featureSet(&[_]Feature{}),973 .dependencies = featureSet(&[_]Feature{}),
865 };974 };
975 result[@intFromEnum(Feature.mtetc)] = .{
976 .llvm_name = "mtetc",
977 .description = "Enable Virtual Memory Tagging Extension",
978 .dependencies = featureSet(&[_]Feature{
979 .mte,
980 }),
981 };
866 result[@intFromEnum(Feature.neon)] = .{982 result[@intFromEnum(Feature.neon)] = .{
867 .llvm_name = "neon",983 .llvm_name = "neon",
868 .description = "Enable Advanced SIMD instructions",984 .description = "Enable Advanced SIMD instructions",
...@@ -890,9 +1006,9 @@ pub const all_features = blk: {...@@ -890,9 +1006,9 @@ pub const all_features = blk: {
890 .description = "Avoid using LD1RX instructions for FP",1006 .description = "Avoid using LD1RX instructions for FP",
891 .dependencies = featureSet(&[_]Feature{}),1007 .dependencies = featureSet(&[_]Feature{}),
892 };1008 };
893 result[@intFromEnum(Feature.no_zcz_fp)] = .{1009 result[@intFromEnum(Feature.no_zcz_fpr64)] = .{
894 .llvm_name = "no-zcz-fp",1010 .llvm_name = "no-zcz-fpr64",
895 .description = "Has no zero-cycle zeroing instructions for FP registers",1011 .description = "Has no zero-cycle zeroing instructions for FPR64 registers",
896 .dependencies = featureSet(&[_]Feature{}),1012 .dependencies = featureSet(&[_]Feature{}),
897 };1013 };
898 result[@intFromEnum(Feature.nv)] = .{1014 result[@intFromEnum(Feature.nv)] = .{
...@@ -914,6 +1030,7 @@ pub const all_features = blk: {...@@ -914,6 +1030,7 @@ pub const all_features = blk: {
914 .enable_select_opt,1030 .enable_select_opt,
915 .fuse_adrp_add,1031 .fuse_adrp_add,
916 .fuse_aes,1032 .fuse_aes,
1033 .max_interleave_factor_4,
917 .predictable_select_expensive,1034 .predictable_select_expensive,
918 .use_fixed_over_scalable_if_equal_cost,1035 .use_fixed_over_scalable_if_equal_cost,
919 .use_postra_scheduler,1036 .use_postra_scheduler,
...@@ -956,6 +1073,11 @@ pub const all_features = blk: {...@@ -956,6 +1073,11 @@ pub const all_features = blk: {
956 .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension",1073 .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension",
957 .dependencies = featureSet(&[_]Feature{}),1074 .dependencies = featureSet(&[_]Feature{}),
958 };1075 };
1076 result[@intFromEnum(Feature.poe2)] = .{
1077 .llvm_name = "poe2",
1078 .description = "Enable Stage 1 Permission Overlays Extension 2 instructions",
1079 .dependencies = featureSet(&[_]Feature{}),
1080 };
959 result[@intFromEnum(Feature.pops)] = .{1081 result[@intFromEnum(Feature.pops)] = .{
960 .llvm_name = "pops",1082 .llvm_name = "pops",
961 .description = "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions",1083 .description = "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions",
...@@ -1224,6 +1346,13 @@ pub const all_features = blk: {...@@ -1224,6 +1346,13 @@ pub const all_features = blk: {
1224 .sme2p1,1346 .sme2p1,
1225 }),1347 }),
1226 };1348 };
1349 result[@intFromEnum(Feature.sme2p3)] = .{
1350 .llvm_name = "sme2p3",
1351 .description = "Enable Armv9.7-A Scalable Matrix Extension 2.3 instructions",
1352 .dependencies = featureSet(&[_]Feature{
1353 .sme2p2,
1354 }),
1355 };
1227 result[@intFromEnum(Feature.sme_b16b16)] = .{1356 result[@intFromEnum(Feature.sme_b16b16)] = .{
1228 .llvm_name = "sme-b16b16",1357 .llvm_name = "sme-b16b16",
1229 .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",1358 .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",
...@@ -1447,6 +1576,13 @@ pub const all_features = blk: {...@@ -1447,6 +1576,13 @@ pub const all_features = blk: {
1447 .sve2p1,1576 .sve2p1,
1448 }),1577 }),
1449 };1578 };
1579 result[@intFromEnum(Feature.sve2p3)] = .{
1580 .llvm_name = "sve2p3",
1581 .description = "Enable Armv9.7-A Scalable Vector Extension 2.3 instructions",
1582 .dependencies = featureSet(&[_]Feature{
1583 .sve2p2,
1584 }),
1585 };
1450 result[@intFromEnum(Feature.sve_aes)] = .{1586 result[@intFromEnum(Feature.sve_aes)] = .{
1451 .llvm_name = "sve-aes",1587 .llvm_name = "sve-aes",
1452 .description = "Enable SVE AES and quadword SVE polynomial multiply instructions",1588 .description = "Enable SVE AES and quadword SVE polynomial multiply instructions",
...@@ -1464,6 +1600,13 @@ pub const all_features = blk: {...@@ -1464,6 +1600,13 @@ pub const all_features = blk: {
1464 .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions",1600 .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions",
1465 .dependencies = featureSet(&[_]Feature{}),1601 .dependencies = featureSet(&[_]Feature{}),
1466 };1602 };
1603 result[@intFromEnum(Feature.sve_b16mm)] = .{
1604 .llvm_name = "sve-b16mm",
1605 .description = "Enable Armv9.7-A SVE non-widening BFloat16 matrix multiply-accumulate",
1606 .dependencies = featureSet(&[_]Feature{
1607 .sve,
1608 }),
1609 };
1467 result[@intFromEnum(Feature.sve_bfscale)] = .{1610 result[@intFromEnum(Feature.sve_bfscale)] = .{
1468 .llvm_name = "sve-bfscale",1611 .llvm_name = "sve-bfscale",
1469 .description = "Enable Armv9.6-A SVE BFloat16 scaling instructions",1612 .description = "Enable Armv9.6-A SVE BFloat16 scaling instructions",
...@@ -1500,6 +1643,11 @@ pub const all_features = blk: {...@@ -1500,6 +1643,11 @@ pub const all_features = blk: {
1500 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",1643 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
1501 .dependencies = featureSet(&[_]Feature{}),1644 .dependencies = featureSet(&[_]Feature{}),
1502 };1645 };
1646 result[@intFromEnum(Feature.tev)] = .{
1647 .llvm_name = "tev",
1648 .description = "Enable TIndex Exception-like Vector instructions",
1649 .dependencies = featureSet(&[_]Feature{}),
1650 };
1503 result[@intFromEnum(Feature.the)] = .{1651 result[@intFromEnum(Feature.the)] = .{
1504 .llvm_name = "the",1652 .llvm_name = "the",
1505 .description = "Enable Armv8.9-A Translation Hardening Extension",1653 .description = "Enable Armv8.9-A Translation Hardening Extension",
...@@ -1510,16 +1658,16 @@ pub const all_features = blk: {...@@ -1510,16 +1658,16 @@ pub const all_features = blk: {
1510 .description = "Enable Armv8.4-A TLB Range and Maintenance instructions",1658 .description = "Enable Armv8.4-A TLB Range and Maintenance instructions",
1511 .dependencies = featureSet(&[_]Feature{}),1659 .dependencies = featureSet(&[_]Feature{}),
1512 };1660 };
1661 result[@intFromEnum(Feature.tlbid)] = .{
1662 .llvm_name = "tlbid",
1663 .description = "Enable Armv9.7-A TLBI Domains extension",
1664 .dependencies = featureSet(&[_]Feature{}),
1665 };
1513 result[@intFromEnum(Feature.tlbiw)] = .{1666 result[@intFromEnum(Feature.tlbiw)] = .{
1514 .llvm_name = "tlbiw",1667 .llvm_name = "tlbiw",
1515 .description = "Enable Armv9.5-A TLBI VMALL for Dirty State",1668 .description = "Enable Armv9.5-A TLBI VMALL for Dirty State",
1516 .dependencies = featureSet(&[_]Feature{}),1669 .dependencies = featureSet(&[_]Feature{}),
1517 };1670 };
1518 result[@intFromEnum(Feature.tme)] = .{
1519 .llvm_name = "tme",
1520 .description = "Enable Transactional Memory Extension",
1521 .dependencies = featureSet(&[_]Feature{}),
1522 };
1523 result[@intFromEnum(Feature.tpidr_el1)] = .{1671 result[@intFromEnum(Feature.tpidr_el1)] = .{
1524 .llvm_name = "tpidr-el1",1672 .llvm_name = "tpidr-el1",
1525 .description = "Permit use of TPIDR_EL1 for the TLS base",1673 .description = "Permit use of TPIDR_EL1 for the TLS base",
...@@ -1575,6 +1723,11 @@ pub const all_features = blk: {...@@ -1575,6 +1723,11 @@ pub const all_features = blk: {
1575 .description = "Use the reciprocal square root approximation",1723 .description = "Use the reciprocal square root approximation",
1576 .dependencies = featureSet(&[_]Feature{}),1724 .dependencies = featureSet(&[_]Feature{}),
1577 };1725 };
1726 result[@intFromEnum(Feature.use_wzr_to_vec_move)] = .{
1727 .llvm_name = "use-wzr-to-vec-move",
1728 .description = "Move from WZR to insert 0 into vector registers",
1729 .dependencies = featureSet(&[_]Feature{}),
1730 };
1578 result[@intFromEnum(Feature.v8_1a)] = .{1731 result[@intFromEnum(Feature.v8_1a)] = .{
1579 .llvm_name = "v8.1a",1732 .llvm_name = "v8.1a",
1580 .description = "Support ARM v8.1a architecture",1733 .description = "Support ARM v8.1a architecture",
...@@ -1783,6 +1936,16 @@ pub const all_features = blk: {...@@ -1783,6 +1936,16 @@ pub const all_features = blk: {
1783 .v9_5a,1936 .v9_5a,
1784 }),1937 }),
1785 };1938 };
1939 result[@intFromEnum(Feature.v9_7a)] = .{
1940 .llvm_name = "v9.7a",
1941 .description = "Support ARM v9.7a architecture",
1942 .dependencies = featureSet(&[_]Feature{
1943 .f16f32dot,
1944 .fprcvt,
1945 .sve2p3,
1946 .v9_6a,
1947 }),
1948 };
1786 result[@intFromEnum(Feature.v9a)] = .{1949 result[@intFromEnum(Feature.v9a)] = .{
1787 .llvm_name = "v9a",1950 .llvm_name = "v9a",
1788 .description = "Support ARM v9a architecture",1951 .description = "Support ARM v9a architecture",
...@@ -1808,6 +1971,11 @@ pub const all_features = blk: {...@@ -1808,6 +1971,11 @@ pub const all_features = blk: {
1808 .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",1971 .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
1809 .dependencies = featureSet(&[_]Feature{}),1972 .dependencies = featureSet(&[_]Feature{}),
1810 };1973 };
1974 result[@intFromEnum(Feature.zcm_fpr128)] = .{
1975 .llvm_name = "zcm-fpr128",
1976 .description = "Has zero-cycle register moves for FPR128 registers",
1977 .dependencies = featureSet(&[_]Feature{}),
1978 };
1811 result[@intFromEnum(Feature.zcm_fpr32)] = .{1979 result[@intFromEnum(Feature.zcm_fpr32)] = .{
1812 .llvm_name = "zcm-fpr32",1980 .llvm_name = "zcm-fpr32",
1813 .description = "Has zero-cycle register moves for FPR32 registers",1981 .description = "Has zero-cycle register moves for FPR32 registers",
...@@ -1828,21 +1996,24 @@ pub const all_features = blk: {...@@ -1828,21 +1996,24 @@ pub const all_features = blk: {
1828 .description = "Has zero-cycle register moves for GPR64 registers",1996 .description = "Has zero-cycle register moves for GPR64 registers",
1829 .dependencies = featureSet(&[_]Feature{}),1997 .dependencies = featureSet(&[_]Feature{}),
1830 };1998 };
1831 result[@intFromEnum(Feature.zcz)] = .{
1832 .llvm_name = "zcz",
1833 .description = "Has zero-cycle zeroing instructions",
1834 .dependencies = featureSet(&[_]Feature{
1835 .zcz_gp,
1836 }),
1837 };
1838 result[@intFromEnum(Feature.zcz_fp_workaround)] = .{1999 result[@intFromEnum(Feature.zcz_fp_workaround)] = .{
1839 .llvm_name = "zcz-fp-workaround",2000 .llvm_name = "zcz-fp-workaround",
1840 .description = "The zero-cycle floating-point zeroing instruction has a bug",2001 .description = "The zero-cycle floating-point zeroing instruction has a bug",
1841 .dependencies = featureSet(&[_]Feature{}),2002 .dependencies = featureSet(&[_]Feature{}),
1842 };2003 };
1843 result[@intFromEnum(Feature.zcz_gp)] = .{2004 result[@intFromEnum(Feature.zcz_fpr128)] = .{
1844 .llvm_name = "zcz-gp",2005 .llvm_name = "zcz-fpr128",
1845 .description = "Has zero-cycle zeroing instructions for generic registers",2006 .description = "Has zero-cycle zeroing instructions for FPR128 registers",
2007 .dependencies = featureSet(&[_]Feature{}),
2008 };
2009 result[@intFromEnum(Feature.zcz_gpr32)] = .{
2010 .llvm_name = "zcz-gpr32",
2011 .description = "Has zero-cycle zeroing instructions for GPR32 registers",
2012 .dependencies = featureSet(&[_]Feature{}),
2013 };
2014 result[@intFromEnum(Feature.zcz_gpr64)] = .{
2015 .llvm_name = "zcz-gpr64",
2016 .description = "Has zero-cycle zeroing instructions for GPR64 registers",
1846 .dependencies = featureSet(&[_]Feature{}),2017 .dependencies = featureSet(&[_]Feature{}),
1847 };2018 };
1848 const ti = @typeInfo(Feature);2019 const ti = @typeInfo(Feature);
...@@ -1862,6 +2033,8 @@ pub const cpu = struct {...@@ -1862,6 +2033,8 @@ pub const cpu = struct {
1862 .aggressive_fma,2033 .aggressive_fma,
1863 .arith_bcc_fusion,2034 .arith_bcc_fusion,
1864 .complxnum,2035 .complxnum,
2036 .disable_unpredicated_ld_st_lower,
2037 .max_interleave_factor_4,
1865 .perfmon,2038 .perfmon,
1866 .predictable_select_expensive,2039 .predictable_select_expensive,
1867 .sha2,2040 .sha2,
...@@ -1886,6 +2059,7 @@ pub const cpu = struct {...@@ -1886,6 +2059,7 @@ pub const cpu = struct {
1886 .fuse_aes,2059 .fuse_aes,
1887 .fuse_literals,2060 .fuse_literals,
1888 .ldp_aligned_only,2061 .ldp_aligned_only,
2062 .max_interleave_factor_4,
1889 .perfmon,2063 .perfmon,
1890 .rand,2064 .rand,
1891 .sha3,2065 .sha3,
...@@ -1911,6 +2085,7 @@ pub const cpu = struct {...@@ -1911,6 +2085,7 @@ pub const cpu = struct {
1911 .fuse_aes,2085 .fuse_aes,
1912 .fuse_literals,2086 .fuse_literals,
1913 .ldp_aligned_only,2087 .ldp_aligned_only,
2088 .max_interleave_factor_4,
1914 .mte,2089 .mte,
1915 .perfmon,2090 .perfmon,
1916 .rand,2091 .rand,
...@@ -1939,6 +2114,7 @@ pub const cpu = struct {...@@ -1939,6 +2114,7 @@ pub const cpu = struct {
1939 .fuse_aes,2114 .fuse_aes,
1940 .fuse_literals,2115 .fuse_literals,
1941 .ldp_aligned_only,2116 .ldp_aligned_only,
2117 .max_interleave_factor_4,
1942 .mte,2118 .mte,
1943 .perfmon,2119 .perfmon,
1944 .predictable_select_expensive,2120 .predictable_select_expensive,
...@@ -1951,6 +2127,38 @@ pub const cpu = struct {...@@ -1951,6 +2127,38 @@ pub const cpu = struct {
1951 .v8_7a,2127 .v8_7a,
1952 }),2128 }),
1953 };2129 };
2130 pub const ampere1c: CpuModel = .{
2131 .name = "ampere1c",
2132 .llvm_name = "ampere1c",
2133 .features = featureSet(&[_]Feature{
2134 .aggressive_fma,
2135 .alu_lsl_fast,
2136 .arith_bcc_fusion,
2137 .cmp_bcc_fusion,
2138 .cssc,
2139 .enable_select_opt,
2140 .faminmax,
2141 .fp16fml,
2142 .fp8fma,
2143 .fuse_address,
2144 .fuse_adrp_add,
2145 .fuse_aes,
2146 .fuse_literals,
2147 .lut,
2148 .max_interleave_factor_4,
2149 .mte,
2150 .perfmon,
2151 .predictable_select_expensive,
2152 .rand,
2153 .store_pair_suppress,
2154 .sve_aes,
2155 .sve_b16b16,
2156 .sve_sha3,
2157 .sve_sm4,
2158 .use_postra_scheduler,
2159 .v9_2a,
2160 }),
2161 };
1954 pub const apple_a10: CpuModel = .{2162 pub const apple_a10: CpuModel = .{
1955 .name = "apple_a10",2163 .name = "apple_a10",
1956 .llvm_name = "apple-a10",2164 .llvm_name = "apple-a10",
...@@ -1964,6 +2172,7 @@ pub const cpu = struct {...@@ -1964,6 +2172,7 @@ pub const cpu = struct {
1964 .fuse_aes,2172 .fuse_aes,
1965 .fuse_crypto_eor,2173 .fuse_crypto_eor,
1966 .lor,2174 .lor,
2175 .no_zcz_fpr64,
1967 .pan,2176 .pan,
1968 .perfmon,2177 .perfmon,
1969 .rdm,2178 .rdm,
...@@ -1971,9 +2180,11 @@ pub const cpu = struct {...@@ -1971,9 +2180,11 @@ pub const cpu = struct {
1971 .store_pair_suppress,2180 .store_pair_suppress,
1972 .v8a,2181 .v8a,
1973 .vh,2182 .vh,
1974 .zcm_fpr64,2183 .zcm_fpr128,
1975 .zcm_gpr64,2184 .zcm_gpr64,
1976 .zcz,2185 .zcz_fpr128,
2186 .zcz_gpr32,
2187 .zcz_gpr64,
1977 }),2188 }),
1978 };2189 };
1979 pub const apple_a11: CpuModel = .{2190 pub const apple_a11: CpuModel = .{
...@@ -1988,13 +2199,16 @@ pub const cpu = struct {...@@ -1988,13 +2199,16 @@ pub const cpu = struct {
1988 .fullfp16,2199 .fullfp16,
1989 .fuse_aes,2200 .fuse_aes,
1990 .fuse_crypto_eor,2201 .fuse_crypto_eor,
2202 .no_zcz_fpr64,
1991 .perfmon,2203 .perfmon,
1992 .sha2,2204 .sha2,
1993 .store_pair_suppress,2205 .store_pair_suppress,
1994 .v8_2a,2206 .v8_2a,
1995 .zcm_fpr64,2207 .zcm_fpr128,
1996 .zcm_gpr64,2208 .zcm_gpr64,
1997 .zcz,2209 .zcz_fpr128,
2210 .zcz_gpr32,
2211 .zcz_gpr64,
1998 }),2212 }),
1999 };2213 };
2000 pub const apple_a12: CpuModel = .{2214 pub const apple_a12: CpuModel = .{
...@@ -2009,13 +2223,16 @@ pub const cpu = struct {...@@ -2009,13 +2223,16 @@ pub const cpu = struct {
2009 .fullfp16,2223 .fullfp16,
2010 .fuse_aes,2224 .fuse_aes,
2011 .fuse_crypto_eor,2225 .fuse_crypto_eor,
2226 .no_zcz_fpr64,
2012 .perfmon,2227 .perfmon,
2013 .sha2,2228 .sha2,
2014 .store_pair_suppress,2229 .store_pair_suppress,
2015 .v8_3a,2230 .v8_3a,
2016 .zcm_fpr64,2231 .zcm_fpr128,
2017 .zcm_gpr64,2232 .zcm_gpr64,
2018 .zcz,2233 .zcz_fpr128,
2234 .zcz_gpr32,
2235 .zcz_gpr64,
2019 }),2236 }),
2020 };2237 };
2021 pub const apple_a13: CpuModel = .{2238 pub const apple_a13: CpuModel = .{
...@@ -2030,13 +2247,16 @@ pub const cpu = struct {...@@ -2030,13 +2247,16 @@ pub const cpu = struct {
2030 .fp16fml,2247 .fp16fml,
2031 .fuse_aes,2248 .fuse_aes,
2032 .fuse_crypto_eor,2249 .fuse_crypto_eor,
2250 .no_zcz_fpr64,
2033 .perfmon,2251 .perfmon,
2034 .sha3,2252 .sha3,
2035 .store_pair_suppress,2253 .store_pair_suppress,
2036 .v8_4a,2254 .v8_4a,
2037 .zcm_fpr64,2255 .zcm_fpr128,
2038 .zcm_gpr64,2256 .zcm_gpr64,
2039 .zcz,2257 .zcz_fpr128,
2258 .zcz_gpr32,
2259 .zcz_gpr64,
2040 }),2260 }),
2041 };2261 };
2042 pub const apple_a14: CpuModel = .{2262 pub const apple_a14: CpuModel = .{
...@@ -2059,6 +2279,8 @@ pub const cpu = struct {...@@ -2059,6 +2279,8 @@ pub const cpu = struct {
2059 .fuse_crypto_eor,2279 .fuse_crypto_eor,
2060 .fuse_csel,2280 .fuse_csel,
2061 .fuse_literals,2281 .fuse_literals,
2282 .max_interleave_factor_4,
2283 .no_zcz_fpr64,
2062 .perfmon,2284 .perfmon,
2063 .predres,2285 .predres,
2064 .sb,2286 .sb,
...@@ -2067,9 +2289,11 @@ pub const cpu = struct {...@@ -2067,9 +2289,11 @@ pub const cpu = struct {
2067 .ssbs,2289 .ssbs,
2068 .store_pair_suppress,2290 .store_pair_suppress,
2069 .v8_4a,2291 .v8_4a,
2070 .zcm_fpr64,2292 .zcm_fpr128,
2071 .zcm_gpr64,2293 .zcm_gpr64,
2072 .zcz,2294 .zcz_fpr128,
2295 .zcz_gpr32,
2296 .zcz_gpr64,
2073 }),2297 }),
2074 };2298 };
2075 pub const apple_a15: CpuModel = .{2299 pub const apple_a15: CpuModel = .{
...@@ -2090,13 +2314,17 @@ pub const cpu = struct {...@@ -2090,13 +2314,17 @@ pub const cpu = struct {
2090 .fuse_crypto_eor,2314 .fuse_crypto_eor,
2091 .fuse_csel,2315 .fuse_csel,
2092 .fuse_literals,2316 .fuse_literals,
2317 .max_interleave_factor_4,
2318 .no_zcz_fpr64,
2093 .perfmon,2319 .perfmon,
2094 .sha3,2320 .sha3,
2095 .store_pair_suppress,2321 .store_pair_suppress,
2096 .v8_6a,2322 .v8_6a,
2097 .zcm_fpr64,2323 .zcm_fpr128,
2098 .zcm_gpr64,2324 .zcm_gpr64,
2099 .zcz,2325 .zcz_fpr128,
2326 .zcz_gpr32,
2327 .zcz_gpr64,
2100 }),2328 }),
2101 };2329 };
2102 pub const apple_a16: CpuModel = .{2330 pub const apple_a16: CpuModel = .{
...@@ -2118,13 +2346,17 @@ pub const cpu = struct {...@@ -2118,13 +2346,17 @@ pub const cpu = struct {
2118 .fuse_csel,2346 .fuse_csel,
2119 .fuse_literals,2347 .fuse_literals,
2120 .hcx,2348 .hcx,
2349 .max_interleave_factor_4,
2350 .no_zcz_fpr64,
2121 .perfmon,2351 .perfmon,
2122 .sha3,2352 .sha3,
2123 .store_pair_suppress,2353 .store_pair_suppress,
2124 .v8_6a,2354 .v8_6a,
2125 .zcm_fpr64,2355 .zcm_fpr128,
2126 .zcm_gpr64,2356 .zcm_gpr64,
2127 .zcz,2357 .zcz_fpr128,
2358 .zcz_gpr32,
2359 .zcz_gpr64,
2128 }),2360 }),
2129 };2361 };
2130 pub const apple_a17: CpuModel = .{2362 pub const apple_a17: CpuModel = .{
...@@ -2146,13 +2378,17 @@ pub const cpu = struct {...@@ -2146,13 +2378,17 @@ pub const cpu = struct {
2146 .fuse_csel,2378 .fuse_csel,
2147 .fuse_literals,2379 .fuse_literals,
2148 .hcx,2380 .hcx,
2381 .max_interleave_factor_4,
2382 .no_zcz_fpr64,
2149 .perfmon,2383 .perfmon,
2150 .sha3,2384 .sha3,
2151 .store_pair_suppress,2385 .store_pair_suppress,
2152 .v8_6a,2386 .v8_6a,
2153 .zcm_fpr64,2387 .zcm_fpr128,
2154 .zcm_gpr64,2388 .zcm_gpr64,
2155 .zcz,2389 .zcz_fpr128,
2390 .zcz_gpr32,
2391 .zcz_gpr64,
2156 }),2392 }),
2157 };2393 };
2158 pub const apple_a18: CpuModel = .{2394 pub const apple_a18: CpuModel = .{
...@@ -2173,15 +2409,58 @@ pub const cpu = struct {...@@ -2173,15 +2409,58 @@ pub const cpu = struct {
2173 .fuse_crypto_eor,2409 .fuse_crypto_eor,
2174 .fuse_csel,2410 .fuse_csel,
2175 .fuse_literals,2411 .fuse_literals,
2412 .max_interleave_factor_4,
2413 .no_zcz_fpr64,
2176 .perfmon,2414 .perfmon,
2177 .sha3,2415 .sha3,
2178 .sme2,2416 .sme2,
2179 .sme_f64f64,2417 .sme_f64f64,
2180 .sme_i16i64,2418 .sme_i16i64,
2181 .v8_7a,2419 .v8_7a,
2182 .zcm_fpr64,2420 .zcm_fpr128,
2183 .zcm_gpr64,2421 .zcm_gpr64,
2184 .zcz,2422 .zcz_fpr128,
2423 .zcz_gpr32,
2424 .zcz_gpr64,
2425 }),
2426 };
2427 pub const apple_a19: CpuModel = .{
2428 .name = "apple_a19",
2429 .llvm_name = "apple-a19",
2430 .features = featureSet(&[_]Feature{
2431 .aes,
2432 .alternate_sextload_cvt_f32_pattern,
2433 .arith_bcc_fusion,
2434 .arith_cbz_fusion,
2435 .cssc,
2436 .disable_latency_sched_heuristic,
2437 .fp16fml,
2438 .fpac,
2439 .fuse_address,
2440 .fuse_adrp_add,
2441 .fuse_aes,
2442 .fuse_arith_logic,
2443 .fuse_crypto_eor,
2444 .fuse_csel,
2445 .fuse_literals,
2446 .hbc,
2447 .max_interleave_factor_4,
2448 .mte,
2449 .no_zcz_fpr64,
2450 .perfmon,
2451 .sha3,
2452 .sme2p1,
2453 .sme_b16b16,
2454 .sme_f16f16,
2455 .sme_f64f64,
2456 .sme_i16i64,
2457 .specres2,
2458 .v8_7a,
2459 .zcm_fpr128,
2460 .zcm_gpr64,
2461 .zcz_fpr128,
2462 .zcz_gpr32,
2463 .zcz_gpr64,
2185 }),2464 }),
2186 };2465 };
2187 pub const apple_a7: CpuModel = .{2466 pub const apple_a7: CpuModel = .{
...@@ -2195,14 +2474,17 @@ pub const cpu = struct {...@@ -2195,14 +2474,17 @@ pub const cpu = struct {
2195 .disable_latency_sched_heuristic,2474 .disable_latency_sched_heuristic,
2196 .fuse_aes,2475 .fuse_aes,
2197 .fuse_crypto_eor,2476 .fuse_crypto_eor,
2477 .no_zcz_fpr64,
2198 .perfmon,2478 .perfmon,
2199 .sha2,2479 .sha2,
2200 .store_pair_suppress,2480 .store_pair_suppress,
2201 .v8a,2481 .v8a,
2202 .zcm_fpr64,2482 .zcm_fpr128,
2203 .zcm_gpr64,2483 .zcm_gpr64,
2204 .zcz,
2205 .zcz_fp_workaround,2484 .zcz_fp_workaround,
2485 .zcz_fpr128,
2486 .zcz_gpr32,
2487 .zcz_gpr64,
2206 }),2488 }),
2207 };2489 };
2208 pub const apple_a8: CpuModel = .{2490 pub const apple_a8: CpuModel = .{
...@@ -2216,14 +2498,17 @@ pub const cpu = struct {...@@ -2216,14 +2498,17 @@ pub const cpu = struct {
2216 .disable_latency_sched_heuristic,2498 .disable_latency_sched_heuristic,
2217 .fuse_aes,2499 .fuse_aes,
2218 .fuse_crypto_eor,2500 .fuse_crypto_eor,
2501 .no_zcz_fpr64,
2219 .perfmon,2502 .perfmon,
2220 .sha2,2503 .sha2,
2221 .store_pair_suppress,2504 .store_pair_suppress,
2222 .v8a,2505 .v8a,
2223 .zcm_fpr64,2506 .zcm_fpr128,
2224 .zcm_gpr64,2507 .zcm_gpr64,
2225 .zcz,
2226 .zcz_fp_workaround,2508 .zcz_fp_workaround,
2509 .zcz_fpr128,
2510 .zcz_gpr32,
2511 .zcz_gpr64,
2227 }),2512 }),
2228 };2513 };
2229 pub const apple_a9: CpuModel = .{2514 pub const apple_a9: CpuModel = .{
...@@ -2237,14 +2522,17 @@ pub const cpu = struct {...@@ -2237,14 +2522,17 @@ pub const cpu = struct {
2237 .disable_latency_sched_heuristic,2522 .disable_latency_sched_heuristic,
2238 .fuse_aes,2523 .fuse_aes,
2239 .fuse_crypto_eor,2524 .fuse_crypto_eor,
2525 .no_zcz_fpr64,
2240 .perfmon,2526 .perfmon,
2241 .sha2,2527 .sha2,
2242 .store_pair_suppress,2528 .store_pair_suppress,
2243 .v8a,2529 .v8a,
2244 .zcm_fpr64,2530 .zcm_fpr128,
2245 .zcm_gpr64,2531 .zcm_gpr64,
2246 .zcz,
2247 .zcz_fp_workaround,2532 .zcz_fp_workaround,
2533 .zcz_fpr128,
2534 .zcz_gpr32,
2535 .zcz_gpr64,
2248 }),2536 }),
2249 };2537 };
2250 pub const apple_m1: CpuModel = .{2538 pub const apple_m1: CpuModel = .{
...@@ -2267,6 +2555,8 @@ pub const cpu = struct {...@@ -2267,6 +2555,8 @@ pub const cpu = struct {
2267 .fuse_crypto_eor,2555 .fuse_crypto_eor,
2268 .fuse_csel,2556 .fuse_csel,
2269 .fuse_literals,2557 .fuse_literals,
2558 .max_interleave_factor_4,
2559 .no_zcz_fpr64,
2270 .perfmon,2560 .perfmon,
2271 .predres,2561 .predres,
2272 .sb,2562 .sb,
...@@ -2275,9 +2565,11 @@ pub const cpu = struct {...@@ -2275,9 +2565,11 @@ pub const cpu = struct {
2275 .ssbs,2565 .ssbs,
2276 .store_pair_suppress,2566 .store_pair_suppress,
2277 .v8_4a,2567 .v8_4a,
2278 .zcm_fpr64,2568 .zcm_fpr128,
2279 .zcm_gpr64,2569 .zcm_gpr64,
2280 .zcz,2570 .zcz_fpr128,
2571 .zcz_gpr32,
2572 .zcz_gpr64,
2281 }),2573 }),
2282 };2574 };
2283 pub const apple_m2: CpuModel = .{2575 pub const apple_m2: CpuModel = .{
...@@ -2298,13 +2590,17 @@ pub const cpu = struct {...@@ -2298,13 +2590,17 @@ pub const cpu = struct {
2298 .fuse_crypto_eor,2590 .fuse_crypto_eor,
2299 .fuse_csel,2591 .fuse_csel,
2300 .fuse_literals,2592 .fuse_literals,
2593 .max_interleave_factor_4,
2594 .no_zcz_fpr64,
2301 .perfmon,2595 .perfmon,
2302 .sha3,2596 .sha3,
2303 .store_pair_suppress,2597 .store_pair_suppress,
2304 .v8_6a,2598 .v8_6a,
2305 .zcm_fpr64,2599 .zcm_fpr128,
2306 .zcm_gpr64,2600 .zcm_gpr64,
2307 .zcz,2601 .zcz_fpr128,
2602 .zcz_gpr32,
2603 .zcz_gpr64,
2308 }),2604 }),
2309 };2605 };
2310 pub const apple_m3: CpuModel = .{2606 pub const apple_m3: CpuModel = .{
...@@ -2326,13 +2622,17 @@ pub const cpu = struct {...@@ -2326,13 +2622,17 @@ pub const cpu = struct {
2326 .fuse_csel,2622 .fuse_csel,
2327 .fuse_literals,2623 .fuse_literals,
2328 .hcx,2624 .hcx,
2625 .max_interleave_factor_4,
2626 .no_zcz_fpr64,
2329 .perfmon,2627 .perfmon,
2330 .sha3,2628 .sha3,
2331 .store_pair_suppress,2629 .store_pair_suppress,
2332 .v8_6a,2630 .v8_6a,
2333 .zcm_fpr64,2631 .zcm_fpr128,
2334 .zcm_gpr64,2632 .zcm_gpr64,
2335 .zcz,2633 .zcz_fpr128,
2634 .zcz_gpr32,
2635 .zcz_gpr64,
2336 }),2636 }),
2337 };2637 };
2338 pub const apple_m4: CpuModel = .{2638 pub const apple_m4: CpuModel = .{
...@@ -2353,15 +2653,58 @@ pub const cpu = struct {...@@ -2353,15 +2653,58 @@ pub const cpu = struct {
2353 .fuse_crypto_eor,2653 .fuse_crypto_eor,
2354 .fuse_csel,2654 .fuse_csel,
2355 .fuse_literals,2655 .fuse_literals,
2656 .max_interleave_factor_4,
2657 .no_zcz_fpr64,
2356 .perfmon,2658 .perfmon,
2357 .sha3,2659 .sha3,
2358 .sme2,2660 .sme2,
2359 .sme_f64f64,2661 .sme_f64f64,
2360 .sme_i16i64,2662 .sme_i16i64,
2361 .v8_7a,2663 .v8_7a,
2362 .zcm_fpr64,2664 .zcm_fpr128,
2665 .zcm_gpr64,
2666 .zcz_fpr128,
2667 .zcz_gpr32,
2668 .zcz_gpr64,
2669 }),
2670 };
2671 pub const apple_m5: CpuModel = .{
2672 .name = "apple_m5",
2673 .llvm_name = "apple-m5",
2674 .features = featureSet(&[_]Feature{
2675 .aes,
2676 .alternate_sextload_cvt_f32_pattern,
2677 .arith_bcc_fusion,
2678 .arith_cbz_fusion,
2679 .cssc,
2680 .disable_latency_sched_heuristic,
2681 .fp16fml,
2682 .fpac,
2683 .fuse_address,
2684 .fuse_adrp_add,
2685 .fuse_aes,
2686 .fuse_arith_logic,
2687 .fuse_crypto_eor,
2688 .fuse_csel,
2689 .fuse_literals,
2690 .hbc,
2691 .max_interleave_factor_4,
2692 .mte,
2693 .no_zcz_fpr64,
2694 .perfmon,
2695 .sha3,
2696 .sme2p1,
2697 .sme_b16b16,
2698 .sme_f16f16,
2699 .sme_f64f64,
2700 .sme_i16i64,
2701 .specres2,
2702 .v8_7a,
2703 .zcm_fpr128,
2363 .zcm_gpr64,2704 .zcm_gpr64,
2364 .zcz,2705 .zcz_fpr128,
2706 .zcz_gpr32,
2707 .zcz_gpr64,
2365 }),2708 }),
2366 };2709 };
2367 pub const apple_s10: CpuModel = .{2710 pub const apple_s10: CpuModel = .{
...@@ -2383,13 +2726,17 @@ pub const cpu = struct {...@@ -2383,13 +2726,17 @@ pub const cpu = struct {
2383 .fuse_csel,2726 .fuse_csel,
2384 .fuse_literals,2727 .fuse_literals,
2385 .hcx,2728 .hcx,
2729 .max_interleave_factor_4,
2730 .no_zcz_fpr64,
2386 .perfmon,2731 .perfmon,
2387 .sha3,2732 .sha3,
2388 .store_pair_suppress,2733 .store_pair_suppress,
2389 .v8_6a,2734 .v8_6a,
2390 .zcm_fpr64,2735 .zcm_fpr128,
2391 .zcm_gpr64,2736 .zcm_gpr64,
2392 .zcz,2737 .zcz_fpr128,
2738 .zcz_gpr32,
2739 .zcz_gpr64,
2393 }),2740 }),
2394 };2741 };
2395 pub const apple_s4: CpuModel = .{2742 pub const apple_s4: CpuModel = .{
...@@ -2404,13 +2751,16 @@ pub const cpu = struct {...@@ -2404,13 +2751,16 @@ pub const cpu = struct {
2404 .fullfp16,2751 .fullfp16,
2405 .fuse_aes,2752 .fuse_aes,
2406 .fuse_crypto_eor,2753 .fuse_crypto_eor,
2754 .no_zcz_fpr64,
2407 .perfmon,2755 .perfmon,
2408 .sha2,2756 .sha2,
2409 .store_pair_suppress,2757 .store_pair_suppress,
2410 .v8_3a,2758 .v8_3a,
2411 .zcm_fpr64,2759 .zcm_fpr128,
2412 .zcm_gpr64,2760 .zcm_gpr64,
2413 .zcz,2761 .zcz_fpr128,
2762 .zcz_gpr32,
2763 .zcz_gpr64,
2414 }),2764 }),
2415 };2765 };
2416 pub const apple_s5: CpuModel = .{2766 pub const apple_s5: CpuModel = .{
...@@ -2425,13 +2775,16 @@ pub const cpu = struct {...@@ -2425,13 +2775,16 @@ pub const cpu = struct {
2425 .fullfp16,2775 .fullfp16,
2426 .fuse_aes,2776 .fuse_aes,
2427 .fuse_crypto_eor,2777 .fuse_crypto_eor,
2778 .no_zcz_fpr64,
2428 .perfmon,2779 .perfmon,
2429 .sha2,2780 .sha2,
2430 .store_pair_suppress,2781 .store_pair_suppress,
2431 .v8_3a,2782 .v8_3a,
2432 .zcm_fpr64,2783 .zcm_fpr128,
2433 .zcm_gpr64,2784 .zcm_gpr64,
2434 .zcz,2785 .zcz_fpr128,
2786 .zcz_gpr32,
2787 .zcz_gpr64,
2435 }),2788 }),
2436 };2789 };
2437 pub const apple_s6: CpuModel = .{2790 pub const apple_s6: CpuModel = .{
...@@ -2446,13 +2799,16 @@ pub const cpu = struct {...@@ -2446,13 +2799,16 @@ pub const cpu = struct {
2446 .fp16fml,2799 .fp16fml,
2447 .fuse_aes,2800 .fuse_aes,
2448 .fuse_crypto_eor,2801 .fuse_crypto_eor,
2802 .no_zcz_fpr64,
2449 .perfmon,2803 .perfmon,
2450 .sha3,2804 .sha3,
2451 .store_pair_suppress,2805 .store_pair_suppress,
2452 .v8_4a,2806 .v8_4a,
2453 .zcm_fpr64,2807 .zcm_fpr128,
2454 .zcm_gpr64,2808 .zcm_gpr64,
2455 .zcz,2809 .zcz_fpr128,
2810 .zcz_gpr32,
2811 .zcz_gpr64,
2456 }),2812 }),
2457 };2813 };
2458 pub const apple_s7: CpuModel = .{2814 pub const apple_s7: CpuModel = .{
...@@ -2467,13 +2823,16 @@ pub const cpu = struct {...@@ -2467,13 +2823,16 @@ pub const cpu = struct {
2467 .fp16fml,2823 .fp16fml,
2468 .fuse_aes,2824 .fuse_aes,
2469 .fuse_crypto_eor,2825 .fuse_crypto_eor,
2826 .no_zcz_fpr64,
2470 .perfmon,2827 .perfmon,
2471 .sha3,2828 .sha3,
2472 .store_pair_suppress,2829 .store_pair_suppress,
2473 .v8_4a,2830 .v8_4a,
2474 .zcm_fpr64,2831 .zcm_fpr128,
2475 .zcm_gpr64,2832 .zcm_gpr64,
2476 .zcz,2833 .zcz_fpr128,
2834 .zcz_gpr32,
2835 .zcz_gpr64,
2477 }),2836 }),
2478 };2837 };
2479 pub const apple_s8: CpuModel = .{2838 pub const apple_s8: CpuModel = .{
...@@ -2488,13 +2847,16 @@ pub const cpu = struct {...@@ -2488,13 +2847,16 @@ pub const cpu = struct {
2488 .fp16fml,2847 .fp16fml,
2489 .fuse_aes,2848 .fuse_aes,
2490 .fuse_crypto_eor,2849 .fuse_crypto_eor,
2850 .no_zcz_fpr64,
2491 .perfmon,2851 .perfmon,
2492 .sha3,2852 .sha3,
2493 .store_pair_suppress,2853 .store_pair_suppress,
2494 .v8_4a,2854 .v8_4a,
2495 .zcm_fpr64,2855 .zcm_fpr128,
2496 .zcm_gpr64,2856 .zcm_gpr64,
2497 .zcz,2857 .zcz_fpr128,
2858 .zcz_gpr32,
2859 .zcz_gpr64,
2498 }),2860 }),
2499 };2861 };
2500 pub const apple_s9: CpuModel = .{2862 pub const apple_s9: CpuModel = .{
...@@ -2516,13 +2878,126 @@ pub const cpu = struct {...@@ -2516,13 +2878,126 @@ pub const cpu = struct {
2516 .fuse_csel,2878 .fuse_csel,
2517 .fuse_literals,2879 .fuse_literals,
2518 .hcx,2880 .hcx,
2881 .max_interleave_factor_4,
2882 .no_zcz_fpr64,
2519 .perfmon,2883 .perfmon,
2520 .sha3,2884 .sha3,
2521 .store_pair_suppress,2885 .store_pair_suppress,
2522 .v8_6a,2886 .v8_6a,
2523 .zcm_fpr64,2887 .zcm_fpr128,
2524 .zcm_gpr64,2888 .zcm_gpr64,
2525 .zcz,2889 .zcz_fpr128,
2890 .zcz_gpr32,
2891 .zcz_gpr64,
2892 }),
2893 };
2894 pub const c1_nano: CpuModel = .{
2895 .name = "c1_nano",
2896 .llvm_name = "c1-nano",
2897 .features = featureSet(&[_]Feature{
2898 .chk,
2899 .clrbhb,
2900 .ete,
2901 .fp16fml,
2902 .fpac,
2903 .fuse_adrp_add,
2904 .fuse_aes,
2905 .mte,
2906 .perfmon,
2907 .rcpc3,
2908 .sme2,
2909 .specres2,
2910 .sve_bitperm,
2911 .use_fixed_over_scalable_if_equal_cost,
2912 .use_postra_scheduler,
2913 .use_wzr_to_vec_move,
2914 .v9_3a,
2915 }),
2916 };
2917 pub const c1_premium: CpuModel = .{
2918 .name = "c1_premium",
2919 .llvm_name = "c1-premium",
2920 .features = featureSet(&[_]Feature{
2921 .alu_lsl_fast,
2922 .avoid_ldapur,
2923 .chk,
2924 .clrbhb,
2925 .enable_select_opt,
2926 .ete,
2927 .fp16fml,
2928 .fpac,
2929 .fuse_adrp_add,
2930 .fuse_aes,
2931 .fuse_csel,
2932 .fuse_cset,
2933 .mte,
2934 .perfmon,
2935 .predictable_select_expensive,
2936 .rcpc3,
2937 .sme2,
2938 .spe,
2939 .specres2,
2940 .sve_bitperm,
2941 .use_fixed_over_scalable_if_equal_cost,
2942 .use_postra_scheduler,
2943 .v9_3a,
2944 }),
2945 };
2946 pub const c1_pro: CpuModel = .{
2947 .name = "c1_pro",
2948 .llvm_name = "c1-pro",
2949 .features = featureSet(&[_]Feature{
2950 .alu_lsl_fast,
2951 .chk,
2952 .clrbhb,
2953 .cmp_bcc_fusion,
2954 .enable_select_opt,
2955 .ete,
2956 .fp16fml,
2957 .fpac,
2958 .fuse_adrp_add,
2959 .fuse_aes,
2960 .fuse_csel,
2961 .fuse_cset,
2962 .mte,
2963 .perfmon,
2964 .predictable_select_expensive,
2965 .rcpc3,
2966 .sme2,
2967 .spe,
2968 .specres2,
2969 .sve_bitperm,
2970 .use_postra_scheduler,
2971 .v9_3a,
2972 }),
2973 };
2974 pub const c1_ultra: CpuModel = .{
2975 .name = "c1_ultra",
2976 .llvm_name = "c1-ultra",
2977 .features = featureSet(&[_]Feature{
2978 .alu_lsl_fast,
2979 .avoid_ldapur,
2980 .chk,
2981 .clrbhb,
2982 .enable_select_opt,
2983 .ete,
2984 .fp16fml,
2985 .fpac,
2986 .fuse_adrp_add,
2987 .fuse_aes,
2988 .fuse_csel,
2989 .fuse_cset,
2990 .mte,
2991 .perfmon,
2992 .predictable_select_expensive,
2993 .rcpc3,
2994 .sme2,
2995 .spe,
2996 .specres2,
2997 .sve_bitperm,
2998 .use_fixed_over_scalable_if_equal_cost,
2999 .use_postra_scheduler,
3000 .v9_3a,
2526 }),3001 }),
2527 };3002 };
2528 pub const carmel: CpuModel = .{3003 pub const carmel: CpuModel = .{
...@@ -2541,12 +3016,15 @@ pub const cpu = struct {...@@ -2541,12 +3016,15 @@ pub const cpu = struct {
2541 .features = featureSet(&[_]Feature{3016 .features = featureSet(&[_]Feature{
2542 .alu_lsl_fast,3017 .alu_lsl_fast,
2543 .bf16,3018 .bf16,
3019 .disable_maximize_scalable_bandwidth,
2544 .enable_select_opt,3020 .enable_select_opt,
2545 .ete,3021 .ete,
2546 .fp16fml,3022 .fp16fml,
2547 .fpac,3023 .fpac,
2548 .fuse_adrp_add,3024 .fuse_adrp_add,
2549 .fuse_aes,3025 .fuse_aes,
3026 .fuse_csel,
3027 .fuse_cset,
2550 .i8mm,3028 .i8mm,
2551 .mte,3029 .mte,
2552 .perfmon,3030 .perfmon,
...@@ -2607,6 +3085,7 @@ pub const cpu = struct {...@@ -2607,6 +3085,7 @@ pub const cpu = struct {
2607 .sve_bitperm,3085 .sve_bitperm,
2608 .use_fixed_over_scalable_if_equal_cost,3086 .use_fixed_over_scalable_if_equal_cost,
2609 .use_postra_scheduler,3087 .use_postra_scheduler,
3088 .use_wzr_to_vec_move,
2610 .v9a,3089 .v9a,
2611 }),3090 }),
2612 };3091 };
...@@ -2624,6 +3103,7 @@ pub const cpu = struct {...@@ -2624,6 +3103,7 @@ pub const cpu = struct {
2624 .sve_bitperm,3103 .sve_bitperm,
2625 .use_fixed_over_scalable_if_equal_cost,3104 .use_fixed_over_scalable_if_equal_cost,
2626 .use_postra_scheduler,3105 .use_postra_scheduler,
3106 .use_wzr_to_vec_move,
2627 .v9_2a,3107 .v9_2a,
2628 }),3108 }),
2629 };3109 };
...@@ -2640,6 +3120,7 @@ pub const cpu = struct {...@@ -2640,6 +3120,7 @@ pub const cpu = struct {
2640 .perfmon,3120 .perfmon,
2641 .sve_bitperm,3121 .sve_bitperm,
2642 .use_postra_scheduler,3122 .use_postra_scheduler,
3123 .use_wzr_to_vec_move,
2643 .v9_2a,3124 .v9_2a,
2644 }),3125 }),
2645 };3126 };
...@@ -2655,6 +3136,7 @@ pub const cpu = struct {...@@ -2655,6 +3136,7 @@ pub const cpu = struct {
2655 .perfmon,3136 .perfmon,
2656 .sha2,3137 .sha2,
2657 .use_postra_scheduler,3138 .use_postra_scheduler,
3139 .use_wzr_to_vec_move,
2658 .v8a,3140 .v8a,
2659 }),3141 }),
2660 };3142 };
...@@ -2672,6 +3154,7 @@ pub const cpu = struct {...@@ -2672,6 +3154,7 @@ pub const cpu = struct {
2672 .rcpc,3154 .rcpc,
2673 .sha2,3155 .sha2,
2674 .use_postra_scheduler,3156 .use_postra_scheduler,
3157 .use_wzr_to_vec_move,
2675 .v8_2a,3158 .v8_2a,
2676 }),3159 }),
2677 };3160 };
...@@ -2687,6 +3170,7 @@ pub const cpu = struct {...@@ -2687,6 +3170,7 @@ pub const cpu = struct {
2687 .fuse_adrp_add,3170 .fuse_adrp_add,
2688 .fuse_aes,3171 .fuse_aes,
2689 .fuse_literals,3172 .fuse_literals,
3173 .max_interleave_factor_4,
2690 .perfmon,3174 .perfmon,
2691 .predictable_select_expensive,3175 .predictable_select_expensive,
2692 .sha2,3176 .sha2,
...@@ -2747,6 +3231,8 @@ pub const cpu = struct {...@@ -2747,6 +3231,8 @@ pub const cpu = struct {
2747 .fpac,3231 .fpac,
2748 .fuse_adrp_add,3232 .fuse_adrp_add,
2749 .fuse_aes,3233 .fuse_aes,
3234 .fuse_csel,
3235 .fuse_cset,
2750 .i8mm,3236 .i8mm,
2751 .mte,3237 .mte,
2752 .perfmon,3238 .perfmon,
...@@ -2769,6 +3255,8 @@ pub const cpu = struct {...@@ -2769,6 +3255,8 @@ pub const cpu = struct {
2769 .fpac,3255 .fpac,
2770 .fuse_adrp_add,3256 .fuse_adrp_add,
2771 .fuse_aes,3257 .fuse_aes,
3258 .fuse_csel,
3259 .fuse_cset,
2772 .i8mm,3260 .i8mm,
2773 .mte,3261 .mte,
2774 .perfmon,3262 .perfmon,
...@@ -2808,6 +3296,8 @@ pub const cpu = struct {...@@ -2808,6 +3296,8 @@ pub const cpu = struct {
2808 .fpac,3296 .fpac,
2809 .fuse_adrp_add,3297 .fuse_adrp_add,
2810 .fuse_aes,3298 .fuse_aes,
3299 .fuse_csel,
3300 .fuse_cset,
2811 .mte,3301 .mte,
2812 .perfmon,3302 .perfmon,
2813 .predictable_select_expensive,3303 .predictable_select_expensive,
...@@ -2829,6 +3319,8 @@ pub const cpu = struct {...@@ -2829,6 +3319,8 @@ pub const cpu = struct {
2829 .fpac,3319 .fpac,
2830 .fuse_adrp_add,3320 .fuse_adrp_add,
2831 .fuse_aes,3321 .fuse_aes,
3322 .fuse_csel,
3323 .fuse_cset,
2832 .mte,3324 .mte,
2833 .perfmon,3325 .perfmon,
2834 .predictable_select_expensive,3326 .predictable_select_expensive,
...@@ -2850,6 +3342,8 @@ pub const cpu = struct {...@@ -2850,6 +3342,8 @@ pub const cpu = struct {
2850 .fpac,3342 .fpac,
2851 .fuse_adrp_add,3343 .fuse_adrp_add,
2852 .fuse_aes,3344 .fuse_aes,
3345 .fuse_csel,
3346 .fuse_cset,
2853 .mte,3347 .mte,
2854 .perfmon,3348 .perfmon,
2855 .predictable_select_expensive,3349 .predictable_select_expensive,
...@@ -2967,6 +3461,8 @@ pub const cpu = struct {...@@ -2967,6 +3461,8 @@ pub const cpu = struct {
2967 .fullfp16,3461 .fullfp16,
2968 .fuse_adrp_add,3462 .fuse_adrp_add,
2969 .fuse_aes,3463 .fuse_aes,
3464 .fuse_csel,
3465 .fuse_cset,
2970 .perfmon,3466 .perfmon,
2971 .predictable_select_expensive,3467 .predictable_select_expensive,
2972 .rcpc,3468 .rcpc,
...@@ -2990,6 +3486,8 @@ pub const cpu = struct {...@@ -2990,6 +3486,8 @@ pub const cpu = struct {
2990 .fullfp16,3486 .fullfp16,
2991 .fuse_adrp_add,3487 .fuse_adrp_add,
2992 .fuse_aes,3488 .fuse_aes,
3489 .fuse_csel,
3490 .fuse_cset,
2993 .perfmon,3491 .perfmon,
2994 .predictable_select_expensive,3492 .predictable_select_expensive,
2995 .rcpc,3493 .rcpc,
...@@ -3014,6 +3512,8 @@ pub const cpu = struct {...@@ -3014,6 +3512,8 @@ pub const cpu = struct {
3014 .fullfp16,3512 .fullfp16,
3015 .fuse_adrp_add,3513 .fuse_adrp_add,
3016 .fuse_aes,3514 .fuse_aes,
3515 .fuse_csel,
3516 .fuse_cset,
3017 .pauth,3517 .pauth,
3018 .perfmon,3518 .perfmon,
3019 .predictable_select_expensive,3519 .predictable_select_expensive,
...@@ -3157,6 +3657,8 @@ pub const cpu = struct {...@@ -3157,6 +3657,8 @@ pub const cpu = struct {
3157 .fpac,3657 .fpac,
3158 .fuse_adrp_add,3658 .fuse_adrp_add,
3159 .fuse_aes,3659 .fuse_aes,
3660 .fuse_csel,
3661 .fuse_cset,
3160 .mte,3662 .mte,
3161 .perfmon,3663 .perfmon,
3162 .predictable_select_expensive,3664 .predictable_select_expensive,
...@@ -3179,6 +3681,8 @@ pub const cpu = struct {...@@ -3179,6 +3681,8 @@ pub const cpu = struct {
3179 .fpac,3681 .fpac,
3180 .fuse_adrp_add,3682 .fuse_adrp_add,
3181 .fuse_aes,3683 .fuse_aes,
3684 .fuse_csel,
3685 .fuse_cset,
3182 .mte,3686 .mte,
3183 .perfmon,3687 .perfmon,
3184 .predictable_select_expensive,3688 .predictable_select_expensive,
...@@ -3200,14 +3704,17 @@ pub const cpu = struct {...@@ -3200,14 +3704,17 @@ pub const cpu = struct {
3200 .disable_latency_sched_heuristic,3704 .disable_latency_sched_heuristic,
3201 .fuse_aes,3705 .fuse_aes,
3202 .fuse_crypto_eor,3706 .fuse_crypto_eor,
3707 .no_zcz_fpr64,
3203 .perfmon,3708 .perfmon,
3204 .sha2,3709 .sha2,
3205 .store_pair_suppress,3710 .store_pair_suppress,
3206 .v8a,3711 .v8a,
3207 .zcm_fpr64,3712 .zcm_fpr128,
3208 .zcm_gpr64,3713 .zcm_gpr64,
3209 .zcz,
3210 .zcz_fp_workaround,3714 .zcz_fp_workaround,
3715 .zcz_fpr128,
3716 .zcz_gpr32,
3717 .zcz_gpr64,
3211 }),3718 }),
3212 };3719 };
3213 pub const emag: CpuModel = .{3720 pub const emag: CpuModel = .{
...@@ -3267,6 +3774,7 @@ pub const cpu = struct {...@@ -3267,6 +3774,7 @@ pub const cpu = struct {
3267 .fuse_aes,3774 .fuse_aes,
3268 .fuse_csel,3775 .fuse_csel,
3269 .fuse_literals,3776 .fuse_literals,
3777 .max_interleave_factor_4,
3270 .perfmon,3778 .perfmon,
3271 .predictable_select_expensive,3779 .predictable_select_expensive,
3272 .sha2,3780 .sha2,
...@@ -3293,12 +3801,14 @@ pub const cpu = struct {...@@ -3293,12 +3801,14 @@ pub const cpu = struct {
3293 .fuse_arith_logic,3801 .fuse_arith_logic,
3294 .fuse_csel,3802 .fuse_csel,
3295 .fuse_literals,3803 .fuse_literals,
3804 .max_interleave_factor_4,
3296 .perfmon,3805 .perfmon,
3297 .sha2,3806 .sha2,
3298 .store_pair_suppress,3807 .store_pair_suppress,
3299 .use_postra_scheduler,3808 .use_postra_scheduler,
3300 .v8_2a,3809 .v8_2a,
3301 .zcz,3810 .zcz_gpr32,
3811 .zcz_gpr64,
3302 }),3812 }),
3303 };3813 };
3304 pub const exynos_m5: CpuModel = .{3814 pub const exynos_m5: CpuModel = .{
...@@ -3319,12 +3829,14 @@ pub const cpu = struct {...@@ -3319,12 +3829,14 @@ pub const cpu = struct {
3319 .fuse_arith_logic,3829 .fuse_arith_logic,
3320 .fuse_csel,3830 .fuse_csel,
3321 .fuse_literals,3831 .fuse_literals,
3832 .max_interleave_factor_4,
3322 .perfmon,3833 .perfmon,
3323 .sha2,3834 .sha2,
3324 .store_pair_suppress,3835 .store_pair_suppress,
3325 .use_postra_scheduler,3836 .use_postra_scheduler,
3326 .v8_2a,3837 .v8_2a,
3327 .zcz,3838 .zcz_gpr32,
3839 .zcz_gpr64,
3328 }),3840 }),
3329 };3841 };
3330 pub const falkor: CpuModel = .{3842 pub const falkor: CpuModel = .{
...@@ -3334,6 +3846,7 @@ pub const cpu = struct {...@@ -3334,6 +3846,7 @@ pub const cpu = struct {
3334 .aes,3846 .aes,
3335 .alu_lsl_fast,3847 .alu_lsl_fast,
3336 .crc,3848 .crc,
3849 .max_interleave_factor_4,
3337 .perfmon,3850 .perfmon,
3338 .predictable_select_expensive,3851 .predictable_select_expensive,
3339 .rdm,3852 .rdm,
...@@ -3342,7 +3855,8 @@ pub const cpu = struct {...@@ -3342,7 +3855,8 @@ pub const cpu = struct {
3342 .store_pair_suppress,3855 .store_pair_suppress,
3343 .use_postra_scheduler,3856 .use_postra_scheduler,
3344 .v8a,3857 .v8a,
3345 .zcz,3858 .zcz_gpr32,
3859 .zcz_gpr64,
3346 }),3860 }),
3347 };3861 };
3348 pub const fujitsu_monaka: CpuModel = .{3862 pub const fujitsu_monaka: CpuModel = .{
...@@ -3382,6 +3896,8 @@ pub const cpu = struct {...@@ -3382,6 +3896,8 @@ pub const cpu = struct {
3382 .fpac,3896 .fpac,
3383 .fuse_adrp_add,3897 .fuse_adrp_add,
3384 .fuse_aes,3898 .fuse_aes,
3899 .fuse_csel,
3900 .fuse_cset,
3385 .mte,3901 .mte,
3386 .perfmon,3902 .perfmon,
3387 .predictable_select_expensive,3903 .predictable_select_expensive,
...@@ -3422,11 +3938,13 @@ pub const cpu = struct {...@@ -3422,11 +3938,13 @@ pub const cpu = struct {
3422 .fpac,3938 .fpac,
3423 .fuse_adrp_add,3939 .fuse_adrp_add,
3424 .fuse_aes,3940 .fuse_aes,
3941 .fuse_csel,
3942 .fuse_cset,
3425 .i8mm,3943 .i8mm,
3944 .max_interleave_factor_4,
3426 .mte,3945 .mte,
3427 .perfmon,3946 .perfmon,
3428 .predictable_select_expensive,3947 .predictable_select_expensive,
3429 .rand,
3430 .spe,3948 .spe,
3431 .sve_aes,3949 .sve_aes,
3432 .sve_bitperm,3950 .sve_bitperm,
...@@ -3444,13 +3962,15 @@ pub const cpu = struct {...@@ -3444,13 +3962,15 @@ pub const cpu = struct {
3444 .aes,3962 .aes,
3445 .alu_lsl_fast,3963 .alu_lsl_fast,
3446 .crc,3964 .crc,
3965 .max_interleave_factor_4,
3447 .perfmon,3966 .perfmon,
3448 .predictable_select_expensive,3967 .predictable_select_expensive,
3449 .sha2,3968 .sha2,
3450 .store_pair_suppress,3969 .store_pair_suppress,
3451 .use_postra_scheduler,3970 .use_postra_scheduler,
3452 .v8a,3971 .v8a,
3453 .zcz,3972 .zcz_gpr32,
3973 .zcz_gpr64,
3454 }),3974 }),
3455 };3975 };
3456 pub const neoverse_512tvb: CpuModel = .{3976 pub const neoverse_512tvb: CpuModel = .{
...@@ -3467,6 +3987,7 @@ pub const cpu = struct {...@@ -3467,6 +3987,7 @@ pub const cpu = struct {
3467 .fuse_adrp_add,3987 .fuse_adrp_add,
3468 .fuse_aes,3988 .fuse_aes,
3469 .i8mm,3989 .i8mm,
3990 .max_interleave_factor_4,
3470 .perfmon,3991 .perfmon,
3471 .predictable_select_expensive,3992 .predictable_select_expensive,
3472 .rand,3993 .rand,
...@@ -3524,12 +4045,15 @@ pub const cpu = struct {...@@ -3524,12 +4045,15 @@ pub const cpu = struct {
3524 .features = featureSet(&[_]Feature{4045 .features = featureSet(&[_]Feature{
3525 .alu_lsl_fast,4046 .alu_lsl_fast,
3526 .bf16,4047 .bf16,
4048 .disable_maximize_scalable_bandwidth,
3527 .enable_select_opt,4049 .enable_select_opt,
3528 .ete,4050 .ete,
3529 .fp16fml,4051 .fp16fml,
3530 .fpac,4052 .fpac,
3531 .fuse_adrp_add,4053 .fuse_adrp_add,
3532 .fuse_aes,4054 .fuse_aes,
4055 .fuse_csel,
4056 .fuse_cset,
3533 .i8mm,4057 .i8mm,
3534 .mte,4058 .mte,
3535 .perfmon,4059 .perfmon,
...@@ -3550,6 +4074,8 @@ pub const cpu = struct {...@@ -3550,6 +4074,8 @@ pub const cpu = struct {
3550 .fpac,4074 .fpac,
3551 .fuse_adrp_add,4075 .fuse_adrp_add,
3552 .fuse_aes,4076 .fuse_aes,
4077 .fuse_csel,
4078 .fuse_cset,
3553 .mte,4079 .mte,
3554 .perfmon,4080 .perfmon,
3555 .predictable_select_expensive,4081 .predictable_select_expensive,
...@@ -3569,10 +4095,13 @@ pub const cpu = struct {...@@ -3569,10 +4095,13 @@ pub const cpu = struct {
3569 .alu_lsl_fast,4095 .alu_lsl_fast,
3570 .bf16,4096 .bf16,
3571 .ccdp,4097 .ccdp,
4098 .disable_maximize_scalable_bandwidth,
3572 .enable_select_opt,4099 .enable_select_opt,
3573 .fp16fml,4100 .fp16fml,
3574 .fuse_adrp_add,4101 .fuse_adrp_add,
3575 .fuse_aes,4102 .fuse_aes,
4103 .fuse_csel,
4104 .fuse_cset,
3576 .i8mm,4105 .i8mm,
3577 .no_sve_fp_ld1r,4106 .no_sve_fp_ld1r,
3578 .perfmon,4107 .perfmon,
...@@ -3602,7 +4131,10 @@ pub const cpu = struct {...@@ -3602,7 +4131,10 @@ pub const cpu = struct {
3602 .fpac,4131 .fpac,
3603 .fuse_adrp_add,4132 .fuse_adrp_add,
3604 .fuse_aes,4133 .fuse_aes,
4134 .fuse_csel,
4135 .fuse_cset,
3605 .i8mm,4136 .i8mm,
4137 .max_interleave_factor_4,
3606 .mte,4138 .mte,
3607 .perfmon,4139 .perfmon,
3608 .predictable_select_expensive,4140 .predictable_select_expensive,
...@@ -3627,7 +4159,10 @@ pub const cpu = struct {...@@ -3627,7 +4159,10 @@ pub const cpu = struct {
3627 .fpac,4159 .fpac,
3628 .fuse_adrp_add,4160 .fuse_adrp_add,
3629 .fuse_aes,4161 .fuse_aes,
4162 .fuse_csel,
4163 .fuse_cset,
3630 .ls64,4164 .ls64,
4165 .max_interleave_factor_4,
3631 .mte,4166 .mte,
3632 .perfmon,4167 .perfmon,
3633 .predictable_select_expensive,4168 .predictable_select_expensive,
...@@ -3651,7 +4186,10 @@ pub const cpu = struct {...@@ -3651,7 +4186,10 @@ pub const cpu = struct {
3651 .fpac,4186 .fpac,
3652 .fuse_adrp_add,4187 .fuse_adrp_add,
3653 .fuse_aes,4188 .fuse_aes,
4189 .fuse_csel,
4190 .fuse_cset,
3654 .ls64,4191 .ls64,
4192 .max_interleave_factor_4,
3655 .mte,4193 .mte,
3656 .perfmon,4194 .perfmon,
3657 .predictable_select_expensive,4195 .predictable_select_expensive,
...@@ -3700,6 +4238,7 @@ pub const cpu = struct {...@@ -3700,6 +4238,7 @@ pub const cpu = struct {
3700 .fuse_adrp_add,4238 .fuse_adrp_add,
3701 .fuse_aes,4239 .fuse_aes,
3702 .fuse_crypto_eor,4240 .fuse_crypto_eor,
4241 .max_interleave_factor_4,
3703 .perfmon,4242 .perfmon,
3704 .rand,4243 .rand,
3705 .sha3,4244 .sha3,
...@@ -3715,6 +4254,7 @@ pub const cpu = struct {...@@ -3715,6 +4254,7 @@ pub const cpu = struct {
3715 .features = featureSet(&[_]Feature{4254 .features = featureSet(&[_]Feature{
3716 .aes,4255 .aes,
3717 .alu_lsl_fast,4256 .alu_lsl_fast,
4257 .max_interleave_factor_4,
3718 .perfmon,4258 .perfmon,
3719 .predictable_select_expensive,4259 .predictable_select_expensive,
3720 .sha2,4260 .sha2,
...@@ -3722,7 +4262,8 @@ pub const cpu = struct {...@@ -3722,7 +4262,8 @@ pub const cpu = struct {
3722 .store_pair_suppress,4262 .store_pair_suppress,
3723 .use_postra_scheduler,4263 .use_postra_scheduler,
3724 .v8_4a,4264 .v8_4a,
3725 .zcz,4265 .zcz_gpr32,
4266 .zcz_gpr64,
3726 }),4267 }),
3727 };4268 };
3728 pub const thunderx: CpuModel = .{4269 pub const thunderx: CpuModel = .{
...@@ -3746,6 +4287,7 @@ pub const cpu = struct {...@@ -3746,6 +4287,7 @@ pub const cpu = struct {
3746 .aes,4287 .aes,
3747 .aggressive_fma,4288 .aggressive_fma,
3748 .arith_bcc_fusion,4289 .arith_bcc_fusion,
4290 .max_interleave_factor_4,
3749 .predictable_select_expensive,4291 .predictable_select_expensive,
3750 .sha2,4292 .sha2,
3751 .store_pair_suppress,4293 .store_pair_suppress,
...@@ -3761,6 +4303,7 @@ pub const cpu = struct {...@@ -3761,6 +4303,7 @@ pub const cpu = struct {
3761 .aggressive_fma,4303 .aggressive_fma,
3762 .arith_bcc_fusion,4304 .arith_bcc_fusion,
3763 .balance_fp_ops,4305 .balance_fp_ops,
4306 .max_interleave_factor_4,
3764 .perfmon,4307 .perfmon,
3765 .predictable_select_expensive,4308 .predictable_select_expensive,
3766 .sha2,4309 .sha2,
lib/std/Target/amdgcn.zig+421-21
...@@ -5,12 +5,17 @@ const CpuFeature = std.Target.Cpu.Feature;...@@ -5,12 +5,17 @@ const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {7pub const Feature = enum {
8 @"1024_addressable_vgprs",
8 @"16_bit_insts",9 @"16_bit_insts",
10 @"45_bit_num_records_buffer_resource",
9 @"64_bit_literals",11 @"64_bit_literals",
10 a16,12 a16,
13 add_min_max_insts,
11 add_no_carry_insts,14 add_no_carry_insts,
15 add_sub_u64_insts,
12 addressablelocalmemorysize163840,16 addressablelocalmemorysize163840,
13 addressablelocalmemorysize32768,17 addressablelocalmemorysize32768,
18 addressablelocalmemorysize327680,
14 addressablelocalmemorysize65536,19 addressablelocalmemorysize65536,
15 agent_scope_fine_grained_remote_memory_atomics,20 agent_scope_fine_grained_remote_memory_atomics,
16 allocate1_5xvgprs,21 allocate1_5xvgprs,
...@@ -18,6 +23,7 @@ pub const Feature = enum {...@@ -18,6 +23,7 @@ pub const Feature = enum {
18 architected_flat_scratch,23 architected_flat_scratch,
19 architected_sgprs,24 architected_sgprs,
20 ashr_pk_insts,25 ashr_pk_insts,
26 assembler_permissive_wavesize,
21 atomic_buffer_global_pk_add_f16_insts,27 atomic_buffer_global_pk_add_f16_insts,
22 atomic_buffer_global_pk_add_f16_no_rtn_insts,28 atomic_buffer_global_pk_add_f16_no_rtn_insts,
23 atomic_buffer_pk_add_bf16_inst,29 atomic_buffer_pk_add_bf16_inst,
...@@ -34,15 +40,22 @@ pub const Feature = enum {...@@ -34,15 +40,22 @@ pub const Feature = enum {
34 auto_waitcnt_before_barrier,40 auto_waitcnt_before_barrier,
35 back_off_barrier,41 back_off_barrier,
36 bf16_cvt_insts,42 bf16_cvt_insts,
43 bf16_pk_insts,
37 bf16_trans_insts,44 bf16_trans_insts,
38 bf8_cvt_scale_insts,45 bf8_cvt_scale_insts,
39 bitop3_insts,46 bitop3_insts,
40 block_vgpr_csr,47 block_vgpr_csr,
41 bvh_dual_bvh_8_insts,48 bvh_dual_bvh_8_insts,
42 ci_insts,49 ci_insts,
50 clusters,
51 cube_insts,
43 cumode,52 cumode,
44 cvt_fp8_vop1_bug,53 cvt_fp8_vop1_bug,
54 cvt_norm_insts,
45 cvt_pk_f16_f32_inst,55 cvt_pk_f16_f32_inst,
56 cvt_pknorm_vop2_insts,
57 cvt_pknorm_vop3_insts,
58 d16_write_vgpr32,
46 default_component_broadcast,59 default_component_broadcast,
47 default_component_zero,60 default_component_zero,
48 dl_insts,61 dl_insts,
...@@ -65,8 +78,7 @@ pub const Feature = enum {...@@ -65,8 +78,7 @@ pub const Feature = enum {
65 dpp_src1_sgpr,78 dpp_src1_sgpr,
66 ds128,79 ds128,
67 ds_src2_insts,80 ds_src2_insts,
68 dynamic_vgpr,81 emulated_system_scope_atomics,
69 dynamic_vgpr_block_size_32,
70 extended_image_insts,82 extended_image_insts,
71 f16bf16_to_fp6bf6_cvt_scale_insts,83 f16bf16_to_fp6bf6_cvt_scale_insts,
72 f32_to_f16bf16_cvt_sr_insts,84 f32_to_f16bf16_cvt_sr_insts,
...@@ -77,10 +89,12 @@ pub const Feature = enum {...@@ -77,10 +89,12 @@ pub const Feature = enum {
77 flat_buffer_global_fadd_f64_inst,89 flat_buffer_global_fadd_f64_inst,
78 flat_for_global,90 flat_for_global,
79 flat_global_insts,91 flat_global_insts,
92 flat_gvs_mode,
80 flat_inst_offsets,93 flat_inst_offsets,
81 flat_scratch,94 flat_scratch,
82 flat_scratch_insts,95 flat_scratch_insts,
83 flat_segment_offset_bug,96 flat_segment_offset_bug,
97 fma_mix_bf16_insts,
84 fma_mix_insts,98 fma_mix_insts,
85 fmacf64_inst,99 fmacf64_inst,
86 fmaf,100 fmaf,
...@@ -113,6 +127,7 @@ pub const Feature = enum {...@@ -113,6 +127,7 @@ pub const Feature = enum {
113 gfx940_insts,127 gfx940_insts,
114 gfx950_insts,128 gfx950_insts,
115 gfx9_insts,129 gfx9_insts,
130 globally_addressable_scratch,
116 gws,131 gws,
117 half_rate_64_ops,132 half_rate_64_ops,
118 ieee_minimum_maximum_insts,133 ieee_minimum_maximum_insts,
...@@ -128,20 +143,24 @@ pub const Feature = enum {...@@ -128,20 +143,24 @@ pub const Feature = enum {
128 lds_misaligned_bug,143 lds_misaligned_bug,
129 ldsbankcount16,144 ldsbankcount16,
130 ldsbankcount32,145 ldsbankcount32,
146 lerp_inst,
131 load_store_opt,147 load_store_opt,
132 lshl_add_u64_inst,148 lshl_add_u64_inst,
133 mad_intra_fwd_bug,149 mad_intra_fwd_bug,
134 mad_mac_f32_insts,150 mad_mac_f32_insts,
135 mad_mix_insts,151 mad_mix_insts,
152 mad_u32_inst,
136 mai_insts,153 mai_insts,
137 max_hard_clause_length_32,154 max_hard_clause_length_32,
138 max_hard_clause_length_63,155 max_hard_clause_length_63,
139 max_private_element_size_16,156 max_private_element_size_16,
140 max_private_element_size_4,157 max_private_element_size_4,
141 max_private_element_size_8,158 max_private_element_size_8,
159 mcast_load_insts,
142 memory_atomic_fadd_f32_denormal_support,160 memory_atomic_fadd_f32_denormal_support,
143 mfma_inline_literal_bug,161 mfma_inline_literal_bug,
144 mimg_r128,162 mimg_r128,
163 min3_max3_pkf16,
145 minimum3_maximum3_f16,164 minimum3_maximum3_f16,
146 minimum3_maximum3_f32,165 minimum3_maximum3_f32,
147 minimum3_maximum3_pkf16,166 minimum3_maximum3_pkf16,
...@@ -160,6 +179,7 @@ pub const Feature = enum {...@@ -160,6 +179,7 @@ pub const Feature = enum {
160 partial_nsa_encoding,179 partial_nsa_encoding,
161 permlane16_swap,180 permlane16_swap,
162 permlane32_swap,181 permlane32_swap,
182 pk_add_min_max_insts,
163 pk_fmac_f16_inst,183 pk_fmac_f16_inst,
164 point_sample_accel,184 point_sample_accel,
165 precise_memory,185 precise_memory,
...@@ -168,6 +188,7 @@ pub const Feature = enum {...@@ -168,6 +188,7 @@ pub const Feature = enum {
168 promote_alloca,188 promote_alloca,
169 prt_strict_null,189 prt_strict_null,
170 pseudo_scalar_trans,190 pseudo_scalar_trans,
191 qsad_insts,
171 r128_a16,192 r128_a16,
172 real_true16,193 real_true16,
173 relaxed_buffer_oob_mode,194 relaxed_buffer_oob_mode,
...@@ -176,6 +197,9 @@ pub const Feature = enum {...@@ -176,6 +197,9 @@ pub const Feature = enum {
176 restricted_soffset,197 restricted_soffset,
177 s_memrealtime,198 s_memrealtime,
178 s_memtime_inst,199 s_memtime_inst,
200 s_wakeup_barrier_inst,
201 sad_insts,
202 safe_cu_prefetch,
179 safe_smem_prefetch,203 safe_smem_prefetch,
180 salu_float,204 salu_float,
181 scalar_atomics,205 scalar_atomics,
...@@ -190,6 +214,7 @@ pub const Feature = enum {...@@ -190,6 +214,7 @@ pub const Feature = enum {
190 sdwa_sdst,214 sdwa_sdst,
191 sea_islands,215 sea_islands,
192 setprio_inc_wg_inst,216 setprio_inc_wg_inst,
217 setreg_vgpr_msb_fixup,
193 sgpr_init_bug,218 sgpr_init_bug,
194 shader_cycles_hi_lo_registers,219 shader_cycles_hi_lo_registers,
195 shader_cycles_register,220 shader_cycles_register,
...@@ -198,6 +223,8 @@ pub const Feature = enum {...@@ -198,6 +223,8 @@ pub const Feature = enum {
198 southern_islands,223 southern_islands,
199 sramecc,224 sramecc,
200 sramecc_support,225 sramecc_support,
226 tanh_insts,
227 tensor_cvt_lut_insts,
201 tgsplit,228 tgsplit,
202 transpose_load_f4f6_insts,229 transpose_load_f4f6_insts,
203 trap_handler,230 trap_handler,
...@@ -213,7 +240,9 @@ pub const Feature = enum {...@@ -213,7 +240,9 @@ pub const Feature = enum {
213 valu_trans_use_hazard,240 valu_trans_use_hazard,
214 vcmpx_exec_war_hazard,241 vcmpx_exec_war_hazard,
215 vcmpx_permlane_hazard,242 vcmpx_permlane_hazard,
243 vgpr_align2,
216 vgpr_index_mode,244 vgpr_index_mode,
245 vmem_pref_insts,
217 vmem_to_lds_load_insts,246 vmem_to_lds_load_insts,
218 vmem_to_scalar_write_hazard,247 vmem_to_scalar_write_hazard,
219 vmem_write_vgpr_in_order,248 vmem_write_vgpr_in_order,
...@@ -223,6 +252,7 @@ pub const Feature = enum {...@@ -223,6 +252,7 @@ pub const Feature = enum {
223 vopd,252 vopd,
224 vscnt,253 vscnt,
225 wait_xcnt,254 wait_xcnt,
255 waits_before_system_scope_stores,
226 wavefrontsize16,256 wavefrontsize16,
227 wavefrontsize32,257 wavefrontsize32,
228 wavefrontsize64,258 wavefrontsize64,
...@@ -241,11 +271,21 @@ pub const all_features = blk: {...@@ -241,11 +271,21 @@ pub const all_features = blk: {
241 const len = @typeInfo(Feature).@"enum".fields.len;271 const len = @typeInfo(Feature).@"enum".fields.len;
242 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);272 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
243 var result: [len]CpuFeature = undefined;273 var result: [len]CpuFeature = undefined;
274 result[@intFromEnum(Feature.@"1024_addressable_vgprs")] = .{
275 .llvm_name = "1024-addressable-vgprs",
276 .description = "Has 1024 addressable VGPRs",
277 .dependencies = featureSet(&[_]Feature{}),
278 };
244 result[@intFromEnum(Feature.@"16_bit_insts")] = .{279 result[@intFromEnum(Feature.@"16_bit_insts")] = .{
245 .llvm_name = "16-bit-insts",280 .llvm_name = "16-bit-insts",
246 .description = "Has i16/f16 instructions",281 .description = "Has i16/f16 instructions",
247 .dependencies = featureSet(&[_]Feature{}),282 .dependencies = featureSet(&[_]Feature{}),
248 };283 };
284 result[@intFromEnum(Feature.@"45_bit_num_records_buffer_resource")] = .{
285 .llvm_name = "45-bit-num-records-buffer-resource",
286 .description = "The buffer resource (V#) supports 45-bit num_records",
287 .dependencies = featureSet(&[_]Feature{}),
288 };
249 result[@intFromEnum(Feature.@"64_bit_literals")] = .{289 result[@intFromEnum(Feature.@"64_bit_literals")] = .{
250 .llvm_name = "64-bit-literals",290 .llvm_name = "64-bit-literals",
251 .description = "Can use 64-bit literals with single DWORD instructions",291 .description = "Can use 64-bit literals with single DWORD instructions",
...@@ -256,11 +296,21 @@ pub const all_features = blk: {...@@ -256,11 +296,21 @@ pub const all_features = blk: {
256 .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",296 .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
257 .dependencies = featureSet(&[_]Feature{}),297 .dependencies = featureSet(&[_]Feature{}),
258 };298 };
299 result[@intFromEnum(Feature.add_min_max_insts)] = .{
300 .llvm_name = "add-min-max-insts",
301 .description = "Has v_add_{min|max}_{i|u}32 instructions",
302 .dependencies = featureSet(&[_]Feature{}),
303 };
259 result[@intFromEnum(Feature.add_no_carry_insts)] = .{304 result[@intFromEnum(Feature.add_no_carry_insts)] = .{
260 .llvm_name = "add-no-carry-insts",305 .llvm_name = "add-no-carry-insts",
261 .description = "Have VALU add/sub instructions without carry out",306 .description = "Have VALU add/sub instructions without carry out",
262 .dependencies = featureSet(&[_]Feature{}),307 .dependencies = featureSet(&[_]Feature{}),
263 };308 };
309 result[@intFromEnum(Feature.add_sub_u64_insts)] = .{
310 .llvm_name = "add-sub-u64-insts",
311 .description = "Has v_add_u64 and v_sub_u64 instructions",
312 .dependencies = featureSet(&[_]Feature{}),
313 };
264 result[@intFromEnum(Feature.addressablelocalmemorysize163840)] = .{314 result[@intFromEnum(Feature.addressablelocalmemorysize163840)] = .{
265 .llvm_name = "addressablelocalmemorysize163840",315 .llvm_name = "addressablelocalmemorysize163840",
266 .description = "The size of local memory in bytes",316 .description = "The size of local memory in bytes",
...@@ -271,6 +321,11 @@ pub const all_features = blk: {...@@ -271,6 +321,11 @@ pub const all_features = blk: {
271 .description = "The size of local memory in bytes",321 .description = "The size of local memory in bytes",
272 .dependencies = featureSet(&[_]Feature{}),322 .dependencies = featureSet(&[_]Feature{}),
273 };323 };
324 result[@intFromEnum(Feature.addressablelocalmemorysize327680)] = .{
325 .llvm_name = "addressablelocalmemorysize327680",
326 .description = "The size of local memory in bytes",
327 .dependencies = featureSet(&[_]Feature{}),
328 };
274 result[@intFromEnum(Feature.addressablelocalmemorysize65536)] = .{329 result[@intFromEnum(Feature.addressablelocalmemorysize65536)] = .{
275 .llvm_name = "addressablelocalmemorysize65536",330 .llvm_name = "addressablelocalmemorysize65536",
276 .description = "The size of local memory in bytes",331 .description = "The size of local memory in bytes",
...@@ -306,6 +361,11 @@ pub const all_features = blk: {...@@ -306,6 +361,11 @@ pub const all_features = blk: {
306 .description = "Has Arithmetic Shift Pack instructions",361 .description = "Has Arithmetic Shift Pack instructions",
307 .dependencies = featureSet(&[_]Feature{}),362 .dependencies = featureSet(&[_]Feature{}),
308 };363 };
364 result[@intFromEnum(Feature.assembler_permissive_wavesize)] = .{
365 .llvm_name = "assembler-permissive-wavesize",
366 .description = "allow parsing wave32 and wave64 variants of instructions",
367 .dependencies = featureSet(&[_]Feature{}),
368 };
309 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{369 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
310 .llvm_name = "atomic-buffer-global-pk-add-f16-insts",370 .llvm_name = "atomic-buffer-global-pk-add-f16-insts",
311 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",371 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
...@@ -357,12 +417,16 @@ pub const all_features = blk: {...@@ -357,12 +417,16 @@ pub const all_features = blk: {
357 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{417 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{
358 .llvm_name = "atomic-fmin-fmax-flat-f32",418 .llvm_name = "atomic-fmin-fmax-flat-f32",
359 .description = "Has flat memory instructions for atomicrmw fmin/fmax for float",419 .description = "Has flat memory instructions for atomicrmw fmin/fmax for float",
360 .dependencies = featureSet(&[_]Feature{}),420 .dependencies = featureSet(&[_]Feature{
421 .flat_address_space,
422 }),
361 };423 };
362 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{424 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{
363 .llvm_name = "atomic-fmin-fmax-flat-f64",425 .llvm_name = "atomic-fmin-fmax-flat-f64",
364 .description = "Has flat memory instructions for atomicrmw fmin/fmax for double",426 .description = "Has flat memory instructions for atomicrmw fmin/fmax for double",
365 .dependencies = featureSet(&[_]Feature{}),427 .dependencies = featureSet(&[_]Feature{
428 .flat_address_space,
429 }),
366 };430 };
367 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{431 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{
368 .llvm_name = "atomic-fmin-fmax-global-f32",432 .llvm_name = "atomic-fmin-fmax-global-f32",
...@@ -396,6 +460,11 @@ pub const all_features = blk: {...@@ -396,6 +460,11 @@ pub const all_features = blk: {
396 .description = "Has bf16 conversion instructions",460 .description = "Has bf16 conversion instructions",
397 .dependencies = featureSet(&[_]Feature{}),461 .dependencies = featureSet(&[_]Feature{}),
398 };462 };
463 result[@intFromEnum(Feature.bf16_pk_insts)] = .{
464 .llvm_name = "bf16-pk-insts",
465 .description = "Has bf16 packed instructions (fma, add, mul, max, min)",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
399 result[@intFromEnum(Feature.bf16_trans_insts)] = .{468 result[@intFromEnum(Feature.bf16_trans_insts)] = .{
400 .llvm_name = "bf16-trans-insts",469 .llvm_name = "bf16-trans-insts",
401 .description = "Has bf16 transcendental instructions",470 .description = "Has bf16 transcendental instructions",
...@@ -426,6 +495,16 @@ pub const all_features = blk: {...@@ -426,6 +495,16 @@ pub const all_features = blk: {
426 .description = "Additional instructions for CI+",495 .description = "Additional instructions for CI+",
427 .dependencies = featureSet(&[_]Feature{}),496 .dependencies = featureSet(&[_]Feature{}),
428 };497 };
498 result[@intFromEnum(Feature.clusters)] = .{
499 .llvm_name = "clusters",
500 .description = "Has clusters of workgroups support",
501 .dependencies = featureSet(&[_]Feature{}),
502 };
503 result[@intFromEnum(Feature.cube_insts)] = .{
504 .llvm_name = "cube-insts",
505 .description = "Has v_cube* instructions",
506 .dependencies = featureSet(&[_]Feature{}),
507 };
429 result[@intFromEnum(Feature.cumode)] = .{508 result[@intFromEnum(Feature.cumode)] = .{
430 .llvm_name = "cumode",509 .llvm_name = "cumode",
431 .description = "Enable CU wavefront execution mode",510 .description = "Enable CU wavefront execution mode",
...@@ -438,11 +517,31 @@ pub const all_features = blk: {...@@ -438,11 +517,31 @@ pub const all_features = blk: {
438 .fp8_conversion_insts,517 .fp8_conversion_insts,
439 }),518 }),
440 };519 };
520 result[@intFromEnum(Feature.cvt_norm_insts)] = .{
521 .llvm_name = "cvt-norm-insts",
522 .description = "Has v_cvt_norm* instructions",
523 .dependencies = featureSet(&[_]Feature{}),
524 };
441 result[@intFromEnum(Feature.cvt_pk_f16_f32_inst)] = .{525 result[@intFromEnum(Feature.cvt_pk_f16_f32_inst)] = .{
442 .llvm_name = "cvt-pk-f16-f32-inst",526 .llvm_name = "cvt-pk-f16-f32-inst",
443 .description = "Has cvt_pk_f16_f32 instruction",527 .description = "Has cvt_pk_f16_f32 instruction",
444 .dependencies = featureSet(&[_]Feature{}),528 .dependencies = featureSet(&[_]Feature{}),
445 };529 };
530 result[@intFromEnum(Feature.cvt_pknorm_vop2_insts)] = .{
531 .llvm_name = "cvt-pknorm-vop2-insts",
532 .description = "Has v_cvt_pk_norm_*f32 instructions/Has v_cvt_pk_norm_*_f16 instructions",
533 .dependencies = featureSet(&[_]Feature{}),
534 };
535 result[@intFromEnum(Feature.cvt_pknorm_vop3_insts)] = .{
536 .llvm_name = "cvt-pknorm-vop3-insts",
537 .description = "Has v_cvt_pk_norm_*f32 instructions/Has v_cvt_pk_norm_*_f16 instructions",
538 .dependencies = featureSet(&[_]Feature{}),
539 };
540 result[@intFromEnum(Feature.d16_write_vgpr32)] = .{
541 .llvm_name = "d16-write-vgpr32",
542 .description = "D16 instructions potentially have 32-bit data dependencies",
543 .dependencies = featureSet(&[_]Feature{}),
544 };
446 result[@intFromEnum(Feature.default_component_broadcast)] = .{545 result[@intFromEnum(Feature.default_component_broadcast)] = .{
447 .llvm_name = "default-component-broadcast",546 .llvm_name = "default-component-broadcast",
448 .description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",547 .description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",
...@@ -553,14 +652,9 @@ pub const all_features = blk: {...@@ -553,14 +652,9 @@ pub const all_features = blk: {
553 .description = "Has ds_*_src2 instructions",652 .description = "Has ds_*_src2 instructions",
554 .dependencies = featureSet(&[_]Feature{}),653 .dependencies = featureSet(&[_]Feature{}),
555 };654 };
556 result[@intFromEnum(Feature.dynamic_vgpr)] = .{655 result[@intFromEnum(Feature.emulated_system_scope_atomics)] = .{
557 .llvm_name = "dynamic-vgpr",656 .llvm_name = "emulated-system-scope-atomics",
558 .description = "Enable dynamic VGPR mode",657 .description = "System scope atomics unsupported by the PCI-e are emulated in HW via CAS loop and functional.",
559 .dependencies = featureSet(&[_]Feature{}),
560 };
561 result[@intFromEnum(Feature.dynamic_vgpr_block_size_32)] = .{
562 .llvm_name = "dynamic-vgpr-block-size-32",
563 .description = "Use a block size of 32 for dynamic VGPR allocation (default is 16)",
564 .dependencies = featureSet(&[_]Feature{}),658 .dependencies = featureSet(&[_]Feature{}),
565 };659 };
566 result[@intFromEnum(Feature.extended_image_insts)] = .{660 result[@intFromEnum(Feature.extended_image_insts)] = .{
...@@ -596,7 +690,9 @@ pub const all_features = blk: {...@@ -596,7 +690,9 @@ pub const all_features = blk: {
596 result[@intFromEnum(Feature.flat_atomic_fadd_f32_inst)] = .{690 result[@intFromEnum(Feature.flat_atomic_fadd_f32_inst)] = .{
597 .llvm_name = "flat-atomic-fadd-f32-inst",691 .llvm_name = "flat-atomic-fadd-f32-inst",
598 .description = "Has flat_atomic_add_f32 instruction",692 .description = "Has flat_atomic_add_f32 instruction",
599 .dependencies = featureSet(&[_]Feature{}),693 .dependencies = featureSet(&[_]Feature{
694 .flat_address_space,
695 }),
600 };696 };
601 result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{697 result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{
602 .llvm_name = "flat-buffer-global-fadd-f64-inst",698 .llvm_name = "flat-buffer-global-fadd-f64-inst",
...@@ -611,7 +707,16 @@ pub const all_features = blk: {...@@ -611,7 +707,16 @@ pub const all_features = blk: {
611 result[@intFromEnum(Feature.flat_global_insts)] = .{707 result[@intFromEnum(Feature.flat_global_insts)] = .{
612 .llvm_name = "flat-global-insts",708 .llvm_name = "flat-global-insts",
613 .description = "Have global_* flat memory instructions",709 .description = "Have global_* flat memory instructions",
614 .dependencies = featureSet(&[_]Feature{}),710 .dependencies = featureSet(&[_]Feature{
711 .flat_address_space,
712 }),
713 };
714 result[@intFromEnum(Feature.flat_gvs_mode)] = .{
715 .llvm_name = "flat-gvs-mode",
716 .description = "Have GVS addressing mode with flat_* instructions",
717 .dependencies = featureSet(&[_]Feature{
718 .flat_address_space,
719 }),
615 };720 };
616 result[@intFromEnum(Feature.flat_inst_offsets)] = .{721 result[@intFromEnum(Feature.flat_inst_offsets)] = .{
617 .llvm_name = "flat-inst-offsets",722 .llvm_name = "flat-inst-offsets",
...@@ -626,13 +731,20 @@ pub const all_features = blk: {...@@ -626,13 +731,20 @@ pub const all_features = blk: {
626 result[@intFromEnum(Feature.flat_scratch_insts)] = .{731 result[@intFromEnum(Feature.flat_scratch_insts)] = .{
627 .llvm_name = "flat-scratch-insts",732 .llvm_name = "flat-scratch-insts",
628 .description = "Have scratch_* flat memory instructions",733 .description = "Have scratch_* flat memory instructions",
629 .dependencies = featureSet(&[_]Feature{}),734 .dependencies = featureSet(&[_]Feature{
735 .flat_address_space,
736 }),
630 };737 };
631 result[@intFromEnum(Feature.flat_segment_offset_bug)] = .{738 result[@intFromEnum(Feature.flat_segment_offset_bug)] = .{
632 .llvm_name = "flat-segment-offset-bug",739 .llvm_name = "flat-segment-offset-bug",
633 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",740 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
634 .dependencies = featureSet(&[_]Feature{}),741 .dependencies = featureSet(&[_]Feature{}),
635 };742 };
743 result[@intFromEnum(Feature.fma_mix_bf16_insts)] = .{
744 .llvm_name = "fma-mix-bf16-insts",
745 .description = "Has v_fma_mix_f32_bf16, v_fma_mixlo_bf16, v_fma_mixhi_bf16 instructions",
746 .dependencies = featureSet(&[_]Feature{}),
747 };
636 result[@intFromEnum(Feature.fma_mix_insts)] = .{748 result[@intFromEnum(Feature.fma_mix_insts)] = .{
637 .llvm_name = "fma-mix-insts",749 .llvm_name = "fma-mix-insts",
638 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",750 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
...@@ -722,13 +834,16 @@ pub const all_features = blk: {...@@ -722,13 +834,16 @@ pub const all_features = blk: {
722 .atomic_fmin_fmax_global_f32,834 .atomic_fmin_fmax_global_f32,
723 .atomic_fmin_fmax_global_f64,835 .atomic_fmin_fmax_global_f64,
724 .ci_insts,836 .ci_insts,
837 .cube_insts,
838 .cvt_norm_insts,
839 .cvt_pknorm_vop2_insts,
840 .cvt_pknorm_vop3_insts,
725 .default_component_zero,841 .default_component_zero,
726 .dpp,842 .dpp,
727 .dpp8,843 .dpp8,
728 .extended_image_insts,844 .extended_image_insts,
729 .fast_denormal_f32,845 .fast_denormal_f32,
730 .fast_fmaf,846 .fast_fmaf,
731 .flat_address_space,
732 .flat_global_insts,847 .flat_global_insts,
733 .flat_inst_offsets,848 .flat_inst_offsets,
734 .flat_scratch_insts,849 .flat_scratch_insts,
...@@ -743,14 +858,17 @@ pub const all_features = blk: {...@@ -743,14 +858,17 @@ pub const all_features = blk: {
743 .image_insts,858 .image_insts,
744 .int_clamp_insts,859 .int_clamp_insts,
745 .inv_2pi_inline_imm,860 .inv_2pi_inline_imm,
861 .lerp_inst,
746 .max_hard_clause_length_63,862 .max_hard_clause_length_63,
747 .mimg_r128,863 .mimg_r128,
748 .movrel,864 .movrel,
749 .no_data_dep_hazard,865 .no_data_dep_hazard,
750 .no_sdst_cmpx,866 .no_sdst_cmpx,
751 .pk_fmac_f16_inst,867 .pk_fmac_f16_inst,
868 .qsad_insts,
752 .s_memrealtime,869 .s_memrealtime,
753 .s_memtime_inst,870 .s_memtime_inst,
871 .sad_insts,
754 .sdwa,872 .sdwa,
755 .sdwa_omod,873 .sdwa_omod,
756 .sdwa_scalar,874 .sdwa_scalar,
...@@ -797,13 +915,16 @@ pub const all_features = blk: {...@@ -797,13 +915,16 @@ pub const all_features = blk: {
797 .atomic_fmin_fmax_flat_f32,915 .atomic_fmin_fmax_flat_f32,
798 .atomic_fmin_fmax_global_f32,916 .atomic_fmin_fmax_global_f32,
799 .ci_insts,917 .ci_insts,
918 .cube_insts,
919 .cvt_norm_insts,
920 .cvt_pknorm_vop2_insts,
921 .cvt_pknorm_vop3_insts,
800 .default_component_zero,922 .default_component_zero,
801 .dpp,923 .dpp,
802 .dpp8,924 .dpp8,
803 .extended_image_insts,925 .extended_image_insts,
804 .fast_denormal_f32,926 .fast_denormal_f32,
805 .fast_fmaf,927 .fast_fmaf,
806 .flat_address_space,
807 .flat_global_insts,928 .flat_global_insts,
808 .flat_inst_offsets,929 .flat_inst_offsets,
809 .flat_scratch_insts,930 .flat_scratch_insts,
...@@ -821,12 +942,15 @@ pub const all_features = blk: {...@@ -821,12 +942,15 @@ pub const all_features = blk: {
821 .gws,942 .gws,
822 .int_clamp_insts,943 .int_clamp_insts,
823 .inv_2pi_inline_imm,944 .inv_2pi_inline_imm,
945 .lerp_inst,
824 .max_hard_clause_length_32,946 .max_hard_clause_length_32,
825 .mimg_r128,947 .mimg_r128,
826 .movrel,948 .movrel,
827 .no_data_dep_hazard,949 .no_data_dep_hazard,
828 .no_sdst_cmpx,950 .no_sdst_cmpx,
829 .pk_fmac_f16_inst,951 .pk_fmac_f16_inst,
952 .qsad_insts,
953 .sad_insts,
830 .true16,954 .true16,
831 .unaligned_buffer_access,955 .unaligned_buffer_access,
832 .unaligned_ds_access,956 .unaligned_ds_access,
...@@ -850,7 +974,6 @@ pub const all_features = blk: {...@@ -850,7 +974,6 @@ pub const all_features = blk: {
850 .@"16_bit_insts",974 .@"16_bit_insts",
851 .a16,975 .a16,
852 .add_no_carry_insts,976 .add_no_carry_insts,
853 .addressablelocalmemorysize65536,
854 .agent_scope_fine_grained_remote_memory_atomics,977 .agent_scope_fine_grained_remote_memory_atomics,
855 .aperture_regs,978 .aperture_regs,
856 .atomic_fmin_fmax_flat_f32,979 .atomic_fmin_fmax_flat_f32,
...@@ -861,7 +984,6 @@ pub const all_features = blk: {...@@ -861,7 +984,6 @@ pub const all_features = blk: {
861 .dpp8,984 .dpp8,
862 .fast_denormal_f32,985 .fast_denormal_f32,
863 .fast_fmaf,986 .fast_fmaf,
864 .flat_address_space,
865 .flat_global_insts,987 .flat_global_insts,
866 .flat_inst_offsets,988 .flat_inst_offsets,
867 .flat_scratch_insts,989 .flat_scratch_insts,
...@@ -926,11 +1048,14 @@ pub const all_features = blk: {...@@ -926,11 +1048,14 @@ pub const all_features = blk: {
926 .add_no_carry_insts,1048 .add_no_carry_insts,
927 .aperture_regs,1049 .aperture_regs,
928 .ci_insts,1050 .ci_insts,
1051 .cube_insts,
1052 .cvt_norm_insts,
1053 .cvt_pknorm_vop2_insts,
1054 .cvt_pknorm_vop3_insts,
929 .default_component_zero,1055 .default_component_zero,
930 .dpp,1056 .dpp,
931 .fast_denormal_f32,1057 .fast_denormal_f32,
932 .fast_fmaf,1058 .fast_fmaf,
933 .flat_address_space,
934 .flat_global_insts,1059 .flat_global_insts,
935 .flat_inst_offsets,1060 .flat_inst_offsets,
936 .flat_scratch_insts,1061 .flat_scratch_insts,
...@@ -942,10 +1067,13 @@ pub const all_features = blk: {...@@ -942,10 +1067,13 @@ pub const all_features = blk: {
942 .gws,1067 .gws,
943 .int_clamp_insts,1068 .int_clamp_insts,
944 .inv_2pi_inline_imm,1069 .inv_2pi_inline_imm,
1070 .lerp_inst,
945 .negative_scratch_offset_bug,1071 .negative_scratch_offset_bug,
1072 .qsad_insts,
946 .r128_a16,1073 .r128_a16,
947 .s_memrealtime,1074 .s_memrealtime,
948 .s_memtime_inst,1075 .s_memtime_inst,
1076 .sad_insts,
949 .scalar_atomics,1077 .scalar_atomics,
950 .scalar_flat_scratch_insts,1078 .scalar_flat_scratch_insts,
951 .scalar_stores,1079 .scalar_stores,
...@@ -997,6 +1125,11 @@ pub const all_features = blk: {...@@ -997,6 +1125,11 @@ pub const all_features = blk: {
997 .description = "Additional instructions for GFX9+",1125 .description = "Additional instructions for GFX9+",
998 .dependencies = featureSet(&[_]Feature{}),1126 .dependencies = featureSet(&[_]Feature{}),
999 };1127 };
1128 result[@intFromEnum(Feature.globally_addressable_scratch)] = .{
1129 .llvm_name = "globally-addressable-scratch",
1130 .description = "FLAT instructions can access scratch memory for any thread in any wave",
1131 .dependencies = featureSet(&[_]Feature{}),
1132 };
1000 result[@intFromEnum(Feature.gws)] = .{1133 result[@intFromEnum(Feature.gws)] = .{
1001 .llvm_name = "gws",1134 .llvm_name = "gws",
1002 .description = "Has Global Wave Sync",1135 .description = "Has Global Wave Sync",
...@@ -1072,6 +1205,11 @@ pub const all_features = blk: {...@@ -1072,6 +1205,11 @@ pub const all_features = blk: {
1072 .description = "The number of LDS banks per compute unit.",1205 .description = "The number of LDS banks per compute unit.",
1073 .dependencies = featureSet(&[_]Feature{}),1206 .dependencies = featureSet(&[_]Feature{}),
1074 };1207 };
1208 result[@intFromEnum(Feature.lerp_inst)] = .{
1209 .llvm_name = "lerp-inst",
1210 .description = "Has v_lerp_u8 instruction",
1211 .dependencies = featureSet(&[_]Feature{}),
1212 };
1075 result[@intFromEnum(Feature.load_store_opt)] = .{1213 result[@intFromEnum(Feature.load_store_opt)] = .{
1076 .llvm_name = "load-store-opt",1214 .llvm_name = "load-store-opt",
1077 .description = "Enable SI load/store optimizer pass",1215 .description = "Enable SI load/store optimizer pass",
...@@ -1097,6 +1235,11 @@ pub const all_features = blk: {...@@ -1097,6 +1235,11 @@ pub const all_features = blk: {
1097 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",1235 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
1098 .dependencies = featureSet(&[_]Feature{}),1236 .dependencies = featureSet(&[_]Feature{}),
1099 };1237 };
1238 result[@intFromEnum(Feature.mad_u32_inst)] = .{
1239 .llvm_name = "mad-u32-inst",
1240 .description = "Has v_mad_u32 instruction",
1241 .dependencies = featureSet(&[_]Feature{}),
1242 };
1100 result[@intFromEnum(Feature.mai_insts)] = .{1243 result[@intFromEnum(Feature.mai_insts)] = .{
1101 .llvm_name = "mai-insts",1244 .llvm_name = "mai-insts",
1102 .description = "Has mAI instructions",1245 .description = "Has mAI instructions",
...@@ -1127,6 +1270,11 @@ pub const all_features = blk: {...@@ -1127,6 +1270,11 @@ pub const all_features = blk: {
1127 .description = "Maximum private access size may be 8",1270 .description = "Maximum private access size may be 8",
1128 .dependencies = featureSet(&[_]Feature{}),1271 .dependencies = featureSet(&[_]Feature{}),
1129 };1272 };
1273 result[@intFromEnum(Feature.mcast_load_insts)] = .{
1274 .llvm_name = "mcast-load-insts",
1275 .description = "Has multicast load instructions",
1276 .dependencies = featureSet(&[_]Feature{}),
1277 };
1130 result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{1278 result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{
1131 .llvm_name = "memory-atomic-fadd-f32-denormal-support",1279 .llvm_name = "memory-atomic-fadd-f32-denormal-support",
1132 .description = "global/flat/buffer atomic fadd for float supports denormal handling",1280 .description = "global/flat/buffer atomic fadd for float supports denormal handling",
...@@ -1142,6 +1290,11 @@ pub const all_features = blk: {...@@ -1142,6 +1290,11 @@ pub const all_features = blk: {
1142 .description = "Support 128-bit texture resources",1290 .description = "Support 128-bit texture resources",
1143 .dependencies = featureSet(&[_]Feature{}),1291 .dependencies = featureSet(&[_]Feature{}),
1144 };1292 };
1293 result[@intFromEnum(Feature.min3_max3_pkf16)] = .{
1294 .llvm_name = "min3-max3-pkf16",
1295 .description = "Has v_pk_min3_num_f16 and v_pk_max3_num_f16 instructions",
1296 .dependencies = featureSet(&[_]Feature{}),
1297 };
1145 result[@intFromEnum(Feature.minimum3_maximum3_f16)] = .{1298 result[@intFromEnum(Feature.minimum3_maximum3_f16)] = .{
1146 .llvm_name = "minimum3-maximum3-f16",1299 .llvm_name = "minimum3-maximum3-f16",
1147 .description = "Has v_minimum3_f16 and v_maximum3_f16 instructions",1300 .description = "Has v_minimum3_f16 and v_maximum3_f16 instructions",
...@@ -1232,6 +1385,11 @@ pub const all_features = blk: {...@@ -1232,6 +1385,11 @@ pub const all_features = blk: {
1232 .description = "Has v_permlane32_swap_b32 instructions",1385 .description = "Has v_permlane32_swap_b32 instructions",
1233 .dependencies = featureSet(&[_]Feature{}),1386 .dependencies = featureSet(&[_]Feature{}),
1234 };1387 };
1388 result[@intFromEnum(Feature.pk_add_min_max_insts)] = .{
1389 .llvm_name = "pk-add-min-max-insts",
1390 .description = "Has v_pk_add_{min|max}_{i|u}16 instructions",
1391 .dependencies = featureSet(&[_]Feature{}),
1392 };
1235 result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{1393 result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
1236 .llvm_name = "pk-fmac-f16-inst",1394 .llvm_name = "pk-fmac-f16-inst",
1237 .description = "Has v_pk_fmac_f16 instruction",1395 .description = "Has v_pk_fmac_f16 instruction",
...@@ -1272,6 +1430,11 @@ pub const all_features = blk: {...@@ -1272,6 +1430,11 @@ pub const all_features = blk: {
1272 .description = "Has Pseudo Scalar Transcendental instructions",1430 .description = "Has Pseudo Scalar Transcendental instructions",
1273 .dependencies = featureSet(&[_]Feature{}),1431 .dependencies = featureSet(&[_]Feature{}),
1274 };1432 };
1433 result[@intFromEnum(Feature.qsad_insts)] = .{
1434 .llvm_name = "qsad-insts",
1435 .description = "Has v_qsad* instructions",
1436 .dependencies = featureSet(&[_]Feature{}),
1437 };
1275 result[@intFromEnum(Feature.r128_a16)] = .{1438 result[@intFromEnum(Feature.r128_a16)] = .{
1276 .llvm_name = "r128-a16",1439 .llvm_name = "r128-a16",
1277 .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",1440 .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
...@@ -1312,6 +1475,21 @@ pub const all_features = blk: {...@@ -1312,6 +1475,21 @@ pub const all_features = blk: {
1312 .description = "Has s_memtime instruction",1475 .description = "Has s_memtime instruction",
1313 .dependencies = featureSet(&[_]Feature{}),1476 .dependencies = featureSet(&[_]Feature{}),
1314 };1477 };
1478 result[@intFromEnum(Feature.s_wakeup_barrier_inst)] = .{
1479 .llvm_name = "s-wakeup-barrier-inst",
1480 .description = "Has s_wakeup_barrier instruction.",
1481 .dependencies = featureSet(&[_]Feature{}),
1482 };
1483 result[@intFromEnum(Feature.sad_insts)] = .{
1484 .llvm_name = "sad-insts",
1485 .description = "Has v_sad* instructions",
1486 .dependencies = featureSet(&[_]Feature{}),
1487 };
1488 result[@intFromEnum(Feature.safe_cu_prefetch)] = .{
1489 .llvm_name = "safe-cu-prefetch",
1490 .description = "VMEM CU scope prefetches do not fail on illegal address",
1491 .dependencies = featureSet(&[_]Feature{}),
1492 };
1315 result[@intFromEnum(Feature.safe_smem_prefetch)] = .{1493 result[@intFromEnum(Feature.safe_smem_prefetch)] = .{
1316 .llvm_name = "safe-smem-prefetch",1494 .llvm_name = "safe-smem-prefetch",
1317 .description = "SMEM prefetches do not fail on illegal address",1495 .description = "SMEM prefetches do not fail on illegal address",
...@@ -1382,19 +1560,23 @@ pub const all_features = blk: {...@@ -1382,19 +1560,23 @@ pub const all_features = blk: {
1382 .atomic_fmin_fmax_global_f32,1560 .atomic_fmin_fmax_global_f32,
1383 .atomic_fmin_fmax_global_f64,1561 .atomic_fmin_fmax_global_f64,
1384 .ci_insts,1562 .ci_insts,
1563 .cube_insts,
1564 .cvt_pknorm_vop2_insts,
1385 .default_component_zero,1565 .default_component_zero,
1386 .ds_src2_insts,1566 .ds_src2_insts,
1387 .extended_image_insts,1567 .extended_image_insts,
1388 .flat_address_space,
1389 .fp64,1568 .fp64,
1390 .gds,1569 .gds,
1391 .gfx7_gfx8_gfx9_insts,1570 .gfx7_gfx8_gfx9_insts,
1392 .gws,1571 .gws,
1393 .image_insts,1572 .image_insts,
1573 .lerp_inst,
1394 .mad_mac_f32_insts,1574 .mad_mac_f32_insts,
1395 .mimg_r128,1575 .mimg_r128,
1396 .movrel,1576 .movrel,
1577 .qsad_insts,
1397 .s_memtime_inst,1578 .s_memtime_inst,
1579 .sad_insts,
1398 .trig_reduced_range,1580 .trig_reduced_range,
1399 .unaligned_buffer_access,1581 .unaligned_buffer_access,
1400 .vmem_write_vgpr_in_order,1582 .vmem_write_vgpr_in_order,
...@@ -1406,6 +1588,11 @@ pub const all_features = blk: {...@@ -1406,6 +1588,11 @@ pub const all_features = blk: {
1406 .description = "Has s_setprio_inc_wg instruction.",1588 .description = "Has s_setprio_inc_wg instruction.",
1407 .dependencies = featureSet(&[_]Feature{}),1589 .dependencies = featureSet(&[_]Feature{}),
1408 };1590 };
1591 result[@intFromEnum(Feature.setreg_vgpr_msb_fixup)] = .{
1592 .llvm_name = "setreg-vgpr-msb-fixup",
1593 .description = "S_SETREG to MODE clobbers VGPR MSB bits, requires fixup",
1594 .dependencies = featureSet(&[_]Feature{}),
1595 };
1409 result[@intFromEnum(Feature.sgpr_init_bug)] = .{1596 result[@intFromEnum(Feature.sgpr_init_bug)] = .{
1410 .llvm_name = "sgpr-init-bug",1597 .llvm_name = "sgpr-init-bug",
1411 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",1598 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
...@@ -1438,6 +1625,8 @@ pub const all_features = blk: {...@@ -1438,6 +1625,8 @@ pub const all_features = blk: {
1438 .addressablelocalmemorysize32768,1625 .addressablelocalmemorysize32768,
1439 .atomic_fmin_fmax_global_f32,1626 .atomic_fmin_fmax_global_f32,
1440 .atomic_fmin_fmax_global_f64,1627 .atomic_fmin_fmax_global_f64,
1628 .cube_insts,
1629 .cvt_pknorm_vop2_insts,
1441 .default_component_zero,1630 .default_component_zero,
1442 .ds_src2_insts,1631 .ds_src2_insts,
1443 .extended_image_insts,1632 .extended_image_insts,
...@@ -1446,10 +1635,12 @@ pub const all_features = blk: {...@@ -1446,10 +1635,12 @@ pub const all_features = blk: {
1446 .gws,1635 .gws,
1447 .image_insts,1636 .image_insts,
1448 .ldsbankcount32,1637 .ldsbankcount32,
1638 .lerp_inst,
1449 .mad_mac_f32_insts,1639 .mad_mac_f32_insts,
1450 .mimg_r128,1640 .mimg_r128,
1451 .movrel,1641 .movrel,
1452 .s_memtime_inst,1642 .s_memtime_inst,
1643 .sad_insts,
1453 .trig_reduced_range,1644 .trig_reduced_range,
1454 .vmem_write_vgpr_in_order,1645 .vmem_write_vgpr_in_order,
1455 .wavefrontsize64,1646 .wavefrontsize64,
...@@ -1465,6 +1656,16 @@ pub const all_features = blk: {...@@ -1465,6 +1656,16 @@ pub const all_features = blk: {
1465 .description = "Hardware supports SRAMECC",1656 .description = "Hardware supports SRAMECC",
1466 .dependencies = featureSet(&[_]Feature{}),1657 .dependencies = featureSet(&[_]Feature{}),
1467 };1658 };
1659 result[@intFromEnum(Feature.tanh_insts)] = .{
1660 .llvm_name = "tanh-insts",
1661 .description = "Has v_tanh_f32/f16 instructions",
1662 .dependencies = featureSet(&[_]Feature{}),
1663 };
1664 result[@intFromEnum(Feature.tensor_cvt_lut_insts)] = .{
1665 .llvm_name = "tensor-cvt-lut-insts",
1666 .description = "Has v_perm_pk16* instructions",
1667 .dependencies = featureSet(&[_]Feature{}),
1668 };
1468 result[@intFromEnum(Feature.tgsplit)] = .{1669 result[@intFromEnum(Feature.tgsplit)] = .{
1469 .llvm_name = "tgsplit",1670 .llvm_name = "tgsplit",
1470 .description = "Enable threadgroup split execution",1671 .description = "Enable threadgroup split execution",
...@@ -1540,11 +1741,21 @@ pub const all_features = blk: {...@@ -1540,11 +1741,21 @@ pub const all_features = blk: {
1540 .description = "TODO: describe me",1741 .description = "TODO: describe me",
1541 .dependencies = featureSet(&[_]Feature{}),1742 .dependencies = featureSet(&[_]Feature{}),
1542 };1743 };
1744 result[@intFromEnum(Feature.vgpr_align2)] = .{
1745 .llvm_name = "vgpr-align2",
1746 .description = "VGPR and AGPR tuple operands require even alignment",
1747 .dependencies = featureSet(&[_]Feature{}),
1748 };
1543 result[@intFromEnum(Feature.vgpr_index_mode)] = .{1749 result[@intFromEnum(Feature.vgpr_index_mode)] = .{
1544 .llvm_name = "vgpr-index-mode",1750 .llvm_name = "vgpr-index-mode",
1545 .description = "Has VGPR mode register indexing",1751 .description = "Has VGPR mode register indexing",
1546 .dependencies = featureSet(&[_]Feature{}),1752 .dependencies = featureSet(&[_]Feature{}),
1547 };1753 };
1754 result[@intFromEnum(Feature.vmem_pref_insts)] = .{
1755 .llvm_name = "vmem-pref-insts",
1756 .description = "Has flat_prefect_b8 and global_prefetch_b8 instructions",
1757 .dependencies = featureSet(&[_]Feature{}),
1758 };
1548 result[@intFromEnum(Feature.vmem_to_lds_load_insts)] = .{1759 result[@intFromEnum(Feature.vmem_to_lds_load_insts)] = .{
1549 .llvm_name = "vmem-to-lds-load-insts",1760 .llvm_name = "vmem-to-lds-load-insts",
1550 .description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.",1761 .description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.",
...@@ -1567,6 +1778,8 @@ pub const all_features = blk: {...@@ -1567,6 +1778,8 @@ pub const all_features = blk: {
1567 .@"16_bit_insts",1778 .@"16_bit_insts",
1568 .addressablelocalmemorysize65536,1779 .addressablelocalmemorysize65536,
1569 .ci_insts,1780 .ci_insts,
1781 .cube_insts,
1782 .cvt_pknorm_vop2_insts,
1570 .default_component_zero,1783 .default_component_zero,
1571 .dpp,1784 .dpp,
1572 .ds_src2_insts,1785 .ds_src2_insts,
...@@ -1582,11 +1795,14 @@ pub const all_features = blk: {...@@ -1582,11 +1795,14 @@ pub const all_features = blk: {
1582 .image_insts,1795 .image_insts,
1583 .int_clamp_insts,1796 .int_clamp_insts,
1584 .inv_2pi_inline_imm,1797 .inv_2pi_inline_imm,
1798 .lerp_inst,
1585 .mad_mac_f32_insts,1799 .mad_mac_f32_insts,
1586 .mimg_r128,1800 .mimg_r128,
1587 .movrel,1801 .movrel,
1802 .qsad_insts,
1588 .s_memrealtime,1803 .s_memrealtime,
1589 .s_memtime_inst,1804 .s_memtime_inst,
1805 .sad_insts,
1590 .scalar_stores,1806 .scalar_stores,
1591 .sdwa,1807 .sdwa,
1592 .sdwa_mav,1808 .sdwa_mav,
...@@ -1623,6 +1839,11 @@ pub const all_features = blk: {...@@ -1623,6 +1839,11 @@ pub const all_features = blk: {
1623 .description = "Has s_wait_xcnt instruction",1839 .description = "Has s_wait_xcnt instruction",
1624 .dependencies = featureSet(&[_]Feature{}),1840 .dependencies = featureSet(&[_]Feature{}),
1625 };1841 };
1842 result[@intFromEnum(Feature.waits_before_system_scope_stores)] = .{
1843 .llvm_name = "waits-before-system-scope-stores",
1844 .description = "Target requires waits for loads and atomics before system scope stores",
1845 .dependencies = featureSet(&[_]Feature{}),
1846 };
1626 result[@intFromEnum(Feature.wavefrontsize16)] = .{1847 result[@intFromEnum(Feature.wavefrontsize16)] = .{
1627 .llvm_name = "wavefrontsize16",1848 .llvm_name = "wavefrontsize16",
1628 .description = "The number of threads per wavefront",1849 .description = "The number of threads per wavefront",
...@@ -2044,6 +2265,8 @@ pub const cpu = struct {...@@ -2044,6 +2265,8 @@ pub const cpu = struct {
2044 .architected_flat_scratch,2265 .architected_flat_scratch,
2045 .atomic_fadd_no_rtn_insts,2266 .atomic_fadd_no_rtn_insts,
2046 .atomic_fadd_rtn_insts,2267 .atomic_fadd_rtn_insts,
2268 .back_off_barrier,
2269 .d16_write_vgpr32,
2047 .dl_insts,2270 .dl_insts,
2048 .dot10_insts,2271 .dot10_insts,
2049 .dot12_insts,2272 .dot12_insts,
...@@ -2077,6 +2300,8 @@ pub const cpu = struct {...@@ -2077,6 +2300,8 @@ pub const cpu = struct {
2077 .architected_flat_scratch,2300 .architected_flat_scratch,
2078 .atomic_fadd_no_rtn_insts,2301 .atomic_fadd_no_rtn_insts,
2079 .atomic_fadd_rtn_insts,2302 .atomic_fadd_rtn_insts,
2303 .back_off_barrier,
2304 .d16_write_vgpr32,
2080 .dl_insts,2305 .dl_insts,
2081 .dot10_insts,2306 .dot10_insts,
2082 .dot12_insts,2307 .dot12_insts,
...@@ -2108,6 +2333,8 @@ pub const cpu = struct {...@@ -2108,6 +2333,8 @@ pub const cpu = struct {
2108 .architected_flat_scratch,2333 .architected_flat_scratch,
2109 .atomic_fadd_no_rtn_insts,2334 .atomic_fadd_no_rtn_insts,
2110 .atomic_fadd_rtn_insts,2335 .atomic_fadd_rtn_insts,
2336 .back_off_barrier,
2337 .d16_write_vgpr32,
2111 .dl_insts,2338 .dl_insts,
2112 .dot10_insts,2339 .dot10_insts,
2113 .dot12_insts,2340 .dot12_insts,
...@@ -2140,6 +2367,8 @@ pub const cpu = struct {...@@ -2140,6 +2367,8 @@ pub const cpu = struct {
2140 .architected_flat_scratch,2367 .architected_flat_scratch,
2141 .atomic_fadd_no_rtn_insts,2368 .atomic_fadd_no_rtn_insts,
2142 .atomic_fadd_rtn_insts,2369 .atomic_fadd_rtn_insts,
2370 .back_off_barrier,
2371 .d16_write_vgpr32,
2143 .dl_insts,2372 .dl_insts,
2144 .dot10_insts,2373 .dot10_insts,
2145 .dot12_insts,2374 .dot12_insts,
...@@ -2171,6 +2400,8 @@ pub const cpu = struct {...@@ -2171,6 +2400,8 @@ pub const cpu = struct {
2171 .architected_flat_scratch,2400 .architected_flat_scratch,
2172 .atomic_fadd_no_rtn_insts,2401 .atomic_fadd_no_rtn_insts,
2173 .atomic_fadd_rtn_insts,2402 .atomic_fadd_rtn_insts,
2403 .back_off_barrier,
2404 .d16_write_vgpr32,
2174 .dl_insts,2405 .dl_insts,
2175 .dot10_insts,2406 .dot10_insts,
2176 .dot12_insts,2407 .dot12_insts,
...@@ -2188,6 +2419,7 @@ pub const cpu = struct {...@@ -2188,6 +2419,7 @@ pub const cpu = struct {
2188 .packed_tid,2419 .packed_tid,
2189 .partial_nsa_encoding,2420 .partial_nsa_encoding,
2190 .point_sample_accel,2421 .point_sample_accel,
2422 .real_true16,
2191 .required_export_priority,2423 .required_export_priority,
2192 .salu_float,2424 .salu_float,
2193 .shader_cycles_register,2425 .shader_cycles_register,
...@@ -2202,6 +2434,8 @@ pub const cpu = struct {...@@ -2202,6 +2434,8 @@ pub const cpu = struct {
2202 .architected_flat_scratch,2434 .architected_flat_scratch,
2203 .atomic_fadd_no_rtn_insts,2435 .atomic_fadd_no_rtn_insts,
2204 .atomic_fadd_rtn_insts,2436 .atomic_fadd_rtn_insts,
2437 .back_off_barrier,
2438 .d16_write_vgpr32,
2205 .dl_insts,2439 .dl_insts,
2206 .dot10_insts,2440 .dot10_insts,
2207 .dot12_insts,2441 .dot12_insts,
...@@ -2219,6 +2453,7 @@ pub const cpu = struct {...@@ -2219,6 +2453,7 @@ pub const cpu = struct {
2219 .packed_tid,2453 .packed_tid,
2220 .partial_nsa_encoding,2454 .partial_nsa_encoding,
2221 .point_sample_accel,2455 .point_sample_accel,
2456 .real_true16,
2222 .required_export_priority,2457 .required_export_priority,
2223 .salu_float,2458 .salu_float,
2224 .shader_cycles_register,2459 .shader_cycles_register,
...@@ -2232,6 +2467,8 @@ pub const cpu = struct {...@@ -2232,6 +2467,8 @@ pub const cpu = struct {
2232 .architected_flat_scratch,2467 .architected_flat_scratch,
2233 .atomic_fadd_no_rtn_insts,2468 .atomic_fadd_no_rtn_insts,
2234 .atomic_fadd_rtn_insts,2469 .atomic_fadd_rtn_insts,
2470 .back_off_barrier,
2471 .d16_write_vgpr32,
2235 .dl_insts,2472 .dl_insts,
2236 .dot10_insts,2473 .dot10_insts,
2237 .dot12_insts,2474 .dot12_insts,
...@@ -2249,6 +2486,7 @@ pub const cpu = struct {...@@ -2249,6 +2486,7 @@ pub const cpu = struct {
2249 .packed_tid,2486 .packed_tid,
2250 .partial_nsa_encoding,2487 .partial_nsa_encoding,
2251 .point_sample_accel,2488 .point_sample_accel,
2489 .real_true16,
2252 .required_export_priority,2490 .required_export_priority,
2253 .salu_float,2491 .salu_float,
2254 .shader_cycles_register,2492 .shader_cycles_register,
...@@ -2262,6 +2500,8 @@ pub const cpu = struct {...@@ -2262,6 +2500,8 @@ pub const cpu = struct {
2262 .architected_flat_scratch,2500 .architected_flat_scratch,
2263 .atomic_fadd_no_rtn_insts,2501 .atomic_fadd_no_rtn_insts,
2264 .atomic_fadd_rtn_insts,2502 .atomic_fadd_rtn_insts,
2503 .back_off_barrier,
2504 .d16_write_vgpr32,
2265 .dl_insts,2505 .dl_insts,
2266 .dot10_insts,2506 .dot10_insts,
2267 .dot12_insts,2507 .dot12_insts,
...@@ -2278,6 +2518,7 @@ pub const cpu = struct {...@@ -2278,6 +2518,7 @@ pub const cpu = struct {
2278 .nsa_encoding,2518 .nsa_encoding,
2279 .packed_tid,2519 .packed_tid,
2280 .partial_nsa_encoding,2520 .partial_nsa_encoding,
2521 .real_true16,
2281 .required_export_priority,2522 .required_export_priority,
2282 .salu_float,2523 .salu_float,
2283 .shader_cycles_register,2524 .shader_cycles_register,
...@@ -2291,6 +2532,8 @@ pub const cpu = struct {...@@ -2291,6 +2532,8 @@ pub const cpu = struct {
2291 .architected_flat_scratch,2532 .architected_flat_scratch,
2292 .atomic_fadd_no_rtn_insts,2533 .atomic_fadd_no_rtn_insts,
2293 .atomic_fadd_rtn_insts,2534 .atomic_fadd_rtn_insts,
2535 .back_off_barrier,
2536 .d16_write_vgpr32,
2294 .dl_insts,2537 .dl_insts,
2295 .dot10_insts,2538 .dot10_insts,
2296 .dot12_insts,2539 .dot12_insts,
...@@ -2309,6 +2552,7 @@ pub const cpu = struct {...@@ -2309,6 +2552,7 @@ pub const cpu = struct {
2309 .packed_tid,2552 .packed_tid,
2310 .partial_nsa_encoding,2553 .partial_nsa_encoding,
2311 .priv_enabled_trap2_nop_bug,2554 .priv_enabled_trap2_nop_bug,
2555 .real_true16,
2312 .required_export_priority,2556 .required_export_priority,
2313 .requires_cov6,2557 .requires_cov6,
2314 .shader_cycles_register,2558 .shader_cycles_register,
...@@ -2321,6 +2565,7 @@ pub const cpu = struct {...@@ -2321,6 +2565,7 @@ pub const cpu = struct {
2321 .name = "gfx1200",2565 .name = "gfx1200",
2322 .llvm_name = "gfx1200",2566 .llvm_name = "gfx1200",
2323 .features = featureSet(&[_]Feature{2567 .features = featureSet(&[_]Feature{
2568 .addressablelocalmemorysize65536,
2324 .allocate1_5xvgprs,2569 .allocate1_5xvgprs,
2325 .architected_flat_scratch,2570 .architected_flat_scratch,
2326 .architected_sgprs,2571 .architected_sgprs,
...@@ -2331,7 +2576,13 @@ pub const cpu = struct {...@@ -2331,7 +2576,13 @@ pub const cpu = struct {
2331 .atomic_fadd_rtn_insts,2576 .atomic_fadd_rtn_insts,
2332 .atomic_flat_pk_add_16_insts,2577 .atomic_flat_pk_add_16_insts,
2333 .atomic_global_pk_add_bf16_inst,2578 .atomic_global_pk_add_bf16_inst,
2579 .back_off_barrier,
2334 .bvh_dual_bvh_8_insts,2580 .bvh_dual_bvh_8_insts,
2581 .cube_insts,
2582 .cvt_norm_insts,
2583 .cvt_pknorm_vop2_insts,
2584 .cvt_pknorm_vop3_insts,
2585 .d16_write_vgpr32,
2335 .dl_insts,2586 .dl_insts,
2336 .dot10_insts,2587 .dot10_insts,
2337 .dot11_insts,2588 .dot11_insts,
...@@ -2346,22 +2597,27 @@ pub const cpu = struct {...@@ -2346,22 +2597,27 @@ pub const cpu = struct {
2346 .gfx12,2597 .gfx12,
2347 .image_insts,2598 .image_insts,
2348 .ldsbankcount32,2599 .ldsbankcount32,
2600 .lerp_inst,
2349 .memory_atomic_fadd_f32_denormal_support,2601 .memory_atomic_fadd_f32_denormal_support,
2350 .nsa_encoding,2602 .nsa_encoding,
2351 .packed_tid,2603 .packed_tid,
2352 .partial_nsa_encoding,2604 .partial_nsa_encoding,
2353 .pseudo_scalar_trans,2605 .pseudo_scalar_trans,
2606 .qsad_insts,
2354 .restricted_soffset,2607 .restricted_soffset,
2608 .sad_insts,
2355 .salu_float,2609 .salu_float,
2356 .scalar_dwordx3_loads,2610 .scalar_dwordx3_loads,
2357 .shader_cycles_hi_lo_registers,2611 .shader_cycles_hi_lo_registers,
2358 .vcmpx_permlane_hazard,2612 .vcmpx_permlane_hazard,
2613 .waits_before_system_scope_stores,
2359 }),2614 }),
2360 };2615 };
2361 pub const gfx1201: CpuModel = .{2616 pub const gfx1201: CpuModel = .{
2362 .name = "gfx1201",2617 .name = "gfx1201",
2363 .llvm_name = "gfx1201",2618 .llvm_name = "gfx1201",
2364 .features = featureSet(&[_]Feature{2619 .features = featureSet(&[_]Feature{
2620 .addressablelocalmemorysize65536,
2365 .allocate1_5xvgprs,2621 .allocate1_5xvgprs,
2366 .architected_flat_scratch,2622 .architected_flat_scratch,
2367 .architected_sgprs,2623 .architected_sgprs,
...@@ -2372,7 +2628,13 @@ pub const cpu = struct {...@@ -2372,7 +2628,13 @@ pub const cpu = struct {
2372 .atomic_fadd_rtn_insts,2628 .atomic_fadd_rtn_insts,
2373 .atomic_flat_pk_add_16_insts,2629 .atomic_flat_pk_add_16_insts,
2374 .atomic_global_pk_add_bf16_inst,2630 .atomic_global_pk_add_bf16_inst,
2631 .back_off_barrier,
2375 .bvh_dual_bvh_8_insts,2632 .bvh_dual_bvh_8_insts,
2633 .cube_insts,
2634 .cvt_norm_insts,
2635 .cvt_pknorm_vop2_insts,
2636 .cvt_pknorm_vop3_insts,
2637 .d16_write_vgpr32,
2376 .dl_insts,2638 .dl_insts,
2377 .dot10_insts,2639 .dot10_insts,
2378 .dot11_insts,2640 .dot11_insts,
...@@ -2387,23 +2649,32 @@ pub const cpu = struct {...@@ -2387,23 +2649,32 @@ pub const cpu = struct {
2387 .gfx12,2649 .gfx12,
2388 .image_insts,2650 .image_insts,
2389 .ldsbankcount32,2651 .ldsbankcount32,
2652 .lerp_inst,
2390 .memory_atomic_fadd_f32_denormal_support,2653 .memory_atomic_fadd_f32_denormal_support,
2391 .nsa_encoding,2654 .nsa_encoding,
2392 .packed_tid,2655 .packed_tid,
2393 .partial_nsa_encoding,2656 .partial_nsa_encoding,
2394 .pseudo_scalar_trans,2657 .pseudo_scalar_trans,
2658 .qsad_insts,
2395 .restricted_soffset,2659 .restricted_soffset,
2660 .sad_insts,
2396 .salu_float,2661 .salu_float,
2397 .scalar_dwordx3_loads,2662 .scalar_dwordx3_loads,
2398 .shader_cycles_hi_lo_registers,2663 .shader_cycles_hi_lo_registers,
2399 .vcmpx_permlane_hazard,2664 .vcmpx_permlane_hazard,
2665 .waits_before_system_scope_stores,
2400 }),2666 }),
2401 };2667 };
2402 pub const gfx1250: CpuModel = .{2668 pub const gfx1250: CpuModel = .{
2403 .name = "gfx1250",2669 .name = "gfx1250",
2404 .llvm_name = "gfx1250",2670 .llvm_name = "gfx1250",
2405 .features = featureSet(&[_]Feature{2671 .features = featureSet(&[_]Feature{
2672 .@"1024_addressable_vgprs",
2673 .@"45_bit_num_records_buffer_resource",
2406 .@"64_bit_literals",2674 .@"64_bit_literals",
2675 .add_min_max_insts,
2676 .add_sub_u64_insts,
2677 .addressablelocalmemorysize327680,
2407 .architected_flat_scratch,2678 .architected_flat_scratch,
2408 .architected_sgprs,2679 .architected_sgprs,
2409 .ashr_pk_insts,2680 .ashr_pk_insts,
...@@ -2417,49 +2688,164 @@ pub const cpu = struct {...@@ -2417,49 +2688,164 @@ pub const cpu = struct {
2417 .atomic_fmin_fmax_global_f64,2688 .atomic_fmin_fmax_global_f64,
2418 .atomic_global_pk_add_bf16_inst,2689 .atomic_global_pk_add_bf16_inst,
2419 .bf16_cvt_insts,2690 .bf16_cvt_insts,
2691 .bf16_pk_insts,
2420 .bf16_trans_insts,2692 .bf16_trans_insts,
2421 .bitop3_insts,2693 .bitop3_insts,
2694 .clusters,
2695 .cube_insts,
2422 .cumode,2696 .cumode,
2697 .cvt_norm_insts,
2423 .cvt_pk_f16_f32_inst,2698 .cvt_pk_f16_f32_inst,
2699 .cvt_pknorm_vop2_insts,
2700 .cvt_pknorm_vop3_insts,
2701 .d16_write_vgpr32,
2424 .dl_insts,2702 .dl_insts,
2425 .dot7_insts,2703 .dot7_insts,
2426 .dot8_insts,2704 .dot8_insts,
2427 .dpp_src1_sgpr,2705 .dpp_src1_sgpr,
2706 .emulated_system_scope_atomics,
2428 .flat_atomic_fadd_f32_inst,2707 .flat_atomic_fadd_f32_inst,
2429 .flat_buffer_global_fadd_f64_inst,2708 .flat_buffer_global_fadd_f64_inst,
2709 .flat_gvs_mode,
2710 .fma_mix_bf16_insts,
2430 .fmacf64_inst,2711 .fmacf64_inst,
2431 .fp8_conversion_insts,2712 .fp8_conversion_insts,
2432 .fp8e5m3_insts,2713 .fp8e5m3_insts,
2433 .gfx12,2714 .gfx12,
2434 .gfx1250_insts,2715 .gfx1250_insts,
2716 .globally_addressable_scratch,
2435 .kernarg_preload,2717 .kernarg_preload,
2436 .lds_barrier_arrive_atomic,2718 .lds_barrier_arrive_atomic,
2437 .ldsbankcount32,2719 .ldsbankcount32,
2720 .lerp_inst,
2438 .lshl_add_u64_inst,2721 .lshl_add_u64_inst,
2722 .mad_u32_inst,
2439 .max_hard_clause_length_63,2723 .max_hard_clause_length_63,
2724 .mcast_load_insts,
2440 .memory_atomic_fadd_f32_denormal_support,2725 .memory_atomic_fadd_f32_denormal_support,
2726 .min3_max3_pkf16,
2441 .minimum3_maximum3_pkf16,2727 .minimum3_maximum3_pkf16,
2442 .packed_fp32_ops,2728 .packed_fp32_ops,
2443 .packed_tid,2729 .packed_tid,
2444 .permlane16_swap,2730 .permlane16_swap,
2731 .pk_add_min_max_insts,
2445 .prng_inst,2732 .prng_inst,
2446 .pseudo_scalar_trans,2733 .pseudo_scalar_trans,
2734 .qsad_insts,
2447 .restricted_soffset,2735 .restricted_soffset,
2736 .s_wakeup_barrier_inst,
2737 .sad_insts,
2448 .salu_float,2738 .salu_float,
2449 .scalar_dwordx3_loads,2739 .scalar_dwordx3_loads,
2450 .setprio_inc_wg_inst,2740 .setprio_inc_wg_inst,
2741 .setreg_vgpr_msb_fixup,
2451 .shader_cycles_hi_lo_registers,2742 .shader_cycles_hi_lo_registers,
2452 .sramecc_support,2743 .sramecc_support,
2744 .tanh_insts,
2745 .tensor_cvt_lut_insts,
2453 .transpose_load_f4f6_insts,2746 .transpose_load_f4f6_insts,
2454 .vcmpx_permlane_hazard,2747 .vcmpx_permlane_hazard,
2748 .vgpr_align2,
2749 .vmem_pref_insts,
2455 .wait_xcnt,2750 .wait_xcnt,
2456 .wavefrontsize32,2751 .wavefrontsize32,
2752 .xnack,
2753 .xnack_support,
2754 }),
2755 };
2756 pub const gfx1251: CpuModel = .{
2757 .name = "gfx1251",
2758 .llvm_name = "gfx1251",
2759 .features = featureSet(&[_]Feature{
2760 .@"1024_addressable_vgprs",
2761 .@"45_bit_num_records_buffer_resource",
2762 .@"64_bit_literals",
2763 .add_min_max_insts,
2764 .add_sub_u64_insts,
2765 .addressablelocalmemorysize327680,
2766 .architected_flat_scratch,
2767 .architected_sgprs,
2768 .ashr_pk_insts,
2769 .atomic_buffer_global_pk_add_f16_insts,
2770 .atomic_buffer_pk_add_bf16_inst,
2771 .atomic_ds_pk_add_16_insts,
2772 .atomic_fadd_no_rtn_insts,
2773 .atomic_fadd_rtn_insts,
2774 .atomic_flat_pk_add_16_insts,
2775 .atomic_fmin_fmax_flat_f64,
2776 .atomic_fmin_fmax_global_f64,
2777 .atomic_global_pk_add_bf16_inst,
2778 .bf16_cvt_insts,
2779 .bf16_pk_insts,
2780 .bf16_trans_insts,
2781 .bitop3_insts,
2782 .clusters,
2783 .cube_insts,
2784 .cumode,
2785 .cvt_norm_insts,
2786 .cvt_pk_f16_f32_inst,
2787 .cvt_pknorm_vop2_insts,
2788 .cvt_pknorm_vop3_insts,
2789 .d16_write_vgpr32,
2790 .dl_insts,
2791 .dot7_insts,
2792 .dot8_insts,
2793 .dpp_64bit,
2794 .dpp_src1_sgpr,
2795 .emulated_system_scope_atomics,
2796 .flat_atomic_fadd_f32_inst,
2797 .flat_buffer_global_fadd_f64_inst,
2798 .flat_gvs_mode,
2799 .fma_mix_bf16_insts,
2800 .fmacf64_inst,
2801 .fp8_conversion_insts,
2802 .fp8e5m3_insts,
2803 .gfx12,
2804 .gfx1250_insts,
2805 .globally_addressable_scratch,
2806 .kernarg_preload,
2807 .lds_barrier_arrive_atomic,
2808 .ldsbankcount32,
2809 .lerp_inst,
2810 .lshl_add_u64_inst,
2811 .mad_u32_inst,
2812 .max_hard_clause_length_63,
2813 .mcast_load_insts,
2814 .memory_atomic_fadd_f32_denormal_support,
2815 .min3_max3_pkf16,
2816 .minimum3_maximum3_pkf16,
2817 .packed_fp32_ops,
2818 .packed_tid,
2819 .permlane16_swap,
2820 .pk_add_min_max_insts,
2821 .prng_inst,
2822 .pseudo_scalar_trans,
2823 .qsad_insts,
2824 .restricted_soffset,
2825 .s_wakeup_barrier_inst,
2826 .sad_insts,
2827 .salu_float,
2828 .scalar_dwordx3_loads,
2829 .setprio_inc_wg_inst,
2830 .shader_cycles_hi_lo_registers,
2831 .sramecc_support,
2832 .tanh_insts,
2833 .tensor_cvt_lut_insts,
2834 .transpose_load_f4f6_insts,
2835 .vcmpx_permlane_hazard,
2836 .vgpr_align2,
2837 .vmem_pref_insts,
2838 .wait_xcnt,
2839 .wavefrontsize32,
2840 .xnack,
2841 .xnack_support,
2457 }),2842 }),
2458 };2843 };
2459 pub const gfx12_generic: CpuModel = .{2844 pub const gfx12_generic: CpuModel = .{
2460 .name = "gfx12_generic",2845 .name = "gfx12_generic",
2461 .llvm_name = "gfx12-generic",2846 .llvm_name = "gfx12-generic",
2462 .features = featureSet(&[_]Feature{2847 .features = featureSet(&[_]Feature{
2848 .addressablelocalmemorysize65536,
2463 .allocate1_5xvgprs,2849 .allocate1_5xvgprs,
2464 .architected_flat_scratch,2850 .architected_flat_scratch,
2465 .architected_sgprs,2851 .architected_sgprs,
...@@ -2470,7 +2856,13 @@ pub const cpu = struct {...@@ -2470,7 +2856,13 @@ pub const cpu = struct {
2470 .atomic_fadd_rtn_insts,2856 .atomic_fadd_rtn_insts,
2471 .atomic_flat_pk_add_16_insts,2857 .atomic_flat_pk_add_16_insts,
2472 .atomic_global_pk_add_bf16_inst,2858 .atomic_global_pk_add_bf16_inst,
2859 .back_off_barrier,
2473 .bvh_dual_bvh_8_insts,2860 .bvh_dual_bvh_8_insts,
2861 .cube_insts,
2862 .cvt_norm_insts,
2863 .cvt_pknorm_vop2_insts,
2864 .cvt_pknorm_vop3_insts,
2865 .d16_write_vgpr32,
2474 .dl_insts,2866 .dl_insts,
2475 .dot10_insts,2867 .dot10_insts,
2476 .dot11_insts,2868 .dot11_insts,
...@@ -2485,17 +2877,21 @@ pub const cpu = struct {...@@ -2485,17 +2877,21 @@ pub const cpu = struct {
2485 .gfx12,2877 .gfx12,
2486 .image_insts,2878 .image_insts,
2487 .ldsbankcount32,2879 .ldsbankcount32,
2880 .lerp_inst,
2488 .memory_atomic_fadd_f32_denormal_support,2881 .memory_atomic_fadd_f32_denormal_support,
2489 .nsa_encoding,2882 .nsa_encoding,
2490 .packed_tid,2883 .packed_tid,
2491 .partial_nsa_encoding,2884 .partial_nsa_encoding,
2492 .pseudo_scalar_trans,2885 .pseudo_scalar_trans,
2886 .qsad_insts,
2493 .requires_cov6,2887 .requires_cov6,
2494 .restricted_soffset,2888 .restricted_soffset,
2889 .sad_insts,
2495 .salu_float,2890 .salu_float,
2496 .scalar_dwordx3_loads,2891 .scalar_dwordx3_loads,
2497 .shader_cycles_hi_lo_registers,2892 .shader_cycles_hi_lo_registers,
2498 .vcmpx_permlane_hazard,2893 .vcmpx_permlane_hazard,
2894 .waits_before_system_scope_stores,
2499 }),2895 }),
2500 };2896 };
2501 pub const gfx600: CpuModel = .{2897 pub const gfx600: CpuModel = .{
...@@ -2779,6 +3175,7 @@ pub const cpu = struct {...@@ -2779,6 +3175,7 @@ pub const cpu = struct {
2779 .packed_tid,3175 .packed_tid,
2780 .pk_fmac_f16_inst,3176 .pk_fmac_f16_inst,
2781 .sramecc_support,3177 .sramecc_support,
3178 .vgpr_align2,
2782 }),3179 }),
2783 };3180 };
2784 pub const gfx90c: CpuModel = .{3181 pub const gfx90c: CpuModel = .{
...@@ -2842,6 +3239,7 @@ pub const cpu = struct {...@@ -2842,6 +3239,7 @@ pub const cpu = struct {
2842 .packed_tid,3239 .packed_tid,
2843 .pk_fmac_f16_inst,3240 .pk_fmac_f16_inst,
2844 .sramecc_support,3241 .sramecc_support,
3242 .vgpr_align2,
2845 .xf32_insts,3243 .xf32_insts,
2846 }),3244 }),
2847 };3245 };
...@@ -2897,6 +3295,7 @@ pub const cpu = struct {...@@ -2897,6 +3295,7 @@ pub const cpu = struct {
2897 .pk_fmac_f16_inst,3295 .pk_fmac_f16_inst,
2898 .prng_inst,3296 .prng_inst,
2899 .sramecc_support,3297 .sramecc_support,
3298 .vgpr_align2,
2900 }),3299 }),
2901 };3300 };
2902 pub const gfx9_4_generic: CpuModel = .{3301 pub const gfx9_4_generic: CpuModel = .{
...@@ -2943,6 +3342,7 @@ pub const cpu = struct {...@@ -2943,6 +3342,7 @@ pub const cpu = struct {
2943 .pk_fmac_f16_inst,3342 .pk_fmac_f16_inst,
2944 .requires_cov6,3343 .requires_cov6,
2945 .sramecc_support,3344 .sramecc_support,
3345 .vgpr_align2,
2946 }),3346 }),
2947 };3347 };
2948 pub const gfx9_generic: CpuModel = .{3348 pub const gfx9_generic: CpuModel = .{
lib/std/Target/arm.zig+40-6
...@@ -88,6 +88,7 @@ pub const Feature = enum {...@@ -88,6 +88,7 @@ pub const Feature = enum {
88 has_v9_4a,88 has_v9_4a,
89 has_v9_5a,89 has_v9_5a,
90 has_v9_6a,90 has_v9_6a,
91 has_v9_7a,
91 has_v9a,92 has_v9a,
92 hwdiv,93 hwdiv,
93 hwdiv_arm,94 hwdiv_arm,
...@@ -107,7 +108,6 @@ pub const Feature = enum {...@@ -107,7 +108,6 @@ pub const Feature = enum {
107 mve2beat,108 mve2beat,
108 mve4beat,109 mve4beat,
109 mve_fp,110 mve_fp,
110 nacl_trap,
111 neon,111 neon,
112 neon_fpmovs,112 neon_fpmovs,
113 neonfp,113 neonfp,
...@@ -187,6 +187,7 @@ pub const Feature = enum {...@@ -187,6 +187,7 @@ pub const Feature = enum {
187 v9_4a,187 v9_4a,
188 v9_5a,188 v9_5a,
189 v9_6a,189 v9_6a,
190 v9_7a,
190 v9a,191 v9a,
191 vfp2,192 vfp2,
192 vfp2sp,193 vfp2sp,
...@@ -748,6 +749,13 @@ pub const all_features = blk: {...@@ -748,6 +749,13 @@ pub const all_features = blk: {
748 .has_v9_5a,749 .has_v9_5a,
749 }),750 }),
750 };751 };
752 result[@intFromEnum(Feature.has_v9_7a)] = .{
753 .llvm_name = "v9.7a",
754 .description = "Support ARM v9.7a instructions",
755 .dependencies = featureSet(&[_]Feature{
756 .has_v9_6a,
757 }),
758 };
751 result[@intFromEnum(Feature.has_v9a)] = .{759 result[@intFromEnum(Feature.has_v9a)] = .{
752 .llvm_name = "v9a",760 .llvm_name = "v9a",
753 .description = "Support ARM v9a instructions",761 .description = "Support ARM v9a instructions",
...@@ -859,11 +867,6 @@ pub const all_features = blk: {...@@ -859,11 +867,6 @@ pub const all_features = blk: {
859 .mve,867 .mve,
860 }),868 }),
861 };869 };
862 result[@intFromEnum(Feature.nacl_trap)] = .{
863 .llvm_name = "nacl-trap",
864 .description = "NaCl trap",
865 .dependencies = featureSet(&[_]Feature{}),
866 };
867 result[@intFromEnum(Feature.neon)] = .{870 result[@intFromEnum(Feature.neon)] = .{
868 .llvm_name = "neon",871 .llvm_name = "neon",
869 .description = "Enable NEON instructions",872 .description = "Enable NEON instructions",
...@@ -1579,6 +1582,22 @@ pub const all_features = blk: {...@@ -1579,6 +1582,22 @@ pub const all_features = blk: {
1579 .virtualization,1582 .virtualization,
1580 }),1583 }),
1581 };1584 };
1585 result[@intFromEnum(Feature.v9_7a)] = .{
1586 .llvm_name = "armv9.7-a",
1587 .description = "ARMv97a architecture",
1588 .dependencies = featureSet(&[_]Feature{
1589 .aclass,
1590 .crc,
1591 .db,
1592 .dsp,
1593 .fp_armv8,
1594 .has_v9_7a,
1595 .mp,
1596 .ras,
1597 .trustzone,
1598 .virtualization,
1599 }),
1600 };
1582 result[@intFromEnum(Feature.v9a)] = .{1601 result[@intFromEnum(Feature.v9a)] = .{
1583 .llvm_name = "armv9-a",1602 .llvm_name = "armv9-a",
1584 .description = "ARMv9a architecture",1603 .description = "ARMv9a architecture",
...@@ -2658,6 +2677,21 @@ pub const cpu = struct {...@@ -2658,6 +2677,21 @@ pub const cpu = struct {
2658 .v8m_main,2677 .v8m_main,
2659 }),2678 }),
2660 };2679 };
2680 pub const star_mc3: CpuModel = .{
2681 .name = "star_mc3",
2682 .llvm_name = "star-mc3",
2683 .features = featureSet(&[_]Feature{
2684 .fp_armv8d16,
2685 .loop_align,
2686 .mve1beat,
2687 .mve_fp,
2688 .no_branch_predictor,
2689 .pacbti,
2690 .slowfpvmlx,
2691 .use_misched,
2692 .v8_1m_main,
2693 }),
2694 };
2661 pub const strongarm: CpuModel = .{2695 pub const strongarm: CpuModel = .{
2662 .name = "strongarm",2696 .name = "strongarm",
2663 .llvm_name = "strongarm",2697 .llvm_name = "strongarm",
lib/std/Target/bpf.zig+6
...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {7pub const Feature = enum {
8 allows_misaligned_mem_access,
8 alu32,9 alu32,
9 dummy,10 dummy,
10 dwarfris,11 dwarfris,
...@@ -19,6 +20,11 @@ pub const all_features = blk: {...@@ -19,6 +20,11 @@ pub const all_features = blk: {
19 const len = @typeInfo(Feature).@"enum".fields.len;20 const len = @typeInfo(Feature).@"enum".fields.len;
20 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);21 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
21 var result: [len]CpuFeature = undefined;22 var result: [len]CpuFeature = undefined;
23 result[@intFromEnum(Feature.allows_misaligned_mem_access)] = .{
24 .llvm_name = "allows-misaligned-mem-access",
25 .description = "Allows misaligned memory access",
26 .dependencies = featureSet(&[_]Feature{}),
27 };
22 result[@intFromEnum(Feature.alu32)] = .{28 result[@intFromEnum(Feature.alu32)] = .{
23 .llvm_name = "alu32",29 .llvm_name = "alu32",
24 .description = "Enable ALU32 instructions",30 .description = "Enable ALU32 instructions",
lib/std/Target/hexagon.zig+41-6
...@@ -25,6 +25,7 @@ pub const Feature = enum {...@@ -25,6 +25,7 @@ pub const Feature = enum {
25 hvxv73,25 hvxv73,
26 hvxv75,26 hvxv75,
27 hvxv79,27 hvxv79,
28 hvxv81,
28 long_calls,29 long_calls,
29 mem_noshuf,30 mem_noshuf,
30 memops,31 memops,
...@@ -36,7 +37,6 @@ pub const Feature = enum {...@@ -36,7 +37,6 @@ pub const Feature = enum {
36 reserved_r19,37 reserved_r19,
37 small_data,38 small_data,
38 tinycore,39 tinycore,
39 unsafe_fp,
40 v5,40 v5,
41 v55,41 v55,
42 v60,42 v60,
...@@ -50,6 +50,7 @@ pub const Feature = enum {...@@ -50,6 +50,7 @@ pub const Feature = enum {
50 v73,50 v73,
51 v75,51 v75,
52 v79,52 v79,
53 v81,
53 zreg,54 zreg,
54};55};
5556
...@@ -189,6 +190,13 @@ pub const all_features = blk: {...@@ -189,6 +190,13 @@ pub const all_features = blk: {
189 .hvxv75,190 .hvxv75,
190 }),191 }),
191 };192 };
193 result[@intFromEnum(Feature.hvxv81)] = .{
194 .llvm_name = "hvxv81",
195 .description = "Hexagon HVX instructions",
196 .dependencies = featureSet(&[_]Feature{
197 .hvxv79,
198 }),
199 };
192 result[@intFromEnum(Feature.long_calls)] = .{200 result[@intFromEnum(Feature.long_calls)] = .{
193 .llvm_name = "long-calls",201 .llvm_name = "long-calls",
194 .description = "Use constant-extended calls",202 .description = "Use constant-extended calls",
...@@ -248,11 +256,6 @@ pub const all_features = blk: {...@@ -248,11 +256,6 @@ pub const all_features = blk: {
248 .description = "Hexagon Tiny Core",256 .description = "Hexagon Tiny Core",
249 .dependencies = featureSet(&[_]Feature{}),257 .dependencies = featureSet(&[_]Feature{}),
250 };258 };
251 result[@intFromEnum(Feature.unsafe_fp)] = .{
252 .llvm_name = "unsafe-fp",
253 .description = "Use unsafe FP math",
254 .dependencies = featureSet(&[_]Feature{}),
255 };
256 result[@intFromEnum(Feature.v5)] = .{259 result[@intFromEnum(Feature.v5)] = .{
257 .llvm_name = "v5",260 .llvm_name = "v5",
258 .description = "Enable Hexagon V5 architecture",261 .description = "Enable Hexagon V5 architecture",
...@@ -318,6 +321,11 @@ pub const all_features = blk: {...@@ -318,6 +321,11 @@ pub const all_features = blk: {
318 .description = "Enable Hexagon V79 architecture",321 .description = "Enable Hexagon V79 architecture",
319 .dependencies = featureSet(&[_]Feature{}),322 .dependencies = featureSet(&[_]Feature{}),
320 };323 };
324 result[@intFromEnum(Feature.v81)] = .{
325 .llvm_name = "v81",
326 .description = "Enable Hexagon V81 architecture",
327 .dependencies = featureSet(&[_]Feature{}),
328 };
321 result[@intFromEnum(Feature.zreg)] = .{329 result[@intFromEnum(Feature.zreg)] = .{
322 .llvm_name = "zreg",330 .llvm_name = "zreg",
323 .description = "Hexagon ZReg extension instructions",331 .description = "Hexagon ZReg extension instructions",
...@@ -662,4 +670,31 @@ pub const cpu = struct {...@@ -662,4 +670,31 @@ pub const cpu = struct {
662 .v79,670 .v79,
663 }),671 }),
664 };672 };
673 pub const hexagonv81: CpuModel = .{
674 .name = "hexagonv81",
675 .llvm_name = "hexagonv81",
676 .features = featureSet(&[_]Feature{
677 .compound,
678 .duplex,
679 .mem_noshuf,
680 .memops,
681 .nvj,
682 .nvs,
683 .small_data,
684 .v5,
685 .v55,
686 .v60,
687 .v62,
688 .v65,
689 .v66,
690 .v67,
691 .v68,
692 .v69,
693 .v71,
694 .v73,
695 .v75,
696 .v79,
697 .v81,
698 }),
699 };
665};700};
lib/std/Target/loongarch.zig+18
...@@ -175,6 +175,24 @@ pub const cpu = struct {...@@ -175,6 +175,24 @@ pub const cpu = struct {
175 .ual,175 .ual,
176 }),176 }),
177 };177 };
178 pub const la32rv1_0: CpuModel = .{
179 .name = "la32rv1_0",
180 .llvm_name = null,
181 .features = featureSet(&[_]Feature{
182 .@"32bit",
183 .ual,
184 }),
185 };
186 pub const la32v1_0: CpuModel = .{
187 .name = "la32v1_0",
188 .llvm_name = null,
189 .features = featureSet(&[_]Feature{
190 .@"32bit",
191 .@"32s",
192 .d,
193 .ual,
194 }),
195 };
178 pub const la464: CpuModel = .{196 pub const la464: CpuModel = .{
179 .name = "la464",197 .name = "la464",
180 .llvm_name = "la464",198 .llvm_name = "la464",
lib/std/Target/mips.zig+6
...@@ -56,6 +56,7 @@ pub const Feature = enum {...@@ -56,6 +56,7 @@ pub const Feature = enum {
56 soft_float,56 soft_float,
57 strict_align,57 strict_align,
58 sym32,58 sym32,
59 use_compact_branches,
59 use_indirect_jump_hazard,60 use_indirect_jump_hazard,
60 use_tcc_in_div,61 use_tcc_in_div,
61 vfpu,62 vfpu,
...@@ -391,6 +392,11 @@ pub const all_features = blk: {...@@ -391,6 +392,11 @@ pub const all_features = blk: {
391 .description = "Symbols are 32 bit on Mips64",392 .description = "Symbols are 32 bit on Mips64",
392 .dependencies = featureSet(&[_]Feature{}),393 .dependencies = featureSet(&[_]Feature{}),
393 };394 };
395 result[@intFromEnum(Feature.use_compact_branches)] = .{
396 .llvm_name = "use-compact-branches",
397 .description = "Use compact branch instructions for MIPS32R6/MIPS64R6",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
394 result[@intFromEnum(Feature.use_indirect_jump_hazard)] = .{400 result[@intFromEnum(Feature.use_indirect_jump_hazard)] = .{
395 .llvm_name = "use-indirect-jump-hazard",401 .llvm_name = "use-indirect-jump-hazard",
396 .description = "Use indirect jump guards to prevent certain speculation based attacks",402 .description = "Use indirect jump guards to prevent certain speculation based attacks",
lib/std/Target/nvptx.zig+58-35
...@@ -35,6 +35,7 @@ pub const Feature = enum {...@@ -35,6 +35,7 @@ pub const Feature = enum {
35 ptx86,35 ptx86,
36 ptx87,36 ptx87,
37 ptx88,37 ptx88,
38 ptx90,
38 sm_100,39 sm_100,
39 sm_100a,40 sm_100a,
40 sm_100f,41 sm_100f,
...@@ -44,6 +45,9 @@ pub const Feature = enum {...@@ -44,6 +45,9 @@ pub const Feature = enum {
44 sm_103,45 sm_103,
45 sm_103a,46 sm_103a,
46 sm_103f,47 sm_103f,
48 sm_110,
49 sm_110a,
50 sm_110f,
47 sm_120,51 sm_120,
48 sm_120a,52 sm_120a,
49 sm_120f,53 sm_120f,
...@@ -68,6 +72,7 @@ pub const Feature = enum {...@@ -68,6 +72,7 @@ pub const Feature = enum {
68 sm_80,72 sm_80,
69 sm_86,73 sm_86,
70 sm_87,74 sm_87,
75 sm_88,
71 sm_89,76 sm_89,
72 sm_90,77 sm_90,
73 sm_90a,78 sm_90a,
...@@ -232,6 +237,11 @@ pub const all_features = blk: {...@@ -232,6 +237,11 @@ pub const all_features = blk: {
232 .description = "Use PTX version 88",237 .description = "Use PTX version 88",
233 .dependencies = featureSet(&[_]Feature{}),238 .dependencies = featureSet(&[_]Feature{}),
234 };239 };
240 result[@intFromEnum(Feature.ptx90)] = .{
241 .llvm_name = "ptx90",
242 .description = "Use PTX version 90",
243 .dependencies = featureSet(&[_]Feature{}),
244 };
235 result[@intFromEnum(Feature.sm_100)] = .{245 result[@intFromEnum(Feature.sm_100)] = .{
236 .llvm_name = "sm_100",246 .llvm_name = "sm_100",
237 .description = "Target SM 100",247 .description = "Target SM 100",
...@@ -277,6 +287,21 @@ pub const all_features = blk: {...@@ -277,6 +287,21 @@ pub const all_features = blk: {
277 .description = "Target SM 103f",287 .description = "Target SM 103f",
278 .dependencies = featureSet(&[_]Feature{}),288 .dependencies = featureSet(&[_]Feature{}),
279 };289 };
290 result[@intFromEnum(Feature.sm_110)] = .{
291 .llvm_name = "sm_110",
292 .description = "Target SM 110",
293 .dependencies = featureSet(&[_]Feature{}),
294 };
295 result[@intFromEnum(Feature.sm_110a)] = .{
296 .llvm_name = "sm_110a",
297 .description = "Target SM 110a",
298 .dependencies = featureSet(&[_]Feature{}),
299 };
300 result[@intFromEnum(Feature.sm_110f)] = .{
301 .llvm_name = "sm_110f",
302 .description = "Target SM 110f",
303 .dependencies = featureSet(&[_]Feature{}),
304 };
280 result[@intFromEnum(Feature.sm_120)] = .{305 result[@intFromEnum(Feature.sm_120)] = .{
281 .llvm_name = "sm_120",306 .llvm_name = "sm_120",
282 .description = "Target SM 120",307 .description = "Target SM 120",
...@@ -397,6 +422,11 @@ pub const all_features = blk: {...@@ -397,6 +422,11 @@ pub const all_features = blk: {
397 .description = "Target SM 87",422 .description = "Target SM 87",
398 .dependencies = featureSet(&[_]Feature{}),423 .dependencies = featureSet(&[_]Feature{}),
399 };424 };
425 result[@intFromEnum(Feature.sm_88)] = .{
426 .llvm_name = "sm_88",
427 .description = "Target SM 88",
428 .dependencies = featureSet(&[_]Feature{}),
429 };
400 result[@intFromEnum(Feature.sm_89)] = .{430 result[@intFromEnum(Feature.sm_89)] = .{
401 .llvm_name = "sm_89",431 .llvm_name = "sm_89",
402 .description = "Target SM 89",432 .description = "Target SM 89",
...@@ -425,7 +455,6 @@ pub const cpu = struct {...@@ -425,7 +455,6 @@ pub const cpu = struct {
425 .name = "sm_100",455 .name = "sm_100",
426 .llvm_name = "sm_100",456 .llvm_name = "sm_100",
427 .features = featureSet(&[_]Feature{457 .features = featureSet(&[_]Feature{
428 .ptx86,
429 .sm_100,458 .sm_100,
430 }),459 }),
431 };460 };
...@@ -433,7 +462,6 @@ pub const cpu = struct {...@@ -433,7 +462,6 @@ pub const cpu = struct {
433 .name = "sm_100a",462 .name = "sm_100a",
434 .llvm_name = "sm_100a",463 .llvm_name = "sm_100a",
435 .features = featureSet(&[_]Feature{464 .features = featureSet(&[_]Feature{
436 .ptx86,
437 .sm_100a,465 .sm_100a,
438 }),466 }),
439 };467 };
...@@ -441,7 +469,6 @@ pub const cpu = struct {...@@ -441,7 +469,6 @@ pub const cpu = struct {
441 .name = "sm_100f",469 .name = "sm_100f",
442 .llvm_name = "sm_100f",470 .llvm_name = "sm_100f",
443 .features = featureSet(&[_]Feature{471 .features = featureSet(&[_]Feature{
444 .ptx88,
445 .sm_100f,472 .sm_100f,
446 }),473 }),
447 };474 };
...@@ -449,7 +476,6 @@ pub const cpu = struct {...@@ -449,7 +476,6 @@ pub const cpu = struct {
449 .name = "sm_101",476 .name = "sm_101",
450 .llvm_name = "sm_101",477 .llvm_name = "sm_101",
451 .features = featureSet(&[_]Feature{478 .features = featureSet(&[_]Feature{
452 .ptx86,
453 .sm_101,479 .sm_101,
454 }),480 }),
455 };481 };
...@@ -457,7 +483,6 @@ pub const cpu = struct {...@@ -457,7 +483,6 @@ pub const cpu = struct {
457 .name = "sm_101a",483 .name = "sm_101a",
458 .llvm_name = "sm_101a",484 .llvm_name = "sm_101a",
459 .features = featureSet(&[_]Feature{485 .features = featureSet(&[_]Feature{
460 .ptx86,
461 .sm_101a,486 .sm_101a,
462 }),487 }),
463 };488 };
...@@ -465,7 +490,6 @@ pub const cpu = struct {...@@ -465,7 +490,6 @@ pub const cpu = struct {
465 .name = "sm_101f",490 .name = "sm_101f",
466 .llvm_name = "sm_101f",491 .llvm_name = "sm_101f",
467 .features = featureSet(&[_]Feature{492 .features = featureSet(&[_]Feature{
468 .ptx88,
469 .sm_101f,493 .sm_101f,
470 }),494 }),
471 };495 };
...@@ -473,7 +497,6 @@ pub const cpu = struct {...@@ -473,7 +497,6 @@ pub const cpu = struct {
473 .name = "sm_103",497 .name = "sm_103",
474 .llvm_name = "sm_103",498 .llvm_name = "sm_103",
475 .features = featureSet(&[_]Feature{499 .features = featureSet(&[_]Feature{
476 .ptx88,
477 .sm_103,500 .sm_103,
478 }),501 }),
479 };502 };
...@@ -481,7 +504,6 @@ pub const cpu = struct {...@@ -481,7 +504,6 @@ pub const cpu = struct {
481 .name = "sm_103a",504 .name = "sm_103a",
482 .llvm_name = "sm_103a",505 .llvm_name = "sm_103a",
483 .features = featureSet(&[_]Feature{506 .features = featureSet(&[_]Feature{
484 .ptx88,
485 .sm_103a,507 .sm_103a,
486 }),508 }),
487 };509 };
...@@ -489,15 +511,34 @@ pub const cpu = struct {...@@ -489,15 +511,34 @@ pub const cpu = struct {
489 .name = "sm_103f",511 .name = "sm_103f",
490 .llvm_name = "sm_103f",512 .llvm_name = "sm_103f",
491 .features = featureSet(&[_]Feature{513 .features = featureSet(&[_]Feature{
492 .ptx88,
493 .sm_103f,514 .sm_103f,
494 }),515 }),
495 };516 };
517 pub const sm_110: CpuModel = .{
518 .name = "sm_110",
519 .llvm_name = "sm_110",
520 .features = featureSet(&[_]Feature{
521 .sm_110,
522 }),
523 };
524 pub const sm_110a: CpuModel = .{
525 .name = "sm_110a",
526 .llvm_name = "sm_110a",
527 .features = featureSet(&[_]Feature{
528 .sm_110a,
529 }),
530 };
531 pub const sm_110f: CpuModel = .{
532 .name = "sm_110f",
533 .llvm_name = "sm_110f",
534 .features = featureSet(&[_]Feature{
535 .sm_110f,
536 }),
537 };
496 pub const sm_120: CpuModel = .{538 pub const sm_120: CpuModel = .{
497 .name = "sm_120",539 .name = "sm_120",
498 .llvm_name = "sm_120",540 .llvm_name = "sm_120",
499 .features = featureSet(&[_]Feature{541 .features = featureSet(&[_]Feature{
500 .ptx87,
501 .sm_120,542 .sm_120,
502 }),543 }),
503 };544 };
...@@ -505,7 +546,6 @@ pub const cpu = struct {...@@ -505,7 +546,6 @@ pub const cpu = struct {
505 .name = "sm_120a",546 .name = "sm_120a",
506 .llvm_name = "sm_120a",547 .llvm_name = "sm_120a",
507 .features = featureSet(&[_]Feature{548 .features = featureSet(&[_]Feature{
508 .ptx87,
509 .sm_120a,549 .sm_120a,
510 }),550 }),
511 };551 };
...@@ -513,7 +553,6 @@ pub const cpu = struct {...@@ -513,7 +553,6 @@ pub const cpu = struct {
513 .name = "sm_120f",553 .name = "sm_120f",
514 .llvm_name = "sm_120f",554 .llvm_name = "sm_120f",
515 .features = featureSet(&[_]Feature{555 .features = featureSet(&[_]Feature{
516 .ptx88,
517 .sm_120f,556 .sm_120f,
518 }),557 }),
519 };558 };
...@@ -521,7 +560,6 @@ pub const cpu = struct {...@@ -521,7 +560,6 @@ pub const cpu = struct {
521 .name = "sm_121",560 .name = "sm_121",
522 .llvm_name = "sm_121",561 .llvm_name = "sm_121",
523 .features = featureSet(&[_]Feature{562 .features = featureSet(&[_]Feature{
524 .ptx88,
525 .sm_121,563 .sm_121,
526 }),564 }),
527 };565 };
...@@ -529,7 +567,6 @@ pub const cpu = struct {...@@ -529,7 +567,6 @@ pub const cpu = struct {
529 .name = "sm_121a",567 .name = "sm_121a",
530 .llvm_name = "sm_121a",568 .llvm_name = "sm_121a",
531 .features = featureSet(&[_]Feature{569 .features = featureSet(&[_]Feature{
532 .ptx88,
533 .sm_121a,570 .sm_121a,
534 }),571 }),
535 };572 };
...@@ -537,7 +574,6 @@ pub const cpu = struct {...@@ -537,7 +574,6 @@ pub const cpu = struct {
537 .name = "sm_121f",574 .name = "sm_121f",
538 .llvm_name = "sm_121f",575 .llvm_name = "sm_121f",
539 .features = featureSet(&[_]Feature{576 .features = featureSet(&[_]Feature{
540 .ptx88,
541 .sm_121f,577 .sm_121f,
542 }),578 }),
543 };579 };
...@@ -545,7 +581,6 @@ pub const cpu = struct {...@@ -545,7 +581,6 @@ pub const cpu = struct {
545 .name = "sm_20",581 .name = "sm_20",
546 .llvm_name = "sm_20",582 .llvm_name = "sm_20",
547 .features = featureSet(&[_]Feature{583 .features = featureSet(&[_]Feature{
548 .ptx32,
549 .sm_20,584 .sm_20,
550 }),585 }),
551 };586 };
...@@ -553,7 +588,6 @@ pub const cpu = struct {...@@ -553,7 +588,6 @@ pub const cpu = struct {
553 .name = "sm_21",588 .name = "sm_21",
554 .llvm_name = "sm_21",589 .llvm_name = "sm_21",
555 .features = featureSet(&[_]Feature{590 .features = featureSet(&[_]Feature{
556 .ptx32,
557 .sm_21,591 .sm_21,
558 }),592 }),
559 };593 };
...@@ -568,7 +602,6 @@ pub const cpu = struct {...@@ -568,7 +602,6 @@ pub const cpu = struct {
568 .name = "sm_32",602 .name = "sm_32",
569 .llvm_name = "sm_32",603 .llvm_name = "sm_32",
570 .features = featureSet(&[_]Feature{604 .features = featureSet(&[_]Feature{
571 .ptx40,
572 .sm_32,605 .sm_32,
573 }),606 }),
574 };607 };
...@@ -576,7 +609,6 @@ pub const cpu = struct {...@@ -576,7 +609,6 @@ pub const cpu = struct {
576 .name = "sm_35",609 .name = "sm_35",
577 .llvm_name = "sm_35",610 .llvm_name = "sm_35",
578 .features = featureSet(&[_]Feature{611 .features = featureSet(&[_]Feature{
579 .ptx32,
580 .sm_35,612 .sm_35,
581 }),613 }),
582 };614 };
...@@ -584,7 +616,6 @@ pub const cpu = struct {...@@ -584,7 +616,6 @@ pub const cpu = struct {
584 .name = "sm_37",616 .name = "sm_37",
585 .llvm_name = "sm_37",617 .llvm_name = "sm_37",
586 .features = featureSet(&[_]Feature{618 .features = featureSet(&[_]Feature{
587 .ptx41,
588 .sm_37,619 .sm_37,
589 }),620 }),
590 };621 };
...@@ -592,7 +623,6 @@ pub const cpu = struct {...@@ -592,7 +623,6 @@ pub const cpu = struct {
592 .name = "sm_50",623 .name = "sm_50",
593 .llvm_name = "sm_50",624 .llvm_name = "sm_50",
594 .features = featureSet(&[_]Feature{625 .features = featureSet(&[_]Feature{
595 .ptx40,
596 .sm_50,626 .sm_50,
597 }),627 }),
598 };628 };
...@@ -600,7 +630,6 @@ pub const cpu = struct {...@@ -600,7 +630,6 @@ pub const cpu = struct {
600 .name = "sm_52",630 .name = "sm_52",
601 .llvm_name = "sm_52",631 .llvm_name = "sm_52",
602 .features = featureSet(&[_]Feature{632 .features = featureSet(&[_]Feature{
603 .ptx41,
604 .sm_52,633 .sm_52,
605 }),634 }),
606 };635 };
...@@ -608,7 +637,6 @@ pub const cpu = struct {...@@ -608,7 +637,6 @@ pub const cpu = struct {
608 .name = "sm_53",637 .name = "sm_53",
609 .llvm_name = "sm_53",638 .llvm_name = "sm_53",
610 .features = featureSet(&[_]Feature{639 .features = featureSet(&[_]Feature{
611 .ptx42,
612 .sm_53,640 .sm_53,
613 }),641 }),
614 };642 };
...@@ -616,7 +644,6 @@ pub const cpu = struct {...@@ -616,7 +644,6 @@ pub const cpu = struct {
616 .name = "sm_60",644 .name = "sm_60",
617 .llvm_name = "sm_60",645 .llvm_name = "sm_60",
618 .features = featureSet(&[_]Feature{646 .features = featureSet(&[_]Feature{
619 .ptx50,
620 .sm_60,647 .sm_60,
621 }),648 }),
622 };649 };
...@@ -624,7 +651,6 @@ pub const cpu = struct {...@@ -624,7 +651,6 @@ pub const cpu = struct {
624 .name = "sm_61",651 .name = "sm_61",
625 .llvm_name = "sm_61",652 .llvm_name = "sm_61",
626 .features = featureSet(&[_]Feature{653 .features = featureSet(&[_]Feature{
627 .ptx50,
628 .sm_61,654 .sm_61,
629 }),655 }),
630 };656 };
...@@ -632,7 +658,6 @@ pub const cpu = struct {...@@ -632,7 +658,6 @@ pub const cpu = struct {
632 .name = "sm_62",658 .name = "sm_62",
633 .llvm_name = "sm_62",659 .llvm_name = "sm_62",
634 .features = featureSet(&[_]Feature{660 .features = featureSet(&[_]Feature{
635 .ptx50,
636 .sm_62,661 .sm_62,
637 }),662 }),
638 };663 };
...@@ -640,7 +665,6 @@ pub const cpu = struct {...@@ -640,7 +665,6 @@ pub const cpu = struct {
640 .name = "sm_70",665 .name = "sm_70",
641 .llvm_name = "sm_70",666 .llvm_name = "sm_70",
642 .features = featureSet(&[_]Feature{667 .features = featureSet(&[_]Feature{
643 .ptx60,
644 .sm_70,668 .sm_70,
645 }),669 }),
646 };670 };
...@@ -648,7 +672,6 @@ pub const cpu = struct {...@@ -648,7 +672,6 @@ pub const cpu = struct {
648 .name = "sm_72",672 .name = "sm_72",
649 .llvm_name = "sm_72",673 .llvm_name = "sm_72",
650 .features = featureSet(&[_]Feature{674 .features = featureSet(&[_]Feature{
651 .ptx61,
652 .sm_72,675 .sm_72,
653 }),676 }),
654 };677 };
...@@ -656,7 +679,6 @@ pub const cpu = struct {...@@ -656,7 +679,6 @@ pub const cpu = struct {
656 .name = "sm_75",679 .name = "sm_75",
657 .llvm_name = "sm_75",680 .llvm_name = "sm_75",
658 .features = featureSet(&[_]Feature{681 .features = featureSet(&[_]Feature{
659 .ptx63,
660 .sm_75,682 .sm_75,
661 }),683 }),
662 };684 };
...@@ -664,7 +686,6 @@ pub const cpu = struct {...@@ -664,7 +686,6 @@ pub const cpu = struct {
664 .name = "sm_80",686 .name = "sm_80",
665 .llvm_name = "sm_80",687 .llvm_name = "sm_80",
666 .features = featureSet(&[_]Feature{688 .features = featureSet(&[_]Feature{
667 .ptx70,
668 .sm_80,689 .sm_80,
669 }),690 }),
670 };691 };
...@@ -672,7 +693,6 @@ pub const cpu = struct {...@@ -672,7 +693,6 @@ pub const cpu = struct {
672 .name = "sm_86",693 .name = "sm_86",
673 .llvm_name = "sm_86",694 .llvm_name = "sm_86",
674 .features = featureSet(&[_]Feature{695 .features = featureSet(&[_]Feature{
675 .ptx71,
676 .sm_86,696 .sm_86,
677 }),697 }),
678 };698 };
...@@ -680,15 +700,20 @@ pub const cpu = struct {...@@ -680,15 +700,20 @@ pub const cpu = struct {
680 .name = "sm_87",700 .name = "sm_87",
681 .llvm_name = "sm_87",701 .llvm_name = "sm_87",
682 .features = featureSet(&[_]Feature{702 .features = featureSet(&[_]Feature{
683 .ptx74,
684 .sm_87,703 .sm_87,
685 }),704 }),
686 };705 };
706 pub const sm_88: CpuModel = .{
707 .name = "sm_88",
708 .llvm_name = "sm_88",
709 .features = featureSet(&[_]Feature{
710 .sm_88,
711 }),
712 };
687 pub const sm_89: CpuModel = .{713 pub const sm_89: CpuModel = .{
688 .name = "sm_89",714 .name = "sm_89",
689 .llvm_name = "sm_89",715 .llvm_name = "sm_89",
690 .features = featureSet(&[_]Feature{716 .features = featureSet(&[_]Feature{
691 .ptx78,
692 .sm_89,717 .sm_89,
693 }),718 }),
694 };719 };
...@@ -696,7 +721,6 @@ pub const cpu = struct {...@@ -696,7 +721,6 @@ pub const cpu = struct {
696 .name = "sm_90",721 .name = "sm_90",
697 .llvm_name = "sm_90",722 .llvm_name = "sm_90",
698 .features = featureSet(&[_]Feature{723 .features = featureSet(&[_]Feature{
699 .ptx78,
700 .sm_90,724 .sm_90,
701 }),725 }),
702 };726 };
...@@ -704,7 +728,6 @@ pub const cpu = struct {...@@ -704,7 +728,6 @@ pub const cpu = struct {
704 .name = "sm_90a",728 .name = "sm_90a",
705 .llvm_name = "sm_90a",729 .llvm_name = "sm_90a",
706 .features = featureSet(&[_]Feature{730 .features = featureSet(&[_]Feature{
707 .ptx80,
708 .sm_90a,731 .sm_90a,
709 }),732 }),
710 };733 };
lib/std/Target/powerpc.zig+27-19
...@@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;...@@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {7pub const Feature = enum {
8 @"64bit",8 @"64bit",
9 @"64bit_support",
9 @"64bitregs",10 @"64bitregs",
10 allow_unaligned_fp_access,11 allow_unaligned_fp_access,
11 altivec,12 altivec,
...@@ -97,7 +98,14 @@ pub const all_features = blk: {...@@ -97,7 +98,14 @@ pub const all_features = blk: {
97 var result: [len]CpuFeature = undefined;98 var result: [len]CpuFeature = undefined;
98 result[@intFromEnum(Feature.@"64bit")] = .{99 result[@intFromEnum(Feature.@"64bit")] = .{
99 .llvm_name = "64bit",100 .llvm_name = "64bit",
100 .description = "Enable 64-bit instructions",101 .description = "Enable 64-bit mode",
102 .dependencies = featureSet(&[_]Feature{
103 .@"64bit_support",
104 }),
105 };
106 result[@intFromEnum(Feature.@"64bit_support")] = .{
107 .llvm_name = "64bit-support",
108 .description = "Supports 64-bit instructions",
101 .dependencies = featureSet(&[_]Feature{}),109 .dependencies = featureSet(&[_]Feature{}),
102 };110 };
103 result[@intFromEnum(Feature.@"64bitregs")] = .{111 result[@intFromEnum(Feature.@"64bitregs")] = .{
...@@ -705,7 +713,7 @@ pub const cpu = struct {...@@ -705,7 +713,7 @@ pub const cpu = struct {
705 .name = "970",713 .name = "970",
706 .llvm_name = "970",714 .llvm_name = "970",
707 .features = featureSet(&[_]Feature{715 .features = featureSet(&[_]Feature{
708 .@"64bit",716 .@"64bit_support",
709 .altivec,717 .altivec,
710 .fres,718 .fres,
711 .frsqrte,719 .frsqrte,
...@@ -718,7 +726,7 @@ pub const cpu = struct {...@@ -718,7 +726,7 @@ pub const cpu = struct {
718 .name = "a2",726 .name = "a2",
719 .llvm_name = "a2",727 .llvm_name = "a2",
720 .features = featureSet(&[_]Feature{728 .features = featureSet(&[_]Feature{
721 .@"64bit",729 .@"64bit_support",
722 .booke,730 .booke,
723 .cmpb,731 .cmpb,
724 .fcpsgn,732 .fcpsgn,
...@@ -761,7 +769,7 @@ pub const cpu = struct {...@@ -761,7 +769,7 @@ pub const cpu = struct {
761 .name = "e5500",769 .name = "e5500",
762 .llvm_name = "e5500",770 .llvm_name = "e5500",
763 .features = featureSet(&[_]Feature{771 .features = featureSet(&[_]Feature{
764 .@"64bit",772 .@"64bit_support",
765 .booke,773 .booke,
766 .isel,774 .isel,
767 .mfocrf,775 .mfocrf,
...@@ -772,7 +780,7 @@ pub const cpu = struct {...@@ -772,7 +780,7 @@ pub const cpu = struct {
772 .name = "future",780 .name = "future",
773 .llvm_name = "future",781 .llvm_name = "future",
774 .features = featureSet(&[_]Feature{782 .features = featureSet(&[_]Feature{
775 .@"64bit",783 .@"64bit_support",
776 .allow_unaligned_fp_access,784 .allow_unaligned_fp_access,
777 .bpermd,785 .bpermd,
778 .cmpb,786 .cmpb,
...@@ -846,7 +854,7 @@ pub const cpu = struct {...@@ -846,7 +854,7 @@ pub const cpu = struct {
846 .name = "g5",854 .name = "g5",
847 .llvm_name = "g5",855 .llvm_name = "g5",
848 .features = featureSet(&[_]Feature{856 .features = featureSet(&[_]Feature{
849 .@"64bit",857 .@"64bit_support",
850 .altivec,858 .altivec,
851 .fres,859 .fres,
852 .frsqrte,860 .frsqrte,
...@@ -873,7 +881,7 @@ pub const cpu = struct {...@@ -873,7 +881,7 @@ pub const cpu = struct {
873 .name = "ppc64",881 .name = "ppc64",
874 .llvm_name = "ppc64",882 .llvm_name = "ppc64",
875 .features = featureSet(&[_]Feature{883 .features = featureSet(&[_]Feature{
876 .@"64bit",884 .@"64bit_support",
877 .altivec,885 .altivec,
878 .fres,886 .fres,
879 .frsqrte,887 .frsqrte,
...@@ -886,7 +894,7 @@ pub const cpu = struct {...@@ -886,7 +894,7 @@ pub const cpu = struct {
886 .name = "ppc64le",894 .name = "ppc64le",
887 .llvm_name = "ppc64le",895 .llvm_name = "ppc64le",
888 .features = featureSet(&[_]Feature{896 .features = featureSet(&[_]Feature{
889 .@"64bit",897 .@"64bit_support",
890 .allow_unaligned_fp_access,898 .allow_unaligned_fp_access,
891 .bpermd,899 .bpermd,
892 .cmpb,900 .cmpb,
...@@ -926,7 +934,7 @@ pub const cpu = struct {...@@ -926,7 +934,7 @@ pub const cpu = struct {
926 .name = "pwr10",934 .name = "pwr10",
927 .llvm_name = "pwr10",935 .llvm_name = "pwr10",
928 .features = featureSet(&[_]Feature{936 .features = featureSet(&[_]Feature{
929 .@"64bit",937 .@"64bit_support",
930 .allow_unaligned_fp_access,938 .allow_unaligned_fp_access,
931 .bpermd,939 .bpermd,
932 .cmpb,940 .cmpb,
...@@ -973,7 +981,7 @@ pub const cpu = struct {...@@ -973,7 +981,7 @@ pub const cpu = struct {
973 .name = "pwr11",981 .name = "pwr11",
974 .llvm_name = "pwr11",982 .llvm_name = "pwr11",
975 .features = featureSet(&[_]Feature{983 .features = featureSet(&[_]Feature{
976 .@"64bit",984 .@"64bit_support",
977 .allow_unaligned_fp_access,985 .allow_unaligned_fp_access,
978 .bpermd,986 .bpermd,
979 .cmpb,987 .cmpb,
...@@ -1020,7 +1028,7 @@ pub const cpu = struct {...@@ -1020,7 +1028,7 @@ pub const cpu = struct {
1020 .name = "pwr3",1028 .name = "pwr3",
1021 .llvm_name = "pwr3",1029 .llvm_name = "pwr3",
1022 .features = featureSet(&[_]Feature{1030 .features = featureSet(&[_]Feature{
1023 .@"64bit",1031 .@"64bit_support",
1024 .altivec,1032 .altivec,
1025 .fres,1033 .fres,
1026 .frsqrte,1034 .frsqrte,
...@@ -1032,7 +1040,7 @@ pub const cpu = struct {...@@ -1032,7 +1040,7 @@ pub const cpu = struct {
1032 .name = "pwr4",1040 .name = "pwr4",
1033 .llvm_name = "pwr4",1041 .llvm_name = "pwr4",
1034 .features = featureSet(&[_]Feature{1042 .features = featureSet(&[_]Feature{
1035 .@"64bit",1043 .@"64bit_support",
1036 .altivec,1044 .altivec,
1037 .fres,1045 .fres,
1038 .frsqrte,1046 .frsqrte,
...@@ -1045,7 +1053,7 @@ pub const cpu = struct {...@@ -1045,7 +1053,7 @@ pub const cpu = struct {
1045 .name = "pwr5",1053 .name = "pwr5",
1046 .llvm_name = "pwr5",1054 .llvm_name = "pwr5",
1047 .features = featureSet(&[_]Feature{1055 .features = featureSet(&[_]Feature{
1048 .@"64bit",1056 .@"64bit_support",
1049 .altivec,1057 .altivec,
1050 .fre,1058 .fre,
1051 .fres,1059 .fres,
...@@ -1060,7 +1068,7 @@ pub const cpu = struct {...@@ -1060,7 +1068,7 @@ pub const cpu = struct {
1060 .name = "pwr5x",1068 .name = "pwr5x",
1061 .llvm_name = "pwr5x",1069 .llvm_name = "pwr5x",
1062 .features = featureSet(&[_]Feature{1070 .features = featureSet(&[_]Feature{
1063 .@"64bit",1071 .@"64bit_support",
1064 .altivec,1072 .altivec,
1065 .fprnd,1073 .fprnd,
1066 .fre,1074 .fre,
...@@ -1076,7 +1084,7 @@ pub const cpu = struct {...@@ -1076,7 +1084,7 @@ pub const cpu = struct {
1076 .name = "pwr6",1084 .name = "pwr6",
1077 .llvm_name = "pwr6",1085 .llvm_name = "pwr6",
1078 .features = featureSet(&[_]Feature{1086 .features = featureSet(&[_]Feature{
1079 .@"64bit",1087 .@"64bit_support",
1080 .altivec,1088 .altivec,
1081 .cmpb,1089 .cmpb,
1082 .fcpsgn,1090 .fcpsgn,
...@@ -1096,7 +1104,7 @@ pub const cpu = struct {...@@ -1096,7 +1104,7 @@ pub const cpu = struct {
1096 .name = "pwr6x",1104 .name = "pwr6x",
1097 .llvm_name = "pwr6x",1105 .llvm_name = "pwr6x",
1098 .features = featureSet(&[_]Feature{1106 .features = featureSet(&[_]Feature{
1099 .@"64bit",1107 .@"64bit_support",
1100 .altivec,1108 .altivec,
1101 .cmpb,1109 .cmpb,
1102 .fcpsgn,1110 .fcpsgn,
...@@ -1116,7 +1124,7 @@ pub const cpu = struct {...@@ -1116,7 +1124,7 @@ pub const cpu = struct {
1116 .name = "pwr7",1124 .name = "pwr7",
1117 .llvm_name = "pwr7",1125 .llvm_name = "pwr7",
1118 .features = featureSet(&[_]Feature{1126 .features = featureSet(&[_]Feature{
1119 .@"64bit",1127 .@"64bit_support",
1120 .allow_unaligned_fp_access,1128 .allow_unaligned_fp_access,
1121 .bpermd,1129 .bpermd,
1122 .cmpb,1130 .cmpb,
...@@ -1145,7 +1153,7 @@ pub const cpu = struct {...@@ -1145,7 +1153,7 @@ pub const cpu = struct {
1145 .name = "pwr8",1153 .name = "pwr8",
1146 .llvm_name = "pwr8",1154 .llvm_name = "pwr8",
1147 .features = featureSet(&[_]Feature{1155 .features = featureSet(&[_]Feature{
1148 .@"64bit",1156 .@"64bit_support",
1149 .allow_unaligned_fp_access,1157 .allow_unaligned_fp_access,
1150 .bpermd,1158 .bpermd,
1151 .cmpb,1159 .cmpb,
...@@ -1185,7 +1193,7 @@ pub const cpu = struct {...@@ -1185,7 +1193,7 @@ pub const cpu = struct {
1185 .name = "pwr9",1193 .name = "pwr9",
1186 .llvm_name = "pwr9",1194 .llvm_name = "pwr9",
1187 .features = featureSet(&[_]Feature{1195 .features = featureSet(&[_]Feature{
1188 .@"64bit",1196 .@"64bit_support",
1189 .allow_unaligned_fp_access,1197 .allow_unaligned_fp_access,
1190 .bpermd,1198 .bpermd,
1191 .cmpb,1199 .cmpb,
lib/std/Target/riscv.zig+415-177
...@@ -8,49 +8,40 @@ pub const Feature = enum {...@@ -8,49 +8,40 @@ pub const Feature = enum {
8 @"32bit",8 @"32bit",
9 @"64bit",9 @"64bit",
10 a,10 a,
11 add_load_fusion,
12 addi_load_fusion,
11 andes45,13 andes45,
12 auipc_addi_fusion,14 auipc_addi_fusion,
15 auipc_load_fusion,
13 b,16 b,
17 bfext_fusion,
14 c,18 c,
15 conditional_cmv_fusion,19 conditional_cmv_fusion,
16 d,20 d,
17 disable_latency_sched_heuristic,21 disable_latency_sched_heuristic,
22 disable_misched_load_clustering,
23 disable_misched_store_clustering,
24 disable_postmisched_load_clustering,
25 disable_postmisched_store_clustering,
18 dlen_factor_2,26 dlen_factor_2,
19 e,27 e,
28 enable_vsetvli_sched_heuristic,
20 exact_asm,29 exact_asm,
21 experimental,30 experimental,
22 experimental_p,31 experimental_p,
23 experimental_rvm23u32,32 experimental_rvm23u32,
24 experimental_smctr,33 experimental_smpmpmt,
25 experimental_ssctr,
26 experimental_svukte,34 experimental_svukte,
27 experimental_xqccmp,
28 experimental_xqcia,
29 experimental_xqciac,
30 experimental_xqcibi,
31 experimental_xqcibm,
32 experimental_xqcicli,
33 experimental_xqcicm,
34 experimental_xqcics,
35 experimental_xqcicsr,
36 experimental_xqciint,
37 experimental_xqciio,
38 experimental_xqcilb,
39 experimental_xqcili,
40 experimental_xqcilia,
41 experimental_xqcilo,
42 experimental_xqcilsm,
43 experimental_xqcisim,
44 experimental_xqcisls,
45 experimental_xqcisync,
46 experimental_xrivosvisni,35 experimental_xrivosvisni,
47 experimental_xrivosvizip,36 experimental_xrivosvizip,
48 experimental_xsfmclic,37 experimental_xsfmclic,
49 experimental_xsfsclic,38 experimental_xsfsclic,
50 experimental_zalasr,39 experimental_zibi,
51 experimental_zicfilp,40 experimental_zicfilp,
52 experimental_zicfiss,41 experimental_zicfiss,
53 experimental_zvbc32e,42 experimental_zvbc32e,
43 experimental_zvfbfa,
44 experimental_zvfofp8min,
54 experimental_zvkgs,45 experimental_zvkgs,
55 experimental_zvqdotq,46 experimental_zvqdotq,
56 f,47 f,
...@@ -60,6 +51,7 @@ pub const Feature = enum {...@@ -60,6 +51,7 @@ pub const Feature = enum {
60 ld_add_fusion,51 ld_add_fusion,
61 log_vrgather,52 log_vrgather,
62 lui_addi_fusion,53 lui_addi_fusion,
54 lui_load_fusion,
63 m,55 m,
64 mips_p8700,56 mips_p8700,
65 no_default_unroll,57 no_default_unroll,
...@@ -73,6 +65,7 @@ pub const Feature = enum {...@@ -73,6 +65,7 @@ pub const Feature = enum {
73 optimized_nf7_segment_load_store,65 optimized_nf7_segment_load_store,
74 optimized_nf8_segment_load_store,66 optimized_nf8_segment_load_store,
75 optimized_zero_stride_load,67 optimized_zero_stride_load,
68 permissive_zalrsc,
76 predictable_select_expensive,69 predictable_select_expensive,
77 prefer_vsetvli_over_read_vlenb,70 prefer_vsetvli_over_read_vlenb,
78 prefer_w_inst,71 prefer_w_inst,
...@@ -127,15 +120,21 @@ pub const Feature = enum {...@@ -127,15 +120,21 @@ pub const Feature = enum {
127 shgatpa,120 shgatpa,
128 shifted_zextw_fusion,121 shifted_zextw_fusion,
129 shlcofideleg,122 shlcofideleg,
130 short_forward_branch_opt,123 short_forward_branch_ialu,
124 short_forward_branch_iload,
125 short_forward_branch_iminmax,
126 short_forward_branch_imul,
131 shtvala,127 shtvala,
132 shvsatpa,128 shvsatpa,
133 shvstvala,129 shvstvala,
134 shvstvecd,130 shvstvecd,
131 shxadd_load_fusion,
132 single_element_vec_fp64,
135 smaia,133 smaia,
136 smcdeleg,134 smcdeleg,
137 smcntrpmf,135 smcntrpmf,
138 smcsrind,136 smcsrind,
137 smctr,
139 smdbltrp,138 smdbltrp,
140 smepmp,139 smepmp,
141 smmpm,140 smmpm,
...@@ -148,6 +147,7 @@ pub const Feature = enum {...@@ -148,6 +147,7 @@ pub const Feature = enum {
148 sscofpmf,147 sscofpmf,
149 sscounterenw,148 sscounterenw,
150 sscsrind,149 sscsrind,
150 ssctr,
151 ssdbltrp,151 ssdbltrp,
152 ssnpm,152 ssnpm,
153 sspm,153 sspm,
...@@ -179,6 +179,7 @@ pub const Feature = enum {...@@ -179,6 +179,7 @@ pub const Feature = enum {
179 xandesvbfhcvt,179 xandesvbfhcvt,
180 xandesvdot,180 xandesvdot,
181 xandesvpackfph,181 xandesvpackfph,
182 xandesvsinth,
182 xandesvsintload,183 xandesvsintload,
183 xcvalu,184 xcvalu,
184 xcvbi,185 xcvbi,
...@@ -189,7 +190,28 @@ pub const Feature = enum {...@@ -189,7 +190,28 @@ pub const Feature = enum {
189 xcvsimd,190 xcvsimd,
190 xmipscbop,191 xmipscbop,
191 xmipscmov,192 xmipscmov,
193 xmipsexectl,
192 xmipslsp,194 xmipslsp,
195 xqccmp,
196 xqci,
197 xqcia,
198 xqciac,
199 xqcibi,
200 xqcibm,
201 xqcicli,
202 xqcicm,
203 xqcics,
204 xqcicsr,
205 xqciint,
206 xqciio,
207 xqcilb,
208 xqcili,
209 xqcilia,
210 xqcilo,
211 xqcilsm,
212 xqcisim,
213 xqcisls,
214 xqcisync,
193 xsfcease,215 xsfcease,
194 xsfmm128t,216 xsfmm128t,
195 xsfmm16t,217 xsfmm16t,
...@@ -202,12 +224,18 @@ pub const Feature = enum {...@@ -202,12 +224,18 @@ pub const Feature = enum {
202 xsfmm64t,224 xsfmm64t,
203 xsfmmbase,225 xsfmmbase,
204 xsfvcp,226 xsfvcp,
227 xsfvfbfexp16e,
228 xsfvfexp16e,
229 xsfvfexp32e,
230 xsfvfexpa,
231 xsfvfexpa64e,
205 xsfvfnrclipxfqf,232 xsfvfnrclipxfqf,
206 xsfvfwmaccqqq,233 xsfvfwmaccqqq,
207 xsfvqmaccdod,234 xsfvqmaccdod,
208 xsfvqmaccqoq,235 xsfvqmaccqoq,
209 xsifivecdiscarddlone,236 xsifivecdiscarddlone,
210 xsifivecflushdlone,237 xsifivecflushdlone,
238 xsmtvdot,
211 xtheadba,239 xtheadba,
212 xtheadbb,240 xtheadbb,
213 xtheadbs,241 xtheadbs,
...@@ -226,6 +254,7 @@ pub const Feature = enum {...@@ -226,6 +254,7 @@ pub const Feature = enum {
226 zaamo,254 zaamo,
227 zabha,255 zabha,
228 zacas,256 zacas,
257 zalasr,
229 zalrsc,258 zalrsc,
230 zama16b,259 zama16b,
231 zawrs,260 zawrs,
...@@ -272,6 +301,7 @@ pub const Feature = enum {...@@ -272,6 +301,7 @@ pub const Feature = enum {
272 zihintpause,301 zihintpause,
273 zihpm,302 zihpm,
274 zilsd,303 zilsd,
304 zilsd_4byte_align,
275 zimop,305 zimop,
276 zk,306 zk,
277 zkn,307 zkn,
...@@ -352,6 +382,16 @@ pub const all_features = blk: {...@@ -352,6 +382,16 @@ pub const all_features = blk: {
352 .zalrsc,382 .zalrsc,
353 }),383 }),
354 };384 };
385 result[@intFromEnum(Feature.add_load_fusion)] = .{
386 .llvm_name = "add-load-fusion",
387 .description = "Enable ADD(.UW) + load macrofusion",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@intFromEnum(Feature.addi_load_fusion)] = .{
391 .llvm_name = "addi-load-fusion",
392 .description = "Enable ADDI + load macrofusion",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
355 result[@intFromEnum(Feature.andes45)] = .{395 result[@intFromEnum(Feature.andes45)] = .{
356 .llvm_name = "andes45",396 .llvm_name = "andes45",
357 .description = "Andes 45-Series processors",397 .description = "Andes 45-Series processors",
...@@ -362,6 +402,11 @@ pub const all_features = blk: {...@@ -362,6 +402,11 @@ pub const all_features = blk: {
362 .description = "Enable AUIPC+ADDI macrofusion",402 .description = "Enable AUIPC+ADDI macrofusion",
363 .dependencies = featureSet(&[_]Feature{}),403 .dependencies = featureSet(&[_]Feature{}),
364 };404 };
405 result[@intFromEnum(Feature.auipc_load_fusion)] = .{
406 .llvm_name = "auipc-load-fusion",
407 .description = "Enable AUIPC + load macrofusion",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
365 result[@intFromEnum(Feature.b)] = .{410 result[@intFromEnum(Feature.b)] = .{
366 .llvm_name = "b",411 .llvm_name = "b",
367 .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",412 .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",
...@@ -371,6 +416,11 @@ pub const all_features = blk: {...@@ -371,6 +416,11 @@ pub const all_features = blk: {
371 .zbs,416 .zbs,
372 }),417 }),
373 };418 };
419 result[@intFromEnum(Feature.bfext_fusion)] = .{
420 .llvm_name = "bfext-fusion",
421 .description = "Enable SLLI+SRLI (bitfield extract) macrofusion",
422 .dependencies = featureSet(&[_]Feature{}),
423 };
374 result[@intFromEnum(Feature.c)] = .{424 result[@intFromEnum(Feature.c)] = .{
375 .llvm_name = "c",425 .llvm_name = "c",
376 .description = "'C' (Compressed Instructions)",426 .description = "'C' (Compressed Instructions)",
...@@ -395,6 +445,26 @@ pub const all_features = blk: {...@@ -395,6 +445,26 @@ pub const all_features = blk: {
395 .description = "Disable latency scheduling heuristic",445 .description = "Disable latency scheduling heuristic",
396 .dependencies = featureSet(&[_]Feature{}),446 .dependencies = featureSet(&[_]Feature{}),
397 };447 };
448 result[@intFromEnum(Feature.disable_misched_load_clustering)] = .{
449 .llvm_name = "disable-misched-load-clustering",
450 .description = "Disable load clustering in the machine scheduler",
451 .dependencies = featureSet(&[_]Feature{}),
452 };
453 result[@intFromEnum(Feature.disable_misched_store_clustering)] = .{
454 .llvm_name = "disable-misched-store-clustering",
455 .description = "Disable store clustering in the machine scheduler",
456 .dependencies = featureSet(&[_]Feature{}),
457 };
458 result[@intFromEnum(Feature.disable_postmisched_load_clustering)] = .{
459 .llvm_name = "disable-postmisched-load-clustering",
460 .description = "Disable PostRA load clustering in the machine scheduler",
461 .dependencies = featureSet(&[_]Feature{}),
462 };
463 result[@intFromEnum(Feature.disable_postmisched_store_clustering)] = .{
464 .llvm_name = "disable-postmisched-store-clustering",
465 .description = "Disable PostRA store clustering in the machine scheduler",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
398 result[@intFromEnum(Feature.dlen_factor_2)] = .{468 result[@intFromEnum(Feature.dlen_factor_2)] = .{
399 .llvm_name = "dlen-factor-2",469 .llvm_name = "dlen-factor-2",
400 .description = "Vector unit DLEN(data path width) is half of VLEN",470 .description = "Vector unit DLEN(data path width) is half of VLEN",
...@@ -405,6 +475,11 @@ pub const all_features = blk: {...@@ -405,6 +475,11 @@ pub const all_features = blk: {
405 .description = "'E' (Embedded Instruction Set with 16 GPRs)",475 .description = "'E' (Embedded Instruction Set with 16 GPRs)",
406 .dependencies = featureSet(&[_]Feature{}),476 .dependencies = featureSet(&[_]Feature{}),
407 };477 };
478 result[@intFromEnum(Feature.enable_vsetvli_sched_heuristic)] = .{
479 .llvm_name = "enable-vsetvli-sched-heuristic",
480 .description = "Enable vsetvli-based scheduling heuristic",
481 .dependencies = featureSet(&[_]Feature{}),
482 };
408 result[@intFromEnum(Feature.exact_asm)] = .{483 result[@intFromEnum(Feature.exact_asm)] = .{
409 .llvm_name = "exact-asm",484 .llvm_name = "exact-asm",
410 .description = "Enable Exact Assembly (Disables Compression and Relaxation)",485 .description = "Enable Exact Assembly (Disables Compression and Relaxation)",
...@@ -437,144 +512,16 @@ pub const all_features = blk: {...@@ -437,144 +512,16 @@ pub const all_features = blk: {
437 .zimop,512 .zimop,
438 }),513 }),
439 };514 };
440 result[@intFromEnum(Feature.experimental_smctr)] = .{515 result[@intFromEnum(Feature.experimental_smpmpmt)] = .{
441 .llvm_name = "experimental-smctr",516 .llvm_name = "experimental-smpmpmt",
442 .description = "'Smctr' (Control Transfer Records Machine Level)",517 .description = "'Smpmpmt' (PMP-based Memory Types Extension)",
443 .dependencies = featureSet(&[_]Feature{518 .dependencies = featureSet(&[_]Feature{}),
444 .sscsrind,
445 }),
446 };
447 result[@intFromEnum(Feature.experimental_ssctr)] = .{
448 .llvm_name = "experimental-ssctr",
449 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
450 .dependencies = featureSet(&[_]Feature{
451 .sscsrind,
452 }),
453 };519 };
454 result[@intFromEnum(Feature.experimental_svukte)] = .{520 result[@intFromEnum(Feature.experimental_svukte)] = .{
455 .llvm_name = "experimental-svukte",521 .llvm_name = "experimental-svukte",
456 .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",522 .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
457 .dependencies = featureSet(&[_]Feature{}),523 .dependencies = featureSet(&[_]Feature{}),
458 };524 };
459 result[@intFromEnum(Feature.experimental_xqccmp)] = .{
460 .llvm_name = "experimental-xqccmp",
461 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
462 .dependencies = featureSet(&[_]Feature{
463 .zca,
464 }),
465 };
466 result[@intFromEnum(Feature.experimental_xqcia)] = .{
467 .llvm_name = "experimental-xqcia",
468 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
469 .dependencies = featureSet(&[_]Feature{}),
470 };
471 result[@intFromEnum(Feature.experimental_xqciac)] = .{
472 .llvm_name = "experimental-xqciac",
473 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
474 .dependencies = featureSet(&[_]Feature{
475 .zca,
476 }),
477 };
478 result[@intFromEnum(Feature.experimental_xqcibi)] = .{
479 .llvm_name = "experimental-xqcibi",
480 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
481 .dependencies = featureSet(&[_]Feature{
482 .zca,
483 }),
484 };
485 result[@intFromEnum(Feature.experimental_xqcibm)] = .{
486 .llvm_name = "experimental-xqcibm",
487 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
488 .dependencies = featureSet(&[_]Feature{
489 .zca,
490 }),
491 };
492 result[@intFromEnum(Feature.experimental_xqcicli)] = .{
493 .llvm_name = "experimental-xqcicli",
494 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
495 .dependencies = featureSet(&[_]Feature{}),
496 };
497 result[@intFromEnum(Feature.experimental_xqcicm)] = .{
498 .llvm_name = "experimental-xqcicm",
499 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
500 .dependencies = featureSet(&[_]Feature{
501 .zca,
502 }),
503 };
504 result[@intFromEnum(Feature.experimental_xqcics)] = .{
505 .llvm_name = "experimental-xqcics",
506 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
507 .dependencies = featureSet(&[_]Feature{}),
508 };
509 result[@intFromEnum(Feature.experimental_xqcicsr)] = .{
510 .llvm_name = "experimental-xqcicsr",
511 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
512 .dependencies = featureSet(&[_]Feature{}),
513 };
514 result[@intFromEnum(Feature.experimental_xqciint)] = .{
515 .llvm_name = "experimental-xqciint",
516 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
517 .dependencies = featureSet(&[_]Feature{
518 .zca,
519 }),
520 };
521 result[@intFromEnum(Feature.experimental_xqciio)] = .{
522 .llvm_name = "experimental-xqciio",
523 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
524 .dependencies = featureSet(&[_]Feature{}),
525 };
526 result[@intFromEnum(Feature.experimental_xqcilb)] = .{
527 .llvm_name = "experimental-xqcilb",
528 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
529 .dependencies = featureSet(&[_]Feature{
530 .zca,
531 }),
532 };
533 result[@intFromEnum(Feature.experimental_xqcili)] = .{
534 .llvm_name = "experimental-xqcili",
535 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
536 .dependencies = featureSet(&[_]Feature{
537 .zca,
538 }),
539 };
540 result[@intFromEnum(Feature.experimental_xqcilia)] = .{
541 .llvm_name = "experimental-xqcilia",
542 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
543 .dependencies = featureSet(&[_]Feature{
544 .zca,
545 }),
546 };
547 result[@intFromEnum(Feature.experimental_xqcilo)] = .{
548 .llvm_name = "experimental-xqcilo",
549 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
550 .dependencies = featureSet(&[_]Feature{
551 .zca,
552 }),
553 };
554 result[@intFromEnum(Feature.experimental_xqcilsm)] = .{
555 .llvm_name = "experimental-xqcilsm",
556 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
557 .dependencies = featureSet(&[_]Feature{}),
558 };
559 result[@intFromEnum(Feature.experimental_xqcisim)] = .{
560 .llvm_name = "experimental-xqcisim",
561 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
562 .dependencies = featureSet(&[_]Feature{
563 .zca,
564 }),
565 };
566 result[@intFromEnum(Feature.experimental_xqcisls)] = .{
567 .llvm_name = "experimental-xqcisls",
568 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
569 .dependencies = featureSet(&[_]Feature{}),
570 };
571 result[@intFromEnum(Feature.experimental_xqcisync)] = .{
572 .llvm_name = "experimental-xqcisync",
573 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
574 .dependencies = featureSet(&[_]Feature{
575 .zca,
576 }),
577 };
578 result[@intFromEnum(Feature.experimental_xrivosvisni)] = .{525 result[@intFromEnum(Feature.experimental_xrivosvisni)] = .{
579 .llvm_name = "experimental-xrivosvisni",526 .llvm_name = "experimental-xrivosvisni",
580 .description = "'XRivosVisni' (Rivos Vector Integer Small New)",527 .description = "'XRivosVisni' (Rivos Vector Integer Small New)",
...@@ -595,9 +542,9 @@ pub const all_features = blk: {...@@ -595,9 +542,9 @@ pub const all_features = blk: {
595 .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",542 .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
596 .dependencies = featureSet(&[_]Feature{}),543 .dependencies = featureSet(&[_]Feature{}),
597 };544 };
598 result[@intFromEnum(Feature.experimental_zalasr)] = .{545 result[@intFromEnum(Feature.experimental_zibi)] = .{
599 .llvm_name = "experimental-zalasr",546 .llvm_name = "experimental-zibi",
600 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",547 .description = "'Zibi' (Branch with Immediate)",
601 .dependencies = featureSet(&[_]Feature{}),548 .dependencies = featureSet(&[_]Feature{}),
602 };549 };
603 result[@intFromEnum(Feature.experimental_zicfilp)] = .{550 result[@intFromEnum(Feature.experimental_zicfilp)] = .{
...@@ -622,6 +569,21 @@ pub const all_features = blk: {...@@ -622,6 +569,21 @@ pub const all_features = blk: {
622 .zve32x,569 .zve32x,
623 }),570 }),
624 };571 };
572 result[@intFromEnum(Feature.experimental_zvfbfa)] = .{
573 .llvm_name = "experimental-zvfbfa",
574 .description = "'Zvfbfa' (Additional BF16 vector compute support)",
575 .dependencies = featureSet(&[_]Feature{
576 .zfbfmin,
577 .zve32f,
578 }),
579 };
580 result[@intFromEnum(Feature.experimental_zvfofp8min)] = .{
581 .llvm_name = "experimental-zvfofp8min",
582 .description = "'Zvfofp8min' (Vector OFP8 Converts)",
583 .dependencies = featureSet(&[_]Feature{
584 .zve32f,
585 }),
586 };
625 result[@intFromEnum(Feature.experimental_zvkgs)] = .{587 result[@intFromEnum(Feature.experimental_zvkgs)] = .{
626 .llvm_name = "experimental-zvkgs",588 .llvm_name = "experimental-zvkgs",
627 .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",589 .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
...@@ -673,6 +635,11 @@ pub const all_features = blk: {...@@ -673,6 +635,11 @@ pub const all_features = blk: {
673 .description = "Enable LUI+ADDI macro fusion",635 .description = "Enable LUI+ADDI macro fusion",
674 .dependencies = featureSet(&[_]Feature{}),636 .dependencies = featureSet(&[_]Feature{}),
675 };637 };
638 result[@intFromEnum(Feature.lui_load_fusion)] = .{
639 .llvm_name = "lui-load-fusion",
640 .description = "Enable LUI + load macrofusion",
641 .dependencies = featureSet(&[_]Feature{}),
642 };
676 result[@intFromEnum(Feature.m)] = .{643 result[@intFromEnum(Feature.m)] = .{
677 .llvm_name = "m",644 .llvm_name = "m",
678 .description = "'M' (Integer Multiplication and Division)",645 .description = "'M' (Integer Multiplication and Division)",
...@@ -740,6 +707,11 @@ pub const all_features = blk: {...@@ -740,6 +707,11 @@ pub const all_features = blk: {
740 .description = "Optimized (perform fewer memory operations)zero-stride vector load",707 .description = "Optimized (perform fewer memory operations)zero-stride vector load",
741 .dependencies = featureSet(&[_]Feature{}),708 .dependencies = featureSet(&[_]Feature{}),
742 };709 };
710 result[@intFromEnum(Feature.permissive_zalrsc)] = .{
711 .llvm_name = "permissive-zalrsc",
712 .description = "Implementation permits non-base instructions between LR/SC pairs",
713 .dependencies = featureSet(&[_]Feature{}),
714 };
743 result[@intFromEnum(Feature.predictable_select_expensive)] = .{715 result[@intFromEnum(Feature.predictable_select_expensive)] = .{
744 .llvm_name = "predictable-select-expensive",716 .llvm_name = "predictable-select-expensive",
745 .description = "Prefer likely predicted branches over selects",717 .description = "Prefer likely predicted branches over selects",
...@@ -1262,11 +1234,32 @@ pub const all_features = blk: {...@@ -1262,11 +1234,32 @@ pub const all_features = blk: {
1262 .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",1234 .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
1263 .dependencies = featureSet(&[_]Feature{}),1235 .dependencies = featureSet(&[_]Feature{}),
1264 };1236 };
1265 result[@intFromEnum(Feature.short_forward_branch_opt)] = .{1237 result[@intFromEnum(Feature.short_forward_branch_ialu)] = .{
1266 .llvm_name = "short-forward-branch-opt",1238 .llvm_name = "short-forward-branch-ialu",
1267 .description = "Enable short forward branch optimization",1239 .description = "Enable short forward branch optimization for RVI base instructions",
1268 .dependencies = featureSet(&[_]Feature{}),1240 .dependencies = featureSet(&[_]Feature{}),
1269 };1241 };
1242 result[@intFromEnum(Feature.short_forward_branch_iload)] = .{
1243 .llvm_name = "short-forward-branch-iload",
1244 .description = "Enable short forward branch optimization for load instructions",
1245 .dependencies = featureSet(&[_]Feature{
1246 .short_forward_branch_ialu,
1247 }),
1248 };
1249 result[@intFromEnum(Feature.short_forward_branch_iminmax)] = .{
1250 .llvm_name = "short-forward-branch-iminmax",
1251 .description = "Enable short forward branch optimization for MIN,MAX instructions in Zbb",
1252 .dependencies = featureSet(&[_]Feature{
1253 .short_forward_branch_ialu,
1254 }),
1255 };
1256 result[@intFromEnum(Feature.short_forward_branch_imul)] = .{
1257 .llvm_name = "short-forward-branch-imul",
1258 .description = "Enable short forward branch optimization for MUL instruction",
1259 .dependencies = featureSet(&[_]Feature{
1260 .short_forward_branch_ialu,
1261 }),
1262 };
1270 result[@intFromEnum(Feature.shtvala)] = .{1263 result[@intFromEnum(Feature.shtvala)] = .{
1271 .llvm_name = "shtvala",1264 .llvm_name = "shtvala",
1272 .description = "'Shtvala' (htval provides all needed values)",1265 .description = "'Shtvala' (htval provides all needed values)",
...@@ -1287,6 +1280,16 @@ pub const all_features = blk: {...@@ -1287,6 +1280,16 @@ pub const all_features = blk: {
1287 .description = "'Shvstvecd' (vstvec supports Direct mode)",1280 .description = "'Shvstvecd' (vstvec supports Direct mode)",
1288 .dependencies = featureSet(&[_]Feature{}),1281 .dependencies = featureSet(&[_]Feature{}),
1289 };1282 };
1283 result[@intFromEnum(Feature.shxadd_load_fusion)] = .{
1284 .llvm_name = "shxadd-load-fusion",
1285 .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion",
1286 .dependencies = featureSet(&[_]Feature{}),
1287 };
1288 result[@intFromEnum(Feature.single_element_vec_fp64)] = .{
1289 .llvm_name = "single-element-vec-fp64",
1290 .description = "Certain vector FP64 operations produce a single result element per cycle",
1291 .dependencies = featureSet(&[_]Feature{}),
1292 };
1290 result[@intFromEnum(Feature.smaia)] = .{1293 result[@intFromEnum(Feature.smaia)] = .{
1291 .llvm_name = "smaia",1294 .llvm_name = "smaia",
1292 .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",1295 .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
...@@ -1307,6 +1310,13 @@ pub const all_features = blk: {...@@ -1307,6 +1310,13 @@ pub const all_features = blk: {
1307 .description = "'Smcsrind' (Indirect CSR Access Machine Level)",1310 .description = "'Smcsrind' (Indirect CSR Access Machine Level)",
1308 .dependencies = featureSet(&[_]Feature{}),1311 .dependencies = featureSet(&[_]Feature{}),
1309 };1312 };
1313 result[@intFromEnum(Feature.smctr)] = .{
1314 .llvm_name = "smctr",
1315 .description = "'Smctr' (Control Transfer Records Machine Level)",
1316 .dependencies = featureSet(&[_]Feature{
1317 .sscsrind,
1318 }),
1319 };
1310 result[@intFromEnum(Feature.smdbltrp)] = .{1320 result[@intFromEnum(Feature.smdbltrp)] = .{
1311 .llvm_name = "smdbltrp",1321 .llvm_name = "smdbltrp",
1312 .description = "'Smdbltrp' (Double Trap Machine Level)",1322 .description = "'Smdbltrp' (Double Trap Machine Level)",
...@@ -1369,6 +1379,13 @@ pub const all_features = blk: {...@@ -1369,6 +1379,13 @@ pub const all_features = blk: {
1369 .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",1379 .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",
1370 .dependencies = featureSet(&[_]Feature{}),1380 .dependencies = featureSet(&[_]Feature{}),
1371 };1381 };
1382 result[@intFromEnum(Feature.ssctr)] = .{
1383 .llvm_name = "ssctr",
1384 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
1385 .dependencies = featureSet(&[_]Feature{
1386 .sscsrind,
1387 }),
1388 };
1372 result[@intFromEnum(Feature.ssdbltrp)] = .{1389 result[@intFromEnum(Feature.ssdbltrp)] = .{
1373 .llvm_name = "ssdbltrp",1390 .llvm_name = "ssdbltrp",
1374 .description = "'Ssdbltrp' (Double Trap Supervisor Level)",1391 .description = "'Ssdbltrp' (Double Trap Supervisor Level)",
...@@ -1537,6 +1554,13 @@ pub const all_features = blk: {...@@ -1537,6 +1554,13 @@ pub const all_features = blk: {
1537 .f,1554 .f,
1538 }),1555 }),
1539 };1556 };
1557 result[@intFromEnum(Feature.xandesvsinth)] = .{
1558 .llvm_name = "xandesvsinth",
1559 .description = "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)",
1560 .dependencies = featureSet(&[_]Feature{
1561 .zve32x,
1562 }),
1563 };
1540 result[@intFromEnum(Feature.xandesvsintload)] = .{1564 result[@intFromEnum(Feature.xandesvsintload)] = .{
1541 .llvm_name = "xandesvsintload",1565 .llvm_name = "xandesvsintload",
1542 .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",1566 .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
...@@ -1589,11 +1613,159 @@ pub const all_features = blk: {...@@ -1589,11 +1613,159 @@ pub const all_features = blk: {
1589 .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",1613 .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
1590 .dependencies = featureSet(&[_]Feature{}),1614 .dependencies = featureSet(&[_]Feature{}),
1591 };1615 };
1616 result[@intFromEnum(Feature.xmipsexectl)] = .{
1617 .llvm_name = "xmipsexectl",
1618 .description = "'XMIPSEXECTL' (MIPS execution control)",
1619 .dependencies = featureSet(&[_]Feature{}),
1620 };
1592 result[@intFromEnum(Feature.xmipslsp)] = .{1621 result[@intFromEnum(Feature.xmipslsp)] = .{
1593 .llvm_name = "xmipslsp",1622 .llvm_name = "xmipslsp",
1594 .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",1623 .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",
1595 .dependencies = featureSet(&[_]Feature{}),1624 .dependencies = featureSet(&[_]Feature{}),
1596 };1625 };
1626 result[@intFromEnum(Feature.xqccmp)] = .{
1627 .llvm_name = "xqccmp",
1628 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
1629 .dependencies = featureSet(&[_]Feature{
1630 .zca,
1631 }),
1632 };
1633 result[@intFromEnum(Feature.xqci)] = .{
1634 .llvm_name = "xqci",
1635 .description = "'Xqci' (Qualcomm uC Extension)",
1636 .dependencies = featureSet(&[_]Feature{
1637 .xqcia,
1638 .xqciac,
1639 .xqcibi,
1640 .xqcibm,
1641 .xqcicli,
1642 .xqcicm,
1643 .xqcics,
1644 .xqcicsr,
1645 .xqciint,
1646 .xqciio,
1647 .xqcilb,
1648 .xqcili,
1649 .xqcilia,
1650 .xqcilo,
1651 .xqcilsm,
1652 .xqcisim,
1653 .xqcisls,
1654 .xqcisync,
1655 }),
1656 };
1657 result[@intFromEnum(Feature.xqcia)] = .{
1658 .llvm_name = "xqcia",
1659 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
1660 .dependencies = featureSet(&[_]Feature{}),
1661 };
1662 result[@intFromEnum(Feature.xqciac)] = .{
1663 .llvm_name = "xqciac",
1664 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
1665 .dependencies = featureSet(&[_]Feature{
1666 .zca,
1667 }),
1668 };
1669 result[@intFromEnum(Feature.xqcibi)] = .{
1670 .llvm_name = "xqcibi",
1671 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
1672 .dependencies = featureSet(&[_]Feature{
1673 .zca,
1674 }),
1675 };
1676 result[@intFromEnum(Feature.xqcibm)] = .{
1677 .llvm_name = "xqcibm",
1678 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
1679 .dependencies = featureSet(&[_]Feature{
1680 .zca,
1681 }),
1682 };
1683 result[@intFromEnum(Feature.xqcicli)] = .{
1684 .llvm_name = "xqcicli",
1685 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
1686 .dependencies = featureSet(&[_]Feature{}),
1687 };
1688 result[@intFromEnum(Feature.xqcicm)] = .{
1689 .llvm_name = "xqcicm",
1690 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
1691 .dependencies = featureSet(&[_]Feature{
1692 .zca,
1693 }),
1694 };
1695 result[@intFromEnum(Feature.xqcics)] = .{
1696 .llvm_name = "xqcics",
1697 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
1698 .dependencies = featureSet(&[_]Feature{}),
1699 };
1700 result[@intFromEnum(Feature.xqcicsr)] = .{
1701 .llvm_name = "xqcicsr",
1702 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
1703 .dependencies = featureSet(&[_]Feature{}),
1704 };
1705 result[@intFromEnum(Feature.xqciint)] = .{
1706 .llvm_name = "xqciint",
1707 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
1708 .dependencies = featureSet(&[_]Feature{
1709 .zca,
1710 }),
1711 };
1712 result[@intFromEnum(Feature.xqciio)] = .{
1713 .llvm_name = "xqciio",
1714 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
1715 .dependencies = featureSet(&[_]Feature{}),
1716 };
1717 result[@intFromEnum(Feature.xqcilb)] = .{
1718 .llvm_name = "xqcilb",
1719 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
1720 .dependencies = featureSet(&[_]Feature{
1721 .zca,
1722 }),
1723 };
1724 result[@intFromEnum(Feature.xqcili)] = .{
1725 .llvm_name = "xqcili",
1726 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
1727 .dependencies = featureSet(&[_]Feature{
1728 .zca,
1729 }),
1730 };
1731 result[@intFromEnum(Feature.xqcilia)] = .{
1732 .llvm_name = "xqcilia",
1733 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
1734 .dependencies = featureSet(&[_]Feature{
1735 .zca,
1736 }),
1737 };
1738 result[@intFromEnum(Feature.xqcilo)] = .{
1739 .llvm_name = "xqcilo",
1740 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
1741 .dependencies = featureSet(&[_]Feature{
1742 .zca,
1743 }),
1744 };
1745 result[@intFromEnum(Feature.xqcilsm)] = .{
1746 .llvm_name = "xqcilsm",
1747 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
1748 .dependencies = featureSet(&[_]Feature{}),
1749 };
1750 result[@intFromEnum(Feature.xqcisim)] = .{
1751 .llvm_name = "xqcisim",
1752 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
1753 .dependencies = featureSet(&[_]Feature{
1754 .zca,
1755 }),
1756 };
1757 result[@intFromEnum(Feature.xqcisls)] = .{
1758 .llvm_name = "xqcisls",
1759 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
1760 .dependencies = featureSet(&[_]Feature{}),
1761 };
1762 result[@intFromEnum(Feature.xqcisync)] = .{
1763 .llvm_name = "xqcisync",
1764 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
1765 .dependencies = featureSet(&[_]Feature{
1766 .zca,
1767 }),
1768 };
1597 result[@intFromEnum(Feature.xsfcease)] = .{1769 result[@intFromEnum(Feature.xsfcease)] = .{
1598 .llvm_name = "xsfcease",1770 .llvm_name = "xsfcease",
1599 .description = "'XSfcease' (SiFive sf.cease Instruction)",1771 .description = "'XSfcease' (SiFive sf.cease Instruction)",
...@@ -1684,6 +1856,40 @@ pub const all_features = blk: {...@@ -1684,6 +1856,40 @@ pub const all_features = blk: {
1684 .zve32x,1856 .zve32x,
1685 }),1857 }),
1686 };1858 };
1859 result[@intFromEnum(Feature.xsfvfbfexp16e)] = .{
1860 .llvm_name = "xsfvfbfexp16e",
1861 .description = "'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)",
1862 .dependencies = featureSet(&[_]Feature{}),
1863 };
1864 result[@intFromEnum(Feature.xsfvfexp16e)] = .{
1865 .llvm_name = "xsfvfexp16e",
1866 .description = "'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)",
1867 .dependencies = featureSet(&[_]Feature{
1868 .zvfh,
1869 }),
1870 };
1871 result[@intFromEnum(Feature.xsfvfexp32e)] = .{
1872 .llvm_name = "xsfvfexp32e",
1873 .description = "'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)",
1874 .dependencies = featureSet(&[_]Feature{
1875 .zve32f,
1876 }),
1877 };
1878 result[@intFromEnum(Feature.xsfvfexpa)] = .{
1879 .llvm_name = "xsfvfexpa",
1880 .description = "'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)",
1881 .dependencies = featureSet(&[_]Feature{
1882 .zve32f,
1883 }),
1884 };
1885 result[@intFromEnum(Feature.xsfvfexpa64e)] = .{
1886 .llvm_name = "xsfvfexpa64e",
1887 .description = "'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision)",
1888 .dependencies = featureSet(&[_]Feature{
1889 .xsfvfexpa,
1890 .zve64d,
1891 }),
1892 };
1687 result[@intFromEnum(Feature.xsfvfnrclipxfqf)] = .{1893 result[@intFromEnum(Feature.xsfvfnrclipxfqf)] = .{
1688 .llvm_name = "xsfvfnrclipxfqf",1894 .llvm_name = "xsfvfnrclipxfqf",
1689 .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",1895 .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
...@@ -1696,6 +1902,7 @@ pub const all_features = blk: {...@@ -1696,6 +1902,7 @@ pub const all_features = blk: {
1696 .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",1902 .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
1697 .dependencies = featureSet(&[_]Feature{1903 .dependencies = featureSet(&[_]Feature{
1698 .zvfbfmin,1904 .zvfbfmin,
1905 .zvl128b,
1699 }),1906 }),
1700 };1907 };
1701 result[@intFromEnum(Feature.xsfvqmaccdod)] = .{1908 result[@intFromEnum(Feature.xsfvqmaccdod)] = .{
...@@ -1703,6 +1910,7 @@ pub const all_features = blk: {...@@ -1703,6 +1910,7 @@ pub const all_features = blk: {
1703 .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",1910 .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
1704 .dependencies = featureSet(&[_]Feature{1911 .dependencies = featureSet(&[_]Feature{
1705 .zve32x,1912 .zve32x,
1913 .zvl128b,
1706 }),1914 }),
1707 };1915 };
1708 result[@intFromEnum(Feature.xsfvqmaccqoq)] = .{1916 result[@intFromEnum(Feature.xsfvqmaccqoq)] = .{
...@@ -1710,6 +1918,7 @@ pub const all_features = blk: {...@@ -1710,6 +1918,7 @@ pub const all_features = blk: {
1710 .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",1918 .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
1711 .dependencies = featureSet(&[_]Feature{1919 .dependencies = featureSet(&[_]Feature{
1712 .zve32x,1920 .zve32x,
1921 .zvl256b,
1713 }),1922 }),
1714 };1923 };
1715 result[@intFromEnum(Feature.xsifivecdiscarddlone)] = .{1924 result[@intFromEnum(Feature.xsifivecdiscarddlone)] = .{
...@@ -1722,6 +1931,13 @@ pub const all_features = blk: {...@@ -1722,6 +1931,13 @@ pub const all_features = blk: {
1722 .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",1931 .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",
1723 .dependencies = featureSet(&[_]Feature{}),1932 .dependencies = featureSet(&[_]Feature{}),
1724 };1933 };
1934 result[@intFromEnum(Feature.xsmtvdot)] = .{
1935 .llvm_name = "xsmtvdot",
1936 .description = "'XSMTVDot' (SpacemiT Vector Dot Product Extension)",
1937 .dependencies = featureSet(&[_]Feature{
1938 .zve32f,
1939 }),
1940 };
1725 result[@intFromEnum(Feature.xtheadba)] = .{1941 result[@intFromEnum(Feature.xtheadba)] = .{
1726 .llvm_name = "xtheadba",1942 .llvm_name = "xtheadba",
1727 .description = "'XTHeadBa' (T-Head address calculation instructions)",1943 .description = "'XTHeadBa' (T-Head address calculation instructions)",
...@@ -1820,6 +2036,11 @@ pub const all_features = blk: {...@@ -1820,6 +2036,11 @@ pub const all_features = blk: {
1820 .zaamo,2036 .zaamo,
1821 }),2037 }),
1822 };2038 };
2039 result[@intFromEnum(Feature.zalasr)] = .{
2040 .llvm_name = "zalasr",
2041 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
2042 .dependencies = featureSet(&[_]Feature{}),
2043 };
1823 result[@intFromEnum(Feature.zalrsc)] = .{2044 result[@intFromEnum(Feature.zalrsc)] = .{
1824 .llvm_name = "zalrsc",2045 .llvm_name = "zalrsc",
1825 .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",2046 .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",
...@@ -2092,6 +2313,11 @@ pub const all_features = blk: {...@@ -2092,6 +2313,11 @@ pub const all_features = blk: {
2092 .description = "'Zilsd' (Load/Store Pair Instructions)",2313 .description = "'Zilsd' (Load/Store Pair Instructions)",
2093 .dependencies = featureSet(&[_]Feature{}),2314 .dependencies = featureSet(&[_]Feature{}),
2094 };2315 };
2316 result[@intFromEnum(Feature.zilsd_4byte_align)] = .{
2317 .llvm_name = "zilsd-4byte-align",
2318 .description = "Allow 4-byte alignment for Zilsd LD/SD instructions",
2319 .dependencies = featureSet(&[_]Feature{}),
2320 };
2095 result[@intFromEnum(Feature.zimop)] = .{2321 result[@intFromEnum(Feature.zimop)] = .{
2096 .llvm_name = "zimop",2322 .llvm_name = "zimop",
2097 .description = "'Zimop' (May-Be-Operations)",2323 .description = "'Zimop' (May-Be-Operations)",
...@@ -2461,7 +2687,7 @@ pub const cpu = struct {...@@ -2461,7 +2687,7 @@ pub const cpu = struct {
2461 .features = featureSet(&[_]Feature{2687 .features = featureSet(&[_]Feature{
2462 .andes45,2688 .andes45,
2463 .no_default_unroll,2689 .no_default_unroll,
2464 .short_forward_branch_opt,2690 .short_forward_branch_ialu,
2465 .use_postra_scheduler,2691 .use_postra_scheduler,
2466 }),2692 }),
2467 };2693 };
...@@ -2491,7 +2717,7 @@ pub const cpu = struct {...@@ -2491,7 +2717,7 @@ pub const cpu = struct {
2491 .i,2717 .i,
2492 .m,2718 .m,
2493 .no_default_unroll,2719 .no_default_unroll,
2494 .short_forward_branch_opt,2720 .short_forward_branch_ialu,
2495 .use_postra_scheduler,2721 .use_postra_scheduler,
2496 .xandesperf,2722 .xandesperf,
2497 .zifencei,2723 .zifencei,
...@@ -2523,7 +2749,7 @@ pub const cpu = struct {...@@ -2523,7 +2749,7 @@ pub const cpu = struct {
2523 .i,2749 .i,
2524 .m,2750 .m,
2525 .no_default_unroll,2751 .no_default_unroll,
2526 .short_forward_branch_opt,2752 .short_forward_branch_ialu,
2527 .use_postra_scheduler,2753 .use_postra_scheduler,
2528 .xandesperf,2754 .xandesperf,
2529 .zifencei,2755 .zifencei,
...@@ -2540,7 +2766,7 @@ pub const cpu = struct {...@@ -2540,7 +2766,7 @@ pub const cpu = struct {
2540 .i,2766 .i,
2541 .m,2767 .m,
2542 .no_default_unroll,2768 .no_default_unroll,
2543 .short_forward_branch_opt,2769 .short_forward_branch_ialu,
2544 .use_postra_scheduler,2770 .use_postra_scheduler,
2545 .v,2771 .v,
2546 .xandesperf,2772 .xandesperf,
...@@ -2559,7 +2785,7 @@ pub const cpu = struct {...@@ -2559,7 +2785,7 @@ pub const cpu = struct {
2559 .i,2785 .i,
2560 .m,2786 .m,
2561 .no_default_unroll,2787 .no_default_unroll,
2562 .short_forward_branch_opt,2788 .short_forward_branch_ialu,
2563 .use_postra_scheduler,2789 .use_postra_scheduler,
2564 .xandesperf,2790 .xandesperf,
2565 .zifencei,2791 .zifencei,
...@@ -2577,7 +2803,7 @@ pub const cpu = struct {...@@ -2577,7 +2803,7 @@ pub const cpu = struct {
2577 .i,2803 .i,
2578 .m,2804 .m,
2579 .no_default_unroll,2805 .no_default_unroll,
2580 .short_forward_branch_opt,2806 .short_forward_branch_ialu,
2581 .use_postra_scheduler,2807 .use_postra_scheduler,
2582 .xandesperf,2808 .xandesperf,
2583 .zifencei,2809 .zifencei,
...@@ -2648,6 +2874,7 @@ pub const cpu = struct {...@@ -2648,6 +2874,7 @@ pub const cpu = struct {
2648 .mips_p8700,2874 .mips_p8700,
2649 .xmipscbop,2875 .xmipscbop,
2650 .xmipscmov,2876 .xmipscmov,
2877 .xmipsexectl,
2651 .xmipslsp,2878 .xmipslsp,
2652 .zba,2879 .zba,
2653 .zbb,2880 .zbb,
...@@ -2703,7 +2930,7 @@ pub const cpu = struct {...@@ -2703,7 +2930,7 @@ pub const cpu = struct {
2703 .llvm_name = "sifive-7-series",2930 .llvm_name = "sifive-7-series",
2704 .features = featureSet(&[_]Feature{2931 .features = featureSet(&[_]Feature{
2705 .no_default_unroll,2932 .no_default_unroll,
2706 .short_forward_branch_opt,2933 .short_forward_branch_ialu,
2707 .use_postra_scheduler,2934 .use_postra_scheduler,
2708 }),2935 }),
2709 };2936 };
...@@ -2782,7 +3009,7 @@ pub const cpu = struct {...@@ -2782,7 +3009,7 @@ pub const cpu = struct {
2782 .i,3009 .i,
2783 .m,3010 .m,
2784 .no_default_unroll,3011 .no_default_unroll,
2785 .short_forward_branch_opt,3012 .short_forward_branch_ialu,
2786 .use_postra_scheduler,3013 .use_postra_scheduler,
2787 .zifencei,3014 .zifencei,
2788 }),3015 }),
...@@ -2815,7 +3042,6 @@ pub const cpu = struct {...@@ -2815,7 +3042,6 @@ pub const cpu = struct {
2815 .ziccif,3042 .ziccif,
2816 .zicclsm,3043 .zicclsm,
2817 .ziccrse,3044 .ziccrse,
2818 .zicntr,
2819 .zifencei,3045 .zifencei,
2820 .zihintntl,3046 .zihintntl,
2821 .zihintpause,3047 .zihintpause,
...@@ -2855,7 +3081,6 @@ pub const cpu = struct {...@@ -2855,7 +3081,6 @@ pub const cpu = struct {
2855 .ziccif,3081 .ziccif,
2856 .zicclsm,3082 .zicclsm,
2857 .ziccrse,3083 .ziccrse,
2858 .zicntr,
2859 .zifencei,3084 .zifencei,
2860 .zihintntl,3085 .zihintntl,
2861 .zihintpause,3086 .zihintpause,
...@@ -2918,7 +3143,6 @@ pub const cpu = struct {...@@ -2918,7 +3143,6 @@ pub const cpu = struct {
2918 .ziccif,3143 .ziccif,
2919 .zicclsm,3144 .zicclsm,
2920 .ziccrse,3145 .ziccrse,
2921 .zicntr,
2922 .zifencei,3146 .zifencei,
2923 .zihintntl,3147 .zihintntl,
2924 .zihintpause,3148 .zihintpause,
...@@ -3035,7 +3259,7 @@ pub const cpu = struct {...@@ -3035,7 +3259,7 @@ pub const cpu = struct {
3035 .i,3259 .i,
3036 .m,3260 .m,
3037 .no_default_unroll,3261 .no_default_unroll,
3038 .short_forward_branch_opt,3262 .short_forward_branch_ialu,
3039 .use_postra_scheduler,3263 .use_postra_scheduler,
3040 .zifencei,3264 .zifencei,
3041 .zihintpause,3265 .zihintpause,
...@@ -3065,7 +3289,7 @@ pub const cpu = struct {...@@ -3065,7 +3289,7 @@ pub const cpu = struct {
3065 .i,3289 .i,
3066 .m,3290 .m,
3067 .no_default_unroll,3291 .no_default_unroll,
3068 .short_forward_branch_opt,3292 .short_forward_branch_ialu,
3069 .use_postra_scheduler,3293 .use_postra_scheduler,
3070 .zifencei,3294 .zifencei,
3071 }),3295 }),
...@@ -3083,7 +3307,7 @@ pub const cpu = struct {...@@ -3083,7 +3307,7 @@ pub const cpu = struct {
3083 .no_default_unroll,3307 .no_default_unroll,
3084 .optimized_nf2_segment_load_store,3308 .optimized_nf2_segment_load_store,
3085 .optimized_zero_stride_load,3309 .optimized_zero_stride_load,
3086 .short_forward_branch_opt,3310 .short_forward_branch_ialu,
3087 .use_postra_scheduler,3311 .use_postra_scheduler,
3088 .v,3312 .v,
3089 .vl_dependent_latency,3313 .vl_dependent_latency,
...@@ -3111,7 +3335,8 @@ pub const cpu = struct {...@@ -3111,7 +3335,8 @@ pub const cpu = struct {
3111 .no_default_unroll,3335 .no_default_unroll,
3112 .optimized_nf2_segment_load_store,3336 .optimized_nf2_segment_load_store,
3113 .optimized_zero_stride_load,3337 .optimized_zero_stride_load,
3114 .short_forward_branch_opt,3338 .short_forward_branch_ialu,
3339 .single_element_vec_fp64,
3115 .use_postra_scheduler,3340 .use_postra_scheduler,
3116 .v,3341 .v,
3117 .vl_dependent_latency,3342 .vl_dependent_latency,
...@@ -3173,6 +3398,7 @@ pub const cpu = struct {...@@ -3173,6 +3398,7 @@ pub const cpu = struct {
3173 .unaligned_scalar_mem,3398 .unaligned_scalar_mem,
3174 .v,3399 .v,
3175 .vxrm_pipeline_flush,3400 .vxrm_pipeline_flush,
3401 .xsmtvdot,
3176 .za64rs,3402 .za64rs,
3177 .zbc,3403 .zbc,
3178 .zbkc,3404 .zbkc,
...@@ -3341,6 +3567,13 @@ pub const cpu = struct {...@@ -3341,6 +3567,13 @@ pub const cpu = struct {
3341 .log_vrgather,3567 .log_vrgather,
3342 .m,3568 .m,
3343 .no_default_unroll,3569 .no_default_unroll,
3570 .optimized_nf2_segment_load_store,
3571 .optimized_nf3_segment_load_store,
3572 .optimized_nf4_segment_load_store,
3573 .optimized_nf5_segment_load_store,
3574 .optimized_nf6_segment_load_store,
3575 .optimized_nf7_segment_load_store,
3576 .optimized_nf8_segment_load_store,
3344 .optimized_zero_stride_load,3577 .optimized_zero_stride_load,
3345 .sha,3578 .sha,
3346 .smaia,3579 .smaia,
...@@ -3400,12 +3633,17 @@ pub const cpu = struct {...@@ -3400,12 +3633,17 @@ pub const cpu = struct {
3400 .features = featureSet(&[_]Feature{3633 .features = featureSet(&[_]Feature{
3401 .@"64bit",3634 .@"64bit",
3402 .a,3635 .a,
3636 .add_load_fusion,
3403 .auipc_addi_fusion,3637 .auipc_addi_fusion,
3638 .auipc_load_fusion,
3404 .c,3639 .c,
3405 .d,3640 .d,
3641 .disable_misched_load_clustering,
3642 .disable_postmisched_load_clustering,
3643 .disable_postmisched_store_clustering,
3406 .i,3644 .i,
3407 .ld_add_fusion,
3408 .lui_addi_fusion,3645 .lui_addi_fusion,
3646 .lui_load_fusion,
3409 .m,3647 .m,
3410 .shifted_zextw_fusion,3648 .shifted_zextw_fusion,
3411 .ventana_veyron,3649 .ventana_veyron,
lib/std/Target/sparc.zig+17
...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {7pub const Feature = enum {
8 @"64bit",
8 crypto,9 crypto,
9 deprecated_v8,10 deprecated_v8,
10 detectroundchange,11 detectroundchange,
...@@ -23,6 +24,7 @@ pub const Feature = enum {...@@ -23,6 +24,7 @@ pub const Feature = enum {
23 leonpwrpsr,24 leonpwrpsr,
24 no_fmuls,25 no_fmuls,
25 no_fsmuld,26 no_fsmuld,
27 no_predictor,
26 osa2011,28 osa2011,
27 popc,29 popc,
28 reserve_g1,30 reserve_g1,
...@@ -73,6 +75,13 @@ pub const all_features = blk: {...@@ -73,6 +75,13 @@ pub const all_features = blk: {
73 const len = @typeInfo(Feature).@"enum".fields.len;75 const len = @typeInfo(Feature).@"enum".fields.len;
74 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);76 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
75 var result: [len]CpuFeature = undefined;77 var result: [len]CpuFeature = undefined;
78 result[@intFromEnum(Feature.@"64bit")] = .{
79 .llvm_name = "64bit",
80 .description = "Enable 64-bit mode",
81 .dependencies = featureSet(&[_]Feature{
82 .v9,
83 }),
84 };
76 result[@intFromEnum(Feature.crypto)] = .{85 result[@intFromEnum(Feature.crypto)] = .{
77 .llvm_name = "crypto",86 .llvm_name = "crypto",
78 .description = "Enable cryptographic extensions",87 .description = "Enable cryptographic extensions",
...@@ -165,6 +174,11 @@ pub const all_features = blk: {...@@ -165,6 +174,11 @@ pub const all_features = blk: {
165 .description = "Disable the fsmuld instruction.",174 .description = "Disable the fsmuld instruction.",
166 .dependencies = featureSet(&[_]Feature{}),175 .dependencies = featureSet(&[_]Feature{}),
167 };176 };
177 result[@intFromEnum(Feature.no_predictor)] = .{
178 .llvm_name = "no-predictor",
179 .description = "Processor has no branch predictor, branches stall execution",
180 .dependencies = featureSet(&[_]Feature{}),
181 };
168 result[@intFromEnum(Feature.osa2011)] = .{182 result[@intFromEnum(Feature.osa2011)] = .{
169 .llvm_name = "osa2011",183 .llvm_name = "osa2011",
170 .description = "Enable Oracle SPARC Architecture 2011 extensions",184 .description = "Enable Oracle SPARC Architecture 2011 extensions",
...@@ -586,6 +600,7 @@ pub const cpu = struct {...@@ -586,6 +600,7 @@ pub const cpu = struct {
586 .llvm_name = "niagara",600 .llvm_name = "niagara",
587 .features = featureSet(&[_]Feature{601 .features = featureSet(&[_]Feature{
588 .deprecated_v8,602 .deprecated_v8,
603 .no_predictor,
589 .ua2005,604 .ua2005,
590 }),605 }),
591 };606 };
...@@ -594,6 +609,7 @@ pub const cpu = struct {...@@ -594,6 +609,7 @@ pub const cpu = struct {
594 .llvm_name = "niagara2",609 .llvm_name = "niagara2",
595 .features = featureSet(&[_]Feature{610 .features = featureSet(&[_]Feature{
596 .deprecated_v8,611 .deprecated_v8,
612 .no_predictor,
597 .popc,613 .popc,
598 .ua2005,614 .ua2005,
599 }),615 }),
...@@ -603,6 +619,7 @@ pub const cpu = struct {...@@ -603,6 +619,7 @@ pub const cpu = struct {
603 .llvm_name = "niagara3",619 .llvm_name = "niagara3",
604 .features = featureSet(&[_]Feature{620 .features = featureSet(&[_]Feature{
605 .deprecated_v8,621 .deprecated_v8,
622 .no_predictor,
606 .popc,623 .popc,
607 .ua2005,624 .ua2005,
608 .ua2007,625 .ua2007,
lib/std/Target/wasm.zig+7
...@@ -12,6 +12,7 @@ pub const Feature = enum {...@@ -12,6 +12,7 @@ pub const Feature = enum {
12 exception_handling,12 exception_handling,
13 extended_const,13 extended_const,
14 fp16,14 fp16,
15 gc,
15 multimemory,16 multimemory,
16 multivalue,17 multivalue,
17 mutable_globals,18 mutable_globals,
...@@ -71,6 +72,11 @@ pub const all_features = blk: {...@@ -71,6 +72,11 @@ pub const all_features = blk: {
71 .description = "Enable FP16 instructions",72 .description = "Enable FP16 instructions",
72 .dependencies = featureSet(&[_]Feature{}),73 .dependencies = featureSet(&[_]Feature{}),
73 };74 };
75 result[@intFromEnum(Feature.gc)] = .{
76 .llvm_name = "gc",
77 .description = "Enable wasm gc",
78 .dependencies = featureSet(&[_]Feature{}),
79 };
74 result[@intFromEnum(Feature.multimemory)] = .{80 result[@intFromEnum(Feature.multimemory)] = .{
75 .llvm_name = "multimemory",81 .llvm_name = "multimemory",
76 .description = "Enable multiple memories",82 .description = "Enable multiple memories",
...@@ -148,6 +154,7 @@ pub const cpu = struct {...@@ -148,6 +154,7 @@ pub const cpu = struct {
148 .exception_handling,154 .exception_handling,
149 .extended_const,155 .extended_const,
150 .fp16,156 .fp16,
157 .gc,
151 .multimemory,158 .multimemory,
152 .multivalue,159 .multivalue,
153 .mutable_globals,160 .mutable_globals,
lib/std/Target/x86.zig+200-31
...@@ -22,7 +22,6 @@ pub const Feature = enum {...@@ -22,7 +22,6 @@ pub const Feature = enum {
22 amx_movrs,22 amx_movrs,
23 amx_tf32,23 amx_tf32,
24 amx_tile,24 amx_tile,
25 amx_transpose,
26 avx,25 avx,
27 avx10_1,26 avx10_1,
28 avx10_2,27 avx10_2,
...@@ -67,7 +66,6 @@ pub const Feature = enum {...@@ -67,7 +66,6 @@ pub const Feature = enum {
67 egpr,66 egpr,
68 enqcmd,67 enqcmd,
69 ermsb,68 ermsb,
70 evex512,
71 f16c,69 f16c,
72 false_deps_getmant,70 false_deps_getmant,
73 false_deps_lzcnt_tzcnt,71 false_deps_lzcnt_tzcnt,
...@@ -136,6 +134,7 @@ pub const Feature = enum {...@@ -136,6 +134,7 @@ pub const Feature = enum {
136 ppx,134 ppx,
137 prefer_128_bit,135 prefer_128_bit,
138 prefer_256_bit,136 prefer_256_bit,
137 prefer_legacy_setcc,
139 prefer_mask_registers,138 prefer_mask_registers,
140 prefer_movmsk_over_vtest,139 prefer_movmsk_over_vtest,
141 prefer_no_gather,140 prefer_no_gather,
...@@ -168,6 +167,7 @@ pub const Feature = enum {...@@ -168,6 +167,7 @@ pub const Feature = enum {
168 slow_lea,167 slow_lea,
169 slow_pmaddwd,168 slow_pmaddwd,
170 slow_pmulld,169 slow_pmulld,
170 slow_pmullq,
171 slow_shld,171 slow_shld,
172 slow_two_mem_ops,172 slow_two_mem_ops,
173 slow_unaligned_mem_16,173 slow_unaligned_mem_16,
...@@ -199,6 +199,7 @@ pub const Feature = enum {...@@ -199,6 +199,7 @@ pub const Feature = enum {
199 waitpkg,199 waitpkg,
200 wbnoinvd,200 wbnoinvd,
201 widekl,201 widekl,
202 x32,
202 x87,203 x87,
203 xop,204 xop,
204 xsave,205 xsave,
...@@ -324,13 +325,6 @@ pub const all_features = blk: {...@@ -324,13 +325,6 @@ pub const all_features = blk: {
324 .description = "Support AMX-TILE instructions",325 .description = "Support AMX-TILE instructions",
325 .dependencies = featureSet(&[_]Feature{}),326 .dependencies = featureSet(&[_]Feature{}),
326 };327 };
327 result[@intFromEnum(Feature.amx_transpose)] = .{
328 .llvm_name = "amx-transpose",
329 .description = "Support AMX amx-transpose instructions",
330 .dependencies = featureSet(&[_]Feature{
331 .amx_tile,
332 }),
333 };
334 result[@intFromEnum(Feature.avx)] = .{328 result[@intFromEnum(Feature.avx)] = .{
335 .llvm_name = "avx",329 .llvm_name = "avx",
336 .description = "Enable AVX instructions",330 .description = "Enable AVX instructions",
...@@ -339,8 +333,8 @@ pub const all_features = blk: {...@@ -339,8 +333,8 @@ pub const all_features = blk: {
339 }),333 }),
340 };334 };
341 result[@intFromEnum(Feature.avx10_1)] = .{335 result[@intFromEnum(Feature.avx10_1)] = .{
342 .llvm_name = "avx10.1-512",336 .llvm_name = "avx10.1",
343 .description = "Support AVX10.1 up to 512-bit instruction",337 .description = "Support AVX10.1 instruction",
344 .dependencies = featureSet(&[_]Feature{338 .dependencies = featureSet(&[_]Feature{
345 .avx512bf16,339 .avx512bf16,
346 .avx512bitalg,340 .avx512bitalg,
...@@ -356,8 +350,8 @@ pub const all_features = blk: {...@@ -356,8 +350,8 @@ pub const all_features = blk: {
356 }),350 }),
357 };351 };
358 result[@intFromEnum(Feature.avx10_2)] = .{352 result[@intFromEnum(Feature.avx10_2)] = .{
359 .llvm_name = "avx10.2-512",353 .llvm_name = "avx10.2",
360 .description = "Support AVX10.2 up to 512-bit instruction",354 .description = "Support AVX10.2 instruction",
361 .dependencies = featureSet(&[_]Feature{355 .dependencies = featureSet(&[_]Feature{
362 .avx10_1,356 .avx10_1,
363 }),357 }),
...@@ -416,7 +410,6 @@ pub const all_features = blk: {...@@ -416,7 +410,6 @@ pub const all_features = blk: {
416 .description = "Enable AVX-512 instructions",410 .description = "Enable AVX-512 instructions",
417 .dependencies = featureSet(&[_]Feature{411 .dependencies = featureSet(&[_]Feature{
418 .avx2,412 .avx2,
419 .evex512,
420 .f16c,413 .f16c,
421 .fma,414 .fma,
422 }),415 }),
...@@ -616,11 +609,6 @@ pub const all_features = blk: {...@@ -616,11 +609,6 @@ pub const all_features = blk: {
616 .description = "REP MOVS/STOS are fast",609 .description = "REP MOVS/STOS are fast",
617 .dependencies = featureSet(&[_]Feature{}),610 .dependencies = featureSet(&[_]Feature{}),
618 };611 };
619 result[@intFromEnum(Feature.evex512)] = .{
620 .llvm_name = "evex512",
621 .description = "Support ZMM and 64-bit mask instructions",
622 .dependencies = featureSet(&[_]Feature{}),
623 };
624 result[@intFromEnum(Feature.f16c)] = .{612 result[@intFromEnum(Feature.f16c)] = .{
625 .llvm_name = "f16c",613 .llvm_name = "f16c",
626 .description = "Support 16-bit floating point conversion instructions",614 .description = "Support 16-bit floating point conversion instructions",
...@@ -974,6 +962,11 @@ pub const all_features = blk: {...@@ -974,6 +962,11 @@ pub const all_features = blk: {
974 .description = "Prefer 256-bit AVX instructions",962 .description = "Prefer 256-bit AVX instructions",
975 .dependencies = featureSet(&[_]Feature{}),963 .dependencies = featureSet(&[_]Feature{}),
976 };964 };
965 result[@intFromEnum(Feature.prefer_legacy_setcc)] = .{
966 .llvm_name = "prefer-legacy-setcc",
967 .description = "Prefer to emit legacy SetCC.",
968 .dependencies = featureSet(&[_]Feature{}),
969 };
977 result[@intFromEnum(Feature.prefer_mask_registers)] = .{970 result[@intFromEnum(Feature.prefer_mask_registers)] = .{
978 .llvm_name = "prefer-mask-registers",971 .llvm_name = "prefer-mask-registers",
979 .description = "Prefer AVX512 mask registers over PTEST/MOVMSK",972 .description = "Prefer AVX512 mask registers over PTEST/MOVMSK",
...@@ -1145,6 +1138,11 @@ pub const all_features = blk: {...@@ -1145,6 +1138,11 @@ pub const all_features = blk: {
1145 .description = "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)",1138 .description = "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)",
1146 .dependencies = featureSet(&[_]Feature{}),1139 .dependencies = featureSet(&[_]Feature{}),
1147 };1140 };
1141 result[@intFromEnum(Feature.slow_pmullq)] = .{
1142 .llvm_name = "slow-pmullq",
1143 .description = "PMULLQ instruction is slow",
1144 .dependencies = featureSet(&[_]Feature{}),
1145 };
1148 result[@intFromEnum(Feature.slow_shld)] = .{1146 result[@intFromEnum(Feature.slow_shld)] = .{
1149 .llvm_name = "slow-shld",1147 .llvm_name = "slow-shld",
1150 .description = "SHLD instruction is slow",1148 .description = "SHLD instruction is slow",
...@@ -1325,6 +1323,11 @@ pub const all_features = blk: {...@@ -1325,6 +1323,11 @@ pub const all_features = blk: {
1325 .kl,1323 .kl,
1326 }),1324 }),
1327 };1325 };
1326 result[@intFromEnum(Feature.x32)] = .{
1327 .llvm_name = "x32",
1328 .description = "64-bit with ILP32 programming model (e.g. x32 ABI)",
1329 .dependencies = featureSet(&[_]Feature{}),
1330 };
1328 result[@intFromEnum(Feature.x87)] = .{1331 result[@intFromEnum(Feature.x87)] = .{
1329 .llvm_name = "x87",1332 .llvm_name = "x87",
1330 .description = "Enable X87 float instructions",1333 .description = "Enable X87 float instructions",
...@@ -1393,7 +1396,6 @@ pub const cpu = struct {...@@ -1393,7 +1396,6 @@ pub const cpu = struct {
1393 .cx16,1396 .cx16,
1394 .f16c,1397 .f16c,
1395 .false_deps_perm,1398 .false_deps_perm,
1396 .false_deps_popcnt,
1397 .fast_15bytenop,1399 .fast_15bytenop,
1398 .fast_gather,1400 .fast_gather,
1399 .fast_scalar_fsqrt,1401 .fast_scalar_fsqrt,
...@@ -1432,6 +1434,7 @@ pub const cpu = struct {...@@ -1432,6 +1434,7 @@ pub const cpu = struct {
1432 .sha,1434 .sha,
1433 .shstk,1435 .shstk,
1434 .slow_3ops_lea,1436 .slow_3ops_lea,
1437 .slow_pmullq,
1435 .smap,1438 .smap,
1436 .smep,1439 .smep,
1437 .tuning_fast_imm_vector_shift,1440 .tuning_fast_imm_vector_shift,
...@@ -1490,7 +1493,6 @@ pub const cpu = struct {...@@ -1490,7 +1493,6 @@ pub const cpu = struct {
1490 .enqcmd,1493 .enqcmd,
1491 .f16c,1494 .f16c,
1492 .false_deps_perm,1495 .false_deps_perm,
1493 .false_deps_popcnt,
1494 .fast_15bytenop,1496 .fast_15bytenop,
1495 .fast_gather,1497 .fast_gather,
1496 .fast_scalar_fsqrt,1498 .fast_scalar_fsqrt,
...@@ -1529,6 +1531,7 @@ pub const cpu = struct {...@@ -1529,6 +1531,7 @@ pub const cpu = struct {
1529 .sha,1531 .sha,
1530 .shstk,1532 .shstk,
1531 .slow_3ops_lea,1533 .slow_3ops_lea,
1534 .slow_pmullq,
1532 .smap,1535 .smap,
1533 .smep,1536 .smep,
1534 .tuning_fast_imm_vector_shift,1537 .tuning_fast_imm_vector_shift,
...@@ -1566,7 +1569,6 @@ pub const cpu = struct {...@@ -1566,7 +1569,6 @@ pub const cpu = struct {
1566 .enqcmd,1569 .enqcmd,
1567 .f16c,1570 .f16c,
1568 .false_deps_perm,1571 .false_deps_perm,
1569 .false_deps_popcnt,
1570 .fast_15bytenop,1572 .fast_15bytenop,
1571 .fast_gather,1573 .fast_gather,
1572 .fast_scalar_fsqrt,1574 .fast_scalar_fsqrt,
...@@ -1606,6 +1608,7 @@ pub const cpu = struct {...@@ -1606,6 +1608,7 @@ pub const cpu = struct {
1606 .sha512,1608 .sha512,
1607 .shstk,1609 .shstk,
1608 .slow_3ops_lea,1610 .slow_3ops_lea,
1611 .slow_pmullq,
1609 .sm3,1612 .sm3,
1610 .sm4,1613 .sm4,
1611 .smap,1614 .smap,
...@@ -2204,6 +2207,7 @@ pub const cpu = struct {...@@ -2204,6 +2207,7 @@ pub const cpu = struct {
2204 .sahf,2207 .sahf,
2205 .sha,2208 .sha,
2206 .slow_3ops_lea,2209 .slow_3ops_lea,
2210 .slow_pmullq,
2207 .smap,2211 .smap,
2208 .smep,2212 .smep,
2209 .tuning_fast_imm_vector_shift,2213 .tuning_fast_imm_vector_shift,
...@@ -2297,7 +2301,6 @@ pub const cpu = struct {...@@ -2297,7 +2301,6 @@ pub const cpu = struct {
2297 .enqcmd,2301 .enqcmd,
2298 .f16c,2302 .f16c,
2299 .false_deps_perm,2303 .false_deps_perm,
2300 .false_deps_popcnt,
2301 .fast_15bytenop,2304 .fast_15bytenop,
2302 .fast_gather,2305 .fast_gather,
2303 .fast_scalar_fsqrt,2306 .fast_scalar_fsqrt,
...@@ -2338,6 +2341,7 @@ pub const cpu = struct {...@@ -2338,6 +2341,7 @@ pub const cpu = struct {
2338 .sha512,2341 .sha512,
2339 .shstk,2342 .shstk,
2340 .slow_3ops_lea,2343 .slow_3ops_lea,
2344 .slow_pmullq,
2341 .sm3,2345 .sm3,
2342 .sm4,2346 .sm4,
2343 .tuning_fast_imm_vector_shift,2347 .tuning_fast_imm_vector_shift,
...@@ -2464,7 +2468,6 @@ pub const cpu = struct {...@@ -2464,7 +2468,6 @@ pub const cpu = struct {
2464 .amx_int8,2468 .amx_int8,
2465 .amx_movrs,2469 .amx_movrs,
2466 .amx_tf32,2470 .amx_tf32,
2467 .amx_transpose,
2468 .avx10_2,2471 .avx10_2,
2469 .avxifma,2472 .avxifma,
2470 .avxneconvert,2473 .avxneconvert,
...@@ -2475,7 +2478,6 @@ pub const cpu = struct {...@@ -2475,7 +2478,6 @@ pub const cpu = struct {
2475 .bmi2,2478 .bmi2,
2476 .branch_hint,2479 .branch_hint,
2477 .ccmp,2480 .ccmp,
2478 .cf,
2479 .cldemote,2481 .cldemote,
2480 .clflushopt,2482 .clflushopt,
2481 .clwb,2483 .clwb,
...@@ -2533,12 +2535,12 @@ pub const cpu = struct {...@@ -2533,12 +2535,12 @@ pub const cpu = struct {
2533 .sha,2535 .sha,
2534 .sha512,2536 .sha512,
2535 .shstk,2537 .shstk,
2538 .slow_pmullq,
2536 .sm3,2539 .sm3,
2537 .sm4,2540 .sm4,
2538 .tsxldtrk,2541 .tsxldtrk,
2539 .tuning_fast_imm_vector_shift,2542 .tuning_fast_imm_vector_shift,
2540 .uintr,2543 .uintr,
2541 .usermsr,
2542 .vaes,2544 .vaes,
2543 .vpclmulqdq,2545 .vpclmulqdq,
2544 .vzeroupper,2546 .vzeroupper,
...@@ -2622,6 +2624,7 @@ pub const cpu = struct {...@@ -2622,6 +2624,7 @@ pub const cpu = struct {
2622 .serialize,2624 .serialize,
2623 .sha,2625 .sha,
2624 .shstk,2626 .shstk,
2627 .slow_pmullq,
2625 .smap,2628 .smap,
2626 .smep,2629 .smep,
2627 .tsxldtrk,2630 .tsxldtrk,
...@@ -2935,6 +2938,7 @@ pub const cpu = struct {...@@ -2935,6 +2938,7 @@ pub const cpu = struct {
2935 .serialize,2938 .serialize,
2936 .sha,2939 .sha,
2937 .shstk,2940 .shstk,
2941 .slow_pmullq,
2938 .tsxldtrk,2942 .tsxldtrk,
2939 .tuning_fast_imm_vector_shift,2943 .tuning_fast_imm_vector_shift,
2940 .uintr,2944 .uintr,
...@@ -3024,6 +3028,7 @@ pub const cpu = struct {...@@ -3024,6 +3028,7 @@ pub const cpu = struct {
3024 .serialize,3028 .serialize,
3025 .sha,3029 .sha,
3026 .shstk,3030 .shstk,
3031 .slow_pmullq,
3027 .tsxldtrk,3032 .tsxldtrk,
3028 .tuning_fast_imm_vector_shift,3033 .tuning_fast_imm_vector_shift,
3029 .uintr,3034 .uintr,
...@@ -3181,6 +3186,7 @@ pub const cpu = struct {...@@ -3181,6 +3186,7 @@ pub const cpu = struct {
3181 .rdseed,3186 .rdseed,
3182 .sahf,3187 .sahf,
3183 .sha,3188 .sha,
3189 .slow_pmullq,
3184 .tuning_fast_imm_vector_shift,3190 .tuning_fast_imm_vector_shift,
3185 .vaes,3191 .vaes,
3186 .vpclmulqdq,3192 .vpclmulqdq,
...@@ -3245,6 +3251,7 @@ pub const cpu = struct {...@@ -3245,6 +3251,7 @@ pub const cpu = struct {
3245 .rdseed,3251 .rdseed,
3246 .sahf,3252 .sahf,
3247 .sha,3253 .sha,
3254 .slow_pmullq,
3248 .tuning_fast_imm_vector_shift,3255 .tuning_fast_imm_vector_shift,
3249 .vaes,3256 .vaes,
3250 .vpclmulqdq,3257 .vpclmulqdq,
...@@ -3475,7 +3482,6 @@ pub const cpu = struct {...@@ -3475,7 +3482,6 @@ pub const cpu = struct {
3475 .enqcmd,3482 .enqcmd,
3476 .f16c,3483 .f16c,
3477 .false_deps_perm,3484 .false_deps_perm,
3478 .false_deps_popcnt,
3479 .fast_15bytenop,3485 .fast_15bytenop,
3480 .fast_gather,3486 .fast_gather,
3481 .fast_scalar_fsqrt,3487 .fast_scalar_fsqrt,
...@@ -3515,6 +3521,7 @@ pub const cpu = struct {...@@ -3515,6 +3521,7 @@ pub const cpu = struct {
3515 .sha512,3521 .sha512,
3516 .shstk,3522 .shstk,
3517 .slow_3ops_lea,3523 .slow_3ops_lea,
3524 .slow_pmullq,
3518 .sm3,3525 .sm3,
3519 .sm4,3526 .sm4,
3520 .tuning_fast_imm_vector_shift,3527 .tuning_fast_imm_vector_shift,
...@@ -3546,7 +3553,6 @@ pub const cpu = struct {...@@ -3546,7 +3553,6 @@ pub const cpu = struct {
3546 .cx16,3553 .cx16,
3547 .f16c,3554 .f16c,
3548 .false_deps_perm,3555 .false_deps_perm,
3549 .false_deps_popcnt,
3550 .fast_15bytenop,3556 .fast_15bytenop,
3551 .fast_gather,3557 .fast_gather,
3552 .fast_scalar_fsqrt,3558 .fast_scalar_fsqrt,
...@@ -3585,6 +3591,7 @@ pub const cpu = struct {...@@ -3585,6 +3591,7 @@ pub const cpu = struct {
3585 .sha,3591 .sha,
3586 .shstk,3592 .shstk,
3587 .slow_3ops_lea,3593 .slow_3ops_lea,
3594 .slow_pmullq,
3588 .smap,3595 .smap,
3589 .smep,3596 .smep,
3590 .tuning_fast_imm_vector_shift,3597 .tuning_fast_imm_vector_shift,
...@@ -3635,6 +3642,90 @@ pub const cpu = struct {...@@ -3635,6 +3642,90 @@ pub const cpu = struct {
3635 .x87,3642 .x87,
3636 }),3643 }),
3637 };3644 };
3645 pub const novalake: CpuModel = .{
3646 .name = "novalake",
3647 .llvm_name = "novalake",
3648 .features = featureSet(&[_]Feature{
3649 .@"64bit",
3650 .adx,
3651 .allow_light_256_bit,
3652 .avx10_2,
3653 .avxifma,
3654 .avxneconvert,
3655 .avxvnni,
3656 .avxvnniint16,
3657 .avxvnniint8,
3658 .bmi,
3659 .bmi2,
3660 .ccmp,
3661 .clflushopt,
3662 .clwb,
3663 .cmov,
3664 .cmpccxadd,
3665 .cx16,
3666 .egpr,
3667 .enqcmd,
3668 .false_deps_perm,
3669 .fast_15bytenop,
3670 .fast_gather,
3671 .fast_scalar_fsqrt,
3672 .fast_shld_rotate,
3673 .fast_variable_crosslane_shuffle,
3674 .fast_variable_perlane_shuffle,
3675 .fast_vector_fsqrt,
3676 .fsgsbase,
3677 .fxsr,
3678 .gfni,
3679 .hreset,
3680 .idivq_to_divl,
3681 .invpcid,
3682 .lzcnt,
3683 .macrofusion,
3684 .mmx,
3685 .movbe,
3686 .movdir64b,
3687 .movdiri,
3688 .movrs,
3689 .ndd,
3690 .nf,
3691 .no_bypass_delay_blend,
3692 .no_bypass_delay_mov,
3693 .no_bypass_delay_shuffle,
3694 .nopl,
3695 .pconfig,
3696 .pku,
3697 .popcnt,
3698 .ppx,
3699 .prefer_movmsk_over_vtest,
3700 .prefetchi,
3701 .prfchw,
3702 .ptwrite,
3703 .push2pop2,
3704 .rdpid,
3705 .rdrnd,
3706 .rdseed,
3707 .sahf,
3708 .serialize,
3709 .sha,
3710 .sha512,
3711 .shstk,
3712 .slow_3ops_lea,
3713 .slow_pmullq,
3714 .sm3,
3715 .sm4,
3716 .tuning_fast_imm_vector_shift,
3717 .uintr,
3718 .vaes,
3719 .vpclmulqdq,
3720 .vzeroupper,
3721 .waitpkg,
3722 .x87,
3723 .xsavec,
3724 .xsaveopt,
3725 .xsaves,
3726 .zu,
3727 }),
3728 };
3638 pub const opteron: CpuModel = .{3729 pub const opteron: CpuModel = .{
3639 .name = "opteron",3730 .name = "opteron",
3640 .llvm_name = "opteron",3731 .llvm_name = "opteron",
...@@ -3697,7 +3788,6 @@ pub const cpu = struct {...@@ -3697,7 +3788,6 @@ pub const cpu = struct {
3697 .enqcmd,3788 .enqcmd,
3698 .f16c,3789 .f16c,
3699 .false_deps_perm,3790 .false_deps_perm,
3700 .false_deps_popcnt,
3701 .fast_15bytenop,3791 .fast_15bytenop,
3702 .fast_gather,3792 .fast_gather,
3703 .fast_scalar_fsqrt,3793 .fast_scalar_fsqrt,
...@@ -3726,7 +3816,6 @@ pub const cpu = struct {...@@ -3726,7 +3816,6 @@ pub const cpu = struct {
3726 .pku,3816 .pku,
3727 .popcnt,3817 .popcnt,
3728 .prefer_movmsk_over_vtest,3818 .prefer_movmsk_over_vtest,
3729 .prefetchi,
3730 .prfchw,3819 .prfchw,
3731 .ptwrite,3820 .ptwrite,
3732 .rdpid,3821 .rdpid,
...@@ -3738,6 +3827,7 @@ pub const cpu = struct {...@@ -3738,6 +3827,7 @@ pub const cpu = struct {
3738 .sha512,3827 .sha512,
3739 .shstk,3828 .shstk,
3740 .slow_3ops_lea,3829 .slow_3ops_lea,
3830 .slow_pmullq,
3741 .sm3,3831 .sm3,
3742 .sm4,3832 .sm4,
3743 .tuning_fast_imm_vector_shift,3833 .tuning_fast_imm_vector_shift,
...@@ -3908,7 +3998,6 @@ pub const cpu = struct {...@@ -3908,7 +3998,6 @@ pub const cpu = struct {
3908 .cx16,3998 .cx16,
3909 .f16c,3999 .f16c,
3910 .false_deps_perm,4000 .false_deps_perm,
3911 .false_deps_popcnt,
3912 .fast_15bytenop,4001 .fast_15bytenop,
3913 .fast_gather,4002 .fast_gather,
3914 .fast_scalar_fsqrt,4003 .fast_scalar_fsqrt,
...@@ -3947,6 +4036,7 @@ pub const cpu = struct {...@@ -3947,6 +4036,7 @@ pub const cpu = struct {
3947 .sha,4036 .sha,
3948 .shstk,4037 .shstk,
3949 .slow_3ops_lea,4038 .slow_3ops_lea,
4039 .slow_pmullq,
3950 .smap,4040 .smap,
3951 .smep,4041 .smep,
3952 .tuning_fast_imm_vector_shift,4042 .tuning_fast_imm_vector_shift,
...@@ -4013,6 +4103,7 @@ pub const cpu = struct {...@@ -4013,6 +4103,7 @@ pub const cpu = struct {
4013 .rdseed,4103 .rdseed,
4014 .sahf,4104 .sahf,
4015 .sha,4105 .sha,
4106 .slow_pmullq,
4016 .smap,4107 .smap,
4017 .smep,4108 .smep,
4018 .tuning_fast_imm_vector_shift,4109 .tuning_fast_imm_vector_shift,
...@@ -4124,6 +4215,7 @@ pub const cpu = struct {...@@ -4124,6 +4215,7 @@ pub const cpu = struct {
4124 .serialize,4215 .serialize,
4125 .sha,4216 .sha,
4126 .shstk,4217 .shstk,
4218 .slow_pmullq,
4127 .smap,4219 .smap,
4128 .smep,4220 .smep,
4129 .tsxldtrk,4221 .tsxldtrk,
...@@ -4494,6 +4586,7 @@ pub const cpu = struct {...@@ -4494,6 +4586,7 @@ pub const cpu = struct {
4494 .sahf,4586 .sahf,
4495 .sha,4587 .sha,
4496 .shstk,4588 .shstk,
4589 .slow_pmullq,
4497 .smap,4590 .smap,
4498 .smep,4591 .smep,
4499 .tuning_fast_imm_vector_shift,4592 .tuning_fast_imm_vector_shift,
...@@ -4567,6 +4660,82 @@ pub const cpu = struct {...@@ -4567,6 +4660,82 @@ pub const cpu = struct {
4567 .x87,4660 .x87,
4568 }),4661 }),
4569 };4662 };
4663 pub const wildcatlake: CpuModel = .{
4664 .name = "wildcatlake",
4665 .llvm_name = "wildcatlake",
4666 .features = featureSet(&[_]Feature{
4667 .@"64bit",
4668 .adx,
4669 .allow_light_256_bit,
4670 .avxifma,
4671 .avxneconvert,
4672 .avxvnni,
4673 .avxvnniint16,
4674 .avxvnniint8,
4675 .bmi,
4676 .bmi2,
4677 .clflushopt,
4678 .clwb,
4679 .cmov,
4680 .cmpccxadd,
4681 .cx16,
4682 .enqcmd,
4683 .f16c,
4684 .false_deps_perm,
4685 .fast_15bytenop,
4686 .fast_gather,
4687 .fast_scalar_fsqrt,
4688 .fast_shld_rotate,
4689 .fast_variable_crosslane_shuffle,
4690 .fast_variable_perlane_shuffle,
4691 .fast_vector_fsqrt,
4692 .fma,
4693 .fsgsbase,
4694 .fxsr,
4695 .gfni,
4696 .hreset,
4697 .idivq_to_divl,
4698 .invpcid,
4699 .lzcnt,
4700 .macrofusion,
4701 .mmx,
4702 .movbe,
4703 .movdir64b,
4704 .movdiri,
4705 .no_bypass_delay_blend,
4706 .no_bypass_delay_mov,
4707 .no_bypass_delay_shuffle,
4708 .nopl,
4709 .pconfig,
4710 .pku,
4711 .popcnt,
4712 .prefer_movmsk_over_vtest,
4713 .prfchw,
4714 .ptwrite,
4715 .rdpid,
4716 .rdrnd,
4717 .rdseed,
4718 .sahf,
4719 .serialize,
4720 .sha,
4721 .sha512,
4722 .shstk,
4723 .slow_3ops_lea,
4724 .slow_pmullq,
4725 .sm3,
4726 .sm4,
4727 .tuning_fast_imm_vector_shift,
4728 .uintr,
4729 .vaes,
4730 .vpclmulqdq,
4731 .vzeroupper,
4732 .waitpkg,
4733 .x87,
4734 .xsavec,
4735 .xsaveopt,
4736 .xsaves,
4737 }),
4738 };
4570 pub const winchip2: CpuModel = .{4739 pub const winchip2: CpuModel = .{
4571 .name = "winchip2",4740 .name = "winchip2",
4572 .llvm_name = "winchip2",4741 .llvm_name = "winchip2",
lib/std/Target/xtensa.zig+65
...@@ -15,6 +15,7 @@ pub const Feature = enum {...@@ -15,6 +15,7 @@ pub const Feature = enum {
15 div32,15 div32,
16 exception,16 exception,
17 extendedl32r,17 extendedl32r,
18 forced_atomics,
18 fp,19 fp,
19 highpriinterrupts,20 highpriinterrupts,
20 highpriinterrupts_level3,21 highpriinterrupts_level3,
...@@ -34,6 +35,7 @@ pub const Feature = enum {...@@ -34,6 +35,7 @@ pub const Feature = enum {
34 prid,35 prid,
35 regprotect,36 regprotect,
36 rvector,37 rvector,
38 s32c1i,
37 sext,39 sext,
38 threadptr,40 threadptr,
39 timers1,41 timers1,
...@@ -101,6 +103,11 @@ pub const all_features = blk: {...@@ -101,6 +103,11 @@ pub const all_features = blk: {
101 .description = "Enable Xtensa Extended L32R option",103 .description = "Enable Xtensa Extended L32R option",
102 .dependencies = featureSet(&[_]Feature{}),104 .dependencies = featureSet(&[_]Feature{}),
103 };105 };
106 result[@intFromEnum(Feature.forced_atomics)] = .{
107 .llvm_name = "forced-atomics",
108 .description = "Assume that lock-free native-width atomics are available",
109 .dependencies = featureSet(&[_]Feature{}),
110 };
104 result[@intFromEnum(Feature.fp)] = .{111 result[@intFromEnum(Feature.fp)] = .{
105 .llvm_name = "fp",112 .llvm_name = "fp",
106 .description = "Enable Xtensa Single FP instructions",113 .description = "Enable Xtensa Single FP instructions",
...@@ -206,6 +213,11 @@ pub const all_features = blk: {...@@ -206,6 +213,11 @@ pub const all_features = blk: {
206 .description = "Enable Xtensa Relocatable Vector option",213 .description = "Enable Xtensa Relocatable Vector option",
207 .dependencies = featureSet(&[_]Feature{}),214 .dependencies = featureSet(&[_]Feature{}),
208 };215 };
216 result[@intFromEnum(Feature.s32c1i)] = .{
217 .llvm_name = "s32c1i",
218 .description = "Enable Xtensa S32C1I option",
219 .dependencies = featureSet(&[_]Feature{}),
220 };
209 result[@intFromEnum(Feature.sext)] = .{221 result[@intFromEnum(Feature.sext)] = .{
210 .llvm_name = "sext",222 .llvm_name = "sext",
211 .description = "Enable Xtensa Sign Extend option",223 .description = "Enable Xtensa Sign Extend option",
...@@ -245,6 +257,59 @@ pub const all_features = blk: {...@@ -245,6 +257,59 @@ pub const all_features = blk: {
245};257};
246258
247pub const cpu = struct {259pub const cpu = struct {
260 pub const esp32: CpuModel = .{
261 .name = "esp32",
262 .llvm_name = "esp32",
263 .features = featureSet(&[_]Feature{
264 .bool,
265 .clamps,
266 .coprocessor,
267 .dcache,
268 .debug,
269 .density,
270 .dfpaccel,
271 .div32,
272 .exception,
273 .fp,
274 .highpriinterrupts_level7,
275 .interrupt,
276 .loop,
277 .mac16,
278 .minmax,
279 .miscsr,
280 .mul16,
281 .mul32,
282 .mul32high,
283 .nsa,
284 .prid,
285 .regprotect,
286 .rvector,
287 .s32c1i,
288 .sext,
289 .threadptr,
290 .timers3,
291 .windowed,
292 }),
293 };
294 pub const esp8266: CpuModel = .{
295 .name = "esp8266",
296 .llvm_name = "esp8266",
297 .features = featureSet(&[_]Feature{
298 .debug,
299 .density,
300 .exception,
301 .extendedl32r,
302 .highpriinterrupts_level3,
303 .interrupt,
304 .mul16,
305 .mul32,
306 .nsa,
307 .prid,
308 .regprotect,
309 .rvector,
310 .timers1,
311 }),
312 };
248 pub const generic: CpuModel = .{313 pub const generic: CpuModel = .{
249 .name = "generic",314 .name = "generic",
250 .llvm_name = "generic",315 .llvm_name = "generic",
lib/std/zig/system/x86.zig-2
...@@ -484,7 +484,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {...@@ -484,7 +484,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
484 setFeature(cpu, .rtm, bit(leaf.ebx, 11));484 setFeature(cpu, .rtm, bit(leaf.ebx, 11));
485 // AVX512 is only supported if the OS supports the context save for it.485 // AVX512 is only supported if the OS supports the context save for it.
486 setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);486 setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
487 setFeature(cpu, .evex512, bit(leaf.ebx, 16) and has_avx512_save);
488 setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);487 setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
489 setFeature(cpu, .rdseed, bit(leaf.ebx, 18));488 setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
490 setFeature(cpu, .adx, bit(leaf.ebx, 19));489 setFeature(cpu, .adx, bit(leaf.ebx, 19));
...@@ -605,7 +604,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {...@@ -605,7 +604,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
605 .invpcid,604 .invpcid,
606 .rtm,605 .rtm,
607 .avx512f,606 .avx512f,
608 .evex512,
609 .avx512dq,607 .avx512dq,
610 .rdseed,608 .rdseed,
611 .adx,609 .adx,
src/codegen/llvm.zig+1
...@@ -162,6 +162,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8...@@ -162,6 +162,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
162 .{ .v9_4a, "v9.4a" },162 .{ .v9_4a, "v9.4a" },
163 .{ .v9_5a, "v9.5a" },163 .{ .v9_5a, "v9.5a" },
164 .{ .v9_6a, "v9.6a" },164 .{ .v9_6a, "v9.6a" },
165 .{ .v9_7a, "v9.7a" },
165 }),166 }),
166 .powerpc => subArchName(target, .powerpc, .{167 .powerpc => subArchName(target, .powerpc, .{
167 .{ .spe, "spe" },168 .{ .spe, "spe" },
src/codegen/llvm/FuncGen.zig+4-4
...@@ -6630,11 +6630,11 @@ const ParamTypeIterator = struct {...@@ -6630,11 +6630,11 @@ const ParamTypeIterator = struct {
6630 } else if (isByRef(ty, zcu)) {6630 } else if (isByRef(ty, zcu)) {
6631 return .byref;6631 return .byref;
6632 } else if (target.cpu.arch.isX86() and6632 } else if (target.cpu.arch.isX86() and
6633 !target.cpu.has(.x86, .evex512) and6633 !target.cpu.has(.x86, .avx512f) and
6634 ty.totalVectorBits(zcu) >= 512)6634 ty.totalVectorBits(zcu) >= 512)
6635 {6635 {
6636 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns6636 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
6637 // "512-bit vector arguments require 'evex512' for AVX512"6637 // "512-bit vector arguments require 'avx512f' for AVX512"
6638 return .byref;6638 return .byref;
6639 } else {6639 } else {
6640 return .byval;6640 return .byval;
...@@ -6902,11 +6902,11 @@ fn returnTypeByRef(zcu: *Zcu, target: *const std.Target, ty: Type) bool {...@@ -6902,11 +6902,11 @@ fn returnTypeByRef(zcu: *Zcu, target: *const std.Target, ty: Type) bool {
6902 if (isByRef(ty, zcu)) {6902 if (isByRef(ty, zcu)) {
6903 return true;6903 return true;
6904 } else if (target.cpu.arch.isX86() and6904 } else if (target.cpu.arch.isX86() and
6905 !target.cpu.has(.x86, .evex512) and6905 !target.cpu.has(.x86, .avx512f) and
6906 ty.totalVectorBits(zcu) >= 512)6906 ty.totalVectorBits(zcu) >= 512)
6907 {6907 {
6908 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns6908 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
6909 // "512-bit vector arguments require 'evex512' for AVX512"6909 // "512-bit vector arguments require 'avx512f' for AVX512"
6910 return true;6910 return true;
6911 } else {6911 } else {
6912 return false;6912 return false;
src/link/Wasm.zig+3
...@@ -2829,6 +2829,7 @@ pub const Feature = packed struct(u8) {...@@ -2829,6 +2829,7 @@ pub const Feature = packed struct(u8) {
2829 @"exception-handling",2829 @"exception-handling",
2830 @"extended-const",2830 @"extended-const",
2831 fp16,2831 fp16,
2832 gc,
2832 memory64,2833 memory64,
2833 multimemory,2834 multimemory,
2834 multivalue,2835 multivalue,
...@@ -2852,6 +2853,7 @@ pub const Feature = packed struct(u8) {...@@ -2852,6 +2853,7 @@ pub const Feature = packed struct(u8) {
2852 .exception_handling => .@"exception-handling",2853 .exception_handling => .@"exception-handling",
2853 .extended_const => .@"extended-const",2854 .extended_const => .@"extended-const",
2854 .fp16 => .fp16,2855 .fp16 => .fp16,
2856 .gc => .gc,
2855 .multimemory => .multimemory,2857 .multimemory => .multimemory,
2856 .multivalue => .multivalue,2858 .multivalue => .multivalue,
2857 .mutable_globals => .@"mutable-globals",2859 .mutable_globals => .@"mutable-globals",
...@@ -2875,6 +2877,7 @@ pub const Feature = packed struct(u8) {...@@ -2875,6 +2877,7 @@ pub const Feature = packed struct(u8) {
2875 .@"exception-handling" => .exception_handling,2877 .@"exception-handling" => .exception_handling,
2876 .@"extended-const" => .extended_const,2878 .@"extended-const" => .extended_const,
2877 .fp16 => .fp16,2879 .fp16 => .fp16,
2880 .gc => .gc,
2878 .memory64 => null, // Linker-only feature.2881 .memory64 => null, // Linker-only feature.
2879 .multimemory => .multimemory,2882 .multimemory => .multimemory,
2880 .multivalue => .multivalue,2883 .multivalue => .multivalue,
src/target.zig+2
...@@ -388,6 +388,8 @@ pub fn hasDebugInfo(target: *const std.Target) bool {...@@ -388,6 +388,8 @@ pub fn hasDebugInfo(target: *const std.Target) bool {
388 .ptx85,388 .ptx85,
389 .ptx86,389 .ptx86,
390 .ptx87,390 .ptx87,
391 .ptx88,
392 .ptx90,
391 }),393 }),
392 .bpfel, .bpfeb => false,394 .bpfel, .bpfeb => false,
393 else => true,395 else => true,
tools/update_cpu_features.zig+55-13
...@@ -203,6 +203,10 @@ const targets = [_]ArchTarget{...@@ -203,6 +203,10 @@ const targets = [_]ArchTarget{
203 .llvm_name = "ampere1a",203 .llvm_name = "ampere1a",
204 .flatten = true,204 .flatten = true,
205 },205 },
206 .{
207 .llvm_name = "ampere1c",
208 .flatten = true,
209 },
206 .{210 .{
207 .llvm_name = "apple-a7",211 .llvm_name = "apple-a7",
208 .flatten = true,212 .flatten = true,
...@@ -247,6 +251,26 @@ const targets = [_]ArchTarget{...@@ -247,6 +251,26 @@ const targets = [_]ArchTarget{
247 .llvm_name = "apple-m4",251 .llvm_name = "apple-m4",
248 .flatten = true,252 .flatten = true,
249 },253 },
254 .{
255 .llvm_name = "apple-m5",
256 .flatten = true,
257 },
258 .{
259 .llvm_name = "c1-nano",
260 .flatten = true,
261 },
262 .{
263 .llvm_name = "c1-premium",
264 .flatten = true,
265 },
266 .{
267 .llvm_name = "c1-pro",
268 .flatten = true,
269 },
270 .{
271 .llvm_name = "c1-ultra",
272 .flatten = true,
273 },
250 .{274 .{
251 .llvm_name = "carmel",275 .llvm_name = "carmel",
252 .flatten = true,276 .flatten = true,
...@@ -862,6 +886,10 @@ const targets = [_]ArchTarget{...@@ -862,6 +886,10 @@ const targets = [_]ArchTarget{
862 .llvm_name = "armv9.6-a",886 .llvm_name = "armv9.6-a",
863 .zig_name = "v9_6a",887 .zig_name = "v9_6a",
864 },888 },
889 .{
890 .llvm_name = "armv9.7-a",
891 .zig_name = "v9_7a",
892 },
865 .{893 .{
866 .llvm_name = "armv9-a",894 .llvm_name = "armv9-a",
867 .zig_name = "v9a",895 .zig_name = "v9a",
...@@ -982,6 +1010,10 @@ const targets = [_]ArchTarget{...@@ -982,6 +1010,10 @@ const targets = [_]ArchTarget{
982 .llvm_name = "v9.6a",1010 .llvm_name = "v9.6a",
983 .zig_name = "has_v9_6a",1011 .zig_name = "has_v9_6a",
984 },1012 },
1013 .{
1014 .llvm_name = "v9.7a",
1015 .zig_name = "has_v9_7a",
1016 },
985 },1017 },
986 .extra_cpus = &.{1018 .extra_cpus = &.{
987 .{1019 .{
...@@ -1249,6 +1281,24 @@ const targets = [_]ArchTarget{...@@ -1249,6 +1281,24 @@ const targets = [_]ArchTarget{
1249 .td_name = "LoongArch",1281 .td_name = "LoongArch",
1250 },1282 },
1251 .extra_cpus = &.{1283 .extra_cpus = &.{
1284 .{
1285 .llvm_name = null,
1286 .zig_name = "la32v1_0",
1287 .features = &.{
1288 "32bit",
1289 "32s",
1290 "d",
1291 "ual",
1292 },
1293 },
1294 .{
1295 .llvm_name = null,
1296 .zig_name = "la32rv1_0",
1297 .features = &.{
1298 "32bit",
1299 "ual",
1300 },
1301 },
1252 .{1302 .{
1253 .llvm_name = null,1303 .llvm_name = null,
1254 .zig_name = "la64v1_0",1304 .zig_name = "la64v1_0",
...@@ -1276,6 +1326,7 @@ const targets = [_]ArchTarget{...@@ -1276,6 +1326,7 @@ const targets = [_]ArchTarget{
1276 },1326 },
1277 .omit_cpus = &.{1327 .omit_cpus = &.{
1278 "generic",1328 "generic",
1329 "loongarch32",
1279 "loongarch64",1330 "loongarch64",
1280 },1331 },
1281 },1332 },
...@@ -1557,26 +1608,17 @@ const targets = [_]ArchTarget{...@@ -1557,26 +1608,17 @@ const targets = [_]ArchTarget{
1557 .llvm_name = "64bit-mode",1608 .llvm_name = "64bit-mode",
1558 .omit = true,1609 .omit = true,
1559 },1610 },
1560 // Remove these when LLVM removes AVX10.N-256 support.
1561 .{
1562 .llvm_name = "avx10.1-256",
1563 .flatten = true,
1564 },
1565 .{
1566 .llvm_name = "avx10.2-256",
1567 .flatten = true,
1568 },
1569 .{1611 .{
1570 .llvm_name = "avx10.1-512",1612 .llvm_name = "avx10.1-512",
1571 .zig_name = "avx10_1",1613 .omit = true,
1572 },1614 },
1573 .{1615 .{
1574 .llvm_name = "avx10.2-512",1616 .llvm_name = "avx10.2-512",
1575 .zig_name = "avx10_2",1617 .omit = true,
1576 },1618 },
1577 .{1619 .{
1578 .llvm_name = "avx512f",1620 .llvm_name = "evex512",
1579 .extra_deps = &.{"evex512"},1621 .omit = true,
1580 },1622 },
1581 .{1623 .{
1582 .llvm_name = "alderlake",1624 .llvm_name = "alderlake",