| ... | ... | @@ -3836,61 +3836,17 @@ pub fn atomicPtrAlignment( |
| 3836 | 3836 | ) AtomicPtrAlignmentError!Alignment { |
| 3837 | 3837 | const target = zcu.getTarget(); |
| 3838 | 3838 | const max_atomic_bits: u16 = switch (target.cpu.arch) { |
| 3839 | | .avr, |
| 3840 | | .msp430, |
| 3841 | | => 16, |
| 3842 | | |
| 3843 | | .arc, |
| 3844 | | .arm, |
| 3845 | | .armeb, |
| 3846 | | .hexagon, |
| 3847 | | .m68k, |
| 3848 | | .mips, |
| 3849 | | .mipsel, |
| 3850 | | .nvptx, |
| 3851 | | .or1k, |
| 3852 | | .powerpc, |
| 3853 | | .powerpcle, |
| 3854 | | .riscv32, |
| 3855 | | .riscv32be, |
| 3856 | | .sparc, |
| 3857 | | .thumb, |
| 3858 | | .thumbeb, |
| 3859 | | .x86, |
| 3860 | | .xcore, |
| 3861 | | .kalimba, |
| 3862 | | .lanai, |
| 3863 | | .wasm32, |
| 3864 | | .csky, |
| 3865 | | .spirv32, |
| 3866 | | .loongarch32, |
| 3867 | | .xtensa, |
| 3868 | | .propeller, |
| 3869 | | => 32, |
| 3870 | | |
| 3871 | | .amdgcn, |
| 3872 | | .bpfel, |
| 3873 | | .bpfeb, |
| 3874 | | .mips64, |
| 3875 | | .mips64el, |
| 3876 | | .nvptx64, |
| 3877 | | .powerpc64, |
| 3878 | | .powerpc64le, |
| 3879 | | .riscv64, |
| 3880 | | .riscv64be, |
| 3881 | | .sparc64, |
| 3882 | | .s390x, |
| 3883 | | .wasm64, |
| 3884 | | .ve, |
| 3885 | | .spirv64, |
| 3886 | | .loongarch64, |
| 3887 | | => 64, |
| 3888 | | |
| 3889 | 3839 | .aarch64, |
| 3890 | 3840 | .aarch64_be, |
| 3891 | 3841 | => 128, |
| 3892 | 3842 | |
| 3893 | | .x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64, |
| 3843 | .mips64, |
| 3844 | .mips64el, |
| 3845 | => 64, // N32 should be 64, not 32. |
| 3846 | |
| 3847 | .x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64, // x32 should be 64 or 128, not 32. |
| 3848 | |
| 3849 | else => target.ptrBitWidth(), |
| 3894 | 3850 | }; |
| 3895 | 3851 | |
| 3896 | 3852 | if (ty.toIntern() == .bool_type) return .none; |