authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-05-23 05:44:14+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-05-23 05:44:14+02:00
logcece38bc054b801bde76603119fe695be3cb3a06
tree4b1612b2d2fcb662c39cc0c1efb54d92c40f3ec1
parent9e3eaa6be7b2b22d44205012abc4278cdd673526
parent8fe6d5a48e97ec1b3260c86832baa707271d0f8b

Merge pull request 'std.zig.system.loongarch: take HWCAP into consideration' (#31614) from AstraFall/zig:loongarch/cpu-detect into master

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/31614 Reviewed-by: Alex Rønne Petersen <alex@alexrp.com>

3 files changed, 72 insertions(+), 36 deletions(-)

lib/std/os/linux.zig+47-1
......@@ -96,7 +96,6 @@ pub fn clone(
9696}
9797
9898pub const ARCH = arch_bits.ARCH;
99pub const HWCAP = arch_bits.HWCAP;
10099pub const SC = arch_bits.SC;
101100pub const VDSO = arch_bits.VDSO;
102101pub const user_desc = arch_bits.user_desc;
......@@ -524,6 +523,53 @@ pub const O = switch (native_arch) {
524523 else => @compileError("missing std.os.linux.O constants for this architecture"),
525524};
526525
526pub const HWCAP = switch (native_arch) {
527 .arm, .armeb, .thumb, .thumbeb => struct {
528 pub const SWP = 1 << 0;
529 pub const HALF = 1 << 1;
530 pub const THUMB = 1 << 2;
531 pub const @"26BIT" = 1 << 3;
532 pub const FAST_MULT = 1 << 4;
533 pub const FPA = 1 << 5;
534 pub const VFP = 1 << 6;
535 pub const EDSP = 1 << 7;
536 pub const JAVA = 1 << 8;
537 pub const IWMMXT = 1 << 9;
538 pub const CRUNCH = 1 << 10;
539 pub const THUMBEE = 1 << 11;
540 pub const NEON = 1 << 12;
541 pub const VFPv3 = 1 << 13;
542 pub const VFPv3D16 = 1 << 14;
543 pub const TLS = 1 << 15;
544 pub const VFPv4 = 1 << 16;
545 pub const IDIVA = 1 << 17;
546 pub const IDIVT = 1 << 18;
547 pub const VFPD32 = 1 << 19;
548 pub const IDIV = IDIVA | IDIVT;
549 pub const LPAE = 1 << 20;
550 pub const EVTSTRM = 1 << 21;
551 },
552 .loongarch32, .loongarch64 => struct {
553 pub const CPUCFG = 1 << 0;
554 pub const LAM = 1 << 1;
555 pub const UAL = 1 << 2;
556 pub const FPU = 1 << 3;
557 pub const LSX = 1 << 4;
558 pub const LASX = 1 << 5;
559 pub const CRC32 = 1 << 6;
560 pub const COMPLEX = 1 << 7;
561 pub const CRYPTO = 1 << 8;
562 pub const LVZ = 1 << 9;
563 pub const LBT_X86 = 1 << 10;
564 pub const LBT_ARM = 1 << 11;
565 pub const LBT_MIPS = 1 << 12;
566 pub const PTW = 1 << 13;
567 pub const LSPW = 1 << 14;
568 pub const SCQ = 1 << 15;
569 },
570 else => struct {},
571};
572
527573pub const RENAME = packed struct(u32) {
528574 /// Cannot be set together with `EXCHANGE`.
529575 NOREPLACE: bool = false,
lib/std/os/linux/arm.zig-26
......@@ -182,30 +182,4 @@ pub const VDSO = struct {
182182 pub const CGT_VER = "LINUX_2.6";
183183};
184184
185pub const HWCAP = struct {
186 pub const SWP = 1 << 0;
187 pub const HALF = 1 << 1;
188 pub const THUMB = 1 << 2;
189 pub const @"26BIT" = 1 << 3;
190 pub const FAST_MULT = 1 << 4;
191 pub const FPA = 1 << 5;
192 pub const VFP = 1 << 6;
193 pub const EDSP = 1 << 7;
194 pub const JAVA = 1 << 8;
195 pub const IWMMXT = 1 << 9;
196 pub const CRUNCH = 1 << 10;
197 pub const THUMBEE = 1 << 11;
198 pub const NEON = 1 << 12;
199 pub const VFPv3 = 1 << 13;
200 pub const VFPv3D16 = 1 << 14;
201 pub const TLS = 1 << 15;
202 pub const VFPv4 = 1 << 16;
203 pub const IDIVA = 1 << 17;
204 pub const IDIVT = 1 << 18;
205 pub const VFPD32 = 1 << 19;
206 pub const IDIV = IDIVA | IDIVT;
207 pub const LPAE = 1 << 20;
208 pub const EVTSTRM = 1 << 21;
209};
210
211185pub const time_t = i32;
lib/std/zig/system/loongarch.zig+25-9
......@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(
3131
3232 cpu.features.addFeatureSet(cpu.model.features);
3333
34 const cfg1 = cpucfg(1);
3534 const cfg2 = cpucfg(2);
3635 const cfg3 = cpucfg(3);
3736
38 setFeature(&cpu, .ual, bit(cfg1, 20));
37 if (builtin.os.tag == .linux) {
38 const HWCAP = std.os.linux.HWCAP;
39 const hwcap_bits: usize = if (builtin.link_libc)
40 std.c.getauxval(std.elf.AT_HWCAP)
41 else
42 std.os.linux.getauxval(std.elf.AT_HWCAP);
3943
40 const has_fpu = bit(cfg2, 0);
41 setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
42 setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
44 setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
4345
44 setFeature(&cpu, .lsx, bit(cfg2, 6));
45 setFeature(&cpu, .lasx, bit(cfg2, 7));
46 setFeature(&cpu, .lvz, bit(cfg2, 10));
46 const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
47 setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
48 setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
49 setFeature(&cpu, .lsx, (hwcap_bits & HWCAP.LSX) != 0);
50 setFeature(&cpu, .lasx, (hwcap_bits & HWCAP.LASX) != 0);
4751
48 setFeature(&cpu, .lbt, bit(cfg2, 18) and bit(cfg2, 19) and bit(cfg2, 20));
52 setFeature(&cpu, .lvz, (hwcap_bits & HWCAP.LVZ) != 0);
53 setFeature(&cpu, .lbt, (hwcap_bits & HWCAP.LBT_X86) != 0 and (hwcap_bits & HWCAP.LBT_ARM) != 0 and (hwcap_bits & HWCAP.LBT_MIPS) != 0);
54 } else {
55 setFeature(&cpu, .ual, false);
56
57 setFeature(&cpu, .f, false);
58 setFeature(&cpu, .d, false);
59 setFeature(&cpu, .lsx, false);
60 setFeature(&cpu, .lasx, false);
61
62 setFeature(&cpu, .lvz, false);
63 setFeature(&cpu, .lbt, false);
64 }
4965
5066 setFeature(&cpu, .frecipe, bit(cfg2, 25));
5167 setFeature(&cpu, .div32, bit(cfg2, 26));